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Commit | Line | Data |
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da9bb1d2 AC |
1 | /* |
2 | * edac_mc kernel module | |
49c0dab7 | 3 | * (C) 2005, 2006 Linux Networx (http://lnxi.com) |
da9bb1d2 AC |
4 | * This file may be distributed under the terms of the |
5 | * GNU General Public License. | |
6 | * | |
7 | * Written by Thayne Harbaugh | |
8 | * Based on work by Dan Hollis <goemon at anime dot net> and others. | |
9 | * http://www.anime.net/~goemon/linux-ecc/ | |
10 | * | |
11 | * Modified by Dave Peterson and Doug Thompson | |
12 | * | |
13 | */ | |
14 | ||
da9bb1d2 AC |
15 | #include <linux/module.h> |
16 | #include <linux/proc_fs.h> | |
17 | #include <linux/kernel.h> | |
18 | #include <linux/types.h> | |
19 | #include <linux/smp.h> | |
20 | #include <linux/init.h> | |
21 | #include <linux/sysctl.h> | |
22 | #include <linux/highmem.h> | |
23 | #include <linux/timer.h> | |
24 | #include <linux/slab.h> | |
25 | #include <linux/jiffies.h> | |
26 | #include <linux/spinlock.h> | |
27 | #include <linux/list.h> | |
da9bb1d2 | 28 | #include <linux/ctype.h> |
c0d12172 | 29 | #include <linux/edac.h> |
53f2d028 | 30 | #include <linux/bitops.h> |
7c0f6ba6 | 31 | #include <linux/uaccess.h> |
da9bb1d2 | 32 | #include <asm/page.h> |
78d88e8a | 33 | #include "edac_mc.h" |
7c9281d7 | 34 | #include "edac_module.h" |
53f2d028 MCC |
35 | #include <ras/ras_event.h> |
36 | ||
b01aec9b BP |
37 | #ifdef CONFIG_EDAC_ATOMIC_SCRUB |
38 | #include <asm/edac.h> | |
39 | #else | |
40 | #define edac_atomic_scrub(va, size) do { } while (0) | |
41 | #endif | |
42 | ||
8c22b4fe BP |
43 | int edac_op_state = EDAC_OPSTATE_INVAL; |
44 | EXPORT_SYMBOL_GPL(edac_op_state); | |
45 | ||
fee27d7d BP |
46 | static int edac_report = EDAC_REPORTING_ENABLED; |
47 | ||
da9bb1d2 | 48 | /* lock to memory controller's control array */ |
63b7df91 | 49 | static DEFINE_MUTEX(mem_ctls_mutex); |
ff6ac2a6 | 50 | static LIST_HEAD(mc_devices); |
da9bb1d2 | 51 | |
80cc7d87 MCC |
52 | /* |
53 | * Used to lock EDAC MC to just one module, avoiding two drivers e. g. | |
54 | * apei/ghes and i7core_edac to be used at the same time. | |
55 | */ | |
3877c7d1 | 56 | static const char *edac_mc_owner; |
80cc7d87 | 57 | |
bffc7dec | 58 | int edac_get_report_status(void) |
fee27d7d BP |
59 | { |
60 | return edac_report; | |
61 | } | |
bffc7dec | 62 | EXPORT_SYMBOL_GPL(edac_get_report_status); |
fee27d7d | 63 | |
bffc7dec | 64 | void edac_set_report_status(int new) |
fee27d7d BP |
65 | { |
66 | if (new == EDAC_REPORTING_ENABLED || | |
67 | new == EDAC_REPORTING_DISABLED || | |
68 | new == EDAC_REPORTING_FORCE) | |
69 | edac_report = new; | |
70 | } | |
bffc7dec | 71 | EXPORT_SYMBOL_GPL(edac_set_report_status); |
fee27d7d BP |
72 | |
73 | static int edac_report_set(const char *str, const struct kernel_param *kp) | |
74 | { | |
75 | if (!str) | |
76 | return -EINVAL; | |
77 | ||
78 | if (!strncmp(str, "on", 2)) | |
79 | edac_report = EDAC_REPORTING_ENABLED; | |
80 | else if (!strncmp(str, "off", 3)) | |
81 | edac_report = EDAC_REPORTING_DISABLED; | |
82 | else if (!strncmp(str, "force", 5)) | |
83 | edac_report = EDAC_REPORTING_FORCE; | |
84 | ||
85 | return 0; | |
86 | } | |
87 | ||
88 | static int edac_report_get(char *buffer, const struct kernel_param *kp) | |
89 | { | |
90 | int ret = 0; | |
91 | ||
92 | switch (edac_report) { | |
93 | case EDAC_REPORTING_ENABLED: | |
94 | ret = sprintf(buffer, "on"); | |
95 | break; | |
96 | case EDAC_REPORTING_DISABLED: | |
97 | ret = sprintf(buffer, "off"); | |
98 | break; | |
99 | case EDAC_REPORTING_FORCE: | |
100 | ret = sprintf(buffer, "force"); | |
101 | break; | |
102 | default: | |
103 | ret = -EINVAL; | |
104 | break; | |
105 | } | |
106 | ||
107 | return ret; | |
108 | } | |
109 | ||
110 | static const struct kernel_param_ops edac_report_ops = { | |
111 | .set = edac_report_set, | |
112 | .get = edac_report_get, | |
113 | }; | |
114 | ||
115 | module_param_cb(edac_report, &edac_report_ops, &edac_report, 0644); | |
116 | ||
d55c79ac RR |
117 | unsigned int edac_dimm_info_location(struct dimm_info *dimm, char *buf, |
118 | unsigned int len) | |
6e84d359 MCC |
119 | { |
120 | struct mem_ctl_info *mci = dimm->mci; | |
121 | int i, n, count = 0; | |
122 | char *p = buf; | |
123 | ||
124 | for (i = 0; i < mci->n_layers; i++) { | |
125 | n = snprintf(p, len, "%s %d ", | |
126 | edac_layer_name[mci->layers[i].type], | |
127 | dimm->location[i]); | |
128 | p += n; | |
129 | len -= n; | |
130 | count += n; | |
131 | if (!len) | |
132 | break; | |
133 | } | |
134 | ||
135 | return count; | |
136 | } | |
137 | ||
da9bb1d2 AC |
138 | #ifdef CONFIG_EDAC_DEBUG |
139 | ||
a4b4be3f | 140 | static void edac_mc_dump_channel(struct rank_info *chan) |
da9bb1d2 | 141 | { |
6e84d359 MCC |
142 | edac_dbg(4, " channel->chan_idx = %d\n", chan->chan_idx); |
143 | edac_dbg(4, " channel = %p\n", chan); | |
144 | edac_dbg(4, " channel->csrow = %p\n", chan->csrow); | |
145 | edac_dbg(4, " channel->dimm = %p\n", chan->dimm); | |
4275be63 MCC |
146 | } |
147 | ||
c498afaf | 148 | static void edac_mc_dump_dimm(struct dimm_info *dimm) |
4275be63 | 149 | { |
6e84d359 MCC |
150 | char location[80]; |
151 | ||
c498afaf RR |
152 | if (!dimm->nr_pages) |
153 | return; | |
154 | ||
6e84d359 MCC |
155 | edac_dimm_info_location(dimm, location, sizeof(location)); |
156 | ||
157 | edac_dbg(4, "%s%i: %smapped as virtual row %d, chan %d\n", | |
9713faec | 158 | dimm->mci->csbased ? "rank" : "dimm", |
c498afaf | 159 | dimm->idx, location, dimm->csrow, dimm->cschannel); |
6e84d359 MCC |
160 | edac_dbg(4, " dimm = %p\n", dimm); |
161 | edac_dbg(4, " dimm->label = '%s'\n", dimm->label); | |
162 | edac_dbg(4, " dimm->nr_pages = 0x%x\n", dimm->nr_pages); | |
163 | edac_dbg(4, " dimm->grain = %d\n", dimm->grain); | |
164 | edac_dbg(4, " dimm->nr_pages = 0x%x\n", dimm->nr_pages); | |
da9bb1d2 AC |
165 | } |
166 | ||
2da1c119 | 167 | static void edac_mc_dump_csrow(struct csrow_info *csrow) |
da9bb1d2 | 168 | { |
6e84d359 MCC |
169 | edac_dbg(4, "csrow->csrow_idx = %d\n", csrow->csrow_idx); |
170 | edac_dbg(4, " csrow = %p\n", csrow); | |
171 | edac_dbg(4, " csrow->first_page = 0x%lx\n", csrow->first_page); | |
172 | edac_dbg(4, " csrow->last_page = 0x%lx\n", csrow->last_page); | |
173 | edac_dbg(4, " csrow->page_mask = 0x%lx\n", csrow->page_mask); | |
174 | edac_dbg(4, " csrow->nr_channels = %d\n", csrow->nr_channels); | |
175 | edac_dbg(4, " csrow->channels = %p\n", csrow->channels); | |
176 | edac_dbg(4, " csrow->mci = %p\n", csrow->mci); | |
da9bb1d2 AC |
177 | } |
178 | ||
2da1c119 | 179 | static void edac_mc_dump_mci(struct mem_ctl_info *mci) |
da9bb1d2 | 180 | { |
956b9ba1 JP |
181 | edac_dbg(3, "\tmci = %p\n", mci); |
182 | edac_dbg(3, "\tmci->mtype_cap = %lx\n", mci->mtype_cap); | |
183 | edac_dbg(3, "\tmci->edac_ctl_cap = %lx\n", mci->edac_ctl_cap); | |
184 | edac_dbg(3, "\tmci->edac_cap = %lx\n", mci->edac_cap); | |
185 | edac_dbg(4, "\tmci->edac_check = %p\n", mci->edac_check); | |
186 | edac_dbg(3, "\tmci->nr_csrows = %d, csrows = %p\n", | |
187 | mci->nr_csrows, mci->csrows); | |
188 | edac_dbg(3, "\tmci->nr_dimms = %d, dimms = %p\n", | |
189 | mci->tot_dimms, mci->dimms); | |
190 | edac_dbg(3, "\tdev = %p\n", mci->pdev); | |
191 | edac_dbg(3, "\tmod_name:ctl_name = %s:%s\n", | |
192 | mci->mod_name, mci->ctl_name); | |
193 | edac_dbg(3, "\tpvt_info = %p\n\n", mci->pvt_info); | |
da9bb1d2 AC |
194 | } |
195 | ||
24f9a7fe BP |
196 | #endif /* CONFIG_EDAC_DEBUG */ |
197 | ||
f4ce6eca | 198 | const char * const edac_mem_types[] = { |
d6dd77eb TL |
199 | [MEM_EMPTY] = "Empty", |
200 | [MEM_RESERVED] = "Reserved", | |
201 | [MEM_UNKNOWN] = "Unknown", | |
202 | [MEM_FPM] = "FPM", | |
203 | [MEM_EDO] = "EDO", | |
204 | [MEM_BEDO] = "BEDO", | |
205 | [MEM_SDR] = "Unbuffered-SDR", | |
206 | [MEM_RDR] = "Registered-SDR", | |
207 | [MEM_DDR] = "Unbuffered-DDR", | |
208 | [MEM_RDDR] = "Registered-DDR", | |
209 | [MEM_RMBS] = "RMBS", | |
210 | [MEM_DDR2] = "Unbuffered-DDR2", | |
211 | [MEM_FB_DDR2] = "FullyBuffered-DDR2", | |
212 | [MEM_RDDR2] = "Registered-DDR2", | |
213 | [MEM_XDR] = "XDR", | |
214 | [MEM_DDR3] = "Unbuffered-DDR3", | |
215 | [MEM_RDDR3] = "Registered-DDR3", | |
216 | [MEM_LRDDR3] = "Load-Reduced-DDR3-RAM", | |
217 | [MEM_DDR4] = "Unbuffered-DDR4", | |
001f8613 | 218 | [MEM_RDDR4] = "Registered-DDR4", |
b748f2de | 219 | [MEM_LRDDR4] = "Load-Reduced-DDR4-RAM", |
001f8613 | 220 | [MEM_NVDIMM] = "Non-volatile-RAM", |
239642fe BP |
221 | }; |
222 | EXPORT_SYMBOL_GPL(edac_mem_types); | |
223 | ||
93e4fe64 MCC |
224 | /** |
225 | * edac_align_ptr - Prepares the pointer offsets for a single-shot allocation | |
226 | * @p: pointer to a pointer with the memory offset to be used. At | |
227 | * return, this will be incremented to point to the next offset | |
228 | * @size: Size of the data structure to be reserved | |
229 | * @n_elems: Number of elements that should be reserved | |
da9bb1d2 AC |
230 | * |
231 | * If 'size' is a constant, the compiler will optimize this whole function | |
93e4fe64 MCC |
232 | * down to either a no-op or the addition of a constant to the value of '*p'. |
233 | * | |
234 | * The 'p' pointer is absolutely needed to keep the proper advancing | |
235 | * further in memory to the proper offsets when allocating the struct along | |
236 | * with its embedded structs, as edac_device_alloc_ctl_info() does it | |
237 | * above, for example. | |
238 | * | |
239 | * At return, the pointer 'p' will be incremented to be used on a next call | |
240 | * to this function. | |
da9bb1d2 | 241 | */ |
d55c79ac | 242 | void *edac_align_ptr(void **p, unsigned int size, int n_elems) |
da9bb1d2 | 243 | { |
d55c79ac | 244 | unsigned int align, r; |
93e4fe64 | 245 | void *ptr = *p; |
da9bb1d2 | 246 | |
93e4fe64 MCC |
247 | *p += size * n_elems; |
248 | ||
249 | /* | |
250 | * 'p' can possibly be an unaligned item X such that sizeof(X) is | |
251 | * 'size'. Adjust 'p' so that its alignment is at least as | |
252 | * stringent as what the compiler would provide for X and return | |
253 | * the aligned result. | |
254 | * Here we assume that the alignment of a "long long" is the most | |
da9bb1d2 AC |
255 | * stringent alignment that the compiler will ever provide by default. |
256 | * As far as I know, this is a reasonable assumption. | |
257 | */ | |
258 | if (size > sizeof(long)) | |
259 | align = sizeof(long long); | |
260 | else if (size > sizeof(int)) | |
261 | align = sizeof(long); | |
262 | else if (size > sizeof(short)) | |
263 | align = sizeof(int); | |
264 | else if (size > sizeof(char)) | |
265 | align = sizeof(short); | |
266 | else | |
079708b9 | 267 | return (char *)ptr; |
da9bb1d2 | 268 | |
8447c4d1 | 269 | r = (unsigned long)p % align; |
da9bb1d2 AC |
270 | |
271 | if (r == 0) | |
079708b9 | 272 | return (char *)ptr; |
da9bb1d2 | 273 | |
93e4fe64 MCC |
274 | *p += align - r; |
275 | ||
7391c6dc | 276 | return (void *)(((unsigned long)ptr) + align - r); |
da9bb1d2 AC |
277 | } |
278 | ||
faa2ad09 SR |
279 | static void _edac_mc_free(struct mem_ctl_info *mci) |
280 | { | |
faa2ad09 | 281 | struct csrow_info *csr; |
718d5851 | 282 | int i, chn, row; |
faa2ad09 SR |
283 | |
284 | if (mci->dimms) { | |
718d5851 | 285 | for (i = 0; i < mci->tot_dimms; i++) |
faa2ad09 SR |
286 | kfree(mci->dimms[i]); |
287 | kfree(mci->dimms); | |
288 | } | |
718d5851 | 289 | |
faa2ad09 | 290 | if (mci->csrows) { |
718d5851 | 291 | for (row = 0; row < mci->nr_csrows; row++) { |
faa2ad09 | 292 | csr = mci->csrows[row]; |
718d5851 RR |
293 | if (!csr) |
294 | continue; | |
295 | ||
296 | if (csr->channels) { | |
297 | for (chn = 0; chn < mci->num_cschannel; chn++) | |
298 | kfree(csr->channels[chn]); | |
299 | kfree(csr->channels); | |
faa2ad09 | 300 | } |
718d5851 | 301 | kfree(csr); |
faa2ad09 SR |
302 | } |
303 | kfree(mci->csrows); | |
304 | } | |
305 | kfree(mci); | |
306 | } | |
307 | ||
d55c79ac RR |
308 | struct mem_ctl_info *edac_mc_alloc(unsigned int mc_num, |
309 | unsigned int n_layers, | |
ca0907b9 | 310 | struct edac_mc_layer *layers, |
d55c79ac | 311 | unsigned int sz_pvt) |
da9bb1d2 AC |
312 | { |
313 | struct mem_ctl_info *mci; | |
4275be63 | 314 | struct edac_mc_layer *layer; |
de3910eb MCC |
315 | struct csrow_info *csr; |
316 | struct rank_info *chan; | |
a7d7d2e1 | 317 | struct dimm_info *dimm; |
4275be63 | 318 | u32 *ce_per_layer[EDAC_MAX_LAYERS], *ue_per_layer[EDAC_MAX_LAYERS]; |
d55c79ac | 319 | unsigned int pos[EDAC_MAX_LAYERS]; |
977b1ce7 | 320 | unsigned int idx, size, tot_dimms = 1, count = 1; |
d55c79ac | 321 | unsigned int tot_csrows = 1, tot_channels = 1, tot_errcount = 0; |
5926ff50 | 322 | void *pvt, *p, *ptr = NULL; |
977b1ce7 | 323 | int i, j, row, chn, n, len; |
4275be63 MCC |
324 | bool per_rank = false; |
325 | ||
d260e8ff RR |
326 | if (WARN_ON(n_layers > EDAC_MAX_LAYERS || n_layers == 0)) |
327 | return NULL; | |
977b1ce7 | 328 | |
4275be63 MCC |
329 | /* |
330 | * Calculate the total amount of dimms and csrows/cschannels while | |
331 | * in the old API emulation mode | |
332 | */ | |
977b1ce7 RR |
333 | for (idx = 0; idx < n_layers; idx++) { |
334 | tot_dimms *= layers[idx].size; | |
335 | ||
336 | if (layers[idx].is_virt_csrow) | |
337 | tot_csrows *= layers[idx].size; | |
4275be63 | 338 | else |
977b1ce7 | 339 | tot_channels *= layers[idx].size; |
4275be63 | 340 | |
977b1ce7 | 341 | if (layers[idx].type == EDAC_MC_LAYER_CHIP_SELECT) |
4275be63 MCC |
342 | per_rank = true; |
343 | } | |
da9bb1d2 AC |
344 | |
345 | /* Figure out the offsets of the various items from the start of an mc | |
346 | * structure. We want the alignment of each item to be at least as | |
347 | * stringent as what the compiler would provide if we could simply | |
348 | * hardcode everything into a single struct. | |
349 | */ | |
93e4fe64 | 350 | mci = edac_align_ptr(&ptr, sizeof(*mci), 1); |
4275be63 | 351 | layer = edac_align_ptr(&ptr, sizeof(*layer), n_layers); |
4275be63 MCC |
352 | for (i = 0; i < n_layers; i++) { |
353 | count *= layers[i].size; | |
956b9ba1 | 354 | edac_dbg(4, "errcount layer %d size %d\n", i, count); |
4275be63 MCC |
355 | ce_per_layer[i] = edac_align_ptr(&ptr, sizeof(u32), count); |
356 | ue_per_layer[i] = edac_align_ptr(&ptr, sizeof(u32), count); | |
357 | tot_errcount += 2 * count; | |
358 | } | |
359 | ||
956b9ba1 | 360 | edac_dbg(4, "allocating %d error counters\n", tot_errcount); |
93e4fe64 | 361 | pvt = edac_align_ptr(&ptr, sz_pvt, 1); |
079708b9 | 362 | size = ((unsigned long)pvt) + sz_pvt; |
da9bb1d2 | 363 | |
956b9ba1 JP |
364 | edac_dbg(1, "allocating %u bytes for mci data (%d %s, %d csrows/channels)\n", |
365 | size, | |
366 | tot_dimms, | |
367 | per_rank ? "ranks" : "dimms", | |
368 | tot_csrows * tot_channels); | |
de3910eb | 369 | |
8096cfaf DT |
370 | mci = kzalloc(size, GFP_KERNEL); |
371 | if (mci == NULL) | |
da9bb1d2 AC |
372 | return NULL; |
373 | ||
374 | /* Adjust pointers so they point within the memory we just allocated | |
375 | * rather than an imaginary chunk of memory located at address 0. | |
376 | */ | |
4275be63 | 377 | layer = (struct edac_mc_layer *)(((char *)mci) + ((unsigned long)layer)); |
4275be63 MCC |
378 | for (i = 0; i < n_layers; i++) { |
379 | mci->ce_per_layer[i] = (u32 *)((char *)mci + ((unsigned long)ce_per_layer[i])); | |
380 | mci->ue_per_layer[i] = (u32 *)((char *)mci + ((unsigned long)ue_per_layer[i])); | |
381 | } | |
079708b9 | 382 | pvt = sz_pvt ? (((char *)mci) + ((unsigned long)pvt)) : NULL; |
da9bb1d2 | 383 | |
b8f6f975 | 384 | /* setup index and various internal pointers */ |
4275be63 | 385 | mci->mc_idx = mc_num; |
4275be63 | 386 | mci->tot_dimms = tot_dimms; |
da9bb1d2 | 387 | mci->pvt_info = pvt; |
4275be63 MCC |
388 | mci->n_layers = n_layers; |
389 | mci->layers = layer; | |
390 | memcpy(mci->layers, layers, sizeof(*layer) * n_layers); | |
391 | mci->nr_csrows = tot_csrows; | |
392 | mci->num_cschannel = tot_channels; | |
9713faec | 393 | mci->csbased = per_rank; |
da9bb1d2 | 394 | |
a7d7d2e1 | 395 | /* |
de3910eb | 396 | * Alocate and fill the csrow/channels structs |
a7d7d2e1 | 397 | */ |
d3d09e18 | 398 | mci->csrows = kcalloc(tot_csrows, sizeof(*mci->csrows), GFP_KERNEL); |
de3910eb MCC |
399 | if (!mci->csrows) |
400 | goto error; | |
4275be63 | 401 | for (row = 0; row < tot_csrows; row++) { |
de3910eb MCC |
402 | csr = kzalloc(sizeof(**mci->csrows), GFP_KERNEL); |
403 | if (!csr) | |
404 | goto error; | |
405 | mci->csrows[row] = csr; | |
4275be63 MCC |
406 | csr->csrow_idx = row; |
407 | csr->mci = mci; | |
408 | csr->nr_channels = tot_channels; | |
d3d09e18 | 409 | csr->channels = kcalloc(tot_channels, sizeof(*csr->channels), |
de3910eb MCC |
410 | GFP_KERNEL); |
411 | if (!csr->channels) | |
412 | goto error; | |
4275be63 MCC |
413 | |
414 | for (chn = 0; chn < tot_channels; chn++) { | |
de3910eb MCC |
415 | chan = kzalloc(sizeof(**csr->channels), GFP_KERNEL); |
416 | if (!chan) | |
417 | goto error; | |
418 | csr->channels[chn] = chan; | |
da9bb1d2 | 419 | chan->chan_idx = chn; |
4275be63 MCC |
420 | chan->csrow = csr; |
421 | } | |
422 | } | |
423 | ||
424 | /* | |
de3910eb | 425 | * Allocate and fill the dimm structs |
4275be63 | 426 | */ |
d3d09e18 | 427 | mci->dimms = kcalloc(tot_dimms, sizeof(*mci->dimms), GFP_KERNEL); |
de3910eb MCC |
428 | if (!mci->dimms) |
429 | goto error; | |
430 | ||
4275be63 MCC |
431 | memset(&pos, 0, sizeof(pos)); |
432 | row = 0; | |
433 | chn = 0; | |
977b1ce7 | 434 | for (idx = 0; idx < tot_dimms; idx++) { |
de3910eb | 435 | chan = mci->csrows[row]->channels[chn]; |
4275be63 | 436 | |
de3910eb | 437 | dimm = kzalloc(sizeof(**mci->dimms), GFP_KERNEL); |
08a4a136 DC |
438 | if (!dimm) |
439 | goto error; | |
977b1ce7 | 440 | mci->dimms[idx] = dimm; |
4275be63 | 441 | dimm->mci = mci; |
977b1ce7 | 442 | dimm->idx = idx; |
4275be63 | 443 | |
5926ff50 MCC |
444 | /* |
445 | * Copy DIMM location and initialize it. | |
446 | */ | |
447 | len = sizeof(dimm->label); | |
448 | p = dimm->label; | |
449 | n = snprintf(p, len, "mc#%u", mc_num); | |
450 | p += n; | |
451 | len -= n; | |
452 | for (j = 0; j < n_layers; j++) { | |
453 | n = snprintf(p, len, "%s#%u", | |
454 | edac_layer_name[layers[j].type], | |
455 | pos[j]); | |
456 | p += n; | |
457 | len -= n; | |
4275be63 MCC |
458 | dimm->location[j] = pos[j]; |
459 | ||
5926ff50 MCC |
460 | if (len <= 0) |
461 | break; | |
462 | } | |
463 | ||
4275be63 MCC |
464 | /* Link it to the csrows old API data */ |
465 | chan->dimm = dimm; | |
466 | dimm->csrow = row; | |
467 | dimm->cschannel = chn; | |
468 | ||
469 | /* Increment csrow location */ | |
24bef66e | 470 | if (layers[0].is_virt_csrow) { |
4275be63 | 471 | chn++; |
24bef66e MCC |
472 | if (chn == tot_channels) { |
473 | chn = 0; | |
474 | row++; | |
475 | } | |
476 | } else { | |
477 | row++; | |
478 | if (row == tot_csrows) { | |
479 | row = 0; | |
480 | chn++; | |
481 | } | |
4275be63 | 482 | } |
a7d7d2e1 | 483 | |
4275be63 MCC |
484 | /* Increment dimm location */ |
485 | for (j = n_layers - 1; j >= 0; j--) { | |
486 | pos[j]++; | |
487 | if (pos[j] < layers[j].size) | |
488 | break; | |
489 | pos[j] = 0; | |
da9bb1d2 AC |
490 | } |
491 | } | |
492 | ||
81d87cb1 | 493 | mci->op_state = OP_ALLOC; |
8096cfaf | 494 | |
da9bb1d2 | 495 | return mci; |
de3910eb MCC |
496 | |
497 | error: | |
faa2ad09 | 498 | _edac_mc_free(mci); |
de3910eb MCC |
499 | |
500 | return NULL; | |
4275be63 | 501 | } |
9110540f | 502 | EXPORT_SYMBOL_GPL(edac_mc_alloc); |
da9bb1d2 | 503 | |
da9bb1d2 AC |
504 | void edac_mc_free(struct mem_ctl_info *mci) |
505 | { | |
956b9ba1 | 506 | edac_dbg(1, "\n"); |
bbc560ae | 507 | |
faa2ad09 SR |
508 | /* If we're not yet registered with sysfs free only what was allocated |
509 | * in edac_mc_alloc(). | |
510 | */ | |
511 | if (!device_is_registered(&mci->dev)) { | |
512 | _edac_mc_free(mci); | |
513 | return; | |
514 | } | |
515 | ||
de3910eb | 516 | /* the mci instance is freed here, when the sysfs object is dropped */ |
7a623c03 | 517 | edac_unregister_sysfs(mci); |
da9bb1d2 | 518 | } |
9110540f | 519 | EXPORT_SYMBOL_GPL(edac_mc_free); |
da9bb1d2 | 520 | |
d7fc9d77 YG |
521 | bool edac_has_mcs(void) |
522 | { | |
523 | bool ret; | |
524 | ||
525 | mutex_lock(&mem_ctls_mutex); | |
526 | ||
527 | ret = list_empty(&mc_devices); | |
528 | ||
529 | mutex_unlock(&mem_ctls_mutex); | |
530 | ||
531 | return !ret; | |
532 | } | |
533 | EXPORT_SYMBOL_GPL(edac_has_mcs); | |
534 | ||
c73e8833 BP |
535 | /* Caller must hold mem_ctls_mutex */ |
536 | static struct mem_ctl_info *__find_mci_by_dev(struct device *dev) | |
da9bb1d2 AC |
537 | { |
538 | struct mem_ctl_info *mci; | |
539 | struct list_head *item; | |
540 | ||
956b9ba1 | 541 | edac_dbg(3, "\n"); |
da9bb1d2 AC |
542 | |
543 | list_for_each(item, &mc_devices) { | |
544 | mci = list_entry(item, struct mem_ctl_info, link); | |
545 | ||
fd687502 | 546 | if (mci->pdev == dev) |
da9bb1d2 AC |
547 | return mci; |
548 | } | |
549 | ||
550 | return NULL; | |
551 | } | |
c73e8833 BP |
552 | |
553 | /** | |
554 | * find_mci_by_dev | |
555 | * | |
556 | * scan list of controllers looking for the one that manages | |
557 | * the 'dev' device | |
558 | * @dev: pointer to a struct device related with the MCI | |
559 | */ | |
560 | struct mem_ctl_info *find_mci_by_dev(struct device *dev) | |
561 | { | |
562 | struct mem_ctl_info *ret; | |
563 | ||
564 | mutex_lock(&mem_ctls_mutex); | |
565 | ret = __find_mci_by_dev(dev); | |
566 | mutex_unlock(&mem_ctls_mutex); | |
567 | ||
568 | return ret; | |
569 | } | |
939747bd | 570 | EXPORT_SYMBOL_GPL(find_mci_by_dev); |
da9bb1d2 | 571 | |
81d87cb1 DJ |
572 | /* |
573 | * edac_mc_workq_function | |
574 | * performs the operation scheduled by a workq request | |
575 | */ | |
81d87cb1 DJ |
576 | static void edac_mc_workq_function(struct work_struct *work_req) |
577 | { | |
fbeb4384 | 578 | struct delayed_work *d_work = to_delayed_work(work_req); |
81d87cb1 | 579 | struct mem_ctl_info *mci = to_edac_mem_ctl_work(d_work); |
81d87cb1 DJ |
580 | |
581 | mutex_lock(&mem_ctls_mutex); | |
582 | ||
06e912d4 | 583 | if (mci->op_state != OP_RUNNING_POLL) { |
bf52fa4a DT |
584 | mutex_unlock(&mem_ctls_mutex); |
585 | return; | |
586 | } | |
587 | ||
d3116a08 | 588 | if (edac_op_state == EDAC_OPSTATE_POLL) |
81d87cb1 DJ |
589 | mci->edac_check(mci); |
590 | ||
81d87cb1 DJ |
591 | mutex_unlock(&mem_ctls_mutex); |
592 | ||
06e912d4 | 593 | /* Queue ourselves again. */ |
c4cf3b45 | 594 | edac_queue_work(&mci->work, msecs_to_jiffies(edac_mc_get_poll_msec())); |
81d87cb1 DJ |
595 | } |
596 | ||
81d87cb1 | 597 | /* |
bce19683 DT |
598 | * edac_mc_reset_delay_period(unsigned long value) |
599 | * | |
600 | * user space has updated our poll period value, need to | |
601 | * reset our workq delays | |
81d87cb1 | 602 | */ |
9da21b15 | 603 | void edac_mc_reset_delay_period(unsigned long value) |
81d87cb1 | 604 | { |
bce19683 DT |
605 | struct mem_ctl_info *mci; |
606 | struct list_head *item; | |
607 | ||
608 | mutex_lock(&mem_ctls_mutex); | |
609 | ||
bce19683 DT |
610 | list_for_each(item, &mc_devices) { |
611 | mci = list_entry(item, struct mem_ctl_info, link); | |
612 | ||
fbedcaf4 NK |
613 | if (mci->op_state == OP_RUNNING_POLL) |
614 | edac_mod_work(&mci->work, value); | |
bce19683 | 615 | } |
81d87cb1 DJ |
616 | mutex_unlock(&mem_ctls_mutex); |
617 | } | |
618 | ||
bce19683 DT |
619 | |
620 | ||
2d7bbb91 DT |
621 | /* Return 0 on success, 1 on failure. |
622 | * Before calling this function, caller must | |
623 | * assign a unique value to mci->mc_idx. | |
bf52fa4a DT |
624 | * |
625 | * locking model: | |
626 | * | |
627 | * called with the mem_ctls_mutex lock held | |
2d7bbb91 | 628 | */ |
079708b9 | 629 | static int add_mc_to_global_list(struct mem_ctl_info *mci) |
da9bb1d2 AC |
630 | { |
631 | struct list_head *item, *insert_before; | |
632 | struct mem_ctl_info *p; | |
da9bb1d2 | 633 | |
2d7bbb91 | 634 | insert_before = &mc_devices; |
da9bb1d2 | 635 | |
c73e8833 | 636 | p = __find_mci_by_dev(mci->pdev); |
bf52fa4a | 637 | if (unlikely(p != NULL)) |
2d7bbb91 | 638 | goto fail0; |
da9bb1d2 | 639 | |
2d7bbb91 DT |
640 | list_for_each(item, &mc_devices) { |
641 | p = list_entry(item, struct mem_ctl_info, link); | |
da9bb1d2 | 642 | |
2d7bbb91 DT |
643 | if (p->mc_idx >= mci->mc_idx) { |
644 | if (unlikely(p->mc_idx == mci->mc_idx)) | |
645 | goto fail1; | |
da9bb1d2 | 646 | |
2d7bbb91 DT |
647 | insert_before = item; |
648 | break; | |
da9bb1d2 | 649 | } |
da9bb1d2 AC |
650 | } |
651 | ||
652 | list_add_tail_rcu(&mci->link, insert_before); | |
653 | return 0; | |
2d7bbb91 | 654 | |
052dfb45 | 655 | fail0: |
2d7bbb91 | 656 | edac_printk(KERN_WARNING, EDAC_MC, |
fd687502 | 657 | "%s (%s) %s %s already assigned %d\n", dev_name(p->pdev), |
17aa7e03 | 658 | edac_dev_name(mci), p->mod_name, p->ctl_name, p->mc_idx); |
2d7bbb91 DT |
659 | return 1; |
660 | ||
052dfb45 | 661 | fail1: |
2d7bbb91 | 662 | edac_printk(KERN_WARNING, EDAC_MC, |
052dfb45 DT |
663 | "bug in low-level driver: attempt to assign\n" |
664 | " duplicate mc_idx %d in %s()\n", p->mc_idx, __func__); | |
2d7bbb91 | 665 | return 1; |
da9bb1d2 AC |
666 | } |
667 | ||
80cc7d87 | 668 | static int del_mc_from_global_list(struct mem_ctl_info *mci) |
a1d03fcc DP |
669 | { |
670 | list_del_rcu(&mci->link); | |
e2e77098 LJ |
671 | |
672 | /* these are for safe removal of devices from global list while | |
673 | * NMI handlers may be traversing list | |
674 | */ | |
675 | synchronize_rcu(); | |
676 | INIT_LIST_HEAD(&mci->link); | |
80cc7d87 | 677 | |
97bb6c17 | 678 | return list_empty(&mc_devices); |
a1d03fcc DP |
679 | } |
680 | ||
079708b9 | 681 | struct mem_ctl_info *edac_mc_find(int idx) |
5da0831c | 682 | { |
29a0c843 | 683 | struct mem_ctl_info *mci; |
5da0831c | 684 | struct list_head *item; |
c73e8833 BP |
685 | |
686 | mutex_lock(&mem_ctls_mutex); | |
5da0831c DT |
687 | |
688 | list_for_each(item, &mc_devices) { | |
689 | mci = list_entry(item, struct mem_ctl_info, link); | |
29a0c843 RR |
690 | if (mci->mc_idx == idx) |
691 | goto unlock; | |
5da0831c DT |
692 | } |
693 | ||
29a0c843 | 694 | mci = NULL; |
c73e8833 BP |
695 | unlock: |
696 | mutex_unlock(&mem_ctls_mutex); | |
697 | return mci; | |
5da0831c DT |
698 | } |
699 | EXPORT_SYMBOL(edac_mc_find); | |
700 | ||
3877c7d1 TK |
701 | const char *edac_get_owner(void) |
702 | { | |
703 | return edac_mc_owner; | |
704 | } | |
705 | EXPORT_SYMBOL_GPL(edac_get_owner); | |
da9bb1d2 AC |
706 | |
707 | /* FIXME - should a warning be printed if no error detection? correction? */ | |
4e8d230d TI |
708 | int edac_mc_add_mc_with_groups(struct mem_ctl_info *mci, |
709 | const struct attribute_group **groups) | |
da9bb1d2 | 710 | { |
80cc7d87 | 711 | int ret = -EINVAL; |
956b9ba1 | 712 | edac_dbg(0, "\n"); |
b8f6f975 | 713 | |
da9bb1d2 AC |
714 | #ifdef CONFIG_EDAC_DEBUG |
715 | if (edac_debug_level >= 3) | |
716 | edac_mc_dump_mci(mci); | |
e7ecd891 | 717 | |
da9bb1d2 | 718 | if (edac_debug_level >= 4) { |
c498afaf | 719 | struct dimm_info *dimm; |
da9bb1d2 AC |
720 | int i; |
721 | ||
722 | for (i = 0; i < mci->nr_csrows; i++) { | |
6e84d359 MCC |
723 | struct csrow_info *csrow = mci->csrows[i]; |
724 | u32 nr_pages = 0; | |
da9bb1d2 | 725 | int j; |
e7ecd891 | 726 | |
6e84d359 MCC |
727 | for (j = 0; j < csrow->nr_channels; j++) |
728 | nr_pages += csrow->channels[j]->dimm->nr_pages; | |
729 | if (!nr_pages) | |
730 | continue; | |
731 | edac_mc_dump_csrow(csrow); | |
732 | for (j = 0; j < csrow->nr_channels; j++) | |
733 | if (csrow->channels[j]->dimm->nr_pages) | |
734 | edac_mc_dump_channel(csrow->channels[j]); | |
da9bb1d2 | 735 | } |
c498afaf RR |
736 | |
737 | mci_for_each_dimm(mci, dimm) | |
738 | edac_mc_dump_dimm(dimm); | |
da9bb1d2 AC |
739 | } |
740 | #endif | |
63b7df91 | 741 | mutex_lock(&mem_ctls_mutex); |
da9bb1d2 | 742 | |
80cc7d87 MCC |
743 | if (edac_mc_owner && edac_mc_owner != mci->mod_name) { |
744 | ret = -EPERM; | |
745 | goto fail0; | |
746 | } | |
747 | ||
da9bb1d2 | 748 | if (add_mc_to_global_list(mci)) |
028a7b6d | 749 | goto fail0; |
da9bb1d2 AC |
750 | |
751 | /* set load time so that error rate can be tracked */ | |
752 | mci->start_time = jiffies; | |
753 | ||
861e6ed6 | 754 | mci->bus = edac_get_sysfs_subsys(); |
88d84ac9 | 755 | |
4e8d230d | 756 | if (edac_create_sysfs_mci_device(mci, groups)) { |
9794f33d | 757 | edac_mc_printk(mci, KERN_WARNING, |
052dfb45 | 758 | "failed to create sysfs device\n"); |
9794f33d | 759 | goto fail1; |
760 | } | |
da9bb1d2 | 761 | |
09667606 | 762 | if (mci->edac_check) { |
81d87cb1 DJ |
763 | mci->op_state = OP_RUNNING_POLL; |
764 | ||
626a7a4d BP |
765 | INIT_DELAYED_WORK(&mci->work, edac_mc_workq_function); |
766 | edac_queue_work(&mci->work, msecs_to_jiffies(edac_mc_get_poll_msec())); | |
767 | ||
81d87cb1 DJ |
768 | } else { |
769 | mci->op_state = OP_RUNNING_INTERRUPT; | |
770 | } | |
771 | ||
da9bb1d2 | 772 | /* Report action taken */ |
7270a608 RR |
773 | edac_mc_printk(mci, KERN_INFO, |
774 | "Giving out device to module %s controller %s: DEV %s (%s)\n", | |
775 | mci->mod_name, mci->ctl_name, mci->dev_name, | |
776 | edac_op_state_to_string(mci->op_state)); | |
da9bb1d2 | 777 | |
80cc7d87 MCC |
778 | edac_mc_owner = mci->mod_name; |
779 | ||
63b7df91 | 780 | mutex_unlock(&mem_ctls_mutex); |
028a7b6d | 781 | return 0; |
da9bb1d2 | 782 | |
052dfb45 | 783 | fail1: |
028a7b6d DP |
784 | del_mc_from_global_list(mci); |
785 | ||
052dfb45 | 786 | fail0: |
63b7df91 | 787 | mutex_unlock(&mem_ctls_mutex); |
80cc7d87 | 788 | return ret; |
da9bb1d2 | 789 | } |
4e8d230d | 790 | EXPORT_SYMBOL_GPL(edac_mc_add_mc_with_groups); |
da9bb1d2 | 791 | |
079708b9 | 792 | struct mem_ctl_info *edac_mc_del_mc(struct device *dev) |
da9bb1d2 | 793 | { |
18dbc337 | 794 | struct mem_ctl_info *mci; |
da9bb1d2 | 795 | |
956b9ba1 | 796 | edac_dbg(0, "\n"); |
bf52fa4a | 797 | |
63b7df91 | 798 | mutex_lock(&mem_ctls_mutex); |
18dbc337 | 799 | |
bf52fa4a | 800 | /* find the requested mci struct in the global list */ |
c73e8833 | 801 | mci = __find_mci_by_dev(dev); |
bf52fa4a | 802 | if (mci == NULL) { |
63b7df91 | 803 | mutex_unlock(&mem_ctls_mutex); |
18dbc337 DP |
804 | return NULL; |
805 | } | |
806 | ||
09667606 BP |
807 | /* mark MCI offline: */ |
808 | mci->op_state = OP_OFFLINE; | |
809 | ||
97bb6c17 | 810 | if (del_mc_from_global_list(mci)) |
80cc7d87 | 811 | edac_mc_owner = NULL; |
bf52fa4a | 812 | |
09667606 | 813 | mutex_unlock(&mem_ctls_mutex); |
bb31b312 | 814 | |
09667606 | 815 | if (mci->edac_check) |
626a7a4d | 816 | edac_stop_work(&mci->work); |
bb31b312 BP |
817 | |
818 | /* remove from sysfs */ | |
bf52fa4a DT |
819 | edac_remove_sysfs_mci_device(mci); |
820 | ||
537fba28 | 821 | edac_printk(KERN_INFO, EDAC_MC, |
052dfb45 | 822 | "Removed device %d for %s %s: DEV %s\n", mci->mc_idx, |
17aa7e03 | 823 | mci->mod_name, mci->ctl_name, edac_dev_name(mci)); |
bf52fa4a | 824 | |
18dbc337 | 825 | return mci; |
da9bb1d2 | 826 | } |
9110540f | 827 | EXPORT_SYMBOL_GPL(edac_mc_del_mc); |
da9bb1d2 | 828 | |
2da1c119 AB |
829 | static void edac_mc_scrub_block(unsigned long page, unsigned long offset, |
830 | u32 size) | |
da9bb1d2 AC |
831 | { |
832 | struct page *pg; | |
833 | void *virt_addr; | |
834 | unsigned long flags = 0; | |
835 | ||
956b9ba1 | 836 | edac_dbg(3, "\n"); |
da9bb1d2 AC |
837 | |
838 | /* ECC error page was not in our memory. Ignore it. */ | |
079708b9 | 839 | if (!pfn_valid(page)) |
da9bb1d2 AC |
840 | return; |
841 | ||
842 | /* Find the actual page structure then map it and fix */ | |
843 | pg = pfn_to_page(page); | |
844 | ||
845 | if (PageHighMem(pg)) | |
846 | local_irq_save(flags); | |
847 | ||
4e5df7ca | 848 | virt_addr = kmap_atomic(pg); |
da9bb1d2 AC |
849 | |
850 | /* Perform architecture specific atomic scrub operation */ | |
b01aec9b | 851 | edac_atomic_scrub(virt_addr + offset, size); |
da9bb1d2 AC |
852 | |
853 | /* Unmap and complete */ | |
4e5df7ca | 854 | kunmap_atomic(virt_addr); |
da9bb1d2 AC |
855 | |
856 | if (PageHighMem(pg)) | |
857 | local_irq_restore(flags); | |
858 | } | |
859 | ||
da9bb1d2 | 860 | /* FIXME - should return -1 */ |
e7ecd891 | 861 | int edac_mc_find_csrow_by_page(struct mem_ctl_info *mci, unsigned long page) |
da9bb1d2 | 862 | { |
de3910eb | 863 | struct csrow_info **csrows = mci->csrows; |
a895bf8b | 864 | int row, i, j, n; |
da9bb1d2 | 865 | |
956b9ba1 | 866 | edac_dbg(1, "MC%d: 0x%lx\n", mci->mc_idx, page); |
da9bb1d2 AC |
867 | row = -1; |
868 | ||
869 | for (i = 0; i < mci->nr_csrows; i++) { | |
de3910eb | 870 | struct csrow_info *csrow = csrows[i]; |
a895bf8b MCC |
871 | n = 0; |
872 | for (j = 0; j < csrow->nr_channels; j++) { | |
de3910eb | 873 | struct dimm_info *dimm = csrow->channels[j]->dimm; |
a895bf8b MCC |
874 | n += dimm->nr_pages; |
875 | } | |
876 | if (n == 0) | |
da9bb1d2 AC |
877 | continue; |
878 | ||
956b9ba1 JP |
879 | edac_dbg(3, "MC%d: first(0x%lx) page(0x%lx) last(0x%lx) mask(0x%lx)\n", |
880 | mci->mc_idx, | |
881 | csrow->first_page, page, csrow->last_page, | |
882 | csrow->page_mask); | |
da9bb1d2 AC |
883 | |
884 | if ((page >= csrow->first_page) && | |
885 | (page <= csrow->last_page) && | |
886 | ((page & csrow->page_mask) == | |
887 | (csrow->first_page & csrow->page_mask))) { | |
888 | row = i; | |
889 | break; | |
890 | } | |
891 | } | |
892 | ||
893 | if (row == -1) | |
537fba28 | 894 | edac_mc_printk(mci, KERN_ERR, |
052dfb45 DT |
895 | "could not look up page error address %lx\n", |
896 | (unsigned long)page); | |
da9bb1d2 AC |
897 | |
898 | return row; | |
899 | } | |
9110540f | 900 | EXPORT_SYMBOL_GPL(edac_mc_find_csrow_by_page); |
da9bb1d2 | 901 | |
4275be63 MCC |
902 | const char *edac_layer_name[] = { |
903 | [EDAC_MC_LAYER_BRANCH] = "branch", | |
904 | [EDAC_MC_LAYER_CHANNEL] = "channel", | |
905 | [EDAC_MC_LAYER_SLOT] = "slot", | |
906 | [EDAC_MC_LAYER_CHIP_SELECT] = "csrow", | |
c66b5a79 | 907 | [EDAC_MC_LAYER_ALL_MEM] = "memory", |
4275be63 MCC |
908 | }; |
909 | EXPORT_SYMBOL_GPL(edac_layer_name); | |
910 | ||
911 | static void edac_inc_ce_error(struct mem_ctl_info *mci, | |
9eb07a7f MCC |
912 | bool enable_per_layer_report, |
913 | const int pos[EDAC_MAX_LAYERS], | |
914 | const u16 count) | |
da9bb1d2 | 915 | { |
4275be63 | 916 | int i, index = 0; |
da9bb1d2 | 917 | |
9eb07a7f | 918 | mci->ce_mc += count; |
da9bb1d2 | 919 | |
4275be63 | 920 | if (!enable_per_layer_report) { |
9eb07a7f | 921 | mci->ce_noinfo_count += count; |
da9bb1d2 AC |
922 | return; |
923 | } | |
e7ecd891 | 924 | |
4275be63 MCC |
925 | for (i = 0; i < mci->n_layers; i++) { |
926 | if (pos[i] < 0) | |
927 | break; | |
928 | index += pos[i]; | |
9eb07a7f | 929 | mci->ce_per_layer[i][index] += count; |
4275be63 MCC |
930 | |
931 | if (i < mci->n_layers - 1) | |
932 | index *= mci->layers[i + 1].size; | |
933 | } | |
934 | } | |
935 | ||
936 | static void edac_inc_ue_error(struct mem_ctl_info *mci, | |
937 | bool enable_per_layer_report, | |
9eb07a7f MCC |
938 | const int pos[EDAC_MAX_LAYERS], |
939 | const u16 count) | |
4275be63 MCC |
940 | { |
941 | int i, index = 0; | |
942 | ||
9eb07a7f | 943 | mci->ue_mc += count; |
4275be63 MCC |
944 | |
945 | if (!enable_per_layer_report) { | |
993f88f1 | 946 | mci->ue_noinfo_count += count; |
da9bb1d2 AC |
947 | return; |
948 | } | |
949 | ||
4275be63 MCC |
950 | for (i = 0; i < mci->n_layers; i++) { |
951 | if (pos[i] < 0) | |
952 | break; | |
953 | index += pos[i]; | |
9eb07a7f | 954 | mci->ue_per_layer[i][index] += count; |
a7d7d2e1 | 955 | |
4275be63 MCC |
956 | if (i < mci->n_layers - 1) |
957 | index *= mci->layers[i + 1].size; | |
958 | } | |
959 | } | |
da9bb1d2 | 960 | |
4275be63 | 961 | static void edac_ce_error(struct mem_ctl_info *mci, |
9eb07a7f | 962 | const u16 error_count, |
4275be63 MCC |
963 | const int pos[EDAC_MAX_LAYERS], |
964 | const char *msg, | |
965 | const char *location, | |
966 | const char *label, | |
967 | const char *detail, | |
968 | const char *other_detail, | |
969 | const bool enable_per_layer_report, | |
970 | const unsigned long page_frame_number, | |
971 | const unsigned long offset_in_page, | |
53f2d028 | 972 | long grain) |
4275be63 MCC |
973 | { |
974 | unsigned long remapped_page; | |
f430d570 BP |
975 | char *msg_aux = ""; |
976 | ||
977 | if (*msg) | |
978 | msg_aux = " "; | |
4275be63 MCC |
979 | |
980 | if (edac_mc_get_log_ce()) { | |
981 | if (other_detail && *other_detail) | |
982 | edac_mc_printk(mci, KERN_WARNING, | |
f430d570 BP |
983 | "%d CE %s%son %s (%s %s - %s)\n", |
984 | error_count, msg, msg_aux, label, | |
985 | location, detail, other_detail); | |
4275be63 MCC |
986 | else |
987 | edac_mc_printk(mci, KERN_WARNING, | |
f430d570 BP |
988 | "%d CE %s%son %s (%s %s)\n", |
989 | error_count, msg, msg_aux, label, | |
990 | location, detail); | |
4275be63 | 991 | } |
9eb07a7f | 992 | edac_inc_ce_error(mci, enable_per_layer_report, pos, error_count); |
da9bb1d2 | 993 | |
aa2064d7 | 994 | if (mci->scrub_mode == SCRUB_SW_SRC) { |
da9bb1d2 | 995 | /* |
4275be63 MCC |
996 | * Some memory controllers (called MCs below) can remap |
997 | * memory so that it is still available at a different | |
998 | * address when PCI devices map into memory. | |
999 | * MC's that can't do this, lose the memory where PCI | |
1000 | * devices are mapped. This mapping is MC-dependent | |
1001 | * and so we call back into the MC driver for it to | |
1002 | * map the MC page to a physical (CPU) page which can | |
1003 | * then be mapped to a virtual page - which can then | |
1004 | * be scrubbed. | |
1005 | */ | |
da9bb1d2 | 1006 | remapped_page = mci->ctl_page_to_phys ? |
052dfb45 DT |
1007 | mci->ctl_page_to_phys(mci, page_frame_number) : |
1008 | page_frame_number; | |
da9bb1d2 | 1009 | |
4275be63 MCC |
1010 | edac_mc_scrub_block(remapped_page, |
1011 | offset_in_page, grain); | |
da9bb1d2 AC |
1012 | } |
1013 | } | |
1014 | ||
4275be63 | 1015 | static void edac_ue_error(struct mem_ctl_info *mci, |
9eb07a7f | 1016 | const u16 error_count, |
4275be63 MCC |
1017 | const int pos[EDAC_MAX_LAYERS], |
1018 | const char *msg, | |
1019 | const char *location, | |
1020 | const char *label, | |
1021 | const char *detail, | |
1022 | const char *other_detail, | |
1023 | const bool enable_per_layer_report) | |
da9bb1d2 | 1024 | { |
f430d570 BP |
1025 | char *msg_aux = ""; |
1026 | ||
1027 | if (*msg) | |
1028 | msg_aux = " "; | |
1029 | ||
4275be63 MCC |
1030 | if (edac_mc_get_log_ue()) { |
1031 | if (other_detail && *other_detail) | |
1032 | edac_mc_printk(mci, KERN_WARNING, | |
f430d570 BP |
1033 | "%d UE %s%son %s (%s %s - %s)\n", |
1034 | error_count, msg, msg_aux, label, | |
1035 | location, detail, other_detail); | |
4275be63 MCC |
1036 | else |
1037 | edac_mc_printk(mci, KERN_WARNING, | |
f430d570 BP |
1038 | "%d UE %s%son %s (%s %s)\n", |
1039 | error_count, msg, msg_aux, label, | |
1040 | location, detail); | |
4275be63 | 1041 | } |
e7ecd891 | 1042 | |
4275be63 MCC |
1043 | if (edac_mc_get_panic_on_ue()) { |
1044 | if (other_detail && *other_detail) | |
f430d570 BP |
1045 | panic("UE %s%son %s (%s%s - %s)\n", |
1046 | msg, msg_aux, label, location, detail, other_detail); | |
4275be63 | 1047 | else |
f430d570 BP |
1048 | panic("UE %s%son %s (%s%s)\n", |
1049 | msg, msg_aux, label, location, detail); | |
4275be63 MCC |
1050 | } |
1051 | ||
9eb07a7f | 1052 | edac_inc_ue_error(mci, enable_per_layer_report, pos, error_count); |
da9bb1d2 AC |
1053 | } |
1054 | ||
e7e24830 MCC |
1055 | void edac_raw_mc_handle_error(const enum hw_event_mc_err_type type, |
1056 | struct mem_ctl_info *mci, | |
1057 | struct edac_raw_error_desc *e) | |
1058 | { | |
1059 | char detail[80]; | |
1060 | int pos[EDAC_MAX_LAYERS] = { e->top_layer, e->mid_layer, e->low_layer }; | |
1061 | ||
1062 | /* Memory type dependent details about the error */ | |
1063 | if (type == HW_EVENT_ERR_CORRECTED) { | |
1064 | snprintf(detail, sizeof(detail), | |
1065 | "page:0x%lx offset:0x%lx grain:%ld syndrome:0x%lx", | |
1066 | e->page_frame_number, e->offset_in_page, | |
1067 | e->grain, e->syndrome); | |
1068 | edac_ce_error(mci, e->error_count, pos, e->msg, e->location, e->label, | |
1069 | detail, e->other_detail, e->enable_per_layer_report, | |
1070 | e->page_frame_number, e->offset_in_page, e->grain); | |
1071 | } else { | |
1072 | snprintf(detail, sizeof(detail), | |
1073 | "page:0x%lx offset:0x%lx grain:%ld", | |
1074 | e->page_frame_number, e->offset_in_page, e->grain); | |
1075 | ||
1076 | edac_ue_error(mci, e->error_count, pos, e->msg, e->location, e->label, | |
1077 | detail, e->other_detail, e->enable_per_layer_report); | |
1078 | } | |
1079 | ||
1080 | ||
1081 | } | |
1082 | EXPORT_SYMBOL_GPL(edac_raw_mc_handle_error); | |
53f2d028 | 1083 | |
4275be63 MCC |
1084 | void edac_mc_handle_error(const enum hw_event_mc_err_type type, |
1085 | struct mem_ctl_info *mci, | |
9eb07a7f | 1086 | const u16 error_count, |
4275be63 MCC |
1087 | const unsigned long page_frame_number, |
1088 | const unsigned long offset_in_page, | |
1089 | const unsigned long syndrome, | |
53f2d028 MCC |
1090 | const int top_layer, |
1091 | const int mid_layer, | |
1092 | const int low_layer, | |
4275be63 | 1093 | const char *msg, |
03f7eae8 | 1094 | const char *other_detail) |
da9bb1d2 | 1095 | { |
c498afaf | 1096 | struct dimm_info *dimm; |
4275be63 MCC |
1097 | char *p; |
1098 | int row = -1, chan = -1; | |
53f2d028 | 1099 | int pos[EDAC_MAX_LAYERS] = { top_layer, mid_layer, low_layer }; |
c7ef7645 | 1100 | int i, n_labels = 0; |
53f2d028 | 1101 | u8 grain_bits; |
c7ef7645 | 1102 | struct edac_raw_error_desc *e = &mci->error_desc; |
da9bb1d2 | 1103 | |
956b9ba1 | 1104 | edac_dbg(3, "MC%d\n", mci->mc_idx); |
da9bb1d2 | 1105 | |
c7ef7645 MCC |
1106 | /* Fills the error report buffer */ |
1107 | memset(e, 0, sizeof (*e)); | |
1108 | e->error_count = error_count; | |
1109 | e->top_layer = top_layer; | |
1110 | e->mid_layer = mid_layer; | |
1111 | e->low_layer = low_layer; | |
1112 | e->page_frame_number = page_frame_number; | |
1113 | e->offset_in_page = offset_in_page; | |
1114 | e->syndrome = syndrome; | |
1115 | e->msg = msg; | |
1116 | e->other_detail = other_detail; | |
1117 | ||
4275be63 MCC |
1118 | /* |
1119 | * Check if the event report is consistent and if the memory | |
1120 | * location is known. If it is known, enable_per_layer_report will be | |
1121 | * true, the DIMM(s) label info will be filled and the per-layer | |
1122 | * error counters will be incremented. | |
1123 | */ | |
1124 | for (i = 0; i < mci->n_layers; i++) { | |
1125 | if (pos[i] >= (int)mci->layers[i].size) { | |
4275be63 MCC |
1126 | |
1127 | edac_mc_printk(mci, KERN_ERR, | |
1128 | "INTERNAL ERROR: %s value is out of range (%d >= %d)\n", | |
1129 | edac_layer_name[mci->layers[i].type], | |
1130 | pos[i], mci->layers[i].size); | |
1131 | /* | |
1132 | * Instead of just returning it, let's use what's | |
1133 | * known about the error. The increment routines and | |
1134 | * the DIMM filter logic will do the right thing by | |
1135 | * pointing the likely damaged DIMMs. | |
1136 | */ | |
1137 | pos[i] = -1; | |
1138 | } | |
1139 | if (pos[i] >= 0) | |
c7ef7645 | 1140 | e->enable_per_layer_report = true; |
da9bb1d2 AC |
1141 | } |
1142 | ||
4275be63 MCC |
1143 | /* |
1144 | * Get the dimm label/grain that applies to the match criteria. | |
1145 | * As the error algorithm may not be able to point to just one memory | |
1146 | * stick, the logic here will get all possible labels that could | |
1147 | * pottentially be affected by the error. | |
1148 | * On FB-DIMM memory controllers, for uncorrected errors, it is common | |
1149 | * to have only the MC channel and the MC dimm (also called "branch") | |
1150 | * but the channel is not known, as the memory is arranged in pairs, | |
1151 | * where each memory belongs to a separate channel within the same | |
1152 | * branch. | |
1153 | */ | |
c7ef7645 | 1154 | p = e->label; |
4275be63 | 1155 | *p = '\0'; |
4da1b7bf | 1156 | |
c498afaf | 1157 | mci_for_each_dimm(mci, dimm) { |
53f2d028 | 1158 | if (top_layer >= 0 && top_layer != dimm->location[0]) |
4275be63 | 1159 | continue; |
53f2d028 | 1160 | if (mid_layer >= 0 && mid_layer != dimm->location[1]) |
4275be63 | 1161 | continue; |
53f2d028 | 1162 | if (low_layer >= 0 && low_layer != dimm->location[2]) |
4275be63 | 1163 | continue; |
da9bb1d2 | 1164 | |
4275be63 | 1165 | /* get the max grain, over the error match range */ |
c7ef7645 MCC |
1166 | if (dimm->grain > e->grain) |
1167 | e->grain = dimm->grain; | |
9794f33d | 1168 | |
4275be63 MCC |
1169 | /* |
1170 | * If the error is memory-controller wide, there's no need to | |
1171 | * seek for the affected DIMMs because the whole | |
1172 | * channel/memory controller/... may be affected. | |
1173 | * Also, don't show errors for empty DIMM slots. | |
1174 | */ | |
0d8292e0 RR |
1175 | if (!e->enable_per_layer_report || !dimm->nr_pages) |
1176 | continue; | |
4275be63 | 1177 | |
0d8292e0 RR |
1178 | if (n_labels >= EDAC_MAX_LABELS) { |
1179 | e->enable_per_layer_report = false; | |
1180 | break; | |
1181 | } | |
1182 | n_labels++; | |
1183 | if (p != e->label) { | |
1184 | strcpy(p, OTHER_LABEL); | |
1185 | p += strlen(OTHER_LABEL); | |
4275be63 | 1186 | } |
0d8292e0 RR |
1187 | strcpy(p, dimm->label); |
1188 | p += strlen(p); | |
1189 | ||
1190 | /* | |
1191 | * get csrow/channel of the DIMM, in order to allow | |
1192 | * incrementing the compat API counters | |
1193 | */ | |
1194 | edac_dbg(4, "%s csrows map: (%d,%d)\n", | |
1195 | mci->csbased ? "rank" : "dimm", | |
1196 | dimm->csrow, dimm->cschannel); | |
1197 | if (row == -1) | |
1198 | row = dimm->csrow; | |
1199 | else if (row >= 0 && row != dimm->csrow) | |
1200 | row = -2; | |
1201 | ||
1202 | if (chan == -1) | |
1203 | chan = dimm->cschannel; | |
1204 | else if (chan >= 0 && chan != dimm->cschannel) | |
1205 | chan = -2; | |
9794f33d | 1206 | } |
1207 | ||
c7ef7645 MCC |
1208 | if (!e->enable_per_layer_report) { |
1209 | strcpy(e->label, "any memory"); | |
4275be63 | 1210 | } else { |
956b9ba1 | 1211 | edac_dbg(4, "csrow/channel to increment: (%d,%d)\n", row, chan); |
c7ef7645 MCC |
1212 | if (p == e->label) |
1213 | strcpy(e->label, "unknown memory"); | |
4275be63 MCC |
1214 | if (type == HW_EVENT_ERR_CORRECTED) { |
1215 | if (row >= 0) { | |
9eb07a7f | 1216 | mci->csrows[row]->ce_count += error_count; |
4275be63 | 1217 | if (chan >= 0) |
9eb07a7f | 1218 | mci->csrows[row]->channels[chan]->ce_count += error_count; |
4275be63 MCC |
1219 | } |
1220 | } else | |
1221 | if (row >= 0) | |
9eb07a7f | 1222 | mci->csrows[row]->ue_count += error_count; |
9794f33d | 1223 | } |
1224 | ||
4275be63 | 1225 | /* Fill the RAM location data */ |
c7ef7645 | 1226 | p = e->location; |
4da1b7bf | 1227 | |
4275be63 MCC |
1228 | for (i = 0; i < mci->n_layers; i++) { |
1229 | if (pos[i] < 0) | |
1230 | continue; | |
9794f33d | 1231 | |
4275be63 MCC |
1232 | p += sprintf(p, "%s:%d ", |
1233 | edac_layer_name[mci->layers[i].type], | |
1234 | pos[i]); | |
9794f33d | 1235 | } |
c7ef7645 | 1236 | if (p > e->location) |
53f2d028 MCC |
1237 | *(p - 1) = '\0'; |
1238 | ||
3724ace5 RR |
1239 | /* Sanity-check driver-supplied grain value. */ |
1240 | if (WARN_ON_ONCE(!e->grain)) | |
1241 | e->grain = 1; | |
1242 | ||
1243 | grain_bits = fls_long(e->grain - 1); | |
be1d1629 | 1244 | |
3724ace5 | 1245 | /* Report the error via the trace interface */ |
be1d1629 BP |
1246 | if (IS_ENABLED(CONFIG_RAS)) |
1247 | trace_mc_event(type, e->msg, e->label, e->error_count, | |
1248 | mci->mc_idx, e->top_layer, e->mid_layer, | |
1249 | e->low_layer, | |
1250 | (e->page_frame_number << PAGE_SHIFT) | e->offset_in_page, | |
1251 | grain_bits, e->syndrome, e->other_detail); | |
a7d7d2e1 | 1252 | |
e7e24830 | 1253 | edac_raw_mc_handle_error(type, mci, e); |
9794f33d | 1254 | } |
4275be63 | 1255 | EXPORT_SYMBOL_GPL(edac_mc_handle_error); |