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Commit | Line | Data |
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da9bb1d2 AC |
1 | /* |
2 | * edac_mc kernel module | |
49c0dab7 | 3 | * (C) 2005, 2006 Linux Networx (http://lnxi.com) |
da9bb1d2 AC |
4 | * This file may be distributed under the terms of the |
5 | * GNU General Public License. | |
6 | * | |
7 | * Written by Thayne Harbaugh | |
8 | * Based on work by Dan Hollis <goemon at anime dot net> and others. | |
9 | * http://www.anime.net/~goemon/linux-ecc/ | |
10 | * | |
11 | * Modified by Dave Peterson and Doug Thompson | |
12 | * | |
13 | */ | |
14 | ||
da9bb1d2 AC |
15 | #include <linux/module.h> |
16 | #include <linux/proc_fs.h> | |
17 | #include <linux/kernel.h> | |
18 | #include <linux/types.h> | |
19 | #include <linux/smp.h> | |
20 | #include <linux/init.h> | |
21 | #include <linux/sysctl.h> | |
22 | #include <linux/highmem.h> | |
23 | #include <linux/timer.h> | |
24 | #include <linux/slab.h> | |
25 | #include <linux/jiffies.h> | |
26 | #include <linux/spinlock.h> | |
27 | #include <linux/list.h> | |
da9bb1d2 | 28 | #include <linux/ctype.h> |
c0d12172 | 29 | #include <linux/edac.h> |
53f2d028 | 30 | #include <linux/bitops.h> |
7c0f6ba6 | 31 | #include <linux/uaccess.h> |
da9bb1d2 | 32 | #include <asm/page.h> |
78d88e8a | 33 | #include "edac_mc.h" |
7c9281d7 | 34 | #include "edac_module.h" |
53f2d028 MCC |
35 | #include <ras/ras_event.h> |
36 | ||
b01aec9b BP |
37 | #ifdef CONFIG_EDAC_ATOMIC_SCRUB |
38 | #include <asm/edac.h> | |
39 | #else | |
40 | #define edac_atomic_scrub(va, size) do { } while (0) | |
41 | #endif | |
42 | ||
da9bb1d2 | 43 | /* lock to memory controller's control array */ |
63b7df91 | 44 | static DEFINE_MUTEX(mem_ctls_mutex); |
ff6ac2a6 | 45 | static LIST_HEAD(mc_devices); |
da9bb1d2 | 46 | |
80cc7d87 MCC |
47 | /* |
48 | * Used to lock EDAC MC to just one module, avoiding two drivers e. g. | |
49 | * apei/ghes and i7core_edac to be used at the same time. | |
50 | */ | |
51 | static void const *edac_mc_owner; | |
52 | ||
88d84ac9 BP |
53 | static struct bus_type mc_bus[EDAC_MAX_MCS]; |
54 | ||
6e84d359 MCC |
55 | unsigned edac_dimm_info_location(struct dimm_info *dimm, char *buf, |
56 | unsigned len) | |
57 | { | |
58 | struct mem_ctl_info *mci = dimm->mci; | |
59 | int i, n, count = 0; | |
60 | char *p = buf; | |
61 | ||
62 | for (i = 0; i < mci->n_layers; i++) { | |
63 | n = snprintf(p, len, "%s %d ", | |
64 | edac_layer_name[mci->layers[i].type], | |
65 | dimm->location[i]); | |
66 | p += n; | |
67 | len -= n; | |
68 | count += n; | |
69 | if (!len) | |
70 | break; | |
71 | } | |
72 | ||
73 | return count; | |
74 | } | |
75 | ||
da9bb1d2 AC |
76 | #ifdef CONFIG_EDAC_DEBUG |
77 | ||
a4b4be3f | 78 | static void edac_mc_dump_channel(struct rank_info *chan) |
da9bb1d2 | 79 | { |
6e84d359 MCC |
80 | edac_dbg(4, " channel->chan_idx = %d\n", chan->chan_idx); |
81 | edac_dbg(4, " channel = %p\n", chan); | |
82 | edac_dbg(4, " channel->csrow = %p\n", chan->csrow); | |
83 | edac_dbg(4, " channel->dimm = %p\n", chan->dimm); | |
4275be63 MCC |
84 | } |
85 | ||
6e84d359 | 86 | static void edac_mc_dump_dimm(struct dimm_info *dimm, int number) |
4275be63 | 87 | { |
6e84d359 MCC |
88 | char location[80]; |
89 | ||
90 | edac_dimm_info_location(dimm, location, sizeof(location)); | |
91 | ||
92 | edac_dbg(4, "%s%i: %smapped as virtual row %d, chan %d\n", | |
9713faec | 93 | dimm->mci->csbased ? "rank" : "dimm", |
6e84d359 MCC |
94 | number, location, dimm->csrow, dimm->cschannel); |
95 | edac_dbg(4, " dimm = %p\n", dimm); | |
96 | edac_dbg(4, " dimm->label = '%s'\n", dimm->label); | |
97 | edac_dbg(4, " dimm->nr_pages = 0x%x\n", dimm->nr_pages); | |
98 | edac_dbg(4, " dimm->grain = %d\n", dimm->grain); | |
99 | edac_dbg(4, " dimm->nr_pages = 0x%x\n", dimm->nr_pages); | |
da9bb1d2 AC |
100 | } |
101 | ||
2da1c119 | 102 | static void edac_mc_dump_csrow(struct csrow_info *csrow) |
da9bb1d2 | 103 | { |
6e84d359 MCC |
104 | edac_dbg(4, "csrow->csrow_idx = %d\n", csrow->csrow_idx); |
105 | edac_dbg(4, " csrow = %p\n", csrow); | |
106 | edac_dbg(4, " csrow->first_page = 0x%lx\n", csrow->first_page); | |
107 | edac_dbg(4, " csrow->last_page = 0x%lx\n", csrow->last_page); | |
108 | edac_dbg(4, " csrow->page_mask = 0x%lx\n", csrow->page_mask); | |
109 | edac_dbg(4, " csrow->nr_channels = %d\n", csrow->nr_channels); | |
110 | edac_dbg(4, " csrow->channels = %p\n", csrow->channels); | |
111 | edac_dbg(4, " csrow->mci = %p\n", csrow->mci); | |
da9bb1d2 AC |
112 | } |
113 | ||
2da1c119 | 114 | static void edac_mc_dump_mci(struct mem_ctl_info *mci) |
da9bb1d2 | 115 | { |
956b9ba1 JP |
116 | edac_dbg(3, "\tmci = %p\n", mci); |
117 | edac_dbg(3, "\tmci->mtype_cap = %lx\n", mci->mtype_cap); | |
118 | edac_dbg(3, "\tmci->edac_ctl_cap = %lx\n", mci->edac_ctl_cap); | |
119 | edac_dbg(3, "\tmci->edac_cap = %lx\n", mci->edac_cap); | |
120 | edac_dbg(4, "\tmci->edac_check = %p\n", mci->edac_check); | |
121 | edac_dbg(3, "\tmci->nr_csrows = %d, csrows = %p\n", | |
122 | mci->nr_csrows, mci->csrows); | |
123 | edac_dbg(3, "\tmci->nr_dimms = %d, dimms = %p\n", | |
124 | mci->tot_dimms, mci->dimms); | |
125 | edac_dbg(3, "\tdev = %p\n", mci->pdev); | |
126 | edac_dbg(3, "\tmod_name:ctl_name = %s:%s\n", | |
127 | mci->mod_name, mci->ctl_name); | |
128 | edac_dbg(3, "\tpvt_info = %p\n\n", mci->pvt_info); | |
da9bb1d2 AC |
129 | } |
130 | ||
24f9a7fe BP |
131 | #endif /* CONFIG_EDAC_DEBUG */ |
132 | ||
f4ce6eca | 133 | const char * const edac_mem_types[] = { |
4cfc3a40 BP |
134 | [MEM_EMPTY] = "Empty csrow", |
135 | [MEM_RESERVED] = "Reserved csrow type", | |
136 | [MEM_UNKNOWN] = "Unknown csrow type", | |
137 | [MEM_FPM] = "Fast page mode RAM", | |
138 | [MEM_EDO] = "Extended data out RAM", | |
139 | [MEM_BEDO] = "Burst Extended data out RAM", | |
140 | [MEM_SDR] = "Single data rate SDRAM", | |
141 | [MEM_RDR] = "Registered single data rate SDRAM", | |
142 | [MEM_DDR] = "Double data rate SDRAM", | |
143 | [MEM_RDDR] = "Registered Double data rate SDRAM", | |
144 | [MEM_RMBS] = "Rambus DRAM", | |
145 | [MEM_DDR2] = "Unbuffered DDR2 RAM", | |
146 | [MEM_FB_DDR2] = "Fully buffered DDR2", | |
147 | [MEM_RDDR2] = "Registered DDR2 RAM", | |
148 | [MEM_XDR] = "Rambus XDR", | |
149 | [MEM_DDR3] = "Unbuffered DDR3 RAM", | |
150 | [MEM_RDDR3] = "Registered DDR3 RAM", | |
151 | [MEM_LRDDR3] = "Load-Reduced DDR3 RAM", | |
152 | [MEM_DDR4] = "Unbuffered DDR4 RAM", | |
153 | [MEM_RDDR4] = "Registered DDR4 RAM", | |
239642fe BP |
154 | }; |
155 | EXPORT_SYMBOL_GPL(edac_mem_types); | |
156 | ||
93e4fe64 MCC |
157 | /** |
158 | * edac_align_ptr - Prepares the pointer offsets for a single-shot allocation | |
159 | * @p: pointer to a pointer with the memory offset to be used. At | |
160 | * return, this will be incremented to point to the next offset | |
161 | * @size: Size of the data structure to be reserved | |
162 | * @n_elems: Number of elements that should be reserved | |
da9bb1d2 AC |
163 | * |
164 | * If 'size' is a constant, the compiler will optimize this whole function | |
93e4fe64 MCC |
165 | * down to either a no-op or the addition of a constant to the value of '*p'. |
166 | * | |
167 | * The 'p' pointer is absolutely needed to keep the proper advancing | |
168 | * further in memory to the proper offsets when allocating the struct along | |
169 | * with its embedded structs, as edac_device_alloc_ctl_info() does it | |
170 | * above, for example. | |
171 | * | |
172 | * At return, the pointer 'p' will be incremented to be used on a next call | |
173 | * to this function. | |
da9bb1d2 | 174 | */ |
93e4fe64 | 175 | void *edac_align_ptr(void **p, unsigned size, int n_elems) |
da9bb1d2 AC |
176 | { |
177 | unsigned align, r; | |
93e4fe64 | 178 | void *ptr = *p; |
da9bb1d2 | 179 | |
93e4fe64 MCC |
180 | *p += size * n_elems; |
181 | ||
182 | /* | |
183 | * 'p' can possibly be an unaligned item X such that sizeof(X) is | |
184 | * 'size'. Adjust 'p' so that its alignment is at least as | |
185 | * stringent as what the compiler would provide for X and return | |
186 | * the aligned result. | |
187 | * Here we assume that the alignment of a "long long" is the most | |
da9bb1d2 AC |
188 | * stringent alignment that the compiler will ever provide by default. |
189 | * As far as I know, this is a reasonable assumption. | |
190 | */ | |
191 | if (size > sizeof(long)) | |
192 | align = sizeof(long long); | |
193 | else if (size > sizeof(int)) | |
194 | align = sizeof(long); | |
195 | else if (size > sizeof(short)) | |
196 | align = sizeof(int); | |
197 | else if (size > sizeof(char)) | |
198 | align = sizeof(short); | |
199 | else | |
079708b9 | 200 | return (char *)ptr; |
da9bb1d2 | 201 | |
8447c4d1 | 202 | r = (unsigned long)p % align; |
da9bb1d2 AC |
203 | |
204 | if (r == 0) | |
079708b9 | 205 | return (char *)ptr; |
da9bb1d2 | 206 | |
93e4fe64 MCC |
207 | *p += align - r; |
208 | ||
7391c6dc | 209 | return (void *)(((unsigned long)ptr) + align - r); |
da9bb1d2 AC |
210 | } |
211 | ||
faa2ad09 SR |
212 | static void _edac_mc_free(struct mem_ctl_info *mci) |
213 | { | |
214 | int i, chn, row; | |
215 | struct csrow_info *csr; | |
216 | const unsigned int tot_dimms = mci->tot_dimms; | |
217 | const unsigned int tot_channels = mci->num_cschannel; | |
218 | const unsigned int tot_csrows = mci->nr_csrows; | |
219 | ||
220 | if (mci->dimms) { | |
221 | for (i = 0; i < tot_dimms; i++) | |
222 | kfree(mci->dimms[i]); | |
223 | kfree(mci->dimms); | |
224 | } | |
225 | if (mci->csrows) { | |
226 | for (row = 0; row < tot_csrows; row++) { | |
227 | csr = mci->csrows[row]; | |
228 | if (csr) { | |
229 | if (csr->channels) { | |
230 | for (chn = 0; chn < tot_channels; chn++) | |
231 | kfree(csr->channels[chn]); | |
232 | kfree(csr->channels); | |
233 | } | |
234 | kfree(csr); | |
235 | } | |
236 | } | |
237 | kfree(mci->csrows); | |
238 | } | |
239 | kfree(mci); | |
240 | } | |
241 | ||
ca0907b9 MCC |
242 | struct mem_ctl_info *edac_mc_alloc(unsigned mc_num, |
243 | unsigned n_layers, | |
244 | struct edac_mc_layer *layers, | |
245 | unsigned sz_pvt) | |
da9bb1d2 AC |
246 | { |
247 | struct mem_ctl_info *mci; | |
4275be63 | 248 | struct edac_mc_layer *layer; |
de3910eb MCC |
249 | struct csrow_info *csr; |
250 | struct rank_info *chan; | |
a7d7d2e1 | 251 | struct dimm_info *dimm; |
4275be63 MCC |
252 | u32 *ce_per_layer[EDAC_MAX_LAYERS], *ue_per_layer[EDAC_MAX_LAYERS]; |
253 | unsigned pos[EDAC_MAX_LAYERS]; | |
4275be63 MCC |
254 | unsigned size, tot_dimms = 1, count = 1; |
255 | unsigned tot_csrows = 1, tot_channels = 1, tot_errcount = 0; | |
5926ff50 | 256 | void *pvt, *p, *ptr = NULL; |
de3910eb | 257 | int i, j, row, chn, n, len, off; |
4275be63 MCC |
258 | bool per_rank = false; |
259 | ||
260 | BUG_ON(n_layers > EDAC_MAX_LAYERS || n_layers == 0); | |
261 | /* | |
262 | * Calculate the total amount of dimms and csrows/cschannels while | |
263 | * in the old API emulation mode | |
264 | */ | |
265 | for (i = 0; i < n_layers; i++) { | |
266 | tot_dimms *= layers[i].size; | |
267 | if (layers[i].is_virt_csrow) | |
268 | tot_csrows *= layers[i].size; | |
269 | else | |
270 | tot_channels *= layers[i].size; | |
271 | ||
272 | if (layers[i].type == EDAC_MC_LAYER_CHIP_SELECT) | |
273 | per_rank = true; | |
274 | } | |
da9bb1d2 AC |
275 | |
276 | /* Figure out the offsets of the various items from the start of an mc | |
277 | * structure. We want the alignment of each item to be at least as | |
278 | * stringent as what the compiler would provide if we could simply | |
279 | * hardcode everything into a single struct. | |
280 | */ | |
93e4fe64 | 281 | mci = edac_align_ptr(&ptr, sizeof(*mci), 1); |
4275be63 | 282 | layer = edac_align_ptr(&ptr, sizeof(*layer), n_layers); |
4275be63 MCC |
283 | for (i = 0; i < n_layers; i++) { |
284 | count *= layers[i].size; | |
956b9ba1 | 285 | edac_dbg(4, "errcount layer %d size %d\n", i, count); |
4275be63 MCC |
286 | ce_per_layer[i] = edac_align_ptr(&ptr, sizeof(u32), count); |
287 | ue_per_layer[i] = edac_align_ptr(&ptr, sizeof(u32), count); | |
288 | tot_errcount += 2 * count; | |
289 | } | |
290 | ||
956b9ba1 | 291 | edac_dbg(4, "allocating %d error counters\n", tot_errcount); |
93e4fe64 | 292 | pvt = edac_align_ptr(&ptr, sz_pvt, 1); |
079708b9 | 293 | size = ((unsigned long)pvt) + sz_pvt; |
da9bb1d2 | 294 | |
956b9ba1 JP |
295 | edac_dbg(1, "allocating %u bytes for mci data (%d %s, %d csrows/channels)\n", |
296 | size, | |
297 | tot_dimms, | |
298 | per_rank ? "ranks" : "dimms", | |
299 | tot_csrows * tot_channels); | |
de3910eb | 300 | |
8096cfaf DT |
301 | mci = kzalloc(size, GFP_KERNEL); |
302 | if (mci == NULL) | |
da9bb1d2 AC |
303 | return NULL; |
304 | ||
305 | /* Adjust pointers so they point within the memory we just allocated | |
306 | * rather than an imaginary chunk of memory located at address 0. | |
307 | */ | |
4275be63 | 308 | layer = (struct edac_mc_layer *)(((char *)mci) + ((unsigned long)layer)); |
4275be63 MCC |
309 | for (i = 0; i < n_layers; i++) { |
310 | mci->ce_per_layer[i] = (u32 *)((char *)mci + ((unsigned long)ce_per_layer[i])); | |
311 | mci->ue_per_layer[i] = (u32 *)((char *)mci + ((unsigned long)ue_per_layer[i])); | |
312 | } | |
079708b9 | 313 | pvt = sz_pvt ? (((char *)mci) + ((unsigned long)pvt)) : NULL; |
da9bb1d2 | 314 | |
b8f6f975 | 315 | /* setup index and various internal pointers */ |
4275be63 | 316 | mci->mc_idx = mc_num; |
4275be63 | 317 | mci->tot_dimms = tot_dimms; |
da9bb1d2 | 318 | mci->pvt_info = pvt; |
4275be63 MCC |
319 | mci->n_layers = n_layers; |
320 | mci->layers = layer; | |
321 | memcpy(mci->layers, layers, sizeof(*layer) * n_layers); | |
322 | mci->nr_csrows = tot_csrows; | |
323 | mci->num_cschannel = tot_channels; | |
9713faec | 324 | mci->csbased = per_rank; |
da9bb1d2 | 325 | |
a7d7d2e1 | 326 | /* |
de3910eb | 327 | * Alocate and fill the csrow/channels structs |
a7d7d2e1 | 328 | */ |
d3d09e18 | 329 | mci->csrows = kcalloc(tot_csrows, sizeof(*mci->csrows), GFP_KERNEL); |
de3910eb MCC |
330 | if (!mci->csrows) |
331 | goto error; | |
4275be63 | 332 | for (row = 0; row < tot_csrows; row++) { |
de3910eb MCC |
333 | csr = kzalloc(sizeof(**mci->csrows), GFP_KERNEL); |
334 | if (!csr) | |
335 | goto error; | |
336 | mci->csrows[row] = csr; | |
4275be63 MCC |
337 | csr->csrow_idx = row; |
338 | csr->mci = mci; | |
339 | csr->nr_channels = tot_channels; | |
d3d09e18 | 340 | csr->channels = kcalloc(tot_channels, sizeof(*csr->channels), |
de3910eb MCC |
341 | GFP_KERNEL); |
342 | if (!csr->channels) | |
343 | goto error; | |
4275be63 MCC |
344 | |
345 | for (chn = 0; chn < tot_channels; chn++) { | |
de3910eb MCC |
346 | chan = kzalloc(sizeof(**csr->channels), GFP_KERNEL); |
347 | if (!chan) | |
348 | goto error; | |
349 | csr->channels[chn] = chan; | |
da9bb1d2 | 350 | chan->chan_idx = chn; |
4275be63 MCC |
351 | chan->csrow = csr; |
352 | } | |
353 | } | |
354 | ||
355 | /* | |
de3910eb | 356 | * Allocate and fill the dimm structs |
4275be63 | 357 | */ |
d3d09e18 | 358 | mci->dimms = kcalloc(tot_dimms, sizeof(*mci->dimms), GFP_KERNEL); |
de3910eb MCC |
359 | if (!mci->dimms) |
360 | goto error; | |
361 | ||
4275be63 MCC |
362 | memset(&pos, 0, sizeof(pos)); |
363 | row = 0; | |
364 | chn = 0; | |
4275be63 | 365 | for (i = 0; i < tot_dimms; i++) { |
de3910eb MCC |
366 | chan = mci->csrows[row]->channels[chn]; |
367 | off = EDAC_DIMM_OFF(layer, n_layers, pos[0], pos[1], pos[2]); | |
368 | if (off < 0 || off >= tot_dimms) { | |
369 | edac_mc_printk(mci, KERN_ERR, "EDAC core bug: EDAC_DIMM_OFF is trying to do an illegal data access\n"); | |
370 | goto error; | |
371 | } | |
4275be63 | 372 | |
de3910eb | 373 | dimm = kzalloc(sizeof(**mci->dimms), GFP_KERNEL); |
08a4a136 DC |
374 | if (!dimm) |
375 | goto error; | |
de3910eb | 376 | mci->dimms[off] = dimm; |
4275be63 | 377 | dimm->mci = mci; |
4275be63 | 378 | |
5926ff50 MCC |
379 | /* |
380 | * Copy DIMM location and initialize it. | |
381 | */ | |
382 | len = sizeof(dimm->label); | |
383 | p = dimm->label; | |
384 | n = snprintf(p, len, "mc#%u", mc_num); | |
385 | p += n; | |
386 | len -= n; | |
387 | for (j = 0; j < n_layers; j++) { | |
388 | n = snprintf(p, len, "%s#%u", | |
389 | edac_layer_name[layers[j].type], | |
390 | pos[j]); | |
391 | p += n; | |
392 | len -= n; | |
4275be63 MCC |
393 | dimm->location[j] = pos[j]; |
394 | ||
5926ff50 MCC |
395 | if (len <= 0) |
396 | break; | |
397 | } | |
398 | ||
4275be63 MCC |
399 | /* Link it to the csrows old API data */ |
400 | chan->dimm = dimm; | |
401 | dimm->csrow = row; | |
402 | dimm->cschannel = chn; | |
403 | ||
404 | /* Increment csrow location */ | |
24bef66e | 405 | if (layers[0].is_virt_csrow) { |
4275be63 | 406 | chn++; |
24bef66e MCC |
407 | if (chn == tot_channels) { |
408 | chn = 0; | |
409 | row++; | |
410 | } | |
411 | } else { | |
412 | row++; | |
413 | if (row == tot_csrows) { | |
414 | row = 0; | |
415 | chn++; | |
416 | } | |
4275be63 | 417 | } |
a7d7d2e1 | 418 | |
4275be63 MCC |
419 | /* Increment dimm location */ |
420 | for (j = n_layers - 1; j >= 0; j--) { | |
421 | pos[j]++; | |
422 | if (pos[j] < layers[j].size) | |
423 | break; | |
424 | pos[j] = 0; | |
da9bb1d2 AC |
425 | } |
426 | } | |
427 | ||
81d87cb1 | 428 | mci->op_state = OP_ALLOC; |
8096cfaf | 429 | |
da9bb1d2 | 430 | return mci; |
de3910eb MCC |
431 | |
432 | error: | |
faa2ad09 | 433 | _edac_mc_free(mci); |
de3910eb MCC |
434 | |
435 | return NULL; | |
4275be63 | 436 | } |
9110540f | 437 | EXPORT_SYMBOL_GPL(edac_mc_alloc); |
da9bb1d2 | 438 | |
da9bb1d2 AC |
439 | void edac_mc_free(struct mem_ctl_info *mci) |
440 | { | |
956b9ba1 | 441 | edac_dbg(1, "\n"); |
bbc560ae | 442 | |
faa2ad09 SR |
443 | /* If we're not yet registered with sysfs free only what was allocated |
444 | * in edac_mc_alloc(). | |
445 | */ | |
446 | if (!device_is_registered(&mci->dev)) { | |
447 | _edac_mc_free(mci); | |
448 | return; | |
449 | } | |
450 | ||
de3910eb | 451 | /* the mci instance is freed here, when the sysfs object is dropped */ |
7a623c03 | 452 | edac_unregister_sysfs(mci); |
da9bb1d2 | 453 | } |
9110540f | 454 | EXPORT_SYMBOL_GPL(edac_mc_free); |
da9bb1d2 | 455 | |
c73e8833 BP |
456 | /* Caller must hold mem_ctls_mutex */ |
457 | static struct mem_ctl_info *__find_mci_by_dev(struct device *dev) | |
da9bb1d2 AC |
458 | { |
459 | struct mem_ctl_info *mci; | |
460 | struct list_head *item; | |
461 | ||
956b9ba1 | 462 | edac_dbg(3, "\n"); |
da9bb1d2 AC |
463 | |
464 | list_for_each(item, &mc_devices) { | |
465 | mci = list_entry(item, struct mem_ctl_info, link); | |
466 | ||
fd687502 | 467 | if (mci->pdev == dev) |
da9bb1d2 AC |
468 | return mci; |
469 | } | |
470 | ||
471 | return NULL; | |
472 | } | |
c73e8833 BP |
473 | |
474 | /** | |
475 | * find_mci_by_dev | |
476 | * | |
477 | * scan list of controllers looking for the one that manages | |
478 | * the 'dev' device | |
479 | * @dev: pointer to a struct device related with the MCI | |
480 | */ | |
481 | struct mem_ctl_info *find_mci_by_dev(struct device *dev) | |
482 | { | |
483 | struct mem_ctl_info *ret; | |
484 | ||
485 | mutex_lock(&mem_ctls_mutex); | |
486 | ret = __find_mci_by_dev(dev); | |
487 | mutex_unlock(&mem_ctls_mutex); | |
488 | ||
489 | return ret; | |
490 | } | |
939747bd | 491 | EXPORT_SYMBOL_GPL(find_mci_by_dev); |
da9bb1d2 | 492 | |
81d87cb1 DJ |
493 | /* |
494 | * handler for EDAC to check if NMI type handler has asserted interrupt | |
495 | */ | |
496 | static int edac_mc_assert_error_check_and_clear(void) | |
497 | { | |
66ee2f94 | 498 | int old_state; |
81d87cb1 | 499 | |
079708b9 | 500 | if (edac_op_state == EDAC_OPSTATE_POLL) |
81d87cb1 DJ |
501 | return 1; |
502 | ||
66ee2f94 DJ |
503 | old_state = edac_err_assert; |
504 | edac_err_assert = 0; | |
81d87cb1 | 505 | |
66ee2f94 | 506 | return old_state; |
81d87cb1 DJ |
507 | } |
508 | ||
509 | /* | |
510 | * edac_mc_workq_function | |
511 | * performs the operation scheduled by a workq request | |
512 | */ | |
81d87cb1 DJ |
513 | static void edac_mc_workq_function(struct work_struct *work_req) |
514 | { | |
fbeb4384 | 515 | struct delayed_work *d_work = to_delayed_work(work_req); |
81d87cb1 | 516 | struct mem_ctl_info *mci = to_edac_mem_ctl_work(d_work); |
81d87cb1 DJ |
517 | |
518 | mutex_lock(&mem_ctls_mutex); | |
519 | ||
06e912d4 | 520 | if (mci->op_state != OP_RUNNING_POLL) { |
bf52fa4a DT |
521 | mutex_unlock(&mem_ctls_mutex); |
522 | return; | |
523 | } | |
524 | ||
06e912d4 | 525 | if (edac_mc_assert_error_check_and_clear()) |
81d87cb1 DJ |
526 | mci->edac_check(mci); |
527 | ||
81d87cb1 DJ |
528 | mutex_unlock(&mem_ctls_mutex); |
529 | ||
06e912d4 | 530 | /* Queue ourselves again. */ |
c4cf3b45 | 531 | edac_queue_work(&mci->work, msecs_to_jiffies(edac_mc_get_poll_msec())); |
81d87cb1 DJ |
532 | } |
533 | ||
81d87cb1 | 534 | /* |
bce19683 DT |
535 | * edac_mc_reset_delay_period(unsigned long value) |
536 | * | |
537 | * user space has updated our poll period value, need to | |
538 | * reset our workq delays | |
81d87cb1 | 539 | */ |
9da21b15 | 540 | void edac_mc_reset_delay_period(unsigned long value) |
81d87cb1 | 541 | { |
bce19683 DT |
542 | struct mem_ctl_info *mci; |
543 | struct list_head *item; | |
544 | ||
545 | mutex_lock(&mem_ctls_mutex); | |
546 | ||
bce19683 DT |
547 | list_for_each(item, &mc_devices) { |
548 | mci = list_entry(item, struct mem_ctl_info, link); | |
549 | ||
fbedcaf4 NK |
550 | if (mci->op_state == OP_RUNNING_POLL) |
551 | edac_mod_work(&mci->work, value); | |
bce19683 | 552 | } |
81d87cb1 DJ |
553 | mutex_unlock(&mem_ctls_mutex); |
554 | } | |
555 | ||
bce19683 DT |
556 | |
557 | ||
2d7bbb91 DT |
558 | /* Return 0 on success, 1 on failure. |
559 | * Before calling this function, caller must | |
560 | * assign a unique value to mci->mc_idx. | |
bf52fa4a DT |
561 | * |
562 | * locking model: | |
563 | * | |
564 | * called with the mem_ctls_mutex lock held | |
2d7bbb91 | 565 | */ |
079708b9 | 566 | static int add_mc_to_global_list(struct mem_ctl_info *mci) |
da9bb1d2 AC |
567 | { |
568 | struct list_head *item, *insert_before; | |
569 | struct mem_ctl_info *p; | |
da9bb1d2 | 570 | |
2d7bbb91 | 571 | insert_before = &mc_devices; |
da9bb1d2 | 572 | |
c73e8833 | 573 | p = __find_mci_by_dev(mci->pdev); |
bf52fa4a | 574 | if (unlikely(p != NULL)) |
2d7bbb91 | 575 | goto fail0; |
da9bb1d2 | 576 | |
2d7bbb91 DT |
577 | list_for_each(item, &mc_devices) { |
578 | p = list_entry(item, struct mem_ctl_info, link); | |
da9bb1d2 | 579 | |
2d7bbb91 DT |
580 | if (p->mc_idx >= mci->mc_idx) { |
581 | if (unlikely(p->mc_idx == mci->mc_idx)) | |
582 | goto fail1; | |
da9bb1d2 | 583 | |
2d7bbb91 DT |
584 | insert_before = item; |
585 | break; | |
da9bb1d2 | 586 | } |
da9bb1d2 AC |
587 | } |
588 | ||
589 | list_add_tail_rcu(&mci->link, insert_before); | |
c0d12172 | 590 | atomic_inc(&edac_handlers); |
da9bb1d2 | 591 | return 0; |
2d7bbb91 | 592 | |
052dfb45 | 593 | fail0: |
2d7bbb91 | 594 | edac_printk(KERN_WARNING, EDAC_MC, |
fd687502 | 595 | "%s (%s) %s %s already assigned %d\n", dev_name(p->pdev), |
17aa7e03 | 596 | edac_dev_name(mci), p->mod_name, p->ctl_name, p->mc_idx); |
2d7bbb91 DT |
597 | return 1; |
598 | ||
052dfb45 | 599 | fail1: |
2d7bbb91 | 600 | edac_printk(KERN_WARNING, EDAC_MC, |
052dfb45 DT |
601 | "bug in low-level driver: attempt to assign\n" |
602 | " duplicate mc_idx %d in %s()\n", p->mc_idx, __func__); | |
2d7bbb91 | 603 | return 1; |
da9bb1d2 AC |
604 | } |
605 | ||
80cc7d87 | 606 | static int del_mc_from_global_list(struct mem_ctl_info *mci) |
a1d03fcc | 607 | { |
80cc7d87 | 608 | int handlers = atomic_dec_return(&edac_handlers); |
a1d03fcc | 609 | list_del_rcu(&mci->link); |
e2e77098 LJ |
610 | |
611 | /* these are for safe removal of devices from global list while | |
612 | * NMI handlers may be traversing list | |
613 | */ | |
614 | synchronize_rcu(); | |
615 | INIT_LIST_HEAD(&mci->link); | |
80cc7d87 MCC |
616 | |
617 | return handlers; | |
a1d03fcc DP |
618 | } |
619 | ||
079708b9 | 620 | struct mem_ctl_info *edac_mc_find(int idx) |
5da0831c | 621 | { |
c73e8833 | 622 | struct mem_ctl_info *mci = NULL; |
5da0831c | 623 | struct list_head *item; |
c73e8833 BP |
624 | |
625 | mutex_lock(&mem_ctls_mutex); | |
5da0831c DT |
626 | |
627 | list_for_each(item, &mc_devices) { | |
628 | mci = list_entry(item, struct mem_ctl_info, link); | |
629 | ||
630 | if (mci->mc_idx >= idx) { | |
c73e8833 BP |
631 | if (mci->mc_idx == idx) { |
632 | goto unlock; | |
633 | } | |
5da0831c DT |
634 | break; |
635 | } | |
636 | } | |
637 | ||
c73e8833 BP |
638 | unlock: |
639 | mutex_unlock(&mem_ctls_mutex); | |
640 | return mci; | |
5da0831c DT |
641 | } |
642 | EXPORT_SYMBOL(edac_mc_find); | |
643 | ||
da9bb1d2 AC |
644 | |
645 | /* FIXME - should a warning be printed if no error detection? correction? */ | |
4e8d230d TI |
646 | int edac_mc_add_mc_with_groups(struct mem_ctl_info *mci, |
647 | const struct attribute_group **groups) | |
da9bb1d2 | 648 | { |
80cc7d87 | 649 | int ret = -EINVAL; |
956b9ba1 | 650 | edac_dbg(0, "\n"); |
b8f6f975 | 651 | |
88d84ac9 BP |
652 | if (mci->mc_idx >= EDAC_MAX_MCS) { |
653 | pr_warn_once("Too many memory controllers: %d\n", mci->mc_idx); | |
654 | return -ENODEV; | |
655 | } | |
656 | ||
da9bb1d2 AC |
657 | #ifdef CONFIG_EDAC_DEBUG |
658 | if (edac_debug_level >= 3) | |
659 | edac_mc_dump_mci(mci); | |
e7ecd891 | 660 | |
da9bb1d2 AC |
661 | if (edac_debug_level >= 4) { |
662 | int i; | |
663 | ||
664 | for (i = 0; i < mci->nr_csrows; i++) { | |
6e84d359 MCC |
665 | struct csrow_info *csrow = mci->csrows[i]; |
666 | u32 nr_pages = 0; | |
da9bb1d2 | 667 | int j; |
e7ecd891 | 668 | |
6e84d359 MCC |
669 | for (j = 0; j < csrow->nr_channels; j++) |
670 | nr_pages += csrow->channels[j]->dimm->nr_pages; | |
671 | if (!nr_pages) | |
672 | continue; | |
673 | edac_mc_dump_csrow(csrow); | |
674 | for (j = 0; j < csrow->nr_channels; j++) | |
675 | if (csrow->channels[j]->dimm->nr_pages) | |
676 | edac_mc_dump_channel(csrow->channels[j]); | |
da9bb1d2 | 677 | } |
4275be63 | 678 | for (i = 0; i < mci->tot_dimms; i++) |
6e84d359 MCC |
679 | if (mci->dimms[i]->nr_pages) |
680 | edac_mc_dump_dimm(mci->dimms[i], i); | |
da9bb1d2 AC |
681 | } |
682 | #endif | |
63b7df91 | 683 | mutex_lock(&mem_ctls_mutex); |
da9bb1d2 | 684 | |
80cc7d87 MCC |
685 | if (edac_mc_owner && edac_mc_owner != mci->mod_name) { |
686 | ret = -EPERM; | |
687 | goto fail0; | |
688 | } | |
689 | ||
da9bb1d2 | 690 | if (add_mc_to_global_list(mci)) |
028a7b6d | 691 | goto fail0; |
da9bb1d2 AC |
692 | |
693 | /* set load time so that error rate can be tracked */ | |
694 | mci->start_time = jiffies; | |
695 | ||
88d84ac9 BP |
696 | mci->bus = &mc_bus[mci->mc_idx]; |
697 | ||
4e8d230d | 698 | if (edac_create_sysfs_mci_device(mci, groups)) { |
9794f33d | 699 | edac_mc_printk(mci, KERN_WARNING, |
052dfb45 | 700 | "failed to create sysfs device\n"); |
9794f33d | 701 | goto fail1; |
702 | } | |
da9bb1d2 | 703 | |
09667606 | 704 | if (mci->edac_check) { |
81d87cb1 DJ |
705 | mci->op_state = OP_RUNNING_POLL; |
706 | ||
626a7a4d BP |
707 | INIT_DELAYED_WORK(&mci->work, edac_mc_workq_function); |
708 | edac_queue_work(&mci->work, msecs_to_jiffies(edac_mc_get_poll_msec())); | |
709 | ||
81d87cb1 DJ |
710 | } else { |
711 | mci->op_state = OP_RUNNING_INTERRUPT; | |
712 | } | |
713 | ||
da9bb1d2 | 714 | /* Report action taken */ |
7270a608 RR |
715 | edac_mc_printk(mci, KERN_INFO, |
716 | "Giving out device to module %s controller %s: DEV %s (%s)\n", | |
717 | mci->mod_name, mci->ctl_name, mci->dev_name, | |
718 | edac_op_state_to_string(mci->op_state)); | |
da9bb1d2 | 719 | |
80cc7d87 MCC |
720 | edac_mc_owner = mci->mod_name; |
721 | ||
63b7df91 | 722 | mutex_unlock(&mem_ctls_mutex); |
028a7b6d | 723 | return 0; |
da9bb1d2 | 724 | |
052dfb45 | 725 | fail1: |
028a7b6d DP |
726 | del_mc_from_global_list(mci); |
727 | ||
052dfb45 | 728 | fail0: |
63b7df91 | 729 | mutex_unlock(&mem_ctls_mutex); |
80cc7d87 | 730 | return ret; |
da9bb1d2 | 731 | } |
4e8d230d | 732 | EXPORT_SYMBOL_GPL(edac_mc_add_mc_with_groups); |
da9bb1d2 | 733 | |
079708b9 | 734 | struct mem_ctl_info *edac_mc_del_mc(struct device *dev) |
da9bb1d2 | 735 | { |
18dbc337 | 736 | struct mem_ctl_info *mci; |
da9bb1d2 | 737 | |
956b9ba1 | 738 | edac_dbg(0, "\n"); |
bf52fa4a | 739 | |
63b7df91 | 740 | mutex_lock(&mem_ctls_mutex); |
18dbc337 | 741 | |
bf52fa4a | 742 | /* find the requested mci struct in the global list */ |
c73e8833 | 743 | mci = __find_mci_by_dev(dev); |
bf52fa4a | 744 | if (mci == NULL) { |
63b7df91 | 745 | mutex_unlock(&mem_ctls_mutex); |
18dbc337 DP |
746 | return NULL; |
747 | } | |
748 | ||
09667606 BP |
749 | /* mark MCI offline: */ |
750 | mci->op_state = OP_OFFLINE; | |
751 | ||
80cc7d87 MCC |
752 | if (!del_mc_from_global_list(mci)) |
753 | edac_mc_owner = NULL; | |
bf52fa4a | 754 | |
09667606 | 755 | mutex_unlock(&mem_ctls_mutex); |
bb31b312 | 756 | |
09667606 | 757 | if (mci->edac_check) |
626a7a4d | 758 | edac_stop_work(&mci->work); |
bb31b312 BP |
759 | |
760 | /* remove from sysfs */ | |
bf52fa4a DT |
761 | edac_remove_sysfs_mci_device(mci); |
762 | ||
537fba28 | 763 | edac_printk(KERN_INFO, EDAC_MC, |
052dfb45 | 764 | "Removed device %d for %s %s: DEV %s\n", mci->mc_idx, |
17aa7e03 | 765 | mci->mod_name, mci->ctl_name, edac_dev_name(mci)); |
bf52fa4a | 766 | |
18dbc337 | 767 | return mci; |
da9bb1d2 | 768 | } |
9110540f | 769 | EXPORT_SYMBOL_GPL(edac_mc_del_mc); |
da9bb1d2 | 770 | |
2da1c119 AB |
771 | static void edac_mc_scrub_block(unsigned long page, unsigned long offset, |
772 | u32 size) | |
da9bb1d2 AC |
773 | { |
774 | struct page *pg; | |
775 | void *virt_addr; | |
776 | unsigned long flags = 0; | |
777 | ||
956b9ba1 | 778 | edac_dbg(3, "\n"); |
da9bb1d2 AC |
779 | |
780 | /* ECC error page was not in our memory. Ignore it. */ | |
079708b9 | 781 | if (!pfn_valid(page)) |
da9bb1d2 AC |
782 | return; |
783 | ||
784 | /* Find the actual page structure then map it and fix */ | |
785 | pg = pfn_to_page(page); | |
786 | ||
787 | if (PageHighMem(pg)) | |
788 | local_irq_save(flags); | |
789 | ||
4e5df7ca | 790 | virt_addr = kmap_atomic(pg); |
da9bb1d2 AC |
791 | |
792 | /* Perform architecture specific atomic scrub operation */ | |
b01aec9b | 793 | edac_atomic_scrub(virt_addr + offset, size); |
da9bb1d2 AC |
794 | |
795 | /* Unmap and complete */ | |
4e5df7ca | 796 | kunmap_atomic(virt_addr); |
da9bb1d2 AC |
797 | |
798 | if (PageHighMem(pg)) | |
799 | local_irq_restore(flags); | |
800 | } | |
801 | ||
da9bb1d2 | 802 | /* FIXME - should return -1 */ |
e7ecd891 | 803 | int edac_mc_find_csrow_by_page(struct mem_ctl_info *mci, unsigned long page) |
da9bb1d2 | 804 | { |
de3910eb | 805 | struct csrow_info **csrows = mci->csrows; |
a895bf8b | 806 | int row, i, j, n; |
da9bb1d2 | 807 | |
956b9ba1 | 808 | edac_dbg(1, "MC%d: 0x%lx\n", mci->mc_idx, page); |
da9bb1d2 AC |
809 | row = -1; |
810 | ||
811 | for (i = 0; i < mci->nr_csrows; i++) { | |
de3910eb | 812 | struct csrow_info *csrow = csrows[i]; |
a895bf8b MCC |
813 | n = 0; |
814 | for (j = 0; j < csrow->nr_channels; j++) { | |
de3910eb | 815 | struct dimm_info *dimm = csrow->channels[j]->dimm; |
a895bf8b MCC |
816 | n += dimm->nr_pages; |
817 | } | |
818 | if (n == 0) | |
da9bb1d2 AC |
819 | continue; |
820 | ||
956b9ba1 JP |
821 | edac_dbg(3, "MC%d: first(0x%lx) page(0x%lx) last(0x%lx) mask(0x%lx)\n", |
822 | mci->mc_idx, | |
823 | csrow->first_page, page, csrow->last_page, | |
824 | csrow->page_mask); | |
da9bb1d2 AC |
825 | |
826 | if ((page >= csrow->first_page) && | |
827 | (page <= csrow->last_page) && | |
828 | ((page & csrow->page_mask) == | |
829 | (csrow->first_page & csrow->page_mask))) { | |
830 | row = i; | |
831 | break; | |
832 | } | |
833 | } | |
834 | ||
835 | if (row == -1) | |
537fba28 | 836 | edac_mc_printk(mci, KERN_ERR, |
052dfb45 DT |
837 | "could not look up page error address %lx\n", |
838 | (unsigned long)page); | |
da9bb1d2 AC |
839 | |
840 | return row; | |
841 | } | |
9110540f | 842 | EXPORT_SYMBOL_GPL(edac_mc_find_csrow_by_page); |
da9bb1d2 | 843 | |
4275be63 MCC |
844 | const char *edac_layer_name[] = { |
845 | [EDAC_MC_LAYER_BRANCH] = "branch", | |
846 | [EDAC_MC_LAYER_CHANNEL] = "channel", | |
847 | [EDAC_MC_LAYER_SLOT] = "slot", | |
848 | [EDAC_MC_LAYER_CHIP_SELECT] = "csrow", | |
c66b5a79 | 849 | [EDAC_MC_LAYER_ALL_MEM] = "memory", |
4275be63 MCC |
850 | }; |
851 | EXPORT_SYMBOL_GPL(edac_layer_name); | |
852 | ||
853 | static void edac_inc_ce_error(struct mem_ctl_info *mci, | |
9eb07a7f MCC |
854 | bool enable_per_layer_report, |
855 | const int pos[EDAC_MAX_LAYERS], | |
856 | const u16 count) | |
da9bb1d2 | 857 | { |
4275be63 | 858 | int i, index = 0; |
da9bb1d2 | 859 | |
9eb07a7f | 860 | mci->ce_mc += count; |
da9bb1d2 | 861 | |
4275be63 | 862 | if (!enable_per_layer_report) { |
9eb07a7f | 863 | mci->ce_noinfo_count += count; |
da9bb1d2 AC |
864 | return; |
865 | } | |
e7ecd891 | 866 | |
4275be63 MCC |
867 | for (i = 0; i < mci->n_layers; i++) { |
868 | if (pos[i] < 0) | |
869 | break; | |
870 | index += pos[i]; | |
9eb07a7f | 871 | mci->ce_per_layer[i][index] += count; |
4275be63 MCC |
872 | |
873 | if (i < mci->n_layers - 1) | |
874 | index *= mci->layers[i + 1].size; | |
875 | } | |
876 | } | |
877 | ||
878 | static void edac_inc_ue_error(struct mem_ctl_info *mci, | |
879 | bool enable_per_layer_report, | |
9eb07a7f MCC |
880 | const int pos[EDAC_MAX_LAYERS], |
881 | const u16 count) | |
4275be63 MCC |
882 | { |
883 | int i, index = 0; | |
884 | ||
9eb07a7f | 885 | mci->ue_mc += count; |
4275be63 MCC |
886 | |
887 | if (!enable_per_layer_report) { | |
993f88f1 | 888 | mci->ue_noinfo_count += count; |
da9bb1d2 AC |
889 | return; |
890 | } | |
891 | ||
4275be63 MCC |
892 | for (i = 0; i < mci->n_layers; i++) { |
893 | if (pos[i] < 0) | |
894 | break; | |
895 | index += pos[i]; | |
9eb07a7f | 896 | mci->ue_per_layer[i][index] += count; |
a7d7d2e1 | 897 | |
4275be63 MCC |
898 | if (i < mci->n_layers - 1) |
899 | index *= mci->layers[i + 1].size; | |
900 | } | |
901 | } | |
da9bb1d2 | 902 | |
4275be63 | 903 | static void edac_ce_error(struct mem_ctl_info *mci, |
9eb07a7f | 904 | const u16 error_count, |
4275be63 MCC |
905 | const int pos[EDAC_MAX_LAYERS], |
906 | const char *msg, | |
907 | const char *location, | |
908 | const char *label, | |
909 | const char *detail, | |
910 | const char *other_detail, | |
911 | const bool enable_per_layer_report, | |
912 | const unsigned long page_frame_number, | |
913 | const unsigned long offset_in_page, | |
53f2d028 | 914 | long grain) |
4275be63 MCC |
915 | { |
916 | unsigned long remapped_page; | |
f430d570 BP |
917 | char *msg_aux = ""; |
918 | ||
919 | if (*msg) | |
920 | msg_aux = " "; | |
4275be63 MCC |
921 | |
922 | if (edac_mc_get_log_ce()) { | |
923 | if (other_detail && *other_detail) | |
924 | edac_mc_printk(mci, KERN_WARNING, | |
f430d570 BP |
925 | "%d CE %s%son %s (%s %s - %s)\n", |
926 | error_count, msg, msg_aux, label, | |
927 | location, detail, other_detail); | |
4275be63 MCC |
928 | else |
929 | edac_mc_printk(mci, KERN_WARNING, | |
f430d570 BP |
930 | "%d CE %s%son %s (%s %s)\n", |
931 | error_count, msg, msg_aux, label, | |
932 | location, detail); | |
4275be63 | 933 | } |
9eb07a7f | 934 | edac_inc_ce_error(mci, enable_per_layer_report, pos, error_count); |
da9bb1d2 | 935 | |
aa2064d7 | 936 | if (mci->scrub_mode == SCRUB_SW_SRC) { |
da9bb1d2 | 937 | /* |
4275be63 MCC |
938 | * Some memory controllers (called MCs below) can remap |
939 | * memory so that it is still available at a different | |
940 | * address when PCI devices map into memory. | |
941 | * MC's that can't do this, lose the memory where PCI | |
942 | * devices are mapped. This mapping is MC-dependent | |
943 | * and so we call back into the MC driver for it to | |
944 | * map the MC page to a physical (CPU) page which can | |
945 | * then be mapped to a virtual page - which can then | |
946 | * be scrubbed. | |
947 | */ | |
da9bb1d2 | 948 | remapped_page = mci->ctl_page_to_phys ? |
052dfb45 DT |
949 | mci->ctl_page_to_phys(mci, page_frame_number) : |
950 | page_frame_number; | |
da9bb1d2 | 951 | |
4275be63 MCC |
952 | edac_mc_scrub_block(remapped_page, |
953 | offset_in_page, grain); | |
da9bb1d2 AC |
954 | } |
955 | } | |
956 | ||
4275be63 | 957 | static void edac_ue_error(struct mem_ctl_info *mci, |
9eb07a7f | 958 | const u16 error_count, |
4275be63 MCC |
959 | const int pos[EDAC_MAX_LAYERS], |
960 | const char *msg, | |
961 | const char *location, | |
962 | const char *label, | |
963 | const char *detail, | |
964 | const char *other_detail, | |
965 | const bool enable_per_layer_report) | |
da9bb1d2 | 966 | { |
f430d570 BP |
967 | char *msg_aux = ""; |
968 | ||
969 | if (*msg) | |
970 | msg_aux = " "; | |
971 | ||
4275be63 MCC |
972 | if (edac_mc_get_log_ue()) { |
973 | if (other_detail && *other_detail) | |
974 | edac_mc_printk(mci, KERN_WARNING, | |
f430d570 BP |
975 | "%d UE %s%son %s (%s %s - %s)\n", |
976 | error_count, msg, msg_aux, label, | |
977 | location, detail, other_detail); | |
4275be63 MCC |
978 | else |
979 | edac_mc_printk(mci, KERN_WARNING, | |
f430d570 BP |
980 | "%d UE %s%son %s (%s %s)\n", |
981 | error_count, msg, msg_aux, label, | |
982 | location, detail); | |
4275be63 | 983 | } |
e7ecd891 | 984 | |
4275be63 MCC |
985 | if (edac_mc_get_panic_on_ue()) { |
986 | if (other_detail && *other_detail) | |
f430d570 BP |
987 | panic("UE %s%son %s (%s%s - %s)\n", |
988 | msg, msg_aux, label, location, detail, other_detail); | |
4275be63 | 989 | else |
f430d570 BP |
990 | panic("UE %s%son %s (%s%s)\n", |
991 | msg, msg_aux, label, location, detail); | |
4275be63 MCC |
992 | } |
993 | ||
9eb07a7f | 994 | edac_inc_ue_error(mci, enable_per_layer_report, pos, error_count); |
da9bb1d2 AC |
995 | } |
996 | ||
e7e24830 MCC |
997 | void edac_raw_mc_handle_error(const enum hw_event_mc_err_type type, |
998 | struct mem_ctl_info *mci, | |
999 | struct edac_raw_error_desc *e) | |
1000 | { | |
1001 | char detail[80]; | |
1002 | int pos[EDAC_MAX_LAYERS] = { e->top_layer, e->mid_layer, e->low_layer }; | |
1003 | ||
1004 | /* Memory type dependent details about the error */ | |
1005 | if (type == HW_EVENT_ERR_CORRECTED) { | |
1006 | snprintf(detail, sizeof(detail), | |
1007 | "page:0x%lx offset:0x%lx grain:%ld syndrome:0x%lx", | |
1008 | e->page_frame_number, e->offset_in_page, | |
1009 | e->grain, e->syndrome); | |
1010 | edac_ce_error(mci, e->error_count, pos, e->msg, e->location, e->label, | |
1011 | detail, e->other_detail, e->enable_per_layer_report, | |
1012 | e->page_frame_number, e->offset_in_page, e->grain); | |
1013 | } else { | |
1014 | snprintf(detail, sizeof(detail), | |
1015 | "page:0x%lx offset:0x%lx grain:%ld", | |
1016 | e->page_frame_number, e->offset_in_page, e->grain); | |
1017 | ||
1018 | edac_ue_error(mci, e->error_count, pos, e->msg, e->location, e->label, | |
1019 | detail, e->other_detail, e->enable_per_layer_report); | |
1020 | } | |
1021 | ||
1022 | ||
1023 | } | |
1024 | EXPORT_SYMBOL_GPL(edac_raw_mc_handle_error); | |
53f2d028 | 1025 | |
4275be63 MCC |
1026 | void edac_mc_handle_error(const enum hw_event_mc_err_type type, |
1027 | struct mem_ctl_info *mci, | |
9eb07a7f | 1028 | const u16 error_count, |
4275be63 MCC |
1029 | const unsigned long page_frame_number, |
1030 | const unsigned long offset_in_page, | |
1031 | const unsigned long syndrome, | |
53f2d028 MCC |
1032 | const int top_layer, |
1033 | const int mid_layer, | |
1034 | const int low_layer, | |
4275be63 | 1035 | const char *msg, |
03f7eae8 | 1036 | const char *other_detail) |
da9bb1d2 | 1037 | { |
4275be63 MCC |
1038 | char *p; |
1039 | int row = -1, chan = -1; | |
53f2d028 | 1040 | int pos[EDAC_MAX_LAYERS] = { top_layer, mid_layer, low_layer }; |
c7ef7645 | 1041 | int i, n_labels = 0; |
53f2d028 | 1042 | u8 grain_bits; |
c7ef7645 | 1043 | struct edac_raw_error_desc *e = &mci->error_desc; |
da9bb1d2 | 1044 | |
956b9ba1 | 1045 | edac_dbg(3, "MC%d\n", mci->mc_idx); |
da9bb1d2 | 1046 | |
c7ef7645 MCC |
1047 | /* Fills the error report buffer */ |
1048 | memset(e, 0, sizeof (*e)); | |
1049 | e->error_count = error_count; | |
1050 | e->top_layer = top_layer; | |
1051 | e->mid_layer = mid_layer; | |
1052 | e->low_layer = low_layer; | |
1053 | e->page_frame_number = page_frame_number; | |
1054 | e->offset_in_page = offset_in_page; | |
1055 | e->syndrome = syndrome; | |
1056 | e->msg = msg; | |
1057 | e->other_detail = other_detail; | |
1058 | ||
4275be63 MCC |
1059 | /* |
1060 | * Check if the event report is consistent and if the memory | |
1061 | * location is known. If it is known, enable_per_layer_report will be | |
1062 | * true, the DIMM(s) label info will be filled and the per-layer | |
1063 | * error counters will be incremented. | |
1064 | */ | |
1065 | for (i = 0; i < mci->n_layers; i++) { | |
1066 | if (pos[i] >= (int)mci->layers[i].size) { | |
4275be63 MCC |
1067 | |
1068 | edac_mc_printk(mci, KERN_ERR, | |
1069 | "INTERNAL ERROR: %s value is out of range (%d >= %d)\n", | |
1070 | edac_layer_name[mci->layers[i].type], | |
1071 | pos[i], mci->layers[i].size); | |
1072 | /* | |
1073 | * Instead of just returning it, let's use what's | |
1074 | * known about the error. The increment routines and | |
1075 | * the DIMM filter logic will do the right thing by | |
1076 | * pointing the likely damaged DIMMs. | |
1077 | */ | |
1078 | pos[i] = -1; | |
1079 | } | |
1080 | if (pos[i] >= 0) | |
c7ef7645 | 1081 | e->enable_per_layer_report = true; |
da9bb1d2 AC |
1082 | } |
1083 | ||
4275be63 MCC |
1084 | /* |
1085 | * Get the dimm label/grain that applies to the match criteria. | |
1086 | * As the error algorithm may not be able to point to just one memory | |
1087 | * stick, the logic here will get all possible labels that could | |
1088 | * pottentially be affected by the error. | |
1089 | * On FB-DIMM memory controllers, for uncorrected errors, it is common | |
1090 | * to have only the MC channel and the MC dimm (also called "branch") | |
1091 | * but the channel is not known, as the memory is arranged in pairs, | |
1092 | * where each memory belongs to a separate channel within the same | |
1093 | * branch. | |
1094 | */ | |
c7ef7645 | 1095 | p = e->label; |
4275be63 | 1096 | *p = '\0'; |
4da1b7bf | 1097 | |
4275be63 | 1098 | for (i = 0; i < mci->tot_dimms; i++) { |
de3910eb | 1099 | struct dimm_info *dimm = mci->dimms[i]; |
da9bb1d2 | 1100 | |
53f2d028 | 1101 | if (top_layer >= 0 && top_layer != dimm->location[0]) |
4275be63 | 1102 | continue; |
53f2d028 | 1103 | if (mid_layer >= 0 && mid_layer != dimm->location[1]) |
4275be63 | 1104 | continue; |
53f2d028 | 1105 | if (low_layer >= 0 && low_layer != dimm->location[2]) |
4275be63 | 1106 | continue; |
da9bb1d2 | 1107 | |
4275be63 | 1108 | /* get the max grain, over the error match range */ |
c7ef7645 MCC |
1109 | if (dimm->grain > e->grain) |
1110 | e->grain = dimm->grain; | |
9794f33d | 1111 | |
4275be63 MCC |
1112 | /* |
1113 | * If the error is memory-controller wide, there's no need to | |
1114 | * seek for the affected DIMMs because the whole | |
1115 | * channel/memory controller/... may be affected. | |
1116 | * Also, don't show errors for empty DIMM slots. | |
1117 | */ | |
c7ef7645 MCC |
1118 | if (e->enable_per_layer_report && dimm->nr_pages) { |
1119 | if (n_labels >= EDAC_MAX_LABELS) { | |
1120 | e->enable_per_layer_report = false; | |
1121 | break; | |
1122 | } | |
1123 | n_labels++; | |
1124 | if (p != e->label) { | |
4275be63 MCC |
1125 | strcpy(p, OTHER_LABEL); |
1126 | p += strlen(OTHER_LABEL); | |
1127 | } | |
1128 | strcpy(p, dimm->label); | |
1129 | p += strlen(p); | |
1130 | *p = '\0'; | |
1131 | ||
1132 | /* | |
1133 | * get csrow/channel of the DIMM, in order to allow | |
1134 | * incrementing the compat API counters | |
1135 | */ | |
956b9ba1 | 1136 | edac_dbg(4, "%s csrows map: (%d,%d)\n", |
9713faec | 1137 | mci->csbased ? "rank" : "dimm", |
956b9ba1 | 1138 | dimm->csrow, dimm->cschannel); |
4275be63 MCC |
1139 | if (row == -1) |
1140 | row = dimm->csrow; | |
1141 | else if (row >= 0 && row != dimm->csrow) | |
1142 | row = -2; | |
1143 | ||
1144 | if (chan == -1) | |
1145 | chan = dimm->cschannel; | |
1146 | else if (chan >= 0 && chan != dimm->cschannel) | |
1147 | chan = -2; | |
1148 | } | |
9794f33d | 1149 | } |
1150 | ||
c7ef7645 MCC |
1151 | if (!e->enable_per_layer_report) { |
1152 | strcpy(e->label, "any memory"); | |
4275be63 | 1153 | } else { |
956b9ba1 | 1154 | edac_dbg(4, "csrow/channel to increment: (%d,%d)\n", row, chan); |
c7ef7645 MCC |
1155 | if (p == e->label) |
1156 | strcpy(e->label, "unknown memory"); | |
4275be63 MCC |
1157 | if (type == HW_EVENT_ERR_CORRECTED) { |
1158 | if (row >= 0) { | |
9eb07a7f | 1159 | mci->csrows[row]->ce_count += error_count; |
4275be63 | 1160 | if (chan >= 0) |
9eb07a7f | 1161 | mci->csrows[row]->channels[chan]->ce_count += error_count; |
4275be63 MCC |
1162 | } |
1163 | } else | |
1164 | if (row >= 0) | |
9eb07a7f | 1165 | mci->csrows[row]->ue_count += error_count; |
9794f33d | 1166 | } |
1167 | ||
4275be63 | 1168 | /* Fill the RAM location data */ |
c7ef7645 | 1169 | p = e->location; |
4da1b7bf | 1170 | |
4275be63 MCC |
1171 | for (i = 0; i < mci->n_layers; i++) { |
1172 | if (pos[i] < 0) | |
1173 | continue; | |
9794f33d | 1174 | |
4275be63 MCC |
1175 | p += sprintf(p, "%s:%d ", |
1176 | edac_layer_name[mci->layers[i].type], | |
1177 | pos[i]); | |
9794f33d | 1178 | } |
c7ef7645 | 1179 | if (p > e->location) |
53f2d028 MCC |
1180 | *(p - 1) = '\0'; |
1181 | ||
1182 | /* Report the error via the trace interface */ | |
c7ef7645 MCC |
1183 | grain_bits = fls_long(e->grain) + 1; |
1184 | trace_mc_event(type, e->msg, e->label, e->error_count, | |
1185 | mci->mc_idx, e->top_layer, e->mid_layer, e->low_layer, | |
990995ba | 1186 | (e->page_frame_number << PAGE_SHIFT) | e->offset_in_page, |
e7e24830 | 1187 | grain_bits, e->syndrome, e->other_detail); |
a7d7d2e1 | 1188 | |
e7e24830 | 1189 | edac_raw_mc_handle_error(type, mci, e); |
9794f33d | 1190 | } |
4275be63 | 1191 | EXPORT_SYMBOL_GPL(edac_mc_handle_error); |