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1/*
2 * MC kernel module
3 * (C) 2003 Linux Networx (http://lnxi.com)
4 * This file may be distributed under the terms of the
5 * GNU General Public License.
6 *
7 * Written by Thayne Harbaugh
8 * Based on work by Dan Hollis <goemon at anime dot net> and others.
9 * http://www.anime.net/~goemon/linux-ecc/
10 *
11 * NMI handling support added by
12 * Dave Peterson <dsp@llnl.gov> <dave_peterson@pobox.com>
13 *
14 * $Id: edac_mc.h,v 1.4.2.10 2005/10/05 00:43:44 dsp_llnl Exp $
15 *
16 */
17
18
19#ifndef _EDAC_MC_H_
20#define _EDAC_MC_H_
21
22
23#include <linux/config.h>
24#include <linux/kernel.h>
25#include <linux/types.h>
26#include <linux/module.h>
27#include <linux/spinlock.h>
28#include <linux/smp.h>
29#include <linux/pci.h>
30#include <linux/time.h>
31#include <linux/nmi.h>
32#include <linux/rcupdate.h>
33#include <linux/completion.h>
34#include <linux/kobject.h>
35
36
37#define EDAC_MC_LABEL_LEN 31
38#define MC_PROC_NAME_MAX_LEN 7
39
40#if PAGE_SHIFT < 20
41#define PAGES_TO_MiB( pages ) ( ( pages ) >> ( 20 - PAGE_SHIFT ) )
42#else /* PAGE_SHIFT > 20 */
43#define PAGES_TO_MiB( pages ) ( ( pages ) << ( PAGE_SHIFT - 20 ) )
44#endif
45
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46#define edac_printk(level, prefix, fmt, arg...) \
47 printk(level "EDAC " prefix ": " fmt, ##arg)
48
49#define edac_mc_printk(mci, level, fmt, arg...) \
50 printk(level "EDAC MC%d: " fmt, mci->mc_idx, ##arg)
51
52#define edac_mc_chipset_printk(mci, level, prefix, fmt, arg...) \
53 printk(level "EDAC " prefix " MC%d: " fmt, mci->mc_idx, ##arg)
54
55/* prefixes for edac_printk() and edac_mc_printk() */
56#define EDAC_MC "MC"
57#define EDAC_PCI "PCI"
58#define EDAC_DEBUG "DEBUG"
59
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60#ifdef CONFIG_EDAC_DEBUG
61extern int edac_debug_level;
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62
63#define edac_debug_printk(level, fmt, arg...) \
64 do { \
65 if (level <= edac_debug_level) \
66 edac_printk(KERN_DEBUG, EDAC_DEBUG, fmt, ##arg); \
67 } while(0)
68
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69#define debugf0( ... ) edac_debug_printk(0, __VA_ARGS__ )
70#define debugf1( ... ) edac_debug_printk(1, __VA_ARGS__ )
71#define debugf2( ... ) edac_debug_printk(2, __VA_ARGS__ )
72#define debugf3( ... ) edac_debug_printk(3, __VA_ARGS__ )
73#define debugf4( ... ) edac_debug_printk(4, __VA_ARGS__ )
74#else /* !CONFIG_EDAC_DEBUG */
75#define debugf0( ... )
76#define debugf1( ... )
77#define debugf2( ... )
78#define debugf3( ... )
79#define debugf4( ... )
80#endif /* !CONFIG_EDAC_DEBUG */
81
82
83#define bs_xstr(s) bs_str(s)
84#define bs_str(s) #s
85#define BS_MOD_STR bs_xstr(KBUILD_BASENAME)
86
87#define BIT(x) (1 << (x))
88
89#define PCI_VEND_DEV(vend, dev) PCI_VENDOR_ID_ ## vend, PCI_DEVICE_ID_ ## vend ## _ ## dev
90
91/* memory devices */
92enum dev_type {
93 DEV_UNKNOWN = 0,
94 DEV_X1,
95 DEV_X2,
96 DEV_X4,
97 DEV_X8,
98 DEV_X16,
99 DEV_X32, /* Do these parts exist? */
100 DEV_X64 /* Do these parts exist? */
101};
102
103#define DEV_FLAG_UNKNOWN BIT(DEV_UNKNOWN)
104#define DEV_FLAG_X1 BIT(DEV_X1)
105#define DEV_FLAG_X2 BIT(DEV_X2)
106#define DEV_FLAG_X4 BIT(DEV_X4)
107#define DEV_FLAG_X8 BIT(DEV_X8)
108#define DEV_FLAG_X16 BIT(DEV_X16)
109#define DEV_FLAG_X32 BIT(DEV_X32)
110#define DEV_FLAG_X64 BIT(DEV_X64)
111
112/* memory types */
113enum mem_type {
114 MEM_EMPTY = 0, /* Empty csrow */
115 MEM_RESERVED, /* Reserved csrow type */
116 MEM_UNKNOWN, /* Unknown csrow type */
117 MEM_FPM, /* Fast page mode */
118 MEM_EDO, /* Extended data out */
119 MEM_BEDO, /* Burst Extended data out */
120 MEM_SDR, /* Single data rate SDRAM */
121 MEM_RDR, /* Registered single data rate SDRAM */
122 MEM_DDR, /* Double data rate SDRAM */
123 MEM_RDDR, /* Registered Double data rate SDRAM */
124 MEM_RMBS /* Rambus DRAM */
125};
126
127#define MEM_FLAG_EMPTY BIT(MEM_EMPTY)
128#define MEM_FLAG_RESERVED BIT(MEM_RESERVED)
129#define MEM_FLAG_UNKNOWN BIT(MEM_UNKNOWN)
130#define MEM_FLAG_FPM BIT(MEM_FPM)
131#define MEM_FLAG_EDO BIT(MEM_EDO)
132#define MEM_FLAG_BEDO BIT(MEM_BEDO)
133#define MEM_FLAG_SDR BIT(MEM_SDR)
134#define MEM_FLAG_RDR BIT(MEM_RDR)
135#define MEM_FLAG_DDR BIT(MEM_DDR)
136#define MEM_FLAG_RDDR BIT(MEM_RDDR)
137#define MEM_FLAG_RMBS BIT(MEM_RMBS)
138
139
140/* chipset Error Detection and Correction capabilities and mode */
141enum edac_type {
142 EDAC_UNKNOWN = 0, /* Unknown if ECC is available */
143 EDAC_NONE, /* Doesnt support ECC */
144 EDAC_RESERVED, /* Reserved ECC type */
145 EDAC_PARITY, /* Detects parity errors */
146 EDAC_EC, /* Error Checking - no correction */
147 EDAC_SECDED, /* Single bit error correction, Double detection */
148 EDAC_S2ECD2ED, /* Chipkill x2 devices - do these exist? */
149 EDAC_S4ECD4ED, /* Chipkill x4 devices */
150 EDAC_S8ECD8ED, /* Chipkill x8 devices */
151 EDAC_S16ECD16ED, /* Chipkill x16 devices */
152};
153
154#define EDAC_FLAG_UNKNOWN BIT(EDAC_UNKNOWN)
155#define EDAC_FLAG_NONE BIT(EDAC_NONE)
156#define EDAC_FLAG_PARITY BIT(EDAC_PARITY)
157#define EDAC_FLAG_EC BIT(EDAC_EC)
158#define EDAC_FLAG_SECDED BIT(EDAC_SECDED)
159#define EDAC_FLAG_S2ECD2ED BIT(EDAC_S2ECD2ED)
160#define EDAC_FLAG_S4ECD4ED BIT(EDAC_S4ECD4ED)
161#define EDAC_FLAG_S8ECD8ED BIT(EDAC_S8ECD8ED)
162#define EDAC_FLAG_S16ECD16ED BIT(EDAC_S16ECD16ED)
163
164
165/* scrubbing capabilities */
166enum scrub_type {
167 SCRUB_UNKNOWN = 0, /* Unknown if scrubber is available */
168 SCRUB_NONE, /* No scrubber */
169 SCRUB_SW_PROG, /* SW progressive (sequential) scrubbing */
170 SCRUB_SW_SRC, /* Software scrub only errors */
171 SCRUB_SW_PROG_SRC, /* Progressive software scrub from an error */
172 SCRUB_SW_TUNABLE, /* Software scrub frequency is tunable */
173 SCRUB_HW_PROG, /* HW progressive (sequential) scrubbing */
174 SCRUB_HW_SRC, /* Hardware scrub only errors */
175 SCRUB_HW_PROG_SRC, /* Progressive hardware scrub from an error */
176 SCRUB_HW_TUNABLE /* Hardware scrub frequency is tunable */
177};
178
179#define SCRUB_FLAG_SW_PROG BIT(SCRUB_SW_PROG)
180#define SCRUB_FLAG_SW_SRC BIT(SCRUB_SW_SRC_CORR)
181#define SCRUB_FLAG_SW_PROG_SRC BIT(SCRUB_SW_PROG_SRC_CORR)
182#define SCRUB_FLAG_SW_TUN BIT(SCRUB_SW_SCRUB_TUNABLE)
183#define SCRUB_FLAG_HW_PROG BIT(SCRUB_HW_PROG)
184#define SCRUB_FLAG_HW_SRC BIT(SCRUB_HW_SRC_CORR)
185#define SCRUB_FLAG_HW_PROG_SRC BIT(SCRUB_HW_PROG_SRC_CORR)
186#define SCRUB_FLAG_HW_TUN BIT(SCRUB_HW_TUNABLE)
187
188enum mci_sysfs_status {
189 MCI_SYSFS_INACTIVE = 0, /* sysfs entries NOT registered */
190 MCI_SYSFS_ACTIVE /* sysfs entries ARE registered */
191};
192
193/* FIXME - should have notify capabilities: NMI, LOG, PROC, etc */
194
195/*
196 * There are several things to be aware of that aren't at all obvious:
197 *
198 *
199 * SOCKETS, SOCKET SETS, BANKS, ROWS, CHIP-SELECT ROWS, CHANNELS, etc..
200 *
201 * These are some of the many terms that are thrown about that don't always
202 * mean what people think they mean (Inconceivable!). In the interest of
203 * creating a common ground for discussion, terms and their definitions
204 * will be established.
205 *
206 * Memory devices: The individual chip on a memory stick. These devices
207 * commonly output 4 and 8 bits each. Grouping several
208 * of these in parallel provides 64 bits which is common
209 * for a memory stick.
210 *
211 * Memory Stick: A printed circuit board that agregates multiple
212 * memory devices in parallel. This is the atomic
213 * memory component that is purchaseable by Joe consumer
214 * and loaded into a memory socket.
215 *
216 * Socket: A physical connector on the motherboard that accepts
217 * a single memory stick.
218 *
219 * Channel: Set of memory devices on a memory stick that must be
220 * grouped in parallel with one or more additional
221 * channels from other memory sticks. This parallel
222 * grouping of the output from multiple channels are
223 * necessary for the smallest granularity of memory access.
224 * Some memory controllers are capable of single channel -
225 * which means that memory sticks can be loaded
226 * individually. Other memory controllers are only
227 * capable of dual channel - which means that memory
228 * sticks must be loaded as pairs (see "socket set").
229 *
230 * Chip-select row: All of the memory devices that are selected together.
231 * for a single, minimum grain of memory access.
232 * This selects all of the parallel memory devices across
233 * all of the parallel channels. Common chip-select rows
234 * for single channel are 64 bits, for dual channel 128
235 * bits.
236 *
237 * Single-Ranked stick: A Single-ranked stick has 1 chip-select row of memmory.
238 * Motherboards commonly drive two chip-select pins to
239 * a memory stick. A single-ranked stick, will occupy
240 * only one of those rows. The other will be unused.
241 *
242 * Double-Ranked stick: A double-ranked stick has two chip-select rows which
243 * access different sets of memory devices. The two
244 * rows cannot be accessed concurrently.
245 *
246 * Double-sided stick: DEPRECATED TERM, see Double-Ranked stick.
247 * A double-sided stick has two chip-select rows which
248 * access different sets of memory devices. The two
249 * rows cannot be accessed concurrently. "Double-sided"
250 * is irrespective of the memory devices being mounted
251 * on both sides of the memory stick.
252 *
253 * Socket set: All of the memory sticks that are required for for
254 * a single memory access or all of the memory sticks
255 * spanned by a chip-select row. A single socket set
256 * has two chip-select rows and if double-sided sticks
257 * are used these will occupy those chip-select rows.
258 *
259 * Bank: This term is avoided because it is unclear when
260 * needing to distinguish between chip-select rows and
261 * socket sets.
262 *
263 * Controller pages:
264 *
265 * Physical pages:
266 *
267 * Virtual pages:
268 *
269 *
270 * STRUCTURE ORGANIZATION AND CHOICES
271 *
272 *
273 *
274 * PS - I enjoyed writing all that about as much as you enjoyed reading it.
275 */
276
277
278struct channel_info {
279 int chan_idx; /* channel index */
280 u32 ce_count; /* Correctable Errors for this CHANNEL */
281 char label[EDAC_MC_LABEL_LEN + 1]; /* DIMM label on motherboard */
282 struct csrow_info *csrow; /* the parent */
283};
284
285
286struct csrow_info {
287 unsigned long first_page; /* first page number in dimm */
288 unsigned long last_page; /* last page number in dimm */
289 unsigned long page_mask; /* used for interleaving -
290 0UL for non intlv */
291 u32 nr_pages; /* number of pages in csrow */
292 u32 grain; /* granularity of reported error in bytes */
293 int csrow_idx; /* the chip-select row */
294 enum dev_type dtype; /* memory device type */
295 u32 ue_count; /* Uncorrectable Errors for this csrow */
296 u32 ce_count; /* Correctable Errors for this csrow */
297 enum mem_type mtype; /* memory csrow type */
298 enum edac_type edac_mode; /* EDAC mode for this csrow */
299 struct mem_ctl_info *mci; /* the parent */
300
301 struct kobject kobj; /* sysfs kobject for this csrow */
302
303 /* FIXME the number of CHANNELs might need to become dynamic */
304 u32 nr_channels;
305 struct channel_info *channels;
306};
307
308
309struct mem_ctl_info {
310 struct list_head link; /* for global list of mem_ctl_info structs */
311 unsigned long mtype_cap; /* memory types supported by mc */
312 unsigned long edac_ctl_cap; /* Mem controller EDAC capabilities */
313 unsigned long edac_cap; /* configuration capabilities - this is
314 closely related to edac_ctl_cap. The
315 difference is that the controller
316 may be capable of s4ecd4ed which would
317 be listed in edac_ctl_cap, but if
318 channels aren't capable of s4ecd4ed then the
319 edac_cap would not have that capability. */
320 unsigned long scrub_cap; /* chipset scrub capabilities */
321 enum scrub_type scrub_mode; /* current scrub mode */
322
323 enum mci_sysfs_status sysfs_active; /* status of sysfs */
324
325 /* pointer to edac checking routine */
326 void (*edac_check) (struct mem_ctl_info * mci);
327 /*
328 * Remaps memory pages: controller pages to physical pages.
329 * For most MC's, this will be NULL.
330 */
331 /* FIXME - why not send the phys page to begin with? */
332 unsigned long (*ctl_page_to_phys) (struct mem_ctl_info * mci,
333 unsigned long page);
334 int mc_idx;
335 int nr_csrows;
336 struct csrow_info *csrows;
337 /*
338 * FIXME - what about controllers on other busses? - IDs must be
339 * unique. pdev pointer should be sufficiently unique, but
340 * BUS:SLOT.FUNC numbers may not be unique.
341 */
342 struct pci_dev *pdev;
343 const char *mod_name;
344 const char *mod_ver;
345 const char *ctl_name;
346 char proc_name[MC_PROC_NAME_MAX_LEN + 1];
347 void *pvt_info;
348 u32 ue_noinfo_count; /* Uncorrectable Errors w/o info */
349 u32 ce_noinfo_count; /* Correctable Errors w/o info */
350 u32 ue_count; /* Total Uncorrectable Errors for this MC */
351 u32 ce_count; /* Total Correctable Errors for this MC */
352 unsigned long start_time; /* mci load start time (in jiffies) */
353
354 /* this stuff is for safe removal of mc devices from global list while
355 * NMI handlers may be traversing list
356 */
357 struct rcu_head rcu;
358 struct completion complete;
359
360 /* edac sysfs device control */
361 struct kobject edac_mci_kobj;
362};
363
364
365
366/* write all or some bits in a byte-register*/
367static inline void pci_write_bits8(struct pci_dev *pdev, int offset,
368 u8 value, u8 mask)
369{
370 if (mask != 0xff) {
371 u8 buf;
372 pci_read_config_byte(pdev, offset, &buf);
373 value &= mask;
374 buf &= ~mask;
375 value |= buf;
376 }
377 pci_write_config_byte(pdev, offset, value);
378}
379
380
381/* write all or some bits in a word-register*/
382static inline void pci_write_bits16(struct pci_dev *pdev, int offset,
383 u16 value, u16 mask)
384{
385 if (mask != 0xffff) {
386 u16 buf;
387 pci_read_config_word(pdev, offset, &buf);
388 value &= mask;
389 buf &= ~mask;
390 value |= buf;
391 }
392 pci_write_config_word(pdev, offset, value);
393}
394
395
396/* write all or some bits in a dword-register*/
397static inline void pci_write_bits32(struct pci_dev *pdev, int offset,
398 u32 value, u32 mask)
399{
400 if (mask != 0xffff) {
401 u32 buf;
402 pci_read_config_dword(pdev, offset, &buf);
403 value &= mask;
404 buf &= ~mask;
405 value |= buf;
406 }
407 pci_write_config_dword(pdev, offset, value);
408}
409
410
411#ifdef CONFIG_EDAC_DEBUG
412void edac_mc_dump_channel(struct channel_info *chan);
413void edac_mc_dump_mci(struct mem_ctl_info *mci);
414void edac_mc_dump_csrow(struct csrow_info *csrow);
415#endif /* CONFIG_EDAC_DEBUG */
416
417extern int edac_mc_add_mc(struct mem_ctl_info *mci);
418extern int edac_mc_del_mc(struct mem_ctl_info *mci);
419
420extern int edac_mc_find_csrow_by_page(struct mem_ctl_info *mci,
421 unsigned long page);
422
423extern struct mem_ctl_info *edac_mc_find_mci_by_pdev(struct pci_dev
424 *pdev);
425
426extern void edac_mc_scrub_block(unsigned long page,
427 unsigned long offset, u32 size);
428
429/*
430 * The no info errors are used when error overflows are reported.
431 * There are a limited number of error logging registers that can
432 * be exausted. When all registers are exhausted and an additional
433 * error occurs then an error overflow register records that an
434 * error occured and the type of error, but doesn't have any
435 * further information. The ce/ue versions make for cleaner
436 * reporting logic and function interface - reduces conditional
437 * statement clutter and extra function arguments.
438 */
439extern void edac_mc_handle_ce(struct mem_ctl_info *mci,
440 unsigned long page_frame_number,
441 unsigned long offset_in_page,
442 unsigned long syndrome,
443 int row, int channel, const char *msg);
444
445extern void edac_mc_handle_ce_no_info(struct mem_ctl_info *mci,
446 const char *msg);
447
448extern void edac_mc_handle_ue(struct mem_ctl_info *mci,
449 unsigned long page_frame_number,
450 unsigned long offset_in_page,
451 int row, const char *msg);
452
453extern void edac_mc_handle_ue_no_info(struct mem_ctl_info *mci,
454 const char *msg);
455
456/*
457 * This kmalloc's and initializes all the structures.
458 * Can't be used if all structures don't have the same lifetime.
459 */
460extern struct mem_ctl_info *edac_mc_alloc(unsigned sz_pvt,
461 unsigned nr_csrows, unsigned nr_chans);
462
463/* Free an mc previously allocated by edac_mc_alloc() */
464extern void edac_mc_free(struct mem_ctl_info *mci);
465
466
467#endif /* _EDAC_MC_H_ */