[mirror_ubuntu-bionic-kernel.git] / drivers / edac / fsl_ddr_edac.c

/*
 * Freescale Memory Controller kernel module
 *
 * Support Power-based SoCs including MPC85xx, MPC86xx, MPC83xx and
 * ARM-based Layerscape SoCs including LS2xxx. Originally split
 * out from mpc85xx_edac EDAC driver.
 *
 * Parts Copyrighted (c) 2013 by Freescale Semiconductor, Inc.
 *
 * Author: Dave Jiang <djiang@mvista.com>
 *
 * 2006-2007 (c) MontaVista Software, Inc. This file is licensed under
 * the terms of the GNU General Public License version 2. This program
 * is licensed "as is" without any warranty of any kind, whether express
 * or implied.
 */
#include <linux/module.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/ctype.h>
#include <linux/io.h>
#include <linux/mod_devicetable.h>
#include <linux/edac.h>
#include <linux/smp.h>
#include <linux/gfp.h>

#include <linux/of_platform.h>
#include <linux/of_device.h>
#include "edac_module.h"
#include "edac_core.h"
#include "fsl_ddr_edac.h"

#define EDAC_MOD_STR	"fsl_ddr_edac"

static int edac_mc_idx;

static u32 orig_ddr_err_disable;
static u32 orig_ddr_err_sbe;
static bool little_endian;

static inline u32 ddr_in32(void __iomem *addr)
{
	return little_endian ? ioread32(addr) : ioread32be(addr);
}

static inline void ddr_out32(void __iomem *addr, u32 value)
{
	if (little_endian)
		iowrite32(value, addr);
	else
		iowrite32be(value, addr);
}

/************************ MC SYSFS parts ***********************************/

#define to_mci(k) container_of(k, struct mem_ctl_info, dev)

static ssize_t fsl_mc_inject_data_hi_show(struct device *dev,
					  struct device_attribute *mattr,
					  char *data)
{
	struct mem_ctl_info *mci = to_mci(dev);
	struct fsl_mc_pdata *pdata = mci->pvt_info;
	return sprintf(data, "0x%08x",
		       ddr_in32(pdata->mc_vbase + FSL_MC_DATA_ERR_INJECT_HI));
}

static ssize_t fsl_mc_inject_data_lo_show(struct device *dev,
					  struct device_attribute *mattr,
					      char *data)
{
	struct mem_ctl_info *mci = to_mci(dev);
	struct fsl_mc_pdata *pdata = mci->pvt_info;
	return sprintf(data, "0x%08x",
		       ddr_in32(pdata->mc_vbase + FSL_MC_DATA_ERR_INJECT_LO));
}

static ssize_t fsl_mc_inject_ctrl_show(struct device *dev,
				       struct device_attribute *mattr,
					   char *data)
{
	struct mem_ctl_info *mci = to_mci(dev);
	struct fsl_mc_pdata *pdata = mci->pvt_info;
	return sprintf(data, "0x%08x",
		       ddr_in32(pdata->mc_vbase + FSL_MC_ECC_ERR_INJECT));
}

static ssize_t fsl_mc_inject_data_hi_store(struct device *dev,
					   struct device_attribute *mattr,
					       const char *data, size_t count)
{
	struct mem_ctl_info *mci = to_mci(dev);
	struct fsl_mc_pdata *pdata = mci->pvt_info;
	if (isdigit(*data)) {
		ddr_out32(pdata->mc_vbase + FSL_MC_DATA_ERR_INJECT_HI,
			  simple_strtoul(data, NULL, 0));
		return count;
	}
	return 0;
}

static ssize_t fsl_mc_inject_data_lo_store(struct device *dev,
					   struct device_attribute *mattr,
					       const char *data, size_t count)
{
	struct mem_ctl_info *mci = to_mci(dev);
	struct fsl_mc_pdata *pdata = mci->pvt_info;
	if (isdigit(*data)) {
		ddr_out32(pdata->mc_vbase + FSL_MC_DATA_ERR_INJECT_LO,
			  simple_strtoul(data, NULL, 0));
		return count;
	}
	return 0;
}

static ssize_t fsl_mc_inject_ctrl_store(struct device *dev,
					struct device_attribute *mattr,
					       const char *data, size_t count)
{
	struct mem_ctl_info *mci = to_mci(dev);
	struct fsl_mc_pdata *pdata = mci->pvt_info;
	if (isdigit(*data)) {
		ddr_out32(pdata->mc_vbase + FSL_MC_ECC_ERR_INJECT,
			  simple_strtoul(data, NULL, 0));
		return count;
	}
	return 0;
}

DEVICE_ATTR(inject_data_hi, S_IRUGO | S_IWUSR,
	    fsl_mc_inject_data_hi_show, fsl_mc_inject_data_hi_store);
DEVICE_ATTR(inject_data_lo, S_IRUGO | S_IWUSR,
	    fsl_mc_inject_data_lo_show, fsl_mc_inject_data_lo_store);
DEVICE_ATTR(inject_ctrl, S_IRUGO | S_IWUSR,
	    fsl_mc_inject_ctrl_show, fsl_mc_inject_ctrl_store);

static struct attribute *fsl_ddr_dev_attrs[] = {
	&dev_attr_inject_data_hi.attr,
	&dev_attr_inject_data_lo.attr,
	&dev_attr_inject_ctrl.attr,
	NULL
};

ATTRIBUTE_GROUPS(fsl_ddr_dev);

/**************************** MC Err device ***************************/

/*
 * Taken from table 8-55 in the MPC8641 User's Manual and/or 9-61 in the
 * MPC8572 User's Manual.  Each line represents a syndrome bit column as a
 * 64-bit value, but split into an upper and lower 32-bit chunk.  The labels
 * below correspond to Freescale's manuals.
 */
static unsigned int ecc_table[16] = {
	/* MSB           LSB */
	/* [0:31]    [32:63] */
	0xf00fe11e, 0xc33c0ff7,	/* Syndrome bit 7 */
	0x00ff00ff, 0x00fff0ff,
	0x0f0f0f0f, 0x0f0fff00,
	0x11113333, 0x7777000f,
	0x22224444, 0x8888222f,
	0x44448888, 0xffff4441,
	0x8888ffff, 0x11118882,
	0xffff1111, 0x22221114,	/* Syndrome bit 0 */
};

/*
 * Calculate the correct ECC value for a 64-bit value specified by high:low
 */
static u8 calculate_ecc(u32 high, u32 low)
{
	u32 mask_low;
	u32 mask_high;
	int bit_cnt;
	u8 ecc = 0;
	int i;
	int j;

	for (i = 0; i < 8; i++) {
		mask_high = ecc_table[i * 2];
		mask_low = ecc_table[i * 2 + 1];
		bit_cnt = 0;

		for (j = 0; j < 32; j++) {
			if ((mask_high >> j) & 1)
				bit_cnt ^= (high >> j) & 1;
			if ((mask_low >> j) & 1)
				bit_cnt ^= (low >> j) & 1;
		}

		ecc |= bit_cnt << i;
	}

	return ecc;
}

/*
 * Create the syndrome code which is generated if the data line specified by
 * 'bit' failed.  Eg generate an 8-bit codes seen in Table 8-55 in the MPC8641
 * User's Manual and 9-61 in the MPC8572 User's Manual.
 */
static u8 syndrome_from_bit(unsigned int bit) {
	int i;
	u8 syndrome = 0;

	/*
	 * Cycle through the upper or lower 32-bit portion of each value in
	 * ecc_table depending on if 'bit' is in the upper or lower half of
	 * 64-bit data.
	 */
	for (i = bit < 32; i < 16; i += 2)
		syndrome |= ((ecc_table[i] >> (bit % 32)) & 1) << (i / 2);

	return syndrome;
}

/*
 * Decode data and ecc syndrome to determine what went wrong
 * Note: This can only decode single-bit errors
 */
static void sbe_ecc_decode(u32 cap_high, u32 cap_low, u32 cap_ecc,
		       int *bad_data_bit, int *bad_ecc_bit)
{
	int i;
	u8 syndrome;

	*bad_data_bit = -1;
	*bad_ecc_bit = -1;

	/*
	 * Calculate the ECC of the captured data and XOR it with the captured
	 * ECC to find an ECC syndrome value we can search for
	 */
	syndrome = calculate_ecc(cap_high, cap_low) ^ cap_ecc;

	/* Check if a data line is stuck... */
	for (i = 0; i < 64; i++) {
		if (syndrome == syndrome_from_bit(i)) {
			*bad_data_bit = i;
			return;
		}
	}

	/* If data is correct, check ECC bits for errors... */
	for (i = 0; i < 8; i++) {
		if ((syndrome >> i) & 0x1) {
			*bad_ecc_bit = i;
			return;
		}
	}
}

#define make64(high, low) (((u64)(high) << 32) | (low))

static void fsl_mc_check(struct mem_ctl_info *mci)
{
	struct fsl_mc_pdata *pdata = mci->pvt_info;
	struct csrow_info *csrow;
	u32 bus_width;
	u32 err_detect;
	u32 syndrome;
	u64 err_addr;
	u32 pfn;
	int row_index;
	u32 cap_high;
	u32 cap_low;
	int bad_data_bit;
	int bad_ecc_bit;

	err_detect = ddr_in32(pdata->mc_vbase + FSL_MC_ERR_DETECT);
	if (!err_detect)
		return;

	fsl_mc_printk(mci, KERN_ERR, "Err Detect Register: %#8.8x\n",
		      err_detect);

	/* no more processing if not ECC bit errors */
	if (!(err_detect & (DDR_EDE_SBE | DDR_EDE_MBE))) {
		ddr_out32(pdata->mc_vbase + FSL_MC_ERR_DETECT, err_detect);
		return;
	}

	syndrome = ddr_in32(pdata->mc_vbase + FSL_MC_CAPTURE_ECC);

	/* Mask off appropriate bits of syndrome based on bus width */
	bus_width = (ddr_in32(pdata->mc_vbase + FSL_MC_DDR_SDRAM_CFG) &
		     DSC_DBW_MASK) ? 32 : 64;
	if (bus_width == 64)
		syndrome &= 0xff;
	else
		syndrome &= 0xffff;

	err_addr = make64(
		ddr_in32(pdata->mc_vbase + FSL_MC_CAPTURE_EXT_ADDRESS),
		ddr_in32(pdata->mc_vbase + FSL_MC_CAPTURE_ADDRESS));
	pfn = err_addr >> PAGE_SHIFT;

	for (row_index = 0; row_index < mci->nr_csrows; row_index++) {
		csrow = mci->csrows[row_index];
		if ((pfn >= csrow->first_page) && (pfn <= csrow->last_page))
			break;
	}

	cap_high = ddr_in32(pdata->mc_vbase + FSL_MC_CAPTURE_DATA_HI);
	cap_low = ddr_in32(pdata->mc_vbase + FSL_MC_CAPTURE_DATA_LO);

	/*
	 * Analyze single-bit errors on 64-bit wide buses
	 * TODO: Add support for 32-bit wide buses
	 */
	if ((err_detect & DDR_EDE_SBE) && (bus_width == 64)) {
		sbe_ecc_decode(cap_high, cap_low, syndrome,
				&bad_data_bit, &bad_ecc_bit);

		if (bad_data_bit != -1)
			fsl_mc_printk(mci, KERN_ERR,
				"Faulty Data bit: %d\n", bad_data_bit);
		if (bad_ecc_bit != -1)
			fsl_mc_printk(mci, KERN_ERR,
				"Faulty ECC bit: %d\n", bad_ecc_bit);

		fsl_mc_printk(mci, KERN_ERR,
			"Expected Data / ECC:\t%#8.8x_%08x / %#2.2x\n",
			cap_high ^ (1 << (bad_data_bit - 32)),
			cap_low ^ (1 << bad_data_bit),
			syndrome ^ (1 << bad_ecc_bit));
	}

	fsl_mc_printk(mci, KERN_ERR,
			"Captured Data / ECC:\t%#8.8x_%08x / %#2.2x\n",
			cap_high, cap_low, syndrome);
	fsl_mc_printk(mci, KERN_ERR, "Err addr: %#8.8llx\n", err_addr);
	fsl_mc_printk(mci, KERN_ERR, "PFN: %#8.8x\n", pfn);

	/* we are out of range */
	if (row_index == mci->nr_csrows)
		fsl_mc_printk(mci, KERN_ERR, "PFN out of range!\n");

	if (err_detect & DDR_EDE_SBE)
		edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
				     pfn, err_addr & ~PAGE_MASK, syndrome,
				     row_index, 0, -1,
				     mci->ctl_name, "");

	if (err_detect & DDR_EDE_MBE)
		edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
				     pfn, err_addr & ~PAGE_MASK, syndrome,
				     row_index, 0, -1,
				     mci->ctl_name, "");

	ddr_out32(pdata->mc_vbase + FSL_MC_ERR_DETECT, err_detect);
}

static irqreturn_t fsl_mc_isr(int irq, void *dev_id)
{
	struct mem_ctl_info *mci = dev_id;
	struct fsl_mc_pdata *pdata = mci->pvt_info;
	u32 err_detect;

	err_detect = ddr_in32(pdata->mc_vbase + FSL_MC_ERR_DETECT);
	if (!err_detect)
		return IRQ_NONE;

	fsl_mc_check(mci);

	return IRQ_HANDLED;
}

static void fsl_ddr_init_csrows(struct mem_ctl_info *mci)
{
	struct fsl_mc_pdata *pdata = mci->pvt_info;
	struct csrow_info *csrow;
	struct dimm_info *dimm;
	u32 sdram_ctl;
	u32 sdtype;
	enum mem_type mtype;
	u32 cs_bnds;
	int index;

	sdram_ctl = ddr_in32(pdata->mc_vbase + FSL_MC_DDR_SDRAM_CFG);

	sdtype = sdram_ctl & DSC_SDTYPE_MASK;
	if (sdram_ctl & DSC_RD_EN) {
		switch (sdtype) {
		case 0x02000000:
			mtype = MEM_RDDR;
			break;
		case 0x03000000:
			mtype = MEM_RDDR2;
			break;
		case 0x07000000:
			mtype = MEM_RDDR3;
			break;
		case 0x05000000:
			mtype = MEM_RDDR4;
			break;
		default:
			mtype = MEM_UNKNOWN;
			break;
		}
	} else {
		switch (sdtype) {
		case 0x02000000:
			mtype = MEM_DDR;
			break;
		case 0x03000000:
			mtype = MEM_DDR2;
			break;
		case 0x07000000:
			mtype = MEM_DDR3;
			break;
		case 0x05000000:
			mtype = MEM_DDR4;
			break;
		default:
			mtype = MEM_UNKNOWN;
			break;
		}
	}

	for (index = 0; index < mci->nr_csrows; index++) {
		u32 start;
		u32 end;

		csrow = mci->csrows[index];
		dimm = csrow->channels[0]->dimm;

		cs_bnds = ddr_in32(pdata->mc_vbase + FSL_MC_CS_BNDS_0 +
				   (index * FSL_MC_CS_BNDS_OFS));

		start = (cs_bnds & 0xffff0000) >> 16;
		end   = (cs_bnds & 0x0000ffff);

		if (start == end)
			continue;	/* not populated */

		start <<= (24 - PAGE_SHIFT);
		end   <<= (24 - PAGE_SHIFT);
		end    |= (1 << (24 - PAGE_SHIFT)) - 1;

		csrow->first_page = start;
		csrow->last_page = end;

		dimm->nr_pages = end + 1 - start;
		dimm->grain = 8;
		dimm->mtype = mtype;
		dimm->dtype = DEV_UNKNOWN;
		if (sdram_ctl & DSC_X32_EN)
			dimm->dtype = DEV_X32;
		dimm->edac_mode = EDAC_SECDED;
	}
}

int fsl_mc_err_probe(struct platform_device *op)
{
	struct mem_ctl_info *mci;
	struct edac_mc_layer layers[2];
	struct fsl_mc_pdata *pdata;
	struct resource r;
	u32 sdram_ctl;
	int res;

	if (!devres_open_group(&op->dev, fsl_mc_err_probe, GFP_KERNEL))
		return -ENOMEM;

	layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
	layers[0].size = 4;
	layers[0].is_virt_csrow = true;
	layers[1].type = EDAC_MC_LAYER_CHANNEL;
	layers[1].size = 1;
	layers[1].is_virt_csrow = false;
	mci = edac_mc_alloc(edac_mc_idx, ARRAY_SIZE(layers), layers,
			    sizeof(*pdata));
	if (!mci) {
		devres_release_group(&op->dev, fsl_mc_err_probe);
		return -ENOMEM;
	}

	pdata = mci->pvt_info;
	pdata->name = "fsl_mc_err";
	pdata->irq = NO_IRQ;
	mci->pdev = &op->dev;
	pdata->edac_idx = edac_mc_idx++;
	dev_set_drvdata(mci->pdev, mci);
	mci->ctl_name = pdata->name;
	mci->dev_name = pdata->name;

	/*
	 * Get the endianness of DDR controller registers.
	 * Default is big endian.
	 */
	little_endian = of_property_read_bool(op->dev.of_node, "little-endian");

	res = of_address_to_resource(op->dev.of_node, 0, &r);
	if (res) {
		pr_err("%s: Unable to get resource for MC err regs\n",
		       __func__);
		goto err;
	}

	if (!devm_request_mem_region(&op->dev, r.start, resource_size(&r),
				     pdata->name)) {
		pr_err("%s: Error while requesting mem region\n",
		       __func__);
		res = -EBUSY;
		goto err;
	}

	pdata->mc_vbase = devm_ioremap(&op->dev, r.start, resource_size(&r));
	if (!pdata->mc_vbase) {
		pr_err("%s: Unable to setup MC err regs\n", __func__);
		res = -ENOMEM;
		goto err;
	}

	sdram_ctl = ddr_in32(pdata->mc_vbase + FSL_MC_DDR_SDRAM_CFG);
	if (!(sdram_ctl & DSC_ECC_EN)) {
		/* no ECC */
		pr_warn("%s: No ECC DIMMs discovered\n", __func__);
		res = -ENODEV;
		goto err;
	}

	edac_dbg(3, "init mci\n");
	mci->mtype_cap = MEM_FLAG_DDR | MEM_FLAG_RDDR |
			 MEM_FLAG_DDR2 | MEM_FLAG_RDDR2 |
			 MEM_FLAG_DDR3 | MEM_FLAG_RDDR3 |
			 MEM_FLAG_DDR4 | MEM_FLAG_RDDR4;
	mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
	mci->edac_cap = EDAC_FLAG_SECDED;
	mci->mod_name = EDAC_MOD_STR;

	if (edac_op_state == EDAC_OPSTATE_POLL)
		mci->edac_check = fsl_mc_check;

	mci->ctl_page_to_phys = NULL;

	mci->scrub_mode = SCRUB_SW_SRC;

	fsl_ddr_init_csrows(mci);

	/* store the original error disable bits */
	orig_ddr_err_disable = ddr_in32(pdata->mc_vbase + FSL_MC_ERR_DISABLE);
	ddr_out32(pdata->mc_vbase + FSL_MC_ERR_DISABLE, 0);

	/* clear all error bits */
	ddr_out32(pdata->mc_vbase + FSL_MC_ERR_DETECT, ~0);

	if (edac_mc_add_mc_with_groups(mci, fsl_ddr_dev_groups)) {
		edac_dbg(3, "failed edac_mc_add_mc()\n");
		goto err;
	}

	if (edac_op_state == EDAC_OPSTATE_INT) {
		ddr_out32(pdata->mc_vbase + FSL_MC_ERR_INT_EN,
			  DDR_EIE_MBEE | DDR_EIE_SBEE);

		/* store the original error management threshold */
		orig_ddr_err_sbe = ddr_in32(pdata->mc_vbase +
					    FSL_MC_ERR_SBE) & 0xff0000;

		/* set threshold to 1 error per interrupt */
		ddr_out32(pdata->mc_vbase + FSL_MC_ERR_SBE, 0x10000);

		/* register interrupts */
		pdata->irq = platform_get_irq(op, 0);
		res = devm_request_irq(&op->dev, pdata->irq,
				       fsl_mc_isr,
				       IRQF_SHARED,
				       "[EDAC] MC err", mci);
		if (res < 0) {
			pr_err("%s: Unable to request irq %d for FSL DDR DRAM ERR\n",
			       __func__, pdata->irq);
			res = -ENODEV;
			goto err2;
		}

		pr_info(EDAC_MOD_STR " acquired irq %d for MC\n",
		       pdata->irq);
	}

	devres_remove_group(&op->dev, fsl_mc_err_probe);
	edac_dbg(3, "success\n");
	pr_info(EDAC_MOD_STR " MC err registered\n");

	return 0;

err2:
	edac_mc_del_mc(&op->dev);
err:
	devres_release_group(&op->dev, fsl_mc_err_probe);
	edac_mc_free(mci);
	return res;
}

int fsl_mc_err_remove(struct platform_device *op)
{
	struct mem_ctl_info *mci = dev_get_drvdata(&op->dev);
	struct fsl_mc_pdata *pdata = mci->pvt_info;

	edac_dbg(0, "\n");

	if (edac_op_state == EDAC_OPSTATE_INT) {
		ddr_out32(pdata->mc_vbase + FSL_MC_ERR_INT_EN, 0);
	}

	ddr_out32(pdata->mc_vbase + FSL_MC_ERR_DISABLE,
		  orig_ddr_err_disable);
	ddr_out32(pdata->mc_vbase + FSL_MC_ERR_SBE, orig_ddr_err_sbe);

	edac_mc_del_mc(&op->dev);
	edac_mc_free(mci);
	return 0;
}
Commit	Line	Data
ea2eb9a8 YS	1	/*
	2	* Freescale Memory Controller kernel module
	3	*
	4	* Support Power-based SoCs including MPC85xx, MPC86xx, MPC83xx and
	5	* ARM-based Layerscape SoCs including LS2xxx. Originally split
	6	* out from mpc85xx_edac EDAC driver.
	7	*
	8	* Parts Copyrighted (c) 2013 by Freescale Semiconductor, Inc.
	9	*
	10	* Author: Dave Jiang <djiang@mvista.com>
	11	*
	12	* 2006-2007 (c) MontaVista Software, Inc. This file is licensed under
	13	* the terms of the GNU General Public License version 2. This program
	14	* is licensed "as is" without any warranty of any kind, whether express
	15	* or implied.
ea2eb9a8 YS	16	*/
	17	#include <linux/module.h>
	18	#include <linux/init.h>
	19	#include <linux/interrupt.h>
	20	#include <linux/ctype.h>
	21	#include <linux/io.h>
	22	#include <linux/mod_devicetable.h>
	23	#include <linux/edac.h>
	24	#include <linux/smp.h>
	25	#include <linux/gfp.h>
	26
	27	#include <linux/of_platform.h>
	28	#include <linux/of_device.h>
	29	#include "edac_module.h"
	30	#include "edac_core.h"
	31	#include "fsl_ddr_edac.h"
	32
	33	#define EDAC_MOD_STR "fsl_ddr_edac"
	34
	35	static int edac_mc_idx;
	36
	37	static u32 orig_ddr_err_disable;
	38	static u32 orig_ddr_err_sbe;
339fdff1 YS	39	static bool little_endian;
	40
	41	static inline u32 ddr_in32(void __iomem *addr)
	42	{
	43	return little_endian ? ioread32(addr) : ioread32be(addr);
	44	}
	45
	46	static inline void ddr_out32(void __iomem *addr, u32 value)
	47	{
	48	if (little_endian)
	49	iowrite32(value, addr);
	50	else
	51	iowrite32be(value, addr);
	52	}
ea2eb9a8 YS	53
	54	/********************** MC SYSFS parts *********************************/
	55
	56	#define to_mci(k) container_of(k, struct mem_ctl_info, dev)
	57
d43a9fb2 YS	58	static ssize_t fsl_mc_inject_data_hi_show(struct device *dev,
	59	struct device_attribute *mattr,
	60	char *data)
ea2eb9a8 YS	61	{
ea2eb9a8 YS	62	struct mem_ctl_info *mci = to_mci(dev);
d43a9fb2	63	struct fsl_mc_pdata *pdata = mci->pvt_info;
ea2eb9a8	64	return sprintf(data, "0x%08x",
339fdff1	65	ddr_in32(pdata->mc_vbase + FSL_MC_DATA_ERR_INJECT_HI));
ea2eb9a8 YS	66	}
ea2eb9a8 YS	67
d43a9fb2 YS	68	static ssize_t fsl_mc_inject_data_lo_show(struct device *dev,
d43a9fb2 YS	69	struct device_attribute *mattr,
ea2eb9a8 YS	70	char *data)
	71	{
	72	struct mem_ctl_info *mci = to_mci(dev);
d43a9fb2	73	struct fsl_mc_pdata *pdata = mci->pvt_info;
ea2eb9a8	74	return sprintf(data, "0x%08x",
339fdff1	75	ddr_in32(pdata->mc_vbase + FSL_MC_DATA_ERR_INJECT_LO));
ea2eb9a8 YS	76	}
ea2eb9a8 YS	77
d43a9fb2 YS	78	static ssize_t fsl_mc_inject_ctrl_show(struct device *dev,
d43a9fb2 YS	79	struct device_attribute *mattr,
ea2eb9a8 YS	80	char *data)
	81	{
	82	struct mem_ctl_info *mci = to_mci(dev);
d43a9fb2	83	struct fsl_mc_pdata *pdata = mci->pvt_info;
ea2eb9a8	84	return sprintf(data, "0x%08x",
339fdff1	85	ddr_in32(pdata->mc_vbase + FSL_MC_ECC_ERR_INJECT));
ea2eb9a8 YS	86	}
ea2eb9a8 YS	87
d43a9fb2 YS	88	static ssize_t fsl_mc_inject_data_hi_store(struct device *dev,
d43a9fb2 YS	89	struct device_attribute *mattr,
ea2eb9a8 YS	90	const char *data, size_t count)
	91	{
	92	struct mem_ctl_info *mci = to_mci(dev);
d43a9fb2	93	struct fsl_mc_pdata *pdata = mci->pvt_info;
ea2eb9a8	94	if (isdigit(*data)) {
339fdff1 YS	95	ddr_out32(pdata->mc_vbase + FSL_MC_DATA_ERR_INJECT_HI,
339fdff1 YS	96	simple_strtoul(data, NULL, 0));
ea2eb9a8 YS	97	return count;
	98	}
	99	return 0;
	100	}
	101
d43a9fb2 YS	102	static ssize_t fsl_mc_inject_data_lo_store(struct device *dev,
d43a9fb2 YS	103	struct device_attribute *mattr,
ea2eb9a8 YS	104	const char *data, size_t count)
	105	{
	106	struct mem_ctl_info *mci = to_mci(dev);
d43a9fb2	107	struct fsl_mc_pdata *pdata = mci->pvt_info;
ea2eb9a8	108	if (isdigit(*data)) {
339fdff1 YS	109	ddr_out32(pdata->mc_vbase + FSL_MC_DATA_ERR_INJECT_LO,
339fdff1 YS	110	simple_strtoul(data, NULL, 0));
ea2eb9a8 YS	111	return count;
	112	}
	113	return 0;
	114	}
	115
d43a9fb2 YS	116	static ssize_t fsl_mc_inject_ctrl_store(struct device *dev,
d43a9fb2 YS	117	struct device_attribute *mattr,
ea2eb9a8 YS	118	const char *data, size_t count)
	119	{
	120	struct mem_ctl_info *mci = to_mci(dev);
d43a9fb2	121	struct fsl_mc_pdata *pdata = mci->pvt_info;
ea2eb9a8	122	if (isdigit(*data)) {
339fdff1 YS	123	ddr_out32(pdata->mc_vbase + FSL_MC_ECC_ERR_INJECT,
339fdff1 YS	124	simple_strtoul(data, NULL, 0));
ea2eb9a8 YS	125	return count;
	126	}
	127	return 0;
	128	}
	129
	130	DEVICE_ATTR(inject_data_hi, S_IRUGO \| S_IWUSR,
d43a9fb2	131	fsl_mc_inject_data_hi_show, fsl_mc_inject_data_hi_store);
ea2eb9a8	132	DEVICE_ATTR(inject_data_lo, S_IRUGO \| S_IWUSR,
d43a9fb2	133	fsl_mc_inject_data_lo_show, fsl_mc_inject_data_lo_store);
ea2eb9a8	134	DEVICE_ATTR(inject_ctrl, S_IRUGO \| S_IWUSR,
d43a9fb2	135	fsl_mc_inject_ctrl_show, fsl_mc_inject_ctrl_store);
ea2eb9a8	136
d43a9fb2	137	static struct attribute *fsl_ddr_dev_attrs[] = {
ea2eb9a8 YS	138	&dev_attr_inject_data_hi.attr,
	139	&dev_attr_inject_data_lo.attr,
	140	&dev_attr_inject_ctrl.attr,
	141	NULL
	142	};
	143
d43a9fb2	144	ATTRIBUTE_GROUPS(fsl_ddr_dev);
ea2eb9a8 YS	145
	146	/************************** MC Err device *************************/
	147
	148	/*
	149	* Taken from table 8-55 in the MPC8641 User's Manual and/or 9-61 in the
	150	* MPC8572 User's Manual. Each line represents a syndrome bit column as a
	151	* 64-bit value, but split into an upper and lower 32-bit chunk. The labels
	152	* below correspond to Freescale's manuals.
	153	*/
	154	static unsigned int ecc_table[16] = {
	155	/* MSB LSB */
	156	/* [0:31] [32:63] */
	157	0xf00fe11e, 0xc33c0ff7, /* Syndrome bit 7 */
	158	0x00ff00ff, 0x00fff0ff,
	159	0x0f0f0f0f, 0x0f0fff00,
	160	0x11113333, 0x7777000f,
	161	0x22224444, 0x8888222f,
	162	0x44448888, 0xffff4441,
	163	0x8888ffff, 0x11118882,
	164	0xffff1111, 0x22221114, /* Syndrome bit 0 */
	165	};
	166
	167	/*
	168	* Calculate the correct ECC value for a 64-bit value specified by high:low
	169	*/
	170	static u8 calculate_ecc(u32 high, u32 low)
	171	{
	172	u32 mask_low;
	173	u32 mask_high;
	174	int bit_cnt;
	175	u8 ecc = 0;
	176	int i;
	177	int j;
	178
	179	for (i = 0; i < 8; i++) {
	180	mask_high = ecc_table[i * 2];
	181	mask_low = ecc_table[i * 2 + 1];
	182	bit_cnt = 0;
	183
	184	for (j = 0; j < 32; j++) {
	185	if ((mask_high >> j) & 1)
	186	bit_cnt ^= (high >> j) & 1;
	187	if ((mask_low >> j) & 1)
	188	bit_cnt ^= (low >> j) & 1;
	189	}
	190
	191	ecc \|= bit_cnt << i;
	192	}
	193
	194	return ecc;
	195	}
	196
	197	/*
	198	* Create the syndrome code which is generated if the data line specified by
	199	* 'bit' failed. Eg generate an 8-bit codes seen in Table 8-55 in the MPC8641
	200	* User's Manual and 9-61 in the MPC8572 User's Manual.
	201	*/
	202	static u8 syndrome_from_bit(unsigned int bit) {
	203	int i;
	204	u8 syndrome = 0;
	205
	206	/*
	207	* Cycle through the upper or lower 32-bit portion of each value in
	208	* ecc_table depending on if 'bit' is in the upper or lower half of
209	* 64-bit data.
210	*/
211	for (i = bit < 32; i < 16; i += 2)
212	syndrome \|= ((ecc_table[i] >> (bit % 32)) & 1) << (i / 2);
213
214	return syndrome;
215	}
216
217	/*
218	* Decode data and ecc syndrome to determine what went wrong
219	* Note: This can only decode single-bit errors
220	*/
221	static void sbe_ecc_decode(u32 cap_high, u32 cap_low, u32 cap_ecc,
222	int bad_data_bit, int bad_ecc_bit)
223	{
224	int i;
225	u8 syndrome;
226
227	*bad_data_bit = -1;
228	*bad_ecc_bit = -1;
229
230	/*
231	* Calculate the ECC of the captured data and XOR it with the captured
232	* ECC to find an ECC syndrome value we can search for
233	*/
234	syndrome = calculate_ecc(cap_high, cap_low) ^ cap_ecc;
235
236	/* Check if a data line is stuck... */
237	for (i = 0; i < 64; i++) {
238	if (syndrome == syndrome_from_bit(i)) {
239	*bad_data_bit = i;
240	return;
241	}
242	}
243
244	/* If data is correct, check ECC bits for errors... */
245	for (i = 0; i < 8; i++) {
246	if ((syndrome >> i) & 0x1) {
247	*bad_ecc_bit = i;
248	return;
249	}
250	}
251	}
252
253	#define make64(high, low) (((u64)(high) << 32) \| (low))
254
d43a9fb2	255	static void fsl_mc_check(struct mem_ctl_info *mci)
ea2eb9a8	256	{
d43a9fb2	257	struct fsl_mc_pdata *pdata = mci->pvt_info;
ea2eb9a8 YS	258	struct csrow_info *csrow;
	259	u32 bus_width;
	260	u32 err_detect;
	261	u32 syndrome;
	262	u64 err_addr;
	263	u32 pfn;
	264	int row_index;
	265	u32 cap_high;
	266	u32 cap_low;
	267	int bad_data_bit;
	268	int bad_ecc_bit;
	269
339fdff1	270	err_detect = ddr_in32(pdata->mc_vbase + FSL_MC_ERR_DETECT);
ea2eb9a8 YS	271	if (!err_detect)
	272	return;
	273
d43a9fb2 YS	274	fsl_mc_printk(mci, KERN_ERR, "Err Detect Register: %#8.8x\n",
d43a9fb2 YS	275	err_detect);
ea2eb9a8 YS	276
	277	/* no more processing if not ECC bit errors */
	278	if (!(err_detect & (DDR_EDE_SBE \| DDR_EDE_MBE))) {
339fdff1	279	ddr_out32(pdata->mc_vbase + FSL_MC_ERR_DETECT, err_detect);
ea2eb9a8 YS	280	return;
	281	}
	282
339fdff1	283	syndrome = ddr_in32(pdata->mc_vbase + FSL_MC_CAPTURE_ECC);
ea2eb9a8 YS	284
ea2eb9a8 YS	285	/* Mask off appropriate bits of syndrome based on bus width */
339fdff1 YS	286	bus_width = (ddr_in32(pdata->mc_vbase + FSL_MC_DDR_SDRAM_CFG) &
339fdff1 YS	287	DSC_DBW_MASK) ? 32 : 64;
ea2eb9a8 YS	288	if (bus_width == 64)
	289	syndrome &= 0xff;
	290	else
	291	syndrome &= 0xffff;
	292
	293	err_addr = make64(
339fdff1 YS	294	ddr_in32(pdata->mc_vbase + FSL_MC_CAPTURE_EXT_ADDRESS),
339fdff1 YS	295	ddr_in32(pdata->mc_vbase + FSL_MC_CAPTURE_ADDRESS));
ea2eb9a8 YS	296	pfn = err_addr >> PAGE_SHIFT;
	297
	298	for (row_index = 0; row_index < mci->nr_csrows; row_index++) {
	299	csrow = mci->csrows[row_index];
	300	if ((pfn >= csrow->first_page) && (pfn <= csrow->last_page))
	301	break;
	302	}
	303
339fdff1 YS	304	cap_high = ddr_in32(pdata->mc_vbase + FSL_MC_CAPTURE_DATA_HI);
339fdff1 YS	305	cap_low = ddr_in32(pdata->mc_vbase + FSL_MC_CAPTURE_DATA_LO);
ea2eb9a8 YS	306
	307	/*
	308	* Analyze single-bit errors on 64-bit wide buses
	309	* TODO: Add support for 32-bit wide buses
	310	*/
	311	if ((err_detect & DDR_EDE_SBE) && (bus_width == 64)) {
	312	sbe_ecc_decode(cap_high, cap_low, syndrome,
	313	&bad_data_bit, &bad_ecc_bit);
	314
	315	if (bad_data_bit != -1)
d43a9fb2	316	fsl_mc_printk(mci, KERN_ERR,
ea2eb9a8 YS	317	"Faulty Data bit: %d\n", bad_data_bit);
ea2eb9a8 YS	318	if (bad_ecc_bit != -1)
d43a9fb2	319	fsl_mc_printk(mci, KERN_ERR,
ea2eb9a8 YS	320	"Faulty ECC bit: %d\n", bad_ecc_bit);
ea2eb9a8 YS	321
d43a9fb2	322	fsl_mc_printk(mci, KERN_ERR,
ea2eb9a8 YS	323	"Expected Data / ECC:\t%#8.8x_%08x / %#2.2x\n",
	324	cap_high ^ (1 << (bad_data_bit - 32)),
	325	cap_low ^ (1 << bad_data_bit),
	326	syndrome ^ (1 << bad_ecc_bit));
	327	}
	328
d43a9fb2	329	fsl_mc_printk(mci, KERN_ERR,
ea2eb9a8 YS	330	"Captured Data / ECC:\t%#8.8x_%08x / %#2.2x\n",
ea2eb9a8 YS	331	cap_high, cap_low, syndrome);
d43a9fb2 YS	332	fsl_mc_printk(mci, KERN_ERR, "Err addr: %#8.8llx\n", err_addr);
d43a9fb2 YS	333	fsl_mc_printk(mci, KERN_ERR, "PFN: %#8.8x\n", pfn);
ea2eb9a8 YS	334
	335	/* we are out of range */
	336	if (row_index == mci->nr_csrows)
d43a9fb2	337	fsl_mc_printk(mci, KERN_ERR, "PFN out of range!\n");
ea2eb9a8 YS	338
	339	if (err_detect & DDR_EDE_SBE)
	340	edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
	341	pfn, err_addr & ~PAGE_MASK, syndrome,
	342	row_index, 0, -1,
	343	mci->ctl_name, "");
	344
	345	if (err_detect & DDR_EDE_MBE)
	346	edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
	347	pfn, err_addr & ~PAGE_MASK, syndrome,
	348	row_index, 0, -1,
	349	mci->ctl_name, "");
	350
339fdff1	351	ddr_out32(pdata->mc_vbase + FSL_MC_ERR_DETECT, err_detect);
ea2eb9a8 YS	352	}
ea2eb9a8 YS	353
d43a9fb2	354	static irqreturn_t fsl_mc_isr(int irq, void *dev_id)
ea2eb9a8 YS	355	{
ea2eb9a8 YS	356	struct mem_ctl_info *mci = dev_id;
d43a9fb2	357	struct fsl_mc_pdata *pdata = mci->pvt_info;
ea2eb9a8 YS	358	u32 err_detect;
ea2eb9a8 YS	359
339fdff1	360	err_detect = ddr_in32(pdata->mc_vbase + FSL_MC_ERR_DETECT);
ea2eb9a8 YS	361	if (!err_detect)
	362	return IRQ_NONE;
	363
d43a9fb2	364	fsl_mc_check(mci);
ea2eb9a8 YS	365
	366	return IRQ_HANDLED;
	367	}
	368
d43a9fb2	369	static void fsl_ddr_init_csrows(struct mem_ctl_info *mci)
ea2eb9a8	370	{
d43a9fb2	371	struct fsl_mc_pdata *pdata = mci->pvt_info;
ea2eb9a8 YS	372	struct csrow_info *csrow;
	373	struct dimm_info *dimm;
	374	u32 sdram_ctl;
	375	u32 sdtype;
	376	enum mem_type mtype;
	377	u32 cs_bnds;
	378	int index;
	379
339fdff1	380	sdram_ctl = ddr_in32(pdata->mc_vbase + FSL_MC_DDR_SDRAM_CFG);
ea2eb9a8 YS	381
	382	sdtype = sdram_ctl & DSC_SDTYPE_MASK;
	383	if (sdram_ctl & DSC_RD_EN) {
	384	switch (sdtype) {
4e2c3252	385	case 0x02000000:
ea2eb9a8 YS	386	mtype = MEM_RDDR;
ea2eb9a8 YS	387	break;
4e2c3252	388	case 0x03000000:
ea2eb9a8 YS	389	mtype = MEM_RDDR2;
ea2eb9a8 YS	390	break;
4e2c3252	391	case 0x07000000:
ea2eb9a8 YS	392	mtype = MEM_RDDR3;
ea2eb9a8 YS	393	break;
4e2c3252 YS	394	case 0x05000000:
	395	mtype = MEM_RDDR4;
	396	break;
ea2eb9a8 YS	397	default:
	398	mtype = MEM_UNKNOWN;
	399	break;
	400	}
	401	} else {
	402	switch (sdtype) {
4e2c3252	403	case 0x02000000:
ea2eb9a8 YS	404	mtype = MEM_DDR;
ea2eb9a8 YS	405	break;
4e2c3252	406	case 0x03000000:
ea2eb9a8 YS	407	mtype = MEM_DDR2;
ea2eb9a8 YS	408	break;
4e2c3252	409	case 0x07000000:
ea2eb9a8 YS	410	mtype = MEM_DDR3;
ea2eb9a8 YS	411	break;
4e2c3252 YS	412	case 0x05000000:
	413	mtype = MEM_DDR4;
	414	break;
ea2eb9a8 YS	415	default:
	416	mtype = MEM_UNKNOWN;
	417	break;
	418	}
	419	}
	420
	421	for (index = 0; index < mci->nr_csrows; index++) {
	422	u32 start;
	423	u32 end;
	424
	425	csrow = mci->csrows[index];
	426	dimm = csrow->channels[0]->dimm;
	427
339fdff1 YS	428	cs_bnds = ddr_in32(pdata->mc_vbase + FSL_MC_CS_BNDS_0 +
339fdff1 YS	429	(index * FSL_MC_CS_BNDS_OFS));
ea2eb9a8 YS	430
	431	start = (cs_bnds & 0xffff0000) >> 16;
	432	end = (cs_bnds & 0x0000ffff);
	433
	434	if (start == end)
	435	continue; /* not populated */
	436
	437	start <<= (24 - PAGE_SHIFT);
	438	end <<= (24 - PAGE_SHIFT);
	439	end \|= (1 << (24 - PAGE_SHIFT)) - 1;
	440
	441	csrow->first_page = start;
	442	csrow->last_page = end;
	443
	444	dimm->nr_pages = end + 1 - start;
	445	dimm->grain = 8;
	446	dimm->mtype = mtype;
	447	dimm->dtype = DEV_UNKNOWN;
	448	if (sdram_ctl & DSC_X32_EN)
	449	dimm->dtype = DEV_X32;
	450	dimm->edac_mode = EDAC_SECDED;
	451	}
	452	}
	453
d43a9fb2	454	int fsl_mc_err_probe(struct platform_device *op)
ea2eb9a8 YS	455	{
	456	struct mem_ctl_info *mci;
	457	struct edac_mc_layer layers[2];
d43a9fb2	458	struct fsl_mc_pdata *pdata;
ea2eb9a8 YS	459	struct resource r;
	460	u32 sdram_ctl;
	461	int res;
	462
d43a9fb2	463	if (!devres_open_group(&op->dev, fsl_mc_err_probe, GFP_KERNEL))
ea2eb9a8 YS	464	return -ENOMEM;
	465
	466	layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
	467	layers[0].size = 4;
	468	layers[0].is_virt_csrow = true;
	469	layers[1].type = EDAC_MC_LAYER_CHANNEL;
	470	layers[1].size = 1;
	471	layers[1].is_virt_csrow = false;
	472	mci = edac_mc_alloc(edac_mc_idx, ARRAY_SIZE(layers), layers,
	473	sizeof(*pdata));
	474	if (!mci) {
d43a9fb2	475	devres_release_group(&op->dev, fsl_mc_err_probe);
ea2eb9a8 YS	476	return -ENOMEM;
	477	}
	478
	479	pdata = mci->pvt_info;
d43a9fb2	480	pdata->name = "fsl_mc_err";
ea2eb9a8 YS	481	pdata->irq = NO_IRQ;
	482	mci->pdev = &op->dev;
	483	pdata->edac_idx = edac_mc_idx++;
	484	dev_set_drvdata(mci->pdev, mci);
	485	mci->ctl_name = pdata->name;
	486	mci->dev_name = pdata->name;
	487
339fdff1 YS	488	/*
	489	* Get the endianness of DDR controller registers.
	490	* Default is big endian.
	491	*/
	492	little_endian = of_property_read_bool(op->dev.of_node, "little-endian");
	493
ea2eb9a8 YS	494	res = of_address_to_resource(op->dev.of_node, 0, &r);
	495	if (res) {
	496	pr_err("%s: Unable to get resource for MC err regs\n",
	497	__func__);
	498	goto err;
	499	}
	500
	501	if (!devm_request_mem_region(&op->dev, r.start, resource_size(&r),
	502	pdata->name)) {
	503	pr_err("%s: Error while requesting mem region\n",
	504	__func__);
	505	res = -EBUSY;
	506	goto err;
	507	}
	508
	509	pdata->mc_vbase = devm_ioremap(&op->dev, r.start, resource_size(&r));
	510	if (!pdata->mc_vbase) {
	511	pr_err("%s: Unable to setup MC err regs\n", __func__);
	512	res = -ENOMEM;
	513	goto err;
	514	}
	515
339fdff1	516	sdram_ctl = ddr_in32(pdata->mc_vbase + FSL_MC_DDR_SDRAM_CFG);
ea2eb9a8 YS	517	if (!(sdram_ctl & DSC_ECC_EN)) {
	518	/* no ECC */
	519	pr_warn("%s: No ECC DIMMs discovered\n", __func__);
	520	res = -ENODEV;
	521	goto err;
	522	}
	523
	524	edac_dbg(3, "init mci\n");
4e2c3252 YS	525	mci->mtype_cap = MEM_FLAG_DDR \| MEM_FLAG_RDDR \|
	526	MEM_FLAG_DDR2 \| MEM_FLAG_RDDR2 \|
	527	MEM_FLAG_DDR3 \| MEM_FLAG_RDDR3 \|
	528	MEM_FLAG_DDR4 \| MEM_FLAG_RDDR4;
ea2eb9a8 YS	529	mci->edac_ctl_cap = EDAC_FLAG_NONE \| EDAC_FLAG_SECDED;
	530	mci->edac_cap = EDAC_FLAG_SECDED;
	531	mci->mod_name = EDAC_MOD_STR;
	532
	533	if (edac_op_state == EDAC_OPSTATE_POLL)
d43a9fb2	534	mci->edac_check = fsl_mc_check;
ea2eb9a8 YS	535
	536	mci->ctl_page_to_phys = NULL;
	537
	538	mci->scrub_mode = SCRUB_SW_SRC;
	539
d43a9fb2	540	fsl_ddr_init_csrows(mci);
ea2eb9a8 YS	541
ea2eb9a8 YS	542	/* store the original error disable bits */
339fdff1 YS	543	orig_ddr_err_disable = ddr_in32(pdata->mc_vbase + FSL_MC_ERR_DISABLE);
339fdff1 YS	544	ddr_out32(pdata->mc_vbase + FSL_MC_ERR_DISABLE, 0);
ea2eb9a8 YS	545
ea2eb9a8 YS	546	/* clear all error bits */
339fdff1	547	ddr_out32(pdata->mc_vbase + FSL_MC_ERR_DETECT, ~0);
ea2eb9a8	548
d43a9fb2	549	if (edac_mc_add_mc_with_groups(mci, fsl_ddr_dev_groups)) {
ea2eb9a8 YS	550	edac_dbg(3, "failed edac_mc_add_mc()\n");
	551	goto err;
	552	}
	553
	554	if (edac_op_state == EDAC_OPSTATE_INT) {
339fdff1 YS	555	ddr_out32(pdata->mc_vbase + FSL_MC_ERR_INT_EN,
339fdff1 YS	556	DDR_EIE_MBEE \| DDR_EIE_SBEE);
ea2eb9a8 YS	557
ea2eb9a8 YS	558	/* store the original error management threshold */
339fdff1 YS	559	orig_ddr_err_sbe = ddr_in32(pdata->mc_vbase +
339fdff1 YS	560	FSL_MC_ERR_SBE) & 0xff0000;
ea2eb9a8 YS	561
ea2eb9a8 YS	562	/* set threshold to 1 error per interrupt */
339fdff1	563	ddr_out32(pdata->mc_vbase + FSL_MC_ERR_SBE, 0x10000);
ea2eb9a8 YS	564
ea2eb9a8 YS	565	/* register interrupts */
55764ed3	566	pdata->irq = platform_get_irq(op, 0);
ea2eb9a8	567	res = devm_request_irq(&op->dev, pdata->irq,
d43a9fb2	568	fsl_mc_isr,
ea2eb9a8 YS	569	IRQF_SHARED,
	570	"[EDAC] MC err", mci);
	571	if (res < 0) {
d43a9fb2	572	pr_err("%s: Unable to request irq %d for FSL DDR DRAM ERR\n",
ea2eb9a8	573	__func__, pdata->irq);
ea2eb9a8 YS	574	res = -ENODEV;
	575	goto err2;
	576	}
	577
	578	pr_info(EDAC_MOD_STR " acquired irq %d for MC\n",
	579	pdata->irq);
	580	}
	581
d43a9fb2	582	devres_remove_group(&op->dev, fsl_mc_err_probe);
ea2eb9a8 YS	583	edac_dbg(3, "success\n");
	584	pr_info(EDAC_MOD_STR " MC err registered\n");
	585
	586	return 0;
	587
	588	err2:
	589	edac_mc_del_mc(&op->dev);
	590	err:
d43a9fb2	591	devres_release_group(&op->dev, fsl_mc_err_probe);
ea2eb9a8 YS	592	edac_mc_free(mci);
	593	return res;
	594	}
	595
d43a9fb2	596	int fsl_mc_err_remove(struct platform_device *op)
ea2eb9a8 YS	597	{
ea2eb9a8 YS	598	struct mem_ctl_info *mci = dev_get_drvdata(&op->dev);
d43a9fb2	599	struct fsl_mc_pdata *pdata = mci->pvt_info;
ea2eb9a8 YS	600
	601	edac_dbg(0, "\n");
	602
	603	if (edac_op_state == EDAC_OPSTATE_INT) {
339fdff1	604	ddr_out32(pdata->mc_vbase + FSL_MC_ERR_INT_EN, 0);
ea2eb9a8 YS	605	}
ea2eb9a8 YS	606
339fdff1 YS	607	ddr_out32(pdata->mc_vbase + FSL_MC_ERR_DISABLE,
	608	orig_ddr_err_disable);
	609	ddr_out32(pdata->mc_vbase + FSL_MC_ERR_SBE, orig_ddr_err_sbe);
ea2eb9a8 YS	610
	611	edac_mc_del_mc(&op->dev);
	612	edac_mc_free(mci);
	613	return 0;
	614	}