[mirror_ubuntu-eoan-kernel.git] / drivers / edac / fsl_ddr_edac.h

/*
 * Freescale Memory Controller kernel module
 *
 * Support  Power-based SoCs including MPC85xx, MPC86xx, MPC83xx and
 * ARM-based Layerscape SoCs including LS2xxx and LS1021A. Originally
 * split out from mpc85xx_edac EDAC driver.
 *
 * Author: Dave Jiang <djiang@mvista.com>
 *
 * 2006-2007 (c) MontaVista Software, Inc. This file is licensed under
 * the terms of the GNU General Public License version 2. This program
 * is licensed "as is" without any warranty of any kind, whether express
 * or implied.
 *
 */
#ifndef _FSL_DDR_EDAC_H_
#define _FSL_DDR_EDAC_H_

#define fsl_mc_printk(mci, level, fmt, arg...) \
	edac_mc_chipset_printk(mci, level, "FSL_DDR", fmt, ##arg)

/*
 * DRAM error defines
 */

/* DDR_SDRAM_CFG */
#define FSL_MC_DDR_SDRAM_CFG	0x0110
#define FSL_MC_CS_BNDS_0		0x0000
#define FSL_MC_CS_BNDS_OFS		0x0008

#define FSL_MC_DATA_ERR_INJECT_HI	0x0e00
#define FSL_MC_DATA_ERR_INJECT_LO	0x0e04
#define FSL_MC_ECC_ERR_INJECT	0x0e08
#define FSL_MC_CAPTURE_DATA_HI	0x0e20
#define FSL_MC_CAPTURE_DATA_LO	0x0e24
#define FSL_MC_CAPTURE_ECC		0x0e28
#define FSL_MC_ERR_DETECT		0x0e40
#define FSL_MC_ERR_DISABLE		0x0e44
#define FSL_MC_ERR_INT_EN		0x0e48
#define FSL_MC_CAPTURE_ATRIBUTES	0x0e4c
#define FSL_MC_CAPTURE_ADDRESS	0x0e50
#define FSL_MC_CAPTURE_EXT_ADDRESS	0x0e54
#define FSL_MC_ERR_SBE		0x0e58

#define DSC_MEM_EN	0x80000000
#define DSC_ECC_EN	0x20000000
#define DSC_RD_EN	0x10000000
#define DSC_DBW_MASK	0x00180000
#define DSC_DBW_32	0x00080000
#define DSC_DBW_64	0x00000000

#define DSC_SDTYPE_MASK		0x07000000
#define DSC_X32_EN	0x00000020

/* Err_Int_En */
#define DDR_EIE_MSEE	0x1	/* memory select */
#define DDR_EIE_SBEE	0x4	/* single-bit ECC error */
#define DDR_EIE_MBEE	0x8	/* multi-bit ECC error */

/* Err_Detect */
#define DDR_EDE_MSE		0x1	/* memory select */
#define DDR_EDE_SBE		0x4	/* single-bit ECC error */
#define DDR_EDE_MBE		0x8	/* multi-bit ECC error */
#define DDR_EDE_MME		0x80000000	/* multiple memory errors */

/* Err_Disable */
#define DDR_EDI_MSED	0x1	/* memory select disable */
#define	DDR_EDI_SBED	0x4	/* single-bit ECC error disable */
#define	DDR_EDI_MBED	0x8	/* multi-bit ECC error disable */

struct fsl_mc_pdata {
	char *name;
	int edac_idx;
	void __iomem *mc_vbase;
	int irq;
};
int fsl_mc_err_probe(struct platform_device *op);
int fsl_mc_err_remove(struct platform_device *op);
#endif
Commit	Line	Data
ea2eb9a8 YS	1	/*
	2	* Freescale Memory Controller kernel module
	3	*
	4	* Support Power-based SoCs including MPC85xx, MPC86xx, MPC83xx and
75dfa870 PH	5	* ARM-based Layerscape SoCs including LS2xxx and LS1021A. Originally
75dfa870 PH	6	* split out from mpc85xx_edac EDAC driver.
ea2eb9a8 YS	7	*
	8	* Author: Dave Jiang <djiang@mvista.com>
	9	*
	10	* 2006-2007 (c) MontaVista Software, Inc. This file is licensed under
	11	* the terms of the GNU General Public License version 2. This program
	12	* is licensed "as is" without any warranty of any kind, whether express
	13	* or implied.
	14	*
	15	*/
	16	#ifndef _FSL_DDR_EDAC_H_
	17	#define _FSL_DDR_EDAC_H_
	18
d43a9fb2	19	#define fsl_mc_printk(mci, level, fmt, arg...) \
ea2eb9a8 YS	20	edac_mc_chipset_printk(mci, level, "FSL_DDR", fmt, ##arg)
	21
	22	/*
	23	* DRAM error defines
	24	*/
	25
	26	/* DDR_SDRAM_CFG */
d43a9fb2 YS	27	#define FSL_MC_DDR_SDRAM_CFG 0x0110
	28	#define FSL_MC_CS_BNDS_0 0x0000
	29	#define FSL_MC_CS_BNDS_OFS 0x0008
ea2eb9a8	30
d43a9fb2 YS	31	#define FSL_MC_DATA_ERR_INJECT_HI 0x0e00
	32	#define FSL_MC_DATA_ERR_INJECT_LO 0x0e04
	33	#define FSL_MC_ECC_ERR_INJECT 0x0e08
	34	#define FSL_MC_CAPTURE_DATA_HI 0x0e20
	35	#define FSL_MC_CAPTURE_DATA_LO 0x0e24
	36	#define FSL_MC_CAPTURE_ECC 0x0e28
	37	#define FSL_MC_ERR_DETECT 0x0e40
	38	#define FSL_MC_ERR_DISABLE 0x0e44
	39	#define FSL_MC_ERR_INT_EN 0x0e48
	40	#define FSL_MC_CAPTURE_ATRIBUTES 0x0e4c
	41	#define FSL_MC_CAPTURE_ADDRESS 0x0e50
	42	#define FSL_MC_CAPTURE_EXT_ADDRESS 0x0e54
	43	#define FSL_MC_ERR_SBE 0x0e58
ea2eb9a8 YS	44
	45	#define DSC_MEM_EN 0x80000000
	46	#define DSC_ECC_EN 0x20000000
	47	#define DSC_RD_EN 0x10000000
	48	#define DSC_DBW_MASK 0x00180000
	49	#define DSC_DBW_32 0x00080000
	50	#define DSC_DBW_64 0x00000000
	51
	52	#define DSC_SDTYPE_MASK 0x07000000
ea2eb9a8 YS	53	#define DSC_X32_EN 0x00000020
	54
	55	/* Err_Int_En */
	56	#define DDR_EIE_MSEE 0x1 /* memory select */
	57	#define DDR_EIE_SBEE 0x4 /* single-bit ECC error */
	58	#define DDR_EIE_MBEE 0x8 /* multi-bit ECC error */
	59
	60	/* Err_Detect */
	61	#define DDR_EDE_MSE 0x1 /* memory select */
	62	#define DDR_EDE_SBE 0x4 /* single-bit ECC error */
	63	#define DDR_EDE_MBE 0x8 /* multi-bit ECC error */
	64	#define DDR_EDE_MME 0x80000000 /* multiple memory errors */
	65
	66	/* Err_Disable */
	67	#define DDR_EDI_MSED 0x1 /* memory select disable */
	68	#define DDR_EDI_SBED 0x4 /* single-bit ECC error disable */
	69	#define DDR_EDI_MBED 0x8 /* multi-bit ECC error disable */
	70
d43a9fb2	71	struct fsl_mc_pdata {
ea2eb9a8 YS	72	char *name;
	73	int edac_idx;
	74	void __iomem *mc_vbase;
	75	int irq;
	76	};
d43a9fb2 YS	77	int fsl_mc_err_probe(struct platform_device *op);
d43a9fb2 YS	78	int fsl_mc_err_remove(struct platform_device *op);
ea2eb9a8	79	#endif