[mirror_ubuntu-artful-kernel.git] / drivers / edac / highbank_mc_edac.c

/*
 * Copyright 2011-2012 Calxeda, Inc.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program.  If not, see <http://www.gnu.org/licenses/>.
 */
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/ctype.h>
#include <linux/edac.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
#include <linux/of_platform.h>
#include <linux/uaccess.h>

#include "edac_module.h"

/* DDR Ctrlr Error Registers */

#define HB_DDR_ECC_ERR_BASE		0x128
#define MW_DDR_ECC_ERR_BASE		0x1b4

#define HB_DDR_ECC_OPT			0x00
#define HB_DDR_ECC_U_ERR_ADDR		0x08
#define HB_DDR_ECC_U_ERR_STAT		0x0c
#define HB_DDR_ECC_U_ERR_DATAL		0x10
#define HB_DDR_ECC_U_ERR_DATAH		0x14
#define HB_DDR_ECC_C_ERR_ADDR		0x18
#define HB_DDR_ECC_C_ERR_STAT		0x1c
#define HB_DDR_ECC_C_ERR_DATAL		0x20
#define HB_DDR_ECC_C_ERR_DATAH		0x24

#define HB_DDR_ECC_OPT_MODE_MASK	0x3
#define HB_DDR_ECC_OPT_FWC		0x100
#define HB_DDR_ECC_OPT_XOR_SHIFT	16

/* DDR Ctrlr Interrupt Registers */

#define HB_DDR_ECC_INT_BASE		0x180
#define MW_DDR_ECC_INT_BASE		0x218

#define HB_DDR_ECC_INT_STATUS		0x00
#define HB_DDR_ECC_INT_ACK		0x04

#define HB_DDR_ECC_INT_STAT_CE		0x8
#define HB_DDR_ECC_INT_STAT_DOUBLE_CE	0x10
#define HB_DDR_ECC_INT_STAT_UE		0x20
#define HB_DDR_ECC_INT_STAT_DOUBLE_UE	0x40

struct hb_mc_drvdata {
	void __iomem *mc_err_base;
	void __iomem *mc_int_base;
};

static irqreturn_t highbank_mc_err_handler(int irq, void *dev_id)
{
	struct mem_ctl_info *mci = dev_id;
	struct hb_mc_drvdata *drvdata = mci->pvt_info;
	u32 status, err_addr;

	/* Read the interrupt status register */
	status = readl(drvdata->mc_int_base + HB_DDR_ECC_INT_STATUS);

	if (status & HB_DDR_ECC_INT_STAT_UE) {
		err_addr = readl(drvdata->mc_err_base + HB_DDR_ECC_U_ERR_ADDR);
		edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
				     err_addr >> PAGE_SHIFT,
				     err_addr & ~PAGE_MASK, 0,
				     0, 0, -1,
				     mci->ctl_name, "");
	}
	if (status & HB_DDR_ECC_INT_STAT_CE) {
		u32 syndrome = readl(drvdata->mc_err_base + HB_DDR_ECC_C_ERR_STAT);
		syndrome = (syndrome >> 8) & 0xff;
		err_addr = readl(drvdata->mc_err_base + HB_DDR_ECC_C_ERR_ADDR);
		edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
				     err_addr >> PAGE_SHIFT,
				     err_addr & ~PAGE_MASK, syndrome,
				     0, 0, -1,
				     mci->ctl_name, "");
	}

	/* clear the error, clears the interrupt */
	writel(status, drvdata->mc_int_base + HB_DDR_ECC_INT_ACK);
	return IRQ_HANDLED;
}

static void highbank_mc_err_inject(struct mem_ctl_info *mci, u8 synd)
{
	struct hb_mc_drvdata *pdata = mci->pvt_info;
	u32 reg;

	reg = readl(pdata->mc_err_base + HB_DDR_ECC_OPT);
	reg &= HB_DDR_ECC_OPT_MODE_MASK;
	reg |= (synd << HB_DDR_ECC_OPT_XOR_SHIFT) | HB_DDR_ECC_OPT_FWC;
	writel(reg, pdata->mc_err_base + HB_DDR_ECC_OPT);
}

#define to_mci(k) container_of(k, struct mem_ctl_info, dev)

static ssize_t highbank_mc_inject_ctrl(struct device *dev,
	struct device_attribute *attr, const char *buf, size_t count)
{
	struct mem_ctl_info *mci = to_mci(dev);
	u8 synd;

	if (kstrtou8(buf, 16, &synd))
		return -EINVAL;

	highbank_mc_err_inject(mci, synd);

	return count;
}

static DEVICE_ATTR(inject_ctrl, S_IWUSR, NULL, highbank_mc_inject_ctrl);

static struct attribute *highbank_dev_attrs[] = {
	&dev_attr_inject_ctrl.attr,
	NULL
};

ATTRIBUTE_GROUPS(highbank_dev);

struct hb_mc_settings {
	int	err_offset;
	int	int_offset;
};

static struct hb_mc_settings hb_settings = {
	.err_offset = HB_DDR_ECC_ERR_BASE,
	.int_offset = HB_DDR_ECC_INT_BASE,
};

static struct hb_mc_settings mw_settings = {
	.err_offset = MW_DDR_ECC_ERR_BASE,
	.int_offset = MW_DDR_ECC_INT_BASE,
};

static const struct of_device_id hb_ddr_ctrl_of_match[] = {
	{ .compatible = "calxeda,hb-ddr-ctrl",		.data = &hb_settings },
	{ .compatible = "calxeda,ecx-2000-ddr-ctrl",	.data = &mw_settings },
	{},
};
MODULE_DEVICE_TABLE(of, hb_ddr_ctrl_of_match);

static int highbank_mc_probe(struct platform_device *pdev)
{
	const struct of_device_id *id;
	const struct hb_mc_settings *settings;
	struct edac_mc_layer layers[2];
	struct mem_ctl_info *mci;
	struct hb_mc_drvdata *drvdata;
	struct dimm_info *dimm;
	struct resource *r;
	void __iomem *base;
	u32 control;
	int irq;
	int res = 0;

	id = of_match_device(hb_ddr_ctrl_of_match, &pdev->dev);
	if (!id)
		return -ENODEV;

	layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
	layers[0].size = 1;
	layers[0].is_virt_csrow = true;
	layers[1].type = EDAC_MC_LAYER_CHANNEL;
	layers[1].size = 1;
	layers[1].is_virt_csrow = false;
	mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers,
			    sizeof(struct hb_mc_drvdata));
	if (!mci)
		return -ENOMEM;

	mci->pdev = &pdev->dev;
	drvdata = mci->pvt_info;
	platform_set_drvdata(pdev, mci);

	if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL))
		return -ENOMEM;

	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!r) {
		dev_err(&pdev->dev, "Unable to get mem resource\n");
		res = -ENODEV;
		goto err;
	}

	if (!devm_request_mem_region(&pdev->dev, r->start,
				     resource_size(r), dev_name(&pdev->dev))) {
		dev_err(&pdev->dev, "Error while requesting mem region\n");
		res = -EBUSY;
		goto err;
	}

	base = devm_ioremap(&pdev->dev, r->start, resource_size(r));
	if (!base) {
		dev_err(&pdev->dev, "Unable to map regs\n");
		res = -ENOMEM;
		goto err;
	}

	settings = id->data;
	drvdata->mc_err_base = base + settings->err_offset;
	drvdata->mc_int_base = base + settings->int_offset;

	control = readl(drvdata->mc_err_base + HB_DDR_ECC_OPT) & 0x3;
	if (!control || (control == 0x2)) {
		dev_err(&pdev->dev, "No ECC present, or ECC disabled\n");
		res = -ENODEV;
		goto err;
	}

	mci->mtype_cap = MEM_FLAG_DDR3;
	mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
	mci->edac_cap = EDAC_FLAG_SECDED;
	mci->mod_name = pdev->dev.driver->name;
	mci->mod_ver = "1";
	mci->ctl_name = id->compatible;
	mci->dev_name = dev_name(&pdev->dev);
	mci->scrub_mode = SCRUB_SW_SRC;

	/* Only a single 4GB DIMM is supported */
	dimm = *mci->dimms;
	dimm->nr_pages = (~0UL >> PAGE_SHIFT) + 1;
	dimm->grain = 8;
	dimm->dtype = DEV_X8;
	dimm->mtype = MEM_DDR3;
	dimm->edac_mode = EDAC_SECDED;

	res = edac_mc_add_mc_with_groups(mci, highbank_dev_groups);
	if (res < 0)
		goto err;

	irq = platform_get_irq(pdev, 0);
	res = devm_request_irq(&pdev->dev, irq, highbank_mc_err_handler,
			       0, dev_name(&pdev->dev), mci);
	if (res < 0) {
		dev_err(&pdev->dev, "Unable to request irq %d\n", irq);
		goto err2;
	}

	devres_close_group(&pdev->dev, NULL);
	return 0;
err2:
	edac_mc_del_mc(&pdev->dev);
err:
	devres_release_group(&pdev->dev, NULL);
	edac_mc_free(mci);
	return res;
}

static int highbank_mc_remove(struct platform_device *pdev)
{
	struct mem_ctl_info *mci = platform_get_drvdata(pdev);

	edac_mc_del_mc(&pdev->dev);
	edac_mc_free(mci);
	return 0;
}

static struct platform_driver highbank_mc_edac_driver = {
	.probe = highbank_mc_probe,
	.remove = highbank_mc_remove,
	.driver = {
		.name = "hb_mc_edac",
		.of_match_table = hb_ddr_ctrl_of_match,
	},
};

module_platform_driver(highbank_mc_edac_driver);

MODULE_LICENSE("GPL v2");
MODULE_AUTHOR("Calxeda, Inc.");
MODULE_DESCRIPTION("EDAC Driver for Calxeda Highbank");
Commit	Line	Data
a1b01edb RH	1	/*
	2	* Copyright 2011-2012 Calxeda, Inc.
	3	*
	4	* This program is free software; you can redistribute it and/or modify it
	5	* under the terms and conditions of the GNU General Public License,
	6	* version 2, as published by the Free Software Foundation.
	7	*
	8	* This program is distributed in the hope it will be useful, but WITHOUT
	9	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	10	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	11	* more details.
	12	*
	13	* You should have received a copy of the GNU General Public License along with
	14	* this program. If not, see <http://www.gnu.org/licenses/>.
	15	*/
	16	#include <linux/types.h>
	17	#include <linux/kernel.h>
	18	#include <linux/ctype.h>
	19	#include <linux/edac.h>
	20	#include <linux/interrupt.h>
	21	#include <linux/platform_device.h>
	22	#include <linux/of_platform.h>
	23	#include <linux/uaccess.h>
	24
a1b01edb RH	25	#include "edac_module.h"
	26
	27	/* DDR Ctrlr Error Registers */
a1b01edb	28
0ec8579e RR	29	#define HB_DDR_ECC_ERR_BASE 0x128
	30	#define MW_DDR_ECC_ERR_BASE 0x1b4
	31
	32	#define HB_DDR_ECC_OPT 0x00
	33	#define HB_DDR_ECC_U_ERR_ADDR 0x08
	34	#define HB_DDR_ECC_U_ERR_STAT 0x0c
	35	#define HB_DDR_ECC_U_ERR_DATAL 0x10
	36	#define HB_DDR_ECC_U_ERR_DATAH 0x14
	37	#define HB_DDR_ECC_C_ERR_ADDR 0x18
	38	#define HB_DDR_ECC_C_ERR_STAT 0x1c
	39	#define HB_DDR_ECC_C_ERR_DATAL 0x20
	40	#define HB_DDR_ECC_C_ERR_DATAH 0x24
a1b01edb RH	41
	42	#define HB_DDR_ECC_OPT_MODE_MASK 0x3
	43	#define HB_DDR_ECC_OPT_FWC 0x100
	44	#define HB_DDR_ECC_OPT_XOR_SHIFT 16
	45
0ec8579e RR	46	/* DDR Ctrlr Interrupt Registers */
	47
	48	#define HB_DDR_ECC_INT_BASE 0x180
	49	#define MW_DDR_ECC_INT_BASE 0x218
	50
	51	#define HB_DDR_ECC_INT_STATUS 0x00
	52	#define HB_DDR_ECC_INT_ACK 0x04
	53
	54	#define HB_DDR_ECC_INT_STAT_CE 0x8
	55	#define HB_DDR_ECC_INT_STAT_DOUBLE_CE 0x10
	56	#define HB_DDR_ECC_INT_STAT_UE 0x20
	57	#define HB_DDR_ECC_INT_STAT_DOUBLE_UE 0x40
	58
a1b01edb	59	struct hb_mc_drvdata {
0ec8579e RR	60	void __iomem *mc_err_base;
0ec8579e RR	61	void __iomem *mc_int_base;
a1b01edb RH	62	};
	63
	64	static irqreturn_t highbank_mc_err_handler(int irq, void *dev_id)
	65	{
	66	struct mem_ctl_info *mci = dev_id;
	67	struct hb_mc_drvdata *drvdata = mci->pvt_info;
	68	u32 status, err_addr;
	69
	70	/* Read the interrupt status register */
0ec8579e	71	status = readl(drvdata->mc_int_base + HB_DDR_ECC_INT_STATUS);
a1b01edb RH	72
a1b01edb RH	73	if (status & HB_DDR_ECC_INT_STAT_UE) {
0ec8579e	74	err_addr = readl(drvdata->mc_err_base + HB_DDR_ECC_U_ERR_ADDR);
a1b01edb RH	75	edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
	76	err_addr >> PAGE_SHIFT,
	77	err_addr & ~PAGE_MASK, 0,
	78	0, 0, -1,
	79	mci->ctl_name, "");
	80	}
	81	if (status & HB_DDR_ECC_INT_STAT_CE) {
0ec8579e	82	u32 syndrome = readl(drvdata->mc_err_base + HB_DDR_ECC_C_ERR_STAT);
a1b01edb	83	syndrome = (syndrome >> 8) & 0xff;
0ec8579e	84	err_addr = readl(drvdata->mc_err_base + HB_DDR_ECC_C_ERR_ADDR);
a1b01edb RH	85	edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
	86	err_addr >> PAGE_SHIFT,
	87	err_addr & ~PAGE_MASK, syndrome,
	88	0, 0, -1,
	89	mci->ctl_name, "");
	90	}
	91
	92	/* clear the error, clears the interrupt */
0ec8579e	93	writel(status, drvdata->mc_int_base + HB_DDR_ECC_INT_ACK);
a1b01edb RH	94	return IRQ_HANDLED;
	95	}
	96
78cfbf0b	97	static void highbank_mc_err_inject(struct mem_ctl_info *mci, u8 synd)
a1b01edb	98	{
a1b01edb	99	struct hb_mc_drvdata *pdata = mci->pvt_info;
a1b01edb	100	u32 reg;
78cfbf0b RR	101
	102	reg = readl(pdata->mc_err_base + HB_DDR_ECC_OPT);
	103	reg &= HB_DDR_ECC_OPT_MODE_MASK;
	104	reg \|= (synd << HB_DDR_ECC_OPT_XOR_SHIFT) \| HB_DDR_ECC_OPT_FWC;
	105	writel(reg, pdata->mc_err_base + HB_DDR_ECC_OPT);
	106	}
	107
	108	#define to_mci(k) container_of(k, struct mem_ctl_info, dev)
	109
	110	static ssize_t highbank_mc_inject_ctrl(struct device *dev,
	111	struct device_attribute attr, const char buf, size_t count)
	112	{
	113	struct mem_ctl_info *mci = to_mci(dev);
a1b01edb RH	114	u8 synd;
a1b01edb RH	115
78cfbf0b RR	116	if (kstrtou8(buf, 16, &synd))
78cfbf0b RR	117	return -EINVAL;
a1b01edb	118
78cfbf0b	119	highbank_mc_err_inject(mci, synd);
a1b01edb RH	120
	121	return count;
	122	}
	123
78cfbf0b	124	static DEVICE_ATTR(inject_ctrl, S_IWUSR, NULL, highbank_mc_inject_ctrl);
a1b01edb	125
fc7cc6b7 TI	126	static struct attribute *highbank_dev_attrs[] = {
	127	&dev_attr_inject_ctrl.attr,
	128	NULL
	129	};
	130
	131	ATTRIBUTE_GROUPS(highbank_dev);
	132
0ec8579e RR	133	struct hb_mc_settings {
	134	int err_offset;
	135	int int_offset;
	136	};
	137
	138	static struct hb_mc_settings hb_settings = {
	139	.err_offset = HB_DDR_ECC_ERR_BASE,
	140	.int_offset = HB_DDR_ECC_INT_BASE,
	141	};
	142
	143	static struct hb_mc_settings mw_settings = {
	144	.err_offset = MW_DDR_ECC_ERR_BASE,
	145	.int_offset = MW_DDR_ECC_INT_BASE,
	146	};
	147
1afaa055	148	static const struct of_device_id hb_ddr_ctrl_of_match[] = {
0ec8579e RR	149	{ .compatible = "calxeda,hb-ddr-ctrl", .data = &hb_settings },
	150	{ .compatible = "calxeda,ecx-2000-ddr-ctrl", .data = &mw_settings },
	151	{},
	152	};
	153	MODULE_DEVICE_TABLE(of, hb_ddr_ctrl_of_match);
	154
9b3c6e85	155	static int highbank_mc_probe(struct platform_device *pdev)
a1b01edb	156	{
0ec8579e RR	157	const struct of_device_id *id;
0ec8579e RR	158	const struct hb_mc_settings *settings;
a1b01edb RH	159	struct edac_mc_layer layers[2];
	160	struct mem_ctl_info *mci;
	161	struct hb_mc_drvdata *drvdata;
	162	struct dimm_info *dimm;
	163	struct resource *r;
0ec8579e	164	void __iomem *base;
a1b01edb RH	165	u32 control;
	166	int irq;
	167	int res = 0;
	168
0ec8579e RR	169	id = of_match_device(hb_ddr_ctrl_of_match, &pdev->dev);
	170	if (!id)
	171	return -ENODEV;
	172
a1b01edb RH	173	layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
	174	layers[0].size = 1;
	175	layers[0].is_virt_csrow = true;
	176	layers[1].type = EDAC_MC_LAYER_CHANNEL;
	177	layers[1].size = 1;
	178	layers[1].is_virt_csrow = false;
	179	mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers,
	180	sizeof(struct hb_mc_drvdata));
	181	if (!mci)
	182	return -ENOMEM;
	183
	184	mci->pdev = &pdev->dev;
	185	drvdata = mci->pvt_info;
	186	platform_set_drvdata(pdev, mci);
	187
	188	if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL))
	189	return -ENOMEM;
	190
	191	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	192	if (!r) {
	193	dev_err(&pdev->dev, "Unable to get mem resource\n");
	194	res = -ENODEV;
	195	goto err;
	196	}
	197
	198	if (!devm_request_mem_region(&pdev->dev, r->start,
	199	resource_size(r), dev_name(&pdev->dev))) {
	200	dev_err(&pdev->dev, "Error while requesting mem region\n");
	201	res = -EBUSY;
	202	goto err;
	203	}
	204
0ec8579e RR	205	base = devm_ioremap(&pdev->dev, r->start, resource_size(r));
0ec8579e RR	206	if (!base) {
a1b01edb RH	207	dev_err(&pdev->dev, "Unable to map regs\n");
	208	res = -ENOMEM;
	209	goto err;
	210	}
	211
0ec8579e RR	212	settings = id->data;
	213	drvdata->mc_err_base = base + settings->err_offset;
	214	drvdata->mc_int_base = base + settings->int_offset;
	215
	216	control = readl(drvdata->mc_err_base + HB_DDR_ECC_OPT) & 0x3;
a1b01edb RH	217	if (!control \|\| (control == 0x2)) {
	218	dev_err(&pdev->dev, "No ECC present, or ECC disabled\n");
	219	res = -ENODEV;
	220	goto err;
	221	}
	222
a1b01edb RH	223	mci->mtype_cap = MEM_FLAG_DDR3;
	224	mci->edac_ctl_cap = EDAC_FLAG_NONE \| EDAC_FLAG_SECDED;
	225	mci->edac_cap = EDAC_FLAG_SECDED;
41ec0e8d	226	mci->mod_name = pdev->dev.driver->name;
a1b01edb	227	mci->mod_ver = "1";
41ec0e8d RR	228	mci->ctl_name = id->compatible;
41ec0e8d RR	229	mci->dev_name = dev_name(&pdev->dev);
a1b01edb RH	230	mci->scrub_mode = SCRUB_SW_SRC;
	231
	232	/* Only a single 4GB DIMM is supported */
	233	dimm = *mci->dimms;
	234	dimm->nr_pages = (~0UL >> PAGE_SHIFT) + 1;
	235	dimm->grain = 8;
	236	dimm->dtype = DEV_X8;
	237	dimm->mtype = MEM_DDR3;
	238	dimm->edac_mode = EDAC_SECDED;
	239
fc7cc6b7	240	res = edac_mc_add_mc_with_groups(mci, highbank_dev_groups);
a1b01edb RH	241	if (res < 0)
	242	goto err;
	243
a72b8859 RR	244	irq = platform_get_irq(pdev, 0);
	245	res = devm_request_irq(&pdev->dev, irq, highbank_mc_err_handler,
	246	0, dev_name(&pdev->dev), mci);
	247	if (res < 0) {
	248	dev_err(&pdev->dev, "Unable to request irq %d\n", irq);
	249	goto err2;
	250	}
	251
a1b01edb RH	252	devres_close_group(&pdev->dev, NULL);
a1b01edb RH	253	return 0;
a72b8859 RR	254	err2:
a72b8859 RR	255	edac_mc_del_mc(&pdev->dev);
a1b01edb RH	256	err:
	257	devres_release_group(&pdev->dev, NULL);
	258	edac_mc_free(mci);
	259	return res;
	260	}
	261
	262	static int highbank_mc_remove(struct platform_device *pdev)
	263	{
	264	struct mem_ctl_info *mci = platform_get_drvdata(pdev);
	265
	266	edac_mc_del_mc(&pdev->dev);
	267	edac_mc_free(mci);
	268	return 0;
	269	}
	270
a1b01edb RH	271	static struct platform_driver highbank_mc_edac_driver = {
	272	.probe = highbank_mc_probe,
	273	.remove = highbank_mc_remove,
	274	.driver = {
	275	.name = "hb_mc_edac",
	276	.of_match_table = hb_ddr_ctrl_of_match,
	277	},
	278	};
	279
	280	module_platform_driver(highbank_mc_edac_driver);
	281
	282	MODULE_LICENSE("GPL v2");
	283	MODULE_AUTHOR("Calxeda, Inc.");
	284	MODULE_DESCRIPTION("EDAC Driver for Calxeda Highbank");