[mirror_ubuntu-zesty-kernel.git] / drivers / edac / highbank_mc_edac.c

/*
 * Copyright 2011-2012 Calxeda, Inc.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program.  If not, see <http://www.gnu.org/licenses/>.
 */
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/ctype.h>
#include <linux/edac.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
#include <linux/of_platform.h>
#include <linux/uaccess.h>

#include "edac_core.h"
#include "edac_module.h"

/* DDR Ctrlr Error Registers */

#define HB_DDR_ECC_ERR_BASE		0x128
#define MW_DDR_ECC_ERR_BASE		0x1b4

#define HB_DDR_ECC_OPT			0x00
#define HB_DDR_ECC_U_ERR_ADDR		0x08
#define HB_DDR_ECC_U_ERR_STAT		0x0c
#define HB_DDR_ECC_U_ERR_DATAL		0x10
#define HB_DDR_ECC_U_ERR_DATAH		0x14
#define HB_DDR_ECC_C_ERR_ADDR		0x18
#define HB_DDR_ECC_C_ERR_STAT		0x1c
#define HB_DDR_ECC_C_ERR_DATAL		0x20
#define HB_DDR_ECC_C_ERR_DATAH		0x24

#define HB_DDR_ECC_OPT_MODE_MASK	0x3
#define HB_DDR_ECC_OPT_FWC		0x100
#define HB_DDR_ECC_OPT_XOR_SHIFT	16

/* DDR Ctrlr Interrupt Registers */

#define HB_DDR_ECC_INT_BASE		0x180
#define MW_DDR_ECC_INT_BASE		0x218

#define HB_DDR_ECC_INT_STATUS		0x00
#define HB_DDR_ECC_INT_ACK		0x04

#define HB_DDR_ECC_INT_STAT_CE		0x8
#define HB_DDR_ECC_INT_STAT_DOUBLE_CE	0x10
#define HB_DDR_ECC_INT_STAT_UE		0x20
#define HB_DDR_ECC_INT_STAT_DOUBLE_UE	0x40

struct hb_mc_drvdata {
	void __iomem *mc_err_base;
	void __iomem *mc_int_base;
};

static irqreturn_t highbank_mc_err_handler(int irq, void *dev_id)
{
	struct mem_ctl_info *mci = dev_id;
	struct hb_mc_drvdata *drvdata = mci->pvt_info;
	u32 status, err_addr;

	/* Read the interrupt status register */
	status = readl(drvdata->mc_int_base + HB_DDR_ECC_INT_STATUS);

	if (status & HB_DDR_ECC_INT_STAT_UE) {
		err_addr = readl(drvdata->mc_err_base + HB_DDR_ECC_U_ERR_ADDR);
		edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
				     err_addr >> PAGE_SHIFT,
				     err_addr & ~PAGE_MASK, 0,
				     0, 0, -1,
				     mci->ctl_name, "");
	}
	if (status & HB_DDR_ECC_INT_STAT_CE) {
		u32 syndrome = readl(drvdata->mc_err_base + HB_DDR_ECC_C_ERR_STAT);
		syndrome = (syndrome >> 8) & 0xff;
		err_addr = readl(drvdata->mc_err_base + HB_DDR_ECC_C_ERR_ADDR);
		edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
				     err_addr >> PAGE_SHIFT,
				     err_addr & ~PAGE_MASK, syndrome,
				     0, 0, -1,
				     mci->ctl_name, "");
	}

	/* clear the error, clears the interrupt */
	writel(status, drvdata->mc_int_base + HB_DDR_ECC_INT_ACK);
	return IRQ_HANDLED;
}

#ifdef CONFIG_EDAC_DEBUG
static ssize_t highbank_mc_err_inject_write(struct file *file,
				      const char __user *data,
				      size_t count, loff_t *ppos)
{
	struct mem_ctl_info *mci = file->private_data;
	struct hb_mc_drvdata *pdata = mci->pvt_info;
	char buf[32];
	size_t buf_size;
	u32 reg;
	u8 synd;

	buf_size = min(count, (sizeof(buf)-1));
	if (copy_from_user(buf, data, buf_size))
		return -EFAULT;
	buf[buf_size] = 0;

	if (!kstrtou8(buf, 16, &synd)) {
		reg = readl(pdata->mc_err_base + HB_DDR_ECC_OPT);
		reg &= HB_DDR_ECC_OPT_MODE_MASK;
		reg |= (synd << HB_DDR_ECC_OPT_XOR_SHIFT) | HB_DDR_ECC_OPT_FWC;
		writel(reg, pdata->mc_err_base + HB_DDR_ECC_OPT);
	}

	return count;
}

static const struct file_operations highbank_mc_debug_inject_fops = {
	.open = simple_open,
	.write = highbank_mc_err_inject_write,
	.llseek = generic_file_llseek,
};

static void highbank_mc_create_debugfs_nodes(struct mem_ctl_info *mci)
{
	if (mci->debugfs)
		debugfs_create_file("inject_ctrl", S_IWUSR, mci->debugfs, mci,
				    &highbank_mc_debug_inject_fops);
;
}
#else
static void highbank_mc_create_debugfs_nodes(struct mem_ctl_info *mci)
{}
#endif

struct hb_mc_settings {
	int	err_offset;
	int	int_offset;
};

static struct hb_mc_settings hb_settings = {
	.err_offset = HB_DDR_ECC_ERR_BASE,
	.int_offset = HB_DDR_ECC_INT_BASE,
};

static struct hb_mc_settings mw_settings = {
	.err_offset = MW_DDR_ECC_ERR_BASE,
	.int_offset = MW_DDR_ECC_INT_BASE,
};

static struct of_device_id hb_ddr_ctrl_of_match[] = {
	{ .compatible = "calxeda,hb-ddr-ctrl",		.data = &hb_settings },
	{ .compatible = "calxeda,ecx-2000-ddr-ctrl",	.data = &mw_settings },
	{},
};
MODULE_DEVICE_TABLE(of, hb_ddr_ctrl_of_match);

static int highbank_mc_probe(struct platform_device *pdev)
{
	const struct of_device_id *id;
	const struct hb_mc_settings *settings;
	struct edac_mc_layer layers[2];
	struct mem_ctl_info *mci;
	struct hb_mc_drvdata *drvdata;
	struct dimm_info *dimm;
	struct resource *r;
	void __iomem *base;
	u32 control;
	int irq;
	int res = 0;

	id = of_match_device(hb_ddr_ctrl_of_match, &pdev->dev);
	if (!id)
		return -ENODEV;

	layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
	layers[0].size = 1;
	layers[0].is_virt_csrow = true;
	layers[1].type = EDAC_MC_LAYER_CHANNEL;
	layers[1].size = 1;
	layers[1].is_virt_csrow = false;
	mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers,
			    sizeof(struct hb_mc_drvdata));
	if (!mci)
		return -ENOMEM;

	mci->pdev = &pdev->dev;
	drvdata = mci->pvt_info;
	platform_set_drvdata(pdev, mci);

	if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL))
		return -ENOMEM;

	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!r) {
		dev_err(&pdev->dev, "Unable to get mem resource\n");
		res = -ENODEV;
		goto err;
	}

	if (!devm_request_mem_region(&pdev->dev, r->start,
				     resource_size(r), dev_name(&pdev->dev))) {
		dev_err(&pdev->dev, "Error while requesting mem region\n");
		res = -EBUSY;
		goto err;
	}

	base = devm_ioremap(&pdev->dev, r->start, resource_size(r));
	if (!base) {
		dev_err(&pdev->dev, "Unable to map regs\n");
		res = -ENOMEM;
		goto err;
	}

	settings = id->data;
	drvdata->mc_err_base = base + settings->err_offset;
	drvdata->mc_int_base = base + settings->int_offset;

	control = readl(drvdata->mc_err_base + HB_DDR_ECC_OPT) & 0x3;
	if (!control || (control == 0x2)) {
		dev_err(&pdev->dev, "No ECC present, or ECC disabled\n");
		res = -ENODEV;
		goto err;
	}

	mci->mtype_cap = MEM_FLAG_DDR3;
	mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
	mci->edac_cap = EDAC_FLAG_SECDED;
	mci->mod_name = dev_name(&pdev->dev);
	mci->mod_ver = "1";
	mci->ctl_name = dev_name(&pdev->dev);
	mci->scrub_mode = SCRUB_SW_SRC;

	/* Only a single 4GB DIMM is supported */
	dimm = *mci->dimms;
	dimm->nr_pages = (~0UL >> PAGE_SHIFT) + 1;
	dimm->grain = 8;
	dimm->dtype = DEV_X8;
	dimm->mtype = MEM_DDR3;
	dimm->edac_mode = EDAC_SECDED;

	res = edac_mc_add_mc(mci);
	if (res < 0)
		goto err;

	irq = platform_get_irq(pdev, 0);
	res = devm_request_irq(&pdev->dev, irq, highbank_mc_err_handler,
			       0, dev_name(&pdev->dev), mci);
	if (res < 0) {
		dev_err(&pdev->dev, "Unable to request irq %d\n", irq);
		goto err2;
	}

	highbank_mc_create_debugfs_nodes(mci);

	devres_close_group(&pdev->dev, NULL);
	return 0;
err2:
	edac_mc_del_mc(&pdev->dev);
err:
	devres_release_group(&pdev->dev, NULL);
	edac_mc_free(mci);
	return res;
}

static int highbank_mc_remove(struct platform_device *pdev)
{
	struct mem_ctl_info *mci = platform_get_drvdata(pdev);

	edac_mc_del_mc(&pdev->dev);
	edac_mc_free(mci);
	return 0;
}

static struct platform_driver highbank_mc_edac_driver = {
	.probe = highbank_mc_probe,
	.remove = highbank_mc_remove,
	.driver = {
		.name = "hb_mc_edac",
		.of_match_table = hb_ddr_ctrl_of_match,
	},
};

module_platform_driver(highbank_mc_edac_driver);

MODULE_LICENSE("GPL v2");
MODULE_AUTHOR("Calxeda, Inc.");
MODULE_DESCRIPTION("EDAC Driver for Calxeda Highbank");
Commit	Line	Data
a1b01edb RH	1	/*
	2	* Copyright 2011-2012 Calxeda, Inc.
	3	*
	4	* This program is free software; you can redistribute it and/or modify it
	5	* under the terms and conditions of the GNU General Public License,
	6	* version 2, as published by the Free Software Foundation.
	7	*
	8	* This program is distributed in the hope it will be useful, but WITHOUT
	9	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	10	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	11	* more details.
	12	*
	13	* You should have received a copy of the GNU General Public License along with
	14	* this program. If not, see <http://www.gnu.org/licenses/>.
	15	*/
	16	#include <linux/types.h>
	17	#include <linux/kernel.h>
	18	#include <linux/ctype.h>
	19	#include <linux/edac.h>
	20	#include <linux/interrupt.h>
	21	#include <linux/platform_device.h>
	22	#include <linux/of_platform.h>
	23	#include <linux/uaccess.h>
	24
	25	#include "edac_core.h"
	26	#include "edac_module.h"
	27
	28	/* DDR Ctrlr Error Registers */
a1b01edb	29
0ec8579e RR	30	#define HB_DDR_ECC_ERR_BASE 0x128
	31	#define MW_DDR_ECC_ERR_BASE 0x1b4
	32
	33	#define HB_DDR_ECC_OPT 0x00
	34	#define HB_DDR_ECC_U_ERR_ADDR 0x08
	35	#define HB_DDR_ECC_U_ERR_STAT 0x0c
	36	#define HB_DDR_ECC_U_ERR_DATAL 0x10
	37	#define HB_DDR_ECC_U_ERR_DATAH 0x14
	38	#define HB_DDR_ECC_C_ERR_ADDR 0x18
	39	#define HB_DDR_ECC_C_ERR_STAT 0x1c
	40	#define HB_DDR_ECC_C_ERR_DATAL 0x20
	41	#define HB_DDR_ECC_C_ERR_DATAH 0x24
a1b01edb RH	42
	43	#define HB_DDR_ECC_OPT_MODE_MASK 0x3
	44	#define HB_DDR_ECC_OPT_FWC 0x100
	45	#define HB_DDR_ECC_OPT_XOR_SHIFT 16
	46
0ec8579e RR	47	/* DDR Ctrlr Interrupt Registers */
	48
	49	#define HB_DDR_ECC_INT_BASE 0x180
	50	#define MW_DDR_ECC_INT_BASE 0x218
	51
	52	#define HB_DDR_ECC_INT_STATUS 0x00
	53	#define HB_DDR_ECC_INT_ACK 0x04
	54
	55	#define HB_DDR_ECC_INT_STAT_CE 0x8
	56	#define HB_DDR_ECC_INT_STAT_DOUBLE_CE 0x10
	57	#define HB_DDR_ECC_INT_STAT_UE 0x20
	58	#define HB_DDR_ECC_INT_STAT_DOUBLE_UE 0x40
	59
a1b01edb	60	struct hb_mc_drvdata {
0ec8579e RR	61	void __iomem *mc_err_base;
0ec8579e RR	62	void __iomem *mc_int_base;
a1b01edb RH	63	};
	64
	65	static irqreturn_t highbank_mc_err_handler(int irq, void *dev_id)
	66	{
	67	struct mem_ctl_info *mci = dev_id;
	68	struct hb_mc_drvdata *drvdata = mci->pvt_info;
	69	u32 status, err_addr;
	70
	71	/* Read the interrupt status register */
0ec8579e	72	status = readl(drvdata->mc_int_base + HB_DDR_ECC_INT_STATUS);
a1b01edb RH	73
a1b01edb RH	74	if (status & HB_DDR_ECC_INT_STAT_UE) {
0ec8579e	75	err_addr = readl(drvdata->mc_err_base + HB_DDR_ECC_U_ERR_ADDR);
a1b01edb RH	76	edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
	77	err_addr >> PAGE_SHIFT,
	78	err_addr & ~PAGE_MASK, 0,
	79	0, 0, -1,
	80	mci->ctl_name, "");
	81	}
	82	if (status & HB_DDR_ECC_INT_STAT_CE) {
0ec8579e	83	u32 syndrome = readl(drvdata->mc_err_base + HB_DDR_ECC_C_ERR_STAT);
a1b01edb	84	syndrome = (syndrome >> 8) & 0xff;
0ec8579e	85	err_addr = readl(drvdata->mc_err_base + HB_DDR_ECC_C_ERR_ADDR);
a1b01edb RH	86	edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
	87	err_addr >> PAGE_SHIFT,
	88	err_addr & ~PAGE_MASK, syndrome,
	89	0, 0, -1,
	90	mci->ctl_name, "");
	91	}
	92
	93	/* clear the error, clears the interrupt */
0ec8579e	94	writel(status, drvdata->mc_int_base + HB_DDR_ECC_INT_ACK);
a1b01edb RH	95	return IRQ_HANDLED;
	96	}
	97
	98	#ifdef CONFIG_EDAC_DEBUG
	99	static ssize_t highbank_mc_err_inject_write(struct file *file,
	100	const char __user *data,
	101	size_t count, loff_t *ppos)
	102	{
	103	struct mem_ctl_info *mci = file->private_data;
	104	struct hb_mc_drvdata *pdata = mci->pvt_info;
	105	char buf[32];
	106	size_t buf_size;
	107	u32 reg;
	108	u8 synd;
	109
	110	buf_size = min(count, (sizeof(buf)-1));
	111	if (copy_from_user(buf, data, buf_size))
	112	return -EFAULT;
	113	buf[buf_size] = 0;
	114
	115	if (!kstrtou8(buf, 16, &synd)) {
0ec8579e	116	reg = readl(pdata->mc_err_base + HB_DDR_ECC_OPT);
a1b01edb RH	117	reg &= HB_DDR_ECC_OPT_MODE_MASK;
a1b01edb RH	118	reg \|= (synd << HB_DDR_ECC_OPT_XOR_SHIFT) \| HB_DDR_ECC_OPT_FWC;
0ec8579e	119	writel(reg, pdata->mc_err_base + HB_DDR_ECC_OPT);
a1b01edb RH	120	}
	121
	122	return count;
	123	}
	124
a1b01edb	125	static const struct file_operations highbank_mc_debug_inject_fops = {
f35d852e	126	.open = simple_open,
a1b01edb RH	127	.write = highbank_mc_err_inject_write,
	128	.llseek = generic_file_llseek,
	129	};
	130
9b3c6e85	131	static void highbank_mc_create_debugfs_nodes(struct mem_ctl_info *mci)
a1b01edb RH	132	{
	133	if (mci->debugfs)
	134	debugfs_create_file("inject_ctrl", S_IWUSR, mci->debugfs, mci,
	135	&highbank_mc_debug_inject_fops);
	136	;
	137	}
	138	#else
9b3c6e85	139	static void highbank_mc_create_debugfs_nodes(struct mem_ctl_info *mci)
a1b01edb RH	140	{}
	141	#endif
	142
0ec8579e RR	143	struct hb_mc_settings {
	144	int err_offset;
	145	int int_offset;
	146	};
	147
	148	static struct hb_mc_settings hb_settings = {
	149	.err_offset = HB_DDR_ECC_ERR_BASE,
	150	.int_offset = HB_DDR_ECC_INT_BASE,
	151	};
	152
	153	static struct hb_mc_settings mw_settings = {
	154	.err_offset = MW_DDR_ECC_ERR_BASE,
	155	.int_offset = MW_DDR_ECC_INT_BASE,
	156	};
	157
	158	static struct of_device_id hb_ddr_ctrl_of_match[] = {
	159	{ .compatible = "calxeda,hb-ddr-ctrl", .data = &hb_settings },
	160	{ .compatible = "calxeda,ecx-2000-ddr-ctrl", .data = &mw_settings },
	161	{},
	162	};
	163	MODULE_DEVICE_TABLE(of, hb_ddr_ctrl_of_match);
	164
9b3c6e85	165	static int highbank_mc_probe(struct platform_device *pdev)
a1b01edb	166	{
0ec8579e RR	167	const struct of_device_id *id;
0ec8579e RR	168	const struct hb_mc_settings *settings;
a1b01edb RH	169	struct edac_mc_layer layers[2];
	170	struct mem_ctl_info *mci;
	171	struct hb_mc_drvdata *drvdata;
	172	struct dimm_info *dimm;
	173	struct resource *r;
0ec8579e	174	void __iomem *base;
a1b01edb RH	175	u32 control;
	176	int irq;
	177	int res = 0;
	178
0ec8579e RR	179	id = of_match_device(hb_ddr_ctrl_of_match, &pdev->dev);
	180	if (!id)
	181	return -ENODEV;
	182
a1b01edb RH	183	layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
	184	layers[0].size = 1;
	185	layers[0].is_virt_csrow = true;
	186	layers[1].type = EDAC_MC_LAYER_CHANNEL;
	187	layers[1].size = 1;
	188	layers[1].is_virt_csrow = false;
	189	mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers,
	190	sizeof(struct hb_mc_drvdata));
	191	if (!mci)
	192	return -ENOMEM;
	193
	194	mci->pdev = &pdev->dev;
	195	drvdata = mci->pvt_info;
	196	platform_set_drvdata(pdev, mci);
	197
	198	if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL))
	199	return -ENOMEM;
	200
	201	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	202	if (!r) {
	203	dev_err(&pdev->dev, "Unable to get mem resource\n");
	204	res = -ENODEV;
	205	goto err;
	206	}
	207
	208	if (!devm_request_mem_region(&pdev->dev, r->start,
	209	resource_size(r), dev_name(&pdev->dev))) {
	210	dev_err(&pdev->dev, "Error while requesting mem region\n");
	211	res = -EBUSY;
	212	goto err;
	213	}
	214
0ec8579e RR	215	base = devm_ioremap(&pdev->dev, r->start, resource_size(r));
0ec8579e RR	216	if (!base) {
a1b01edb RH	217	dev_err(&pdev->dev, "Unable to map regs\n");
	218	res = -ENOMEM;
	219	goto err;
	220	}
	221
0ec8579e RR	222	settings = id->data;
	223	drvdata->mc_err_base = base + settings->err_offset;
	224	drvdata->mc_int_base = base + settings->int_offset;
	225
	226	control = readl(drvdata->mc_err_base + HB_DDR_ECC_OPT) & 0x3;
a1b01edb RH	227	if (!control \|\| (control == 0x2)) {
	228	dev_err(&pdev->dev, "No ECC present, or ECC disabled\n");
	229	res = -ENODEV;
	230	goto err;
	231	}
	232
a1b01edb RH	233	mci->mtype_cap = MEM_FLAG_DDR3;
	234	mci->edac_ctl_cap = EDAC_FLAG_NONE \| EDAC_FLAG_SECDED;
	235	mci->edac_cap = EDAC_FLAG_SECDED;
	236	mci->mod_name = dev_name(&pdev->dev);
	237	mci->mod_ver = "1";
	238	mci->ctl_name = dev_name(&pdev->dev);
	239	mci->scrub_mode = SCRUB_SW_SRC;
	240
	241	/* Only a single 4GB DIMM is supported */
	242	dimm = *mci->dimms;
	243	dimm->nr_pages = (~0UL >> PAGE_SHIFT) + 1;
	244	dimm->grain = 8;
	245	dimm->dtype = DEV_X8;
	246	dimm->mtype = MEM_DDR3;
	247	dimm->edac_mode = EDAC_SECDED;
	248
	249	res = edac_mc_add_mc(mci);
	250	if (res < 0)
	251	goto err;
	252
a72b8859 RR	253	irq = platform_get_irq(pdev, 0);
	254	res = devm_request_irq(&pdev->dev, irq, highbank_mc_err_handler,
	255	0, dev_name(&pdev->dev), mci);
	256	if (res < 0) {
	257	dev_err(&pdev->dev, "Unable to request irq %d\n", irq);
	258	goto err2;
	259	}
	260
a1b01edb RH	261	highbank_mc_create_debugfs_nodes(mci);
	262
	263	devres_close_group(&pdev->dev, NULL);
	264	return 0;
a72b8859 RR	265	err2:
a72b8859 RR	266	edac_mc_del_mc(&pdev->dev);
a1b01edb RH	267	err:
	268	devres_release_group(&pdev->dev, NULL);
	269	edac_mc_free(mci);
	270	return res;
	271	}
	272
	273	static int highbank_mc_remove(struct platform_device *pdev)
	274	{
	275	struct mem_ctl_info *mci = platform_get_drvdata(pdev);
	276
	277	edac_mc_del_mc(&pdev->dev);
	278	edac_mc_free(mci);
	279	return 0;
	280	}
	281
a1b01edb RH	282	static struct platform_driver highbank_mc_edac_driver = {
	283	.probe = highbank_mc_probe,
	284	.remove = highbank_mc_remove,
	285	.driver = {
	286	.name = "hb_mc_edac",
	287	.of_match_table = hb_ddr_ctrl_of_match,
	288	},
	289	};
	290
	291	module_platform_driver(highbank_mc_edac_driver);
	292
	293	MODULE_LICENSE("GPL v2");
	294	MODULE_AUTHOR("Calxeda, Inc.");
	295	MODULE_DESCRIPTION("EDAC Driver for Calxeda Highbank");