[mirror_ubuntu-artful-kernel.git] / drivers / edac / i3000_edac.c

/*
 * Intel 3000/3010 Memory Controller kernel module
 * Copyright (C) 2007 Akamai Technologies, Inc.
 * Shamelessly copied from:
 * 	Intel D82875P Memory Controller kernel module
 * 	(C) 2003 Linux Networx (http://lnxi.com)
 *
 * This file may be distributed under the terms of the
 * GNU General Public License.
 */

#include <linux/module.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/pci_ids.h>
#include <linux/edac.h>
#include "edac_module.h"

#define I3000_REVISION		"1.1"

#define EDAC_MOD_STR		"i3000_edac"

#define I3000_RANKS		8
#define I3000_RANKS_PER_CHANNEL	4
#define I3000_CHANNELS		2

/* Intel 3000 register addresses - device 0 function 0 - DRAM Controller */

#define I3000_MCHBAR		0x44	/* MCH Memory Mapped Register BAR */
#define I3000_MCHBAR_MASK	0xffffc000
#define I3000_MMR_WINDOW_SIZE	16384

#define I3000_EDEAP	0x70	/* Extended DRAM Error Address Pointer (8b)
				 *
				 * 7:1   reserved
				 * 0     bit 32 of address
				 */
#define I3000_DEAP	0x58	/* DRAM Error Address Pointer (32b)
				 *
				 * 31:7  address
				 * 6:1   reserved
				 * 0     Error channel 0/1
				 */
#define I3000_DEAP_GRAIN 		(1 << 7)

/*
 * Helper functions to decode the DEAP/EDEAP hardware registers.
 *
 * The type promotion here is deliberate; we're deriving an
 * unsigned long pfn and offset from hardware regs which are u8/u32.
 */

static inline unsigned long deap_pfn(u8 edeap, u32 deap)
{
	deap >>= PAGE_SHIFT;
	deap |= (edeap & 1) << (32 - PAGE_SHIFT);
	return deap;
}

static inline unsigned long deap_offset(u32 deap)
{
	return deap & ~(I3000_DEAP_GRAIN - 1) & ~PAGE_MASK;
}

static inline int deap_channel(u32 deap)
{
	return deap & 1;
}

#define I3000_DERRSYN	0x5c	/* DRAM Error Syndrome (8b)
				 *
				 *  7:0  DRAM ECC Syndrome
				 */

#define I3000_ERRSTS	0xc8	/* Error Status Register (16b)
				 *
				 * 15:12 reserved
				 * 11    MCH Thermal Sensor Event
				 *         for SMI/SCI/SERR
				 * 10    reserved
				 *  9    LOCK to non-DRAM Memory Flag (LCKF)
				 *  8    Received Refresh Timeout Flag (RRTOF)
				 *  7:2  reserved
				 *  1    Multi-bit DRAM ECC Error Flag (DMERR)
				 *  0    Single-bit DRAM ECC Error Flag (DSERR)
				 */
#define I3000_ERRSTS_BITS	0x0b03	/* bits which indicate errors */
#define I3000_ERRSTS_UE		0x0002
#define I3000_ERRSTS_CE		0x0001

#define I3000_ERRCMD	0xca	/* Error Command (16b)
				 *
				 * 15:12 reserved
				 * 11    SERR on MCH Thermal Sensor Event
				 *         (TSESERR)
				 * 10    reserved
				 *  9    SERR on LOCK to non-DRAM Memory
				 *         (LCKERR)
				 *  8    SERR on DRAM Refresh Timeout
				 *         (DRTOERR)
				 *  7:2  reserved
				 *  1    SERR Multi-Bit DRAM ECC Error
				 *         (DMERR)
				 *  0    SERR on Single-Bit ECC Error
				 *         (DSERR)
				 */

/* Intel  MMIO register space - device 0 function 0 - MMR space */

#define I3000_DRB_SHIFT 25	/* 32MiB grain */

#define I3000_C0DRB	0x100	/* Channel 0 DRAM Rank Boundary (8b x 4)
				 *
				 * 7:0   Channel 0 DRAM Rank Boundary Address
				 */
#define I3000_C1DRB	0x180	/* Channel 1 DRAM Rank Boundary (8b x 4)
				 *
				 * 7:0   Channel 1 DRAM Rank Boundary Address
				 */

#define I3000_C0DRA	0x108	/* Channel 0 DRAM Rank Attribute (8b x 2)
				 *
				 * 7     reserved
				 * 6:4   DRAM odd Rank Attribute
				 * 3     reserved
				 * 2:0   DRAM even Rank Attribute
				 *
				 * Each attribute defines the page
				 * size of the corresponding rank:
				 *     000: unpopulated
				 *     001: reserved
				 *     010: 4 KB
				 *     011: 8 KB
				 *     100: 16 KB
				 *     Others: reserved
				 */
#define I3000_C1DRA	0x188	/* Channel 1 DRAM Rank Attribute (8b x 2) */

static inline unsigned char odd_rank_attrib(unsigned char dra)
{
	return (dra & 0x70) >> 4;
}

static inline unsigned char even_rank_attrib(unsigned char dra)
{
	return dra & 0x07;
}

#define I3000_C0DRC0	0x120	/* DRAM Controller Mode 0 (32b)
				 *
				 * 31:30 reserved
				 * 29    Initialization Complete (IC)
				 * 28:11 reserved
				 * 10:8  Refresh Mode Select (RMS)
				 * 7     reserved
				 * 6:4   Mode Select (SMS)
				 * 3:2   reserved
				 * 1:0   DRAM Type (DT)
				 */

#define I3000_C0DRC1	0x124	/* DRAM Controller Mode 1 (32b)
				 *
				 * 31    Enhanced Addressing Enable (ENHADE)
				 * 30:0  reserved
				 */

enum i3000p_chips {
	I3000 = 0,
};

struct i3000_dev_info {
	const char *ctl_name;
};

struct i3000_error_info {
	u16 errsts;
	u8 derrsyn;
	u8 edeap;
	u32 deap;
	u16 errsts2;
};

static const struct i3000_dev_info i3000_devs[] = {
	[I3000] = {
		.ctl_name = "i3000"},
};

static struct pci_dev *mci_pdev;
static int i3000_registered = 1;
static struct edac_pci_ctl_info *i3000_pci;

static void i3000_get_error_info(struct mem_ctl_info *mci,
				 struct i3000_error_info *info)
{
	struct pci_dev *pdev;

	pdev = to_pci_dev(mci->pdev);

	/*
	 * This is a mess because there is no atomic way to read all the
	 * registers at once and the registers can transition from CE being
	 * overwritten by UE.
	 */
	pci_read_config_word(pdev, I3000_ERRSTS, &info->errsts);
	if (!(info->errsts & I3000_ERRSTS_BITS))
		return;
	pci_read_config_byte(pdev, I3000_EDEAP, &info->edeap);
	pci_read_config_dword(pdev, I3000_DEAP, &info->deap);
	pci_read_config_byte(pdev, I3000_DERRSYN, &info->derrsyn);
	pci_read_config_word(pdev, I3000_ERRSTS, &info->errsts2);

	/*
	 * If the error is the same for both reads then the first set
	 * of reads is valid.  If there is a change then there is a CE
	 * with no info and the second set of reads is valid and
	 * should be UE info.
	 */
	if ((info->errsts ^ info->errsts2) & I3000_ERRSTS_BITS) {
		pci_read_config_byte(pdev, I3000_EDEAP, &info->edeap);
		pci_read_config_dword(pdev, I3000_DEAP, &info->deap);
		pci_read_config_byte(pdev, I3000_DERRSYN, &info->derrsyn);
	}

	/*
	 * Clear any error bits.
	 * (Yes, we really clear bits by writing 1 to them.)
	 */
	pci_write_bits16(pdev, I3000_ERRSTS, I3000_ERRSTS_BITS,
			 I3000_ERRSTS_BITS);
}

static int i3000_process_error_info(struct mem_ctl_info *mci,
				struct i3000_error_info *info,
				int handle_errors)
{
	int row, multi_chan, channel;
	unsigned long pfn, offset;

	multi_chan = mci->csrows[0]->nr_channels - 1;

	if (!(info->errsts & I3000_ERRSTS_BITS))
		return 0;

	if (!handle_errors)
		return 1;

	if ((info->errsts ^ info->errsts2) & I3000_ERRSTS_BITS) {
		edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, 0, 0, 0,
				     -1, -1, -1,
				     "UE overwrote CE", "");
		info->errsts = info->errsts2;
	}

	pfn = deap_pfn(info->edeap, info->deap);
	offset = deap_offset(info->deap);
	channel = deap_channel(info->deap);

	row = edac_mc_find_csrow_by_page(mci, pfn);

	if (info->errsts & I3000_ERRSTS_UE)
		edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
				     pfn, offset, 0,
				     row, -1, -1,
				     "i3000 UE", "");
	else
		edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
				     pfn, offset, info->derrsyn,
				     row, multi_chan ? channel : 0, -1,
				     "i3000 CE", "");

	return 1;
}

static void i3000_check(struct mem_ctl_info *mci)
{
	struct i3000_error_info info;

	edac_dbg(1, "MC%d\n", mci->mc_idx);
	i3000_get_error_info(mci, &info);
	i3000_process_error_info(mci, &info, 1);
}

static int i3000_is_interleaved(const unsigned char *c0dra,
				const unsigned char *c1dra,
				const unsigned char *c0drb,
				const unsigned char *c1drb)
{
	int i;

	/*
	 * If the channels aren't populated identically then
	 * we're not interleaved.
	 */
	for (i = 0; i < I3000_RANKS_PER_CHANNEL / 2; i++)
		if (odd_rank_attrib(c0dra[i]) != odd_rank_attrib(c1dra[i]) ||
			even_rank_attrib(c0dra[i]) !=
						even_rank_attrib(c1dra[i]))
			return 0;

	/*
	 * If the rank boundaries for the two channels are different
	 * then we're not interleaved.
	 */
	for (i = 0; i < I3000_RANKS_PER_CHANNEL; i++)
		if (c0drb[i] != c1drb[i])
			return 0;

	return 1;
}

static int i3000_probe1(struct pci_dev *pdev, int dev_idx)
{
	int rc;
	int i, j;
	struct mem_ctl_info *mci = NULL;
	struct edac_mc_layer layers[2];
	unsigned long last_cumul_size, nr_pages;
	int interleaved, nr_channels;
	unsigned char dra[I3000_RANKS / 2], drb[I3000_RANKS];
	unsigned char *c0dra = dra, *c1dra = &dra[I3000_RANKS_PER_CHANNEL / 2];
	unsigned char *c0drb = drb, *c1drb = &drb[I3000_RANKS_PER_CHANNEL];
	unsigned long mchbar;
	void __iomem *window;

	edac_dbg(0, "MC:\n");

	pci_read_config_dword(pdev, I3000_MCHBAR, (u32 *) & mchbar);
	mchbar &= I3000_MCHBAR_MASK;
	window = ioremap_nocache(mchbar, I3000_MMR_WINDOW_SIZE);
	if (!window) {
		printk(KERN_ERR "i3000: cannot map mmio space at 0x%lx\n",
			mchbar);
		return -ENODEV;
	}

	c0dra[0] = readb(window + I3000_C0DRA + 0);	/* ranks 0,1 */
	c0dra[1] = readb(window + I3000_C0DRA + 1);	/* ranks 2,3 */
	c1dra[0] = readb(window + I3000_C1DRA + 0);	/* ranks 0,1 */
	c1dra[1] = readb(window + I3000_C1DRA + 1);	/* ranks 2,3 */

	for (i = 0; i < I3000_RANKS_PER_CHANNEL; i++) {
		c0drb[i] = readb(window + I3000_C0DRB + i);
		c1drb[i] = readb(window + I3000_C1DRB + i);
	}

	iounmap(window);

	/*
	 * Figure out how many channels we have.
	 *
	 * If we have what the datasheet calls "asymmetric channels"
	 * (essentially the same as what was called "virtual single
	 * channel mode" in the i82875) then it's a single channel as
	 * far as EDAC is concerned.
	 */
	interleaved = i3000_is_interleaved(c0dra, c1dra, c0drb, c1drb);
	nr_channels = interleaved ? 2 : 1;

	layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
	layers[0].size = I3000_RANKS / nr_channels;
	layers[0].is_virt_csrow = true;
	layers[1].type = EDAC_MC_LAYER_CHANNEL;
	layers[1].size = nr_channels;
	layers[1].is_virt_csrow = false;
	mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0);
	if (!mci)
		return -ENOMEM;

	edac_dbg(3, "MC: init mci\n");

	mci->pdev = &pdev->dev;
	mci->mtype_cap = MEM_FLAG_DDR2;

	mci->edac_ctl_cap = EDAC_FLAG_SECDED;
	mci->edac_cap = EDAC_FLAG_SECDED;

	mci->mod_name = EDAC_MOD_STR;
	mci->mod_ver = I3000_REVISION;
	mci->ctl_name = i3000_devs[dev_idx].ctl_name;
	mci->dev_name = pci_name(pdev);
	mci->edac_check = i3000_check;
	mci->ctl_page_to_phys = NULL;

	/*
	 * The dram rank boundary (DRB) reg values are boundary addresses
	 * for each DRAM rank with a granularity of 32MB.  DRB regs are
	 * cumulative; the last one will contain the total memory
	 * contained in all ranks.
	 *
	 * If we're in interleaved mode then we're only walking through
	 * the ranks of controller 0, so we double all the values we see.
	 */
	for (last_cumul_size = i = 0; i < mci->nr_csrows; i++) {
		u8 value;
		u32 cumul_size;
		struct csrow_info *csrow = mci->csrows[i];

		value = drb[i];
		cumul_size = value << (I3000_DRB_SHIFT - PAGE_SHIFT);
		if (interleaved)
			cumul_size <<= 1;
		edac_dbg(3, "MC: (%d) cumul_size 0x%x\n", i, cumul_size);
		if (cumul_size == last_cumul_size)
			continue;

		csrow->first_page = last_cumul_size;
		csrow->last_page = cumul_size - 1;
		nr_pages = cumul_size - last_cumul_size;
		last_cumul_size = cumul_size;

		for (j = 0; j < nr_channels; j++) {
			struct dimm_info *dimm = csrow->channels[j]->dimm;

			dimm->nr_pages = nr_pages / nr_channels;
			dimm->grain = I3000_DEAP_GRAIN;
			dimm->mtype = MEM_DDR2;
			dimm->dtype = DEV_UNKNOWN;
			dimm->edac_mode = EDAC_UNKNOWN;
		}
	}

	/*
	 * Clear any error bits.
	 * (Yes, we really clear bits by writing 1 to them.)
	 */
	pci_write_bits16(pdev, I3000_ERRSTS, I3000_ERRSTS_BITS,
			 I3000_ERRSTS_BITS);

	rc = -ENODEV;
	if (edac_mc_add_mc(mci)) {
		edac_dbg(3, "MC: failed edac_mc_add_mc()\n");
		goto fail;
	}

	/* allocating generic PCI control info */
	i3000_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
	if (!i3000_pci) {
		printk(KERN_WARNING
			"%s(): Unable to create PCI control\n",
			__func__);
		printk(KERN_WARNING
			"%s(): PCI error report via EDAC not setup\n",
			__func__);
	}

	/* get this far and it's successful */
	edac_dbg(3, "MC: success\n");
	return 0;

fail:
	if (mci)
		edac_mc_free(mci);

	return rc;
}

/* returns count (>= 0), or negative on error */
static int i3000_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
{
	int rc;

	edac_dbg(0, "MC:\n");

	if (pci_enable_device(pdev) < 0)
		return -EIO;

	rc = i3000_probe1(pdev, ent->driver_data);
	if (!mci_pdev)
		mci_pdev = pci_dev_get(pdev);

	return rc;
}

static void i3000_remove_one(struct pci_dev *pdev)
{
	struct mem_ctl_info *mci;

	edac_dbg(0, "\n");

	if (i3000_pci)
		edac_pci_release_generic_ctl(i3000_pci);

	mci = edac_mc_del_mc(&pdev->dev);
	if (!mci)
		return;

	edac_mc_free(mci);
}

static const struct pci_device_id i3000_pci_tbl[] = {
	{
	 PCI_VEND_DEV(INTEL, 3000_HB), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
	 I3000},
	{
	 0,
	 }			/* 0 terminated list. */
};

MODULE_DEVICE_TABLE(pci, i3000_pci_tbl);

static struct pci_driver i3000_driver = {
	.name = EDAC_MOD_STR,
	.probe = i3000_init_one,
	.remove = i3000_remove_one,
	.id_table = i3000_pci_tbl,
};

static int __init i3000_init(void)
{
	int pci_rc;

	edac_dbg(3, "MC:\n");

       /* Ensure that the OPSTATE is set correctly for POLL or NMI */
       opstate_init();

	pci_rc = pci_register_driver(&i3000_driver);
	if (pci_rc < 0)
		goto fail0;

	if (!mci_pdev) {
		i3000_registered = 0;
		mci_pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
					PCI_DEVICE_ID_INTEL_3000_HB, NULL);
		if (!mci_pdev) {
			edac_dbg(0, "i3000 pci_get_device fail\n");
			pci_rc = -ENODEV;
			goto fail1;
		}

		pci_rc = i3000_init_one(mci_pdev, i3000_pci_tbl);
		if (pci_rc < 0) {
			edac_dbg(0, "i3000 init fail\n");
			pci_rc = -ENODEV;
			goto fail1;
		}
	}

	return 0;

fail1:
	pci_unregister_driver(&i3000_driver);

fail0:
	pci_dev_put(mci_pdev);

	return pci_rc;
}

static void __exit i3000_exit(void)
{
	edac_dbg(3, "MC:\n");

	pci_unregister_driver(&i3000_driver);
	if (!i3000_registered) {
		i3000_remove_one(mci_pdev);
		pci_dev_put(mci_pdev);
	}
}

module_init(i3000_init);
module_exit(i3000_exit);

MODULE_LICENSE("GPL");
MODULE_AUTHOR("Akamai Technologies Arthur Ulfeldt/Jason Uhlenkott");
MODULE_DESCRIPTION("MC support for Intel 3000 memory hub controllers");

module_param(edac_op_state, int, 0444);
MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
Commit	Line	Data
535c6a53 JU	1	/*
	2	* Intel 3000/3010 Memory Controller kernel module
	3	* Copyright (C) 2007 Akamai Technologies, Inc.
	4	* Shamelessly copied from:
	5	* Intel D82875P Memory Controller kernel module
	6	* (C) 2003 Linux Networx (http://lnxi.com)
	7	*
	8	* This file may be distributed under the terms of the
	9	* GNU General Public License.
	10	*/
	11
	12	#include <linux/module.h>
	13	#include <linux/init.h>
	14	#include <linux/pci.h>
	15	#include <linux/pci_ids.h>
7ed31e0f	16	#include <linux/edac.h>
78d88e8a	17	#include "edac_module.h"
535c6a53 JU	18
	19	#define I3000_REVISION "1.1"
	20
	21	#define EDAC_MOD_STR "i3000_edac"
	22
	23	#define I3000_RANKS 8
	24	#define I3000_RANKS_PER_CHANNEL 4
	25	#define I3000_CHANNELS 2
	26
	27	/* Intel 3000 register addresses - device 0 function 0 - DRAM Controller */
	28
	29	#define I3000_MCHBAR 0x44 /* MCH Memory Mapped Register BAR */
	30	#define I3000_MCHBAR_MASK 0xffffc000
	31	#define I3000_MMR_WINDOW_SIZE 16384
	32
ce783d70 JU	33	#define I3000_EDEAP 0x70 /* Extended DRAM Error Address Pointer (8b)
	34	*
	35	* 7:1 reserved
	36	* 0 bit 32 of address
	37	*/
	38	#define I3000_DEAP 0x58 /* DRAM Error Address Pointer (32b)
	39	*
	40	* 31:7 address
	41	* 6:1 reserved
	42	* 0 Error channel 0/1
	43	*/
	44	#define I3000_DEAP_GRAIN (1 << 7)
4d2b165e	45
870897a5 JU	46	/*
	47	* Helper functions to decode the DEAP/EDEAP hardware registers.
	48	*
	49	* The type promotion here is deliberate; we're deriving an
	50	* unsigned long pfn and offset from hardware regs which are u8/u32.
	51	*/
	52
4d2b165e JU	53	static inline unsigned long deap_pfn(u8 edeap, u32 deap)
	54	{
	55	deap >>= PAGE_SHIFT;
	56	deap \|= (edeap & 1) << (32 - PAGE_SHIFT);
	57	return deap;
	58	}
	59
	60	static inline unsigned long deap_offset(u32 deap)
	61	{
	62	return deap & ~(I3000_DEAP_GRAIN - 1) & ~PAGE_MASK;
	63	}
	64
	65	static inline int deap_channel(u32 deap)
	66	{
	67	return deap & 1;
	68	}
535c6a53	69
ce783d70 JU	70	#define I3000_DERRSYN 0x5c /* DRAM Error Syndrome (8b)
	71	*
	72	* 7:0 DRAM ECC Syndrome
	73	*/
	74
	75	#define I3000_ERRSTS 0xc8 /* Error Status Register (16b)
	76	*
	77	* 15:12 reserved
	78	* 11 MCH Thermal Sensor Event
	79	* for SMI/SCI/SERR
	80	* 10 reserved
	81	* 9 LOCK to non-DRAM Memory Flag (LCKF)
	82	* 8 Received Refresh Timeout Flag (RRTOF)
	83	* 7:2 reserved
	84	* 1 Multi-bit DRAM ECC Error Flag (DMERR)
	85	* 0 Single-bit DRAM ECC Error Flag (DSERR)
	86	*/
535c6a53 JU	87	#define I3000_ERRSTS_BITS 0x0b03 /* bits which indicate errors */
	88	#define I3000_ERRSTS_UE 0x0002
	89	#define I3000_ERRSTS_CE 0x0001
	90
ce783d70 JU	91	#define I3000_ERRCMD 0xca /* Error Command (16b)
	92	*
	93	* 15:12 reserved
	94	* 11 SERR on MCH Thermal Sensor Event
	95	* (TSESERR)
	96	* 10 reserved
	97	* 9 SERR on LOCK to non-DRAM Memory
	98	* (LCKERR)
	99	* 8 SERR on DRAM Refresh Timeout
	100	* (DRTOERR)
	101	* 7:2 reserved
	102	* 1 SERR Multi-Bit DRAM ECC Error
	103	* (DMERR)
	104	* 0 SERR on Single-Bit ECC Error
	105	* (DSERR)
	106	*/
535c6a53 JU	107
	108	/* Intel MMIO register space - device 0 function 0 - MMR space */
	109
	110	#define I3000_DRB_SHIFT 25 /* 32MiB grain */
	111
ce783d70 JU	112	#define I3000_C0DRB 0x100 /* Channel 0 DRAM Rank Boundary (8b x 4)
	113	*
	114	* 7:0 Channel 0 DRAM Rank Boundary Address
	115	*/
	116	#define I3000_C1DRB 0x180 /* Channel 1 DRAM Rank Boundary (8b x 4)
	117	*
	118	* 7:0 Channel 1 DRAM Rank Boundary Address
	119	*/
	120
	121	#define I3000_C0DRA 0x108 /* Channel 0 DRAM Rank Attribute (8b x 2)
	122	*
	123	* 7 reserved
	124	* 6:4 DRAM odd Rank Attribute
	125	* 3 reserved
	126	* 2:0 DRAM even Rank Attribute
	127	*
	128	* Each attribute defines the page
	129	* size of the corresponding rank:
	130	* 000: unpopulated
	131	* 001: reserved
	132	* 010: 4 KB
	133	* 011: 8 KB
	134	* 100: 16 KB
	135	* Others: reserved
	136	*/
	137	#define I3000_C1DRA 0x188 /* Channel 1 DRAM Rank Attribute (8b x 2) */
4d2b165e JU	138
	139	static inline unsigned char odd_rank_attrib(unsigned char dra)
	140	{
	141	return (dra & 0x70) >> 4;
	142	}
	143
	144	static inline unsigned char even_rank_attrib(unsigned char dra)
	145	{
	146	return dra & 0x07;
	147	}
ce783d70 JU	148
	149	#define I3000_C0DRC0 0x120 /* DRAM Controller Mode 0 (32b)
	150	*
	151	* 31:30 reserved
	152	* 29 Initialization Complete (IC)
	153	* 28:11 reserved
	154	* 10:8 Refresh Mode Select (RMS)
	155	* 7 reserved
	156	* 6:4 Mode Select (SMS)
	157	* 3:2 reserved
	158	* 1:0 DRAM Type (DT)
	159	*/
	160
	161	#define I3000_C0DRC1 0x124 /* DRAM Controller Mode 1 (32b)
	162	*
	163	* 31 Enhanced Addressing Enable (ENHADE)
	164	* 30:0 reserved
	165	*/
535c6a53	166
535c6a53 JU	167	enum i3000p_chips {
	168	I3000 = 0,
	169	};
	170
	171	struct i3000_dev_info {
	172	const char *ctl_name;
	173	};
	174
	175	struct i3000_error_info {
	176	u16 errsts;
	177	u8 derrsyn;
	178	u8 edeap;
	179	u32 deap;
	180	u16 errsts2;
	181	};
	182
	183	static const struct i3000_dev_info i3000_devs[] = {
	184	[I3000] = {
052dfb45	185	.ctl_name = "i3000"},
535c6a53 JU	186	};
535c6a53 JU	187
f044091c	188	static struct pci_dev *mci_pdev;
535c6a53	189	static int i3000_registered = 1;
456a2f95	190	static struct edac_pci_ctl_info *i3000_pci;
535c6a53 JU	191
535c6a53 JU	192	static void i3000_get_error_info(struct mem_ctl_info *mci,
36b8289e	193	struct i3000_error_info *info)
535c6a53 JU	194	{
	195	struct pci_dev *pdev;
	196
fd687502	197	pdev = to_pci_dev(mci->pdev);
535c6a53 JU	198
	199	/*
	200	* This is a mess because there is no atomic way to read all the
	201	* registers at once and the registers can transition from CE being
	202	* overwritten by UE.
	203	*/
	204	pci_read_config_word(pdev, I3000_ERRSTS, &info->errsts);
	205	if (!(info->errsts & I3000_ERRSTS_BITS))
	206	return;
	207	pci_read_config_byte(pdev, I3000_EDEAP, &info->edeap);
	208	pci_read_config_dword(pdev, I3000_DEAP, &info->deap);
	209	pci_read_config_byte(pdev, I3000_DERRSYN, &info->derrsyn);
	210	pci_read_config_word(pdev, I3000_ERRSTS, &info->errsts2);
	211
	212	/*
	213	* If the error is the same for both reads then the first set
	214	* of reads is valid. If there is a change then there is a CE
	215	* with no info and the second set of reads is valid and
	216	* should be UE info.
	217	*/
	218	if ((info->errsts ^ info->errsts2) & I3000_ERRSTS_BITS) {
36b8289e DJ	219	pci_read_config_byte(pdev, I3000_EDEAP, &info->edeap);
	220	pci_read_config_dword(pdev, I3000_DEAP, &info->deap);
	221	pci_read_config_byte(pdev, I3000_DERRSYN, &info->derrsyn);
535c6a53 JU	222	}
535c6a53 JU	223
ce783d70 JU	224	/*
ce783d70 JU	225	* Clear any error bits.
535c6a53 JU	226	* (Yes, we really clear bits by writing 1 to them.)
535c6a53 JU	227	*/
36b8289e DJ	228	pci_write_bits16(pdev, I3000_ERRSTS, I3000_ERRSTS_BITS,
36b8289e DJ	229	I3000_ERRSTS_BITS);
535c6a53 JU	230	}
	231
	232	static int i3000_process_error_info(struct mem_ctl_info *mci,
052dfb45 DT	233	struct i3000_error_info *info,
052dfb45 DT	234	int handle_errors)
535c6a53	235	{
4d2b165e JU	236	int row, multi_chan, channel;
4d2b165e JU	237	unsigned long pfn, offset;
535c6a53	238
de3910eb	239	multi_chan = mci->csrows[0]->nr_channels - 1;
535c6a53 JU	240
	241	if (!(info->errsts & I3000_ERRSTS_BITS))
	242	return 0;
	243
	244	if (!handle_errors)
	245	return 1;
	246
	247	if ((info->errsts ^ info->errsts2) & I3000_ERRSTS_BITS) {
9eb07a7f	248	edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, 0, 0, 0,
884906f1	249	-1, -1, -1,
03f7eae8	250	"UE overwrote CE", "");
535c6a53 JU	251	info->errsts = info->errsts2;
	252	}
	253
4d2b165e JU	254	pfn = deap_pfn(info->edeap, info->deap);
	255	offset = deap_offset(info->deap);
	256	channel = deap_channel(info->deap);
535c6a53 JU	257
	258	row = edac_mc_find_csrow_by_page(mci, pfn);
	259
	260	if (info->errsts & I3000_ERRSTS_UE)
9eb07a7f	261	edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
884906f1 MCC	262	pfn, offset, 0,
884906f1 MCC	263	row, -1, -1,
03f7eae8	264	"i3000 UE", "");
535c6a53	265	else
9eb07a7f	266	edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
884906f1 MCC	267	pfn, offset, info->derrsyn,
884906f1 MCC	268	row, multi_chan ? channel : 0, -1,
03f7eae8	269	"i3000 CE", "");
535c6a53 JU	270
	271	return 1;
	272	}
	273
	274	static void i3000_check(struct mem_ctl_info *mci)
	275	{
	276	struct i3000_error_info info;
	277
956b9ba1	278	edac_dbg(1, "MC%d\n", mci->mc_idx);
535c6a53 JU	279	i3000_get_error_info(mci, &info);
	280	i3000_process_error_info(mci, &info, 1);
	281	}
	282
	283	static int i3000_is_interleaved(const unsigned char *c0dra,
	284	const unsigned char *c1dra,
	285	const unsigned char *c0drb,
	286	const unsigned char *c1drb)
	287	{
	288	int i;
	289
ce783d70 JU	290	/*
ce783d70 JU	291	* If the channels aren't populated identically then
535c6a53 JU	292	* we're not interleaved.
	293	*/
	294	for (i = 0; i < I3000_RANKS_PER_CHANNEL / 2; i++)
4d2b165e JU	295	if (odd_rank_attrib(c0dra[i]) != odd_rank_attrib(c1dra[i]) \|\|
	296	even_rank_attrib(c0dra[i]) !=
	297	even_rank_attrib(c1dra[i]))
535c6a53 JU	298	return 0;
535c6a53 JU	299
ce783d70 JU	300	/*
ce783d70 JU	301	* If the rank boundaries for the two channels are different
535c6a53 JU	302	* then we're not interleaved.
	303	*/
	304	for (i = 0; i < I3000_RANKS_PER_CHANNEL; i++)
	305	if (c0drb[i] != c1drb[i])
	306	return 0;
	307
	308	return 1;
	309	}
	310
	311	static int i3000_probe1(struct pci_dev *pdev, int dev_idx)
	312	{
	313	int rc;
084a4fcc	314	int i, j;
535c6a53	315	struct mem_ctl_info *mci = NULL;
884906f1	316	struct edac_mc_layer layers[2];
a895bf8b	317	unsigned long last_cumul_size, nr_pages;
535c6a53 JU	318	int interleaved, nr_channels;
	319	unsigned char dra[I3000_RANKS / 2], drb[I3000_RANKS];
	320	unsigned char c0dra = dra, c1dra = &dra[I3000_RANKS_PER_CHANNEL / 2];
	321	unsigned char c0drb = drb, c1drb = &drb[I3000_RANKS_PER_CHANNEL];
	322	unsigned long mchbar;
0bd8496b	323	void __iomem *window;
535c6a53	324
956b9ba1	325	edac_dbg(0, "MC:\n");
535c6a53	326
36b8289e	327	pci_read_config_dword(pdev, I3000_MCHBAR, (u32 *) & mchbar);
535c6a53 JU	328	mchbar &= I3000_MCHBAR_MASK;
	329	window = ioremap_nocache(mchbar, I3000_MMR_WINDOW_SIZE);
	330	if (!window) {
36b8289e	331	printk(KERN_ERR "i3000: cannot map mmio space at 0x%lx\n",
052dfb45	332	mchbar);
535c6a53 JU	333	return -ENODEV;
	334	}
	335
36b8289e DJ	336	c0dra[0] = readb(window + I3000_C0DRA + 0); /* ranks 0,1 */
	337	c0dra[1] = readb(window + I3000_C0DRA + 1); /* ranks 2,3 */
	338	c1dra[0] = readb(window + I3000_C1DRA + 0); /* ranks 0,1 */
	339	c1dra[1] = readb(window + I3000_C1DRA + 1); /* ranks 2,3 */
535c6a53 JU	340
	341	for (i = 0; i < I3000_RANKS_PER_CHANNEL; i++) {
	342	c0drb[i] = readb(window + I3000_C0DRB + i);
	343	c1drb[i] = readb(window + I3000_C1DRB + i);
	344	}
	345
	346	iounmap(window);
	347
ce783d70 JU	348	/*
ce783d70 JU	349	* Figure out how many channels we have.
535c6a53 JU	350	*
	351	* If we have what the datasheet calls "asymmetric channels"
	352	* (essentially the same as what was called "virtual single
	353	* channel mode" in the i82875) then it's a single channel as
	354	* far as EDAC is concerned.
	355	*/
	356	interleaved = i3000_is_interleaved(c0dra, c1dra, c0drb, c1drb);
	357	nr_channels = interleaved ? 2 : 1;
884906f1 MCC	358
	359	layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
	360	layers[0].size = I3000_RANKS / nr_channels;
	361	layers[0].is_virt_csrow = true;
	362	layers[1].type = EDAC_MC_LAYER_CHANNEL;
	363	layers[1].size = nr_channels;
	364	layers[1].is_virt_csrow = false;
ca0907b9	365	mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0);
535c6a53 JU	366	if (!mci)
	367	return -ENOMEM;
	368
956b9ba1	369	edac_dbg(3, "MC: init mci\n");
535c6a53	370
fd687502	371	mci->pdev = &pdev->dev;
535c6a53 JU	372	mci->mtype_cap = MEM_FLAG_DDR2;
	373
	374	mci->edac_ctl_cap = EDAC_FLAG_SECDED;
	375	mci->edac_cap = EDAC_FLAG_SECDED;
	376
	377	mci->mod_name = EDAC_MOD_STR;
	378	mci->mod_ver = I3000_REVISION;
	379	mci->ctl_name = i3000_devs[dev_idx].ctl_name;
	380	mci->dev_name = pci_name(pdev);
	381	mci->edac_check = i3000_check;
	382	mci->ctl_page_to_phys = NULL;
	383
	384	/*
	385	* The dram rank boundary (DRB) reg values are boundary addresses
	386	* for each DRAM rank with a granularity of 32MB. DRB regs are
	387	* cumulative; the last one will contain the total memory
	388	* contained in all ranks.
	389	*
	390	* If we're in interleaved mode then we're only walking through
	391	* the ranks of controller 0, so we double all the values we see.
	392	*/
	393	for (last_cumul_size = i = 0; i < mci->nr_csrows; i++) {
	394	u8 value;
	395	u32 cumul_size;
de3910eb	396	struct csrow_info *csrow = mci->csrows[i];
535c6a53 JU	397
	398	value = drb[i];
	399	cumul_size = value << (I3000_DRB_SHIFT - PAGE_SHIFT);
	400	if (interleaved)
	401	cumul_size <<= 1;
956b9ba1	402	edac_dbg(3, "MC: (%d) cumul_size 0x%x\n", i, cumul_size);
084a4fcc	403	if (cumul_size == last_cumul_size)
535c6a53	404	continue;
535c6a53 JU	405
	406	csrow->first_page = last_cumul_size;
	407	csrow->last_page = cumul_size - 1;
a895bf8b	408	nr_pages = cumul_size - last_cumul_size;
535c6a53	409	last_cumul_size = cumul_size;
084a4fcc MCC	410
084a4fcc MCC	411	for (j = 0; j < nr_channels; j++) {
de3910eb	412	struct dimm_info *dimm = csrow->channels[j]->dimm;
a895bf8b MCC	413
a895bf8b MCC	414	dimm->nr_pages = nr_pages / nr_channels;
084a4fcc MCC	415	dimm->grain = I3000_DEAP_GRAIN;
	416	dimm->mtype = MEM_DDR2;
	417	dimm->dtype = DEV_UNKNOWN;
	418	dimm->edac_mode = EDAC_UNKNOWN;
	419	}
535c6a53 JU	420	}
535c6a53 JU	421
ce783d70 JU	422	/*
ce783d70 JU	423	* Clear any error bits.
535c6a53 JU	424	* (Yes, we really clear bits by writing 1 to them.)
535c6a53 JU	425	*/
36b8289e DJ	426	pci_write_bits16(pdev, I3000_ERRSTS, I3000_ERRSTS_BITS,
36b8289e DJ	427	I3000_ERRSTS_BITS);
535c6a53 JU	428
535c6a53 JU	429	rc = -ENODEV;
b8f6f975	430	if (edac_mc_add_mc(mci)) {
956b9ba1	431	edac_dbg(3, "MC: failed edac_mc_add_mc()\n");
535c6a53 JU	432	goto fail;
	433	}
	434
456a2f95 DJ	435	/* allocating generic PCI control info */
	436	i3000_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
	437	if (!i3000_pci) {
	438	printk(KERN_WARNING
	439	"%s(): Unable to create PCI control\n",
	440	__func__);
	441	printk(KERN_WARNING
	442	"%s(): PCI error report via EDAC not setup\n",
	443	__func__);
	444	}
	445
535c6a53	446	/* get this far and it's successful */
956b9ba1	447	edac_dbg(3, "MC: success\n");
535c6a53 JU	448	return 0;
535c6a53 JU	449
ce783d70	450	fail:
535c6a53 JU	451	if (mci)
	452	edac_mc_free(mci);
	453
	454	return rc;
	455	}
	456
	457	/* returns count (>= 0), or negative on error */
9b3c6e85	458	static int i3000_init_one(struct pci_dev pdev, const struct pci_device_id ent)
535c6a53 JU	459	{
	460	int rc;
	461
956b9ba1	462	edac_dbg(0, "MC:\n");
535c6a53 JU	463
	464	if (pci_enable_device(pdev) < 0)
	465	return -EIO;
	466
	467	rc = i3000_probe1(pdev, ent->driver_data);
ce783d70	468	if (!mci_pdev)
535c6a53 JU	469	mci_pdev = pci_dev_get(pdev);
	470
	471	return rc;
	472	}
	473
9b3c6e85	474	static void i3000_remove_one(struct pci_dev *pdev)
535c6a53 JU	475	{
	476	struct mem_ctl_info *mci;
	477
956b9ba1	478	edac_dbg(0, "\n");
535c6a53	479
456a2f95 DJ	480	if (i3000_pci)
	481	edac_pci_release_generic_ctl(i3000_pci);
	482
ce783d70 JU	483	mci = edac_mc_del_mc(&pdev->dev);
ce783d70 JU	484	if (!mci)
535c6a53 JU	485	return;
	486
	487	edac_mc_free(mci);
	488	}
	489
ba935f40	490	static const struct pci_device_id i3000_pci_tbl[] = {
535c6a53	491	{
36b8289e DJ	492	PCI_VEND_DEV(INTEL, 3000_HB), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
36b8289e DJ	493	I3000},
535c6a53	494	{
36b8289e DJ	495	0,
36b8289e DJ	496	} /* 0 terminated list. */
535c6a53 JU	497	};
	498
	499	MODULE_DEVICE_TABLE(pci, i3000_pci_tbl);
	500
	501	static struct pci_driver i3000_driver = {
	502	.name = EDAC_MOD_STR,
	503	.probe = i3000_init_one,
9b3c6e85	504	.remove = i3000_remove_one,
535c6a53 JU	505	.id_table = i3000_pci_tbl,
	506	};
	507
	508	static int __init i3000_init(void)
	509	{
	510	int pci_rc;
	511
956b9ba1	512	edac_dbg(3, "MC:\n");
c3c52bce HM	513
	514	/* Ensure that the OPSTATE is set correctly for POLL or NMI */
	515	opstate_init();
	516
535c6a53 JU	517	pci_rc = pci_register_driver(&i3000_driver);
	518	if (pci_rc < 0)
	519	goto fail0;
	520
ce783d70	521	if (!mci_pdev) {
535c6a53 JU	522	i3000_registered = 0;
535c6a53 JU	523	mci_pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
052dfb45	524	PCI_DEVICE_ID_INTEL_3000_HB, NULL);
535c6a53	525	if (!mci_pdev) {
956b9ba1	526	edac_dbg(0, "i3000 pci_get_device fail\n");
535c6a53 JU	527	pci_rc = -ENODEV;
	528	goto fail1;
	529	}
	530
	531	pci_rc = i3000_init_one(mci_pdev, i3000_pci_tbl);
	532	if (pci_rc < 0) {
956b9ba1	533	edac_dbg(0, "i3000 init fail\n");
535c6a53 JU	534	pci_rc = -ENODEV;
	535	goto fail1;
	536	}
	537	}
	538
	539	return 0;
	540
052dfb45	541	fail1:
535c6a53 JU	542	pci_unregister_driver(&i3000_driver);
535c6a53 JU	543
052dfb45	544	fail0:
0a98babd	545	pci_dev_put(mci_pdev);
535c6a53 JU	546
	547	return pci_rc;
	548	}
	549
	550	static void __exit i3000_exit(void)
	551	{
956b9ba1	552	edac_dbg(3, "MC:\n");
535c6a53 JU	553
	554	pci_unregister_driver(&i3000_driver);
	555	if (!i3000_registered) {
	556	i3000_remove_one(mci_pdev);
	557	pci_dev_put(mci_pdev);
	558	}
	559	}
	560
	561	module_init(i3000_init);
	562	module_exit(i3000_exit);
	563
	564	MODULE_LICENSE("GPL");
	565	MODULE_AUTHOR("Akamai Technologies Arthur Ulfeldt/Jason Uhlenkott");
	566	MODULE_DESCRIPTION("MC support for Intel 3000 memory hub controllers");
7ed31e0f HM	567
	568	module_param(edac_op_state, int, 0444);
	569	MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");