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12237550 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
52707f91 MCC |
2 | /* Intel i7 core/Nehalem Memory Controller kernel module |
3 | * | |
e7bf068a | 4 | * This driver supports the memory controllers found on the Intel |
52707f91 MCC |
5 | * processor families i7core, i7core 7xx/8xx, i5core, Xeon 35xx, |
6 | * Xeon 55xx and Xeon 56xx also known as Nehalem, Nehalem-EP, Lynnfield | |
7 | * and Westmere-EP. | |
a0c36a1f | 8 | * |
52707f91 | 9 | * Copyright (c) 2009-2010 by: |
37e59f87 | 10 | * Mauro Carvalho Chehab |
a0c36a1f MCC |
11 | * |
12 | * Red Hat Inc. http://www.redhat.com | |
13 | * | |
14 | * Forked and adapted from the i5400_edac driver | |
15 | * | |
16 | * Based on the following public Intel datasheets: | |
17 | * Intel Core i7 Processor Extreme Edition and Intel Core i7 Processor | |
18 | * Datasheet, Volume 2: | |
19 | * http://download.intel.com/design/processor/datashts/320835.pdf | |
20 | * Intel Xeon Processor 5500 Series Datasheet Volume 2 | |
21 | * http://www.intel.com/Assets/PDF/datasheet/321322.pdf | |
22 | * also available at: | |
23 | * http://www.arrownac.com/manufacturers/intel/s/nehalem/5500-datasheet-v2.pdf | |
24 | */ | |
25 | ||
a0c36a1f MCC |
26 | #include <linux/module.h> |
27 | #include <linux/init.h> | |
28 | #include <linux/pci.h> | |
29 | #include <linux/pci_ids.h> | |
30 | #include <linux/slab.h> | |
3b918c12 | 31 | #include <linux/delay.h> |
535e9c78 | 32 | #include <linux/dmi.h> |
a0c36a1f MCC |
33 | #include <linux/edac.h> |
34 | #include <linux/mmzone.h> | |
f4742949 | 35 | #include <linux/smp.h> |
4140c542 | 36 | #include <asm/mce.h> |
14d2c083 | 37 | #include <asm/processor.h> |
4fad8098 | 38 | #include <asm/div64.h> |
a0c36a1f | 39 | |
78d88e8a | 40 | #include "edac_module.h" |
a0c36a1f | 41 | |
18c29002 MCC |
42 | /* Static vars */ |
43 | static LIST_HEAD(i7core_edac_list); | |
44 | static DEFINE_MUTEX(i7core_edac_lock); | |
45 | static int probed; | |
46 | ||
54a08ab1 MCC |
47 | static int use_pci_fixup; |
48 | module_param(use_pci_fixup, int, 0444); | |
49 | MODULE_PARM_DESC(use_pci_fixup, "Enable PCI fixup to seek for hidden devices"); | |
f4742949 MCC |
50 | /* |
51 | * This is used for Nehalem-EP and Nehalem-EX devices, where the non-core | |
52 | * registers start at bus 255, and are not reported by BIOS. | |
53 | * We currently find devices with only 2 sockets. In order to support more QPI | |
54 | * Quick Path Interconnect, just increment this number. | |
55 | */ | |
56 | #define MAX_SOCKET_BUSES 2 | |
57 | ||
58 | ||
a0c36a1f MCC |
59 | /* |
60 | * Alter this version for the module when modifications are made | |
61 | */ | |
152ba394 | 62 | #define I7CORE_REVISION " Ver: 1.0.0" |
a0c36a1f MCC |
63 | #define EDAC_MOD_STR "i7core_edac" |
64 | ||
a0c36a1f MCC |
65 | /* |
66 | * Debug macros | |
67 | */ | |
68 | #define i7core_printk(level, fmt, arg...) \ | |
69 | edac_printk(level, "i7core", fmt, ##arg) | |
70 | ||
71 | #define i7core_mc_printk(mci, level, fmt, arg...) \ | |
72 | edac_mc_chipset_printk(mci, level, "i7core", fmt, ##arg) | |
73 | ||
74 | /* | |
75 | * i7core Memory Controller Registers | |
76 | */ | |
77 | ||
e9bd2e73 MCC |
78 | /* OFFSETS for Device 0 Function 0 */ |
79 | ||
80 | #define MC_CFG_CONTROL 0x90 | |
e8b6a127 SG |
81 | #define MC_CFG_UNLOCK 0x02 |
82 | #define MC_CFG_LOCK 0x00 | |
e9bd2e73 | 83 | |
a0c36a1f MCC |
84 | /* OFFSETS for Device 3 Function 0 */ |
85 | ||
86 | #define MC_CONTROL 0x48 | |
87 | #define MC_STATUS 0x4c | |
88 | #define MC_MAX_DOD 0x64 | |
89 | ||
442305b1 | 90 | /* |
15ed103a | 91 | * OFFSETS for Device 3 Function 4, as indicated on Xeon 5500 datasheet: |
442305b1 MCC |
92 | * http://www.arrownac.com/manufacturers/intel/s/nehalem/5500-datasheet-v2.pdf |
93 | */ | |
94 | ||
95 | #define MC_TEST_ERR_RCV1 0x60 | |
96 | #define DIMM2_COR_ERR(r) ((r) & 0x7fff) | |
97 | ||
98 | #define MC_TEST_ERR_RCV0 0x64 | |
99 | #define DIMM1_COR_ERR(r) (((r) >> 16) & 0x7fff) | |
100 | #define DIMM0_COR_ERR(r) ((r) & 0x7fff) | |
101 | ||
15ed103a | 102 | /* OFFSETS for Device 3 Function 2, as indicated on Xeon 5500 datasheet */ |
e8b6a127 SG |
103 | #define MC_SSRCONTROL 0x48 |
104 | #define SSR_MODE_DISABLE 0x00 | |
105 | #define SSR_MODE_ENABLE 0x01 | |
106 | #define SSR_MODE_MASK 0x03 | |
107 | ||
108 | #define MC_SCRUB_CONTROL 0x4c | |
109 | #define STARTSCRUB (1 << 24) | |
535e9c78 | 110 | #define SCRUBINTERVAL_MASK 0xffffff |
e8b6a127 | 111 | |
b4e8f0b6 MCC |
112 | #define MC_COR_ECC_CNT_0 0x80 |
113 | #define MC_COR_ECC_CNT_1 0x84 | |
114 | #define MC_COR_ECC_CNT_2 0x88 | |
115 | #define MC_COR_ECC_CNT_3 0x8c | |
116 | #define MC_COR_ECC_CNT_4 0x90 | |
117 | #define MC_COR_ECC_CNT_5 0x94 | |
118 | ||
119 | #define DIMM_TOP_COR_ERR(r) (((r) >> 16) & 0x7fff) | |
120 | #define DIMM_BOT_COR_ERR(r) ((r) & 0x7fff) | |
121 | ||
122 | ||
a0c36a1f MCC |
123 | /* OFFSETS for Devices 4,5 and 6 Function 0 */ |
124 | ||
0b2b7b7e MCC |
125 | #define MC_CHANNEL_DIMM_INIT_PARAMS 0x58 |
126 | #define THREE_DIMMS_PRESENT (1 << 24) | |
127 | #define SINGLE_QUAD_RANK_PRESENT (1 << 23) | |
128 | #define QUAD_RANK_PRESENT (1 << 22) | |
129 | #define REGISTERED_DIMM (1 << 15) | |
130 | ||
f122a892 MCC |
131 | #define MC_CHANNEL_MAPPER 0x60 |
132 | #define RDLCH(r, ch) ((((r) >> (3 + (ch * 6))) & 0x07) - 1) | |
133 | #define WRLCH(r, ch) ((((r) >> (ch * 6)) & 0x07) - 1) | |
134 | ||
0b2b7b7e MCC |
135 | #define MC_CHANNEL_RANK_PRESENT 0x7c |
136 | #define RANK_PRESENT_MASK 0xffff | |
137 | ||
a0c36a1f | 138 | #define MC_CHANNEL_ADDR_MATCH 0xf0 |
194a40fe MCC |
139 | #define MC_CHANNEL_ERROR_MASK 0xf8 |
140 | #define MC_CHANNEL_ERROR_INJECT 0xfc | |
141 | #define INJECT_ADDR_PARITY 0x10 | |
142 | #define INJECT_ECC 0x08 | |
143 | #define MASK_CACHELINE 0x06 | |
144 | #define MASK_FULL_CACHELINE 0x06 | |
145 | #define MASK_MSB32_CACHELINE 0x04 | |
146 | #define MASK_LSB32_CACHELINE 0x02 | |
147 | #define NO_MASK_CACHELINE 0x00 | |
148 | #define REPEAT_EN 0x01 | |
a0c36a1f | 149 | |
0b2b7b7e | 150 | /* OFFSETS for Devices 4,5 and 6 Function 1 */ |
b990538a | 151 | |
0b2b7b7e MCC |
152 | #define MC_DOD_CH_DIMM0 0x48 |
153 | #define MC_DOD_CH_DIMM1 0x4c | |
154 | #define MC_DOD_CH_DIMM2 0x50 | |
155 | #define RANKOFFSET_MASK ((1 << 12) | (1 << 11) | (1 << 10)) | |
156 | #define RANKOFFSET(x) ((x & RANKOFFSET_MASK) >> 10) | |
157 | #define DIMM_PRESENT_MASK (1 << 9) | |
158 | #define DIMM_PRESENT(x) (((x) & DIMM_PRESENT_MASK) >> 9) | |
854d3349 MCC |
159 | #define MC_DOD_NUMBANK_MASK ((1 << 8) | (1 << 7)) |
160 | #define MC_DOD_NUMBANK(x) (((x) & MC_DOD_NUMBANK_MASK) >> 7) | |
161 | #define MC_DOD_NUMRANK_MASK ((1 << 6) | (1 << 5)) | |
162 | #define MC_DOD_NUMRANK(x) (((x) & MC_DOD_NUMRANK_MASK) >> 5) | |
41fcb7fe | 163 | #define MC_DOD_NUMROW_MASK ((1 << 4) | (1 << 3) | (1 << 2)) |
5566cb7c | 164 | #define MC_DOD_NUMROW(x) (((x) & MC_DOD_NUMROW_MASK) >> 2) |
854d3349 MCC |
165 | #define MC_DOD_NUMCOL_MASK 3 |
166 | #define MC_DOD_NUMCOL(x) ((x) & MC_DOD_NUMCOL_MASK) | |
0b2b7b7e | 167 | |
f122a892 MCC |
168 | #define MC_RANK_PRESENT 0x7c |
169 | ||
0b2b7b7e MCC |
170 | #define MC_SAG_CH_0 0x80 |
171 | #define MC_SAG_CH_1 0x84 | |
172 | #define MC_SAG_CH_2 0x88 | |
173 | #define MC_SAG_CH_3 0x8c | |
174 | #define MC_SAG_CH_4 0x90 | |
175 | #define MC_SAG_CH_5 0x94 | |
176 | #define MC_SAG_CH_6 0x98 | |
177 | #define MC_SAG_CH_7 0x9c | |
178 | ||
179 | #define MC_RIR_LIMIT_CH_0 0x40 | |
180 | #define MC_RIR_LIMIT_CH_1 0x44 | |
181 | #define MC_RIR_LIMIT_CH_2 0x48 | |
182 | #define MC_RIR_LIMIT_CH_3 0x4C | |
183 | #define MC_RIR_LIMIT_CH_4 0x50 | |
184 | #define MC_RIR_LIMIT_CH_5 0x54 | |
185 | #define MC_RIR_LIMIT_CH_6 0x58 | |
186 | #define MC_RIR_LIMIT_CH_7 0x5C | |
187 | #define MC_RIR_LIMIT_MASK ((1 << 10) - 1) | |
188 | ||
189 | #define MC_RIR_WAY_CH 0x80 | |
190 | #define MC_RIR_WAY_OFFSET_MASK (((1 << 14) - 1) & ~0x7) | |
191 | #define MC_RIR_WAY_RANK_MASK 0x7 | |
192 | ||
a0c36a1f MCC |
193 | /* |
194 | * i7core structs | |
195 | */ | |
196 | ||
197 | #define NUM_CHANS 3 | |
442305b1 MCC |
198 | #define MAX_DIMMS 3 /* Max DIMMS per channel */ |
199 | #define MAX_MCR_FUNC 4 | |
200 | #define MAX_CHAN_FUNC 3 | |
a0c36a1f MCC |
201 | |
202 | struct i7core_info { | |
203 | u32 mc_control; | |
204 | u32 mc_status; | |
205 | u32 max_dod; | |
f122a892 | 206 | u32 ch_map; |
a0c36a1f MCC |
207 | }; |
208 | ||
194a40fe MCC |
209 | |
210 | struct i7core_inject { | |
211 | int enable; | |
212 | ||
213 | u32 section; | |
214 | u32 type; | |
215 | u32 eccmask; | |
216 | ||
217 | /* Error address mask */ | |
218 | int channel, dimm, rank, bank, page, col; | |
219 | }; | |
220 | ||
0b2b7b7e | 221 | struct i7core_channel { |
0bf09e82 MCC |
222 | bool is_3dimms_present; |
223 | bool is_single_4rank; | |
224 | bool has_4rank; | |
442305b1 | 225 | u32 dimms; |
0b2b7b7e MCC |
226 | }; |
227 | ||
8f331907 | 228 | struct pci_id_descr { |
66607706 MCC |
229 | int dev; |
230 | int func; | |
231 | int dev_id; | |
de06eeef | 232 | int optional; |
8f331907 MCC |
233 | }; |
234 | ||
bd9e19ca | 235 | struct pci_id_table { |
1288c18f MCC |
236 | const struct pci_id_descr *descr; |
237 | int n_devs; | |
bd9e19ca VM |
238 | }; |
239 | ||
f4742949 MCC |
240 | struct i7core_dev { |
241 | struct list_head list; | |
242 | u8 socket; | |
243 | struct pci_dev **pdev; | |
de06eeef | 244 | int n_devs; |
f4742949 MCC |
245 | struct mem_ctl_info *mci; |
246 | }; | |
247 | ||
a0c36a1f | 248 | struct i7core_pvt { |
356f0a30 | 249 | struct device *addrmatch_dev, *chancounts_dev; |
5c4cdb5a | 250 | |
f4742949 MCC |
251 | struct pci_dev *pci_noncore; |
252 | struct pci_dev *pci_mcr[MAX_MCR_FUNC + 1]; | |
253 | struct pci_dev *pci_ch[NUM_CHANS][MAX_CHAN_FUNC + 1]; | |
254 | ||
255 | struct i7core_dev *i7core_dev; | |
67166af4 | 256 | |
a0c36a1f | 257 | struct i7core_info info; |
194a40fe | 258 | struct i7core_inject inject; |
f4742949 | 259 | struct i7core_channel channel[NUM_CHANS]; |
67166af4 | 260 | |
f4742949 | 261 | int ce_count_available; |
b4e8f0b6 MCC |
262 | |
263 | /* ECC corrected errors counts per udimm */ | |
f4742949 MCC |
264 | unsigned long udimm_ce_count[MAX_DIMMS]; |
265 | int udimm_last_ce_count[MAX_DIMMS]; | |
b4e8f0b6 | 266 | /* ECC corrected errors counts per rdimm */ |
f4742949 MCC |
267 | unsigned long rdimm_ce_count[NUM_CHANS][MAX_DIMMS]; |
268 | int rdimm_last_ce_count[NUM_CHANS][MAX_DIMMS]; | |
442305b1 | 269 | |
27100db0 | 270 | bool is_registered, enable_scrub; |
14d2c083 | 271 | |
535e9c78 NC |
272 | /* DCLK Frequency used for computing scrub rate */ |
273 | int dclk_freq; | |
274 | ||
939747bd MCC |
275 | /* Struct to control EDAC polling */ |
276 | struct edac_pci_ctl_info *i7core_pci; | |
a0c36a1f MCC |
277 | }; |
278 | ||
8f331907 MCC |
279 | #define PCI_DESCR(device, function, device_id) \ |
280 | .dev = (device), \ | |
281 | .func = (function), \ | |
282 | .dev_id = (device_id) | |
283 | ||
1288c18f | 284 | static const struct pci_id_descr pci_dev_descr_i7core_nehalem[] = { |
8f331907 MCC |
285 | /* Memory controller */ |
286 | { PCI_DESCR(3, 0, PCI_DEVICE_ID_INTEL_I7_MCR) }, | |
287 | { PCI_DESCR(3, 1, PCI_DEVICE_ID_INTEL_I7_MC_TAD) }, | |
224e871f | 288 | /* Exists only for RDIMM */ |
de06eeef | 289 | { PCI_DESCR(3, 2, PCI_DEVICE_ID_INTEL_I7_MC_RAS), .optional = 1 }, |
8f331907 MCC |
290 | { PCI_DESCR(3, 4, PCI_DEVICE_ID_INTEL_I7_MC_TEST) }, |
291 | ||
292 | /* Channel 0 */ | |
293 | { PCI_DESCR(4, 0, PCI_DEVICE_ID_INTEL_I7_MC_CH0_CTRL) }, | |
294 | { PCI_DESCR(4, 1, PCI_DEVICE_ID_INTEL_I7_MC_CH0_ADDR) }, | |
295 | { PCI_DESCR(4, 2, PCI_DEVICE_ID_INTEL_I7_MC_CH0_RANK) }, | |
296 | { PCI_DESCR(4, 3, PCI_DEVICE_ID_INTEL_I7_MC_CH0_TC) }, | |
297 | ||
298 | /* Channel 1 */ | |
299 | { PCI_DESCR(5, 0, PCI_DEVICE_ID_INTEL_I7_MC_CH1_CTRL) }, | |
300 | { PCI_DESCR(5, 1, PCI_DEVICE_ID_INTEL_I7_MC_CH1_ADDR) }, | |
301 | { PCI_DESCR(5, 2, PCI_DEVICE_ID_INTEL_I7_MC_CH1_RANK) }, | |
302 | { PCI_DESCR(5, 3, PCI_DEVICE_ID_INTEL_I7_MC_CH1_TC) }, | |
303 | ||
304 | /* Channel 2 */ | |
305 | { PCI_DESCR(6, 0, PCI_DEVICE_ID_INTEL_I7_MC_CH2_CTRL) }, | |
306 | { PCI_DESCR(6, 1, PCI_DEVICE_ID_INTEL_I7_MC_CH2_ADDR) }, | |
307 | { PCI_DESCR(6, 2, PCI_DEVICE_ID_INTEL_I7_MC_CH2_RANK) }, | |
308 | { PCI_DESCR(6, 3, PCI_DEVICE_ID_INTEL_I7_MC_CH2_TC) }, | |
224e871f MCC |
309 | |
310 | /* Generic Non-core registers */ | |
311 | /* | |
312 | * This is the PCI device on i7core and on Xeon 35xx (8086:2c41) | |
313 | * On Xeon 55xx, however, it has a different id (8086:2c40). So, | |
314 | * the probing code needs to test for the other address in case of | |
315 | * failure of this one | |
316 | */ | |
317 | { PCI_DESCR(0, 0, PCI_DEVICE_ID_INTEL_I7_NONCORE) }, | |
318 | ||
a0c36a1f | 319 | }; |
8f331907 | 320 | |
1288c18f | 321 | static const struct pci_id_descr pci_dev_descr_lynnfield[] = { |
52a2e4fc MCC |
322 | { PCI_DESCR( 3, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MCR) }, |
323 | { PCI_DESCR( 3, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TAD) }, | |
324 | { PCI_DESCR( 3, 4, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TEST) }, | |
325 | ||
326 | { PCI_DESCR( 4, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_CTRL) }, | |
327 | { PCI_DESCR( 4, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_ADDR) }, | |
328 | { PCI_DESCR( 4, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_RANK) }, | |
329 | { PCI_DESCR( 4, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_TC) }, | |
330 | ||
508fa179 MCC |
331 | { PCI_DESCR( 5, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_CTRL) }, |
332 | { PCI_DESCR( 5, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_ADDR) }, | |
333 | { PCI_DESCR( 5, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_RANK) }, | |
334 | { PCI_DESCR( 5, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_TC) }, | |
224e871f MCC |
335 | |
336 | /* | |
337 | * This is the PCI device has an alternate address on some | |
338 | * processors like Core i7 860 | |
339 | */ | |
340 | { PCI_DESCR( 0, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE) }, | |
52a2e4fc MCC |
341 | }; |
342 | ||
1288c18f | 343 | static const struct pci_id_descr pci_dev_descr_i7core_westmere[] = { |
bd9e19ca VM |
344 | /* Memory controller */ |
345 | { PCI_DESCR(3, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MCR_REV2) }, | |
346 | { PCI_DESCR(3, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TAD_REV2) }, | |
347 | /* Exists only for RDIMM */ | |
348 | { PCI_DESCR(3, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_RAS_REV2), .optional = 1 }, | |
349 | { PCI_DESCR(3, 4, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TEST_REV2) }, | |
350 | ||
351 | /* Channel 0 */ | |
352 | { PCI_DESCR(4, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_CTRL_REV2) }, | |
353 | { PCI_DESCR(4, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_ADDR_REV2) }, | |
354 | { PCI_DESCR(4, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_RANK_REV2) }, | |
355 | { PCI_DESCR(4, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_TC_REV2) }, | |
356 | ||
357 | /* Channel 1 */ | |
358 | { PCI_DESCR(5, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_CTRL_REV2) }, | |
359 | { PCI_DESCR(5, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_ADDR_REV2) }, | |
360 | { PCI_DESCR(5, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_RANK_REV2) }, | |
361 | { PCI_DESCR(5, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_TC_REV2) }, | |
362 | ||
363 | /* Channel 2 */ | |
364 | { PCI_DESCR(6, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_CTRL_REV2) }, | |
365 | { PCI_DESCR(6, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_ADDR_REV2) }, | |
366 | { PCI_DESCR(6, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_RANK_REV2) }, | |
367 | { PCI_DESCR(6, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_TC_REV2) }, | |
224e871f MCC |
368 | |
369 | /* Generic Non-core registers */ | |
370 | { PCI_DESCR(0, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE_REV2) }, | |
371 | ||
bd9e19ca VM |
372 | }; |
373 | ||
1288c18f MCC |
374 | #define PCI_ID_TABLE_ENTRY(A) { .descr=A, .n_devs = ARRAY_SIZE(A) } |
375 | static const struct pci_id_table pci_dev_table[] = { | |
bd9e19ca VM |
376 | PCI_ID_TABLE_ENTRY(pci_dev_descr_i7core_nehalem), |
377 | PCI_ID_TABLE_ENTRY(pci_dev_descr_lynnfield), | |
378 | PCI_ID_TABLE_ENTRY(pci_dev_descr_i7core_westmere), | |
3c52cc57 | 379 | {0,} /* 0 terminated list. */ |
bd9e19ca VM |
380 | }; |
381 | ||
8f331907 MCC |
382 | /* |
383 | * pci_device_id table for which devices we are looking for | |
8f331907 | 384 | */ |
ba935f40 | 385 | static const struct pci_device_id i7core_pci_tbl[] = { |
d1fd4fb6 | 386 | {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_X58_HUB_MGMT)}, |
f05da2f7 | 387 | {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNNFIELD_QPI_LINK0)}, |
8f331907 MCC |
388 | {0,} /* 0 terminated list. */ |
389 | }; | |
390 | ||
a0c36a1f | 391 | /**************************************************************************** |
15ed103a | 392 | Ancillary status routines |
a0c36a1f MCC |
393 | ****************************************************************************/ |
394 | ||
395 | /* MC_CONTROL bits */ | |
ef708b53 MCC |
396 | #define CH_ACTIVE(pvt, ch) ((pvt)->info.mc_control & (1 << (8 + ch))) |
397 | #define ECCx8(pvt) ((pvt)->info.mc_control & (1 << 1)) | |
a0c36a1f MCC |
398 | |
399 | /* MC_STATUS bits */ | |
61053fde | 400 | #define ECC_ENABLED(pvt) ((pvt)->info.mc_status & (1 << 4)) |
ef708b53 | 401 | #define CH_DISABLED(pvt, ch) ((pvt)->info.mc_status & (1 << ch)) |
a0c36a1f MCC |
402 | |
403 | /* MC_MAX_DOD read functions */ | |
854d3349 | 404 | static inline int numdimms(u32 dimms) |
a0c36a1f | 405 | { |
854d3349 | 406 | return (dimms & 0x3) + 1; |
a0c36a1f MCC |
407 | } |
408 | ||
854d3349 | 409 | static inline int numrank(u32 rank) |
a0c36a1f | 410 | { |
c31d34fe | 411 | static const int ranks[] = { 1, 2, 4, -EINVAL }; |
a0c36a1f | 412 | |
854d3349 | 413 | return ranks[rank & 0x3]; |
a0c36a1f MCC |
414 | } |
415 | ||
854d3349 | 416 | static inline int numbank(u32 bank) |
a0c36a1f | 417 | { |
c31d34fe | 418 | static const int banks[] = { 4, 8, 16, -EINVAL }; |
a0c36a1f | 419 | |
854d3349 | 420 | return banks[bank & 0x3]; |
a0c36a1f MCC |
421 | } |
422 | ||
854d3349 | 423 | static inline int numrow(u32 row) |
a0c36a1f | 424 | { |
c31d34fe | 425 | static const int rows[] = { |
a0c36a1f MCC |
426 | 1 << 12, 1 << 13, 1 << 14, 1 << 15, |
427 | 1 << 16, -EINVAL, -EINVAL, -EINVAL, | |
428 | }; | |
429 | ||
854d3349 | 430 | return rows[row & 0x7]; |
a0c36a1f MCC |
431 | } |
432 | ||
854d3349 | 433 | static inline int numcol(u32 col) |
a0c36a1f | 434 | { |
c31d34fe | 435 | static const int cols[] = { |
a0c36a1f MCC |
436 | 1 << 10, 1 << 11, 1 << 12, -EINVAL, |
437 | }; | |
854d3349 | 438 | return cols[col & 0x3]; |
a0c36a1f MCC |
439 | } |
440 | ||
f4742949 | 441 | static struct i7core_dev *get_i7core_dev(u8 socket) |
66607706 MCC |
442 | { |
443 | struct i7core_dev *i7core_dev; | |
444 | ||
445 | list_for_each_entry(i7core_dev, &i7core_edac_list, list) { | |
446 | if (i7core_dev->socket == socket) | |
447 | return i7core_dev; | |
448 | } | |
449 | ||
450 | return NULL; | |
451 | } | |
452 | ||
848b2f7e HS |
453 | static struct i7core_dev *alloc_i7core_dev(u8 socket, |
454 | const struct pci_id_table *table) | |
455 | { | |
456 | struct i7core_dev *i7core_dev; | |
457 | ||
458 | i7core_dev = kzalloc(sizeof(*i7core_dev), GFP_KERNEL); | |
459 | if (!i7core_dev) | |
460 | return NULL; | |
461 | ||
6396bb22 | 462 | i7core_dev->pdev = kcalloc(table->n_devs, sizeof(*i7core_dev->pdev), |
848b2f7e HS |
463 | GFP_KERNEL); |
464 | if (!i7core_dev->pdev) { | |
465 | kfree(i7core_dev); | |
466 | return NULL; | |
467 | } | |
468 | ||
469 | i7core_dev->socket = socket; | |
470 | i7core_dev->n_devs = table->n_devs; | |
471 | list_add_tail(&i7core_dev->list, &i7core_edac_list); | |
472 | ||
473 | return i7core_dev; | |
474 | } | |
475 | ||
2aa9be44 HS |
476 | static void free_i7core_dev(struct i7core_dev *i7core_dev) |
477 | { | |
478 | list_del(&i7core_dev->list); | |
479 | kfree(i7core_dev->pdev); | |
480 | kfree(i7core_dev); | |
481 | } | |
482 | ||
a0c36a1f MCC |
483 | /**************************************************************************** |
484 | Memory check routines | |
485 | ****************************************************************************/ | |
eb94fc40 | 486 | |
084a4fcc | 487 | static int get_dimm_config(struct mem_ctl_info *mci) |
a0c36a1f MCC |
488 | { |
489 | struct i7core_pvt *pvt = mci->pvt_info; | |
854d3349 | 490 | struct pci_dev *pdev; |
ba6c5c62 | 491 | int i, j; |
1c6fed80 | 492 | enum edac_type mode; |
854d3349 | 493 | enum mem_type mtype; |
084a4fcc | 494 | struct dimm_info *dimm; |
a0c36a1f | 495 | |
854d3349 | 496 | /* Get data from the MC register, function 0 */ |
f4742949 | 497 | pdev = pvt->pci_mcr[0]; |
7dd6953c | 498 | if (!pdev) |
8f331907 MCC |
499 | return -ENODEV; |
500 | ||
f122a892 | 501 | /* Device 3 function 0 reads */ |
7dd6953c MCC |
502 | pci_read_config_dword(pdev, MC_CONTROL, &pvt->info.mc_control); |
503 | pci_read_config_dword(pdev, MC_STATUS, &pvt->info.mc_status); | |
504 | pci_read_config_dword(pdev, MC_MAX_DOD, &pvt->info.max_dod); | |
505 | pci_read_config_dword(pdev, MC_CHANNEL_MAPPER, &pvt->info.ch_map); | |
f122a892 | 506 | |
956b9ba1 JP |
507 | edac_dbg(0, "QPI %d control=0x%08x status=0x%08x dod=0x%08x map=0x%08x\n", |
508 | pvt->i7core_dev->socket, pvt->info.mc_control, | |
509 | pvt->info.mc_status, pvt->info.max_dod, pvt->info.ch_map); | |
a0c36a1f | 510 | |
1c6fed80 | 511 | if (ECC_ENABLED(pvt)) { |
956b9ba1 | 512 | edac_dbg(0, "ECC enabled with x%d SDCC\n", ECCx8(pvt) ? 8 : 4); |
1c6fed80 MCC |
513 | if (ECCx8(pvt)) |
514 | mode = EDAC_S8ECD8ED; | |
515 | else | |
516 | mode = EDAC_S4ECD4ED; | |
517 | } else { | |
956b9ba1 | 518 | edac_dbg(0, "ECC disabled\n"); |
1c6fed80 MCC |
519 | mode = EDAC_NONE; |
520 | } | |
a0c36a1f MCC |
521 | |
522 | /* FIXME: need to handle the error codes */ | |
956b9ba1 JP |
523 | edac_dbg(0, "DOD Max limits: DIMMS: %d, %d-ranked, %d-banked x%x x 0x%x\n", |
524 | numdimms(pvt->info.max_dod), | |
525 | numrank(pvt->info.max_dod >> 2), | |
526 | numbank(pvt->info.max_dod >> 4), | |
527 | numrow(pvt->info.max_dod >> 6), | |
528 | numcol(pvt->info.max_dod >> 9)); | |
a0c36a1f | 529 | |
0b2b7b7e | 530 | for (i = 0; i < NUM_CHANS; i++) { |
854d3349 | 531 | u32 data, dimm_dod[3], value[8]; |
0b2b7b7e | 532 | |
52a2e4fc MCC |
533 | if (!pvt->pci_ch[i][0]) |
534 | continue; | |
535 | ||
0b2b7b7e | 536 | if (!CH_ACTIVE(pvt, i)) { |
956b9ba1 | 537 | edac_dbg(0, "Channel %i is not active\n", i); |
0b2b7b7e MCC |
538 | continue; |
539 | } | |
540 | if (CH_DISABLED(pvt, i)) { | |
956b9ba1 | 541 | edac_dbg(0, "Channel %i is disabled\n", i); |
0b2b7b7e MCC |
542 | continue; |
543 | } | |
544 | ||
f122a892 | 545 | /* Devices 4-6 function 0 */ |
f4742949 | 546 | pci_read_config_dword(pvt->pci_ch[i][0], |
0b2b7b7e MCC |
547 | MC_CHANNEL_DIMM_INIT_PARAMS, &data); |
548 | ||
0bf09e82 MCC |
549 | |
550 | if (data & THREE_DIMMS_PRESENT) | |
551 | pvt->channel[i].is_3dimms_present = true; | |
552 | ||
553 | if (data & SINGLE_QUAD_RANK_PRESENT) | |
554 | pvt->channel[i].is_single_4rank = true; | |
555 | ||
556 | if (data & QUAD_RANK_PRESENT) | |
557 | pvt->channel[i].has_4rank = true; | |
0b2b7b7e | 558 | |
854d3349 MCC |
559 | if (data & REGISTERED_DIMM) |
560 | mtype = MEM_RDDR3; | |
14d2c083 | 561 | else |
854d3349 | 562 | mtype = MEM_DDR3; |
854d3349 MCC |
563 | |
564 | /* Devices 4-6 function 1 */ | |
f4742949 | 565 | pci_read_config_dword(pvt->pci_ch[i][1], |
854d3349 | 566 | MC_DOD_CH_DIMM0, &dimm_dod[0]); |
f4742949 | 567 | pci_read_config_dword(pvt->pci_ch[i][1], |
854d3349 | 568 | MC_DOD_CH_DIMM1, &dimm_dod[1]); |
f4742949 | 569 | pci_read_config_dword(pvt->pci_ch[i][1], |
854d3349 | 570 | MC_DOD_CH_DIMM2, &dimm_dod[2]); |
0b2b7b7e | 571 | |
956b9ba1 JP |
572 | edac_dbg(0, "Ch%d phy rd%d, wr%d (0x%08x): %s%s%s%cDIMMs\n", |
573 | i, | |
574 | RDLCH(pvt->info.ch_map, i), WRLCH(pvt->info.ch_map, i), | |
575 | data, | |
576 | pvt->channel[i].is_3dimms_present ? "3DIMMS " : "", | |
577 | pvt->channel[i].is_3dimms_present ? "SINGLE_4R " : "", | |
578 | pvt->channel[i].has_4rank ? "HAS_4R " : "", | |
579 | (data & REGISTERED_DIMM) ? 'R' : 'U'); | |
854d3349 MCC |
580 | |
581 | for (j = 0; j < 3; j++) { | |
582 | u32 banks, ranks, rows, cols; | |
5566cb7c | 583 | u32 size, npages; |
854d3349 MCC |
584 | |
585 | if (!DIMM_PRESENT(dimm_dod[j])) | |
586 | continue; | |
587 | ||
0975c16f MCC |
588 | dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers, |
589 | i, j, 0); | |
854d3349 MCC |
590 | banks = numbank(MC_DOD_NUMBANK(dimm_dod[j])); |
591 | ranks = numrank(MC_DOD_NUMRANK(dimm_dod[j])); | |
592 | rows = numrow(MC_DOD_NUMROW(dimm_dod[j])); | |
593 | cols = numcol(MC_DOD_NUMCOL(dimm_dod[j])); | |
594 | ||
5566cb7c MCC |
595 | /* DDR3 has 8 I/O banks */ |
596 | size = (rows * cols * banks * ranks) >> (20 - 3); | |
597 | ||
6f6da136 | 598 | edac_dbg(0, "\tdimm %d %d MiB offset: %x, bank: %d, rank: %d, row: %#x, col: %#x\n", |
956b9ba1 JP |
599 | j, size, |
600 | RANKOFFSET(dimm_dod[j]), | |
601 | banks, ranks, rows, cols); | |
854d3349 | 602 | |
e9144601 | 603 | npages = MiB_TO_PAGES(size); |
5566cb7c | 604 | |
a895bf8b | 605 | dimm->nr_pages = npages; |
b4e8f0b6 | 606 | |
854d3349 MCC |
607 | switch (banks) { |
608 | case 4: | |
084a4fcc | 609 | dimm->dtype = DEV_X4; |
854d3349 MCC |
610 | break; |
611 | case 8: | |
084a4fcc | 612 | dimm->dtype = DEV_X8; |
854d3349 MCC |
613 | break; |
614 | case 16: | |
084a4fcc | 615 | dimm->dtype = DEV_X16; |
854d3349 MCC |
616 | break; |
617 | default: | |
084a4fcc | 618 | dimm->dtype = DEV_UNKNOWN; |
854d3349 MCC |
619 | } |
620 | ||
084a4fcc MCC |
621 | snprintf(dimm->label, sizeof(dimm->label), |
622 | "CPU#%uChannel#%u_DIMM#%u", | |
623 | pvt->i7core_dev->socket, i, j); | |
624 | dimm->grain = 8; | |
625 | dimm->edac_mode = mode; | |
626 | dimm->mtype = mtype; | |
854d3349 | 627 | } |
1c6fed80 | 628 | |
854d3349 MCC |
629 | pci_read_config_dword(pdev, MC_SAG_CH_0, &value[0]); |
630 | pci_read_config_dword(pdev, MC_SAG_CH_1, &value[1]); | |
631 | pci_read_config_dword(pdev, MC_SAG_CH_2, &value[2]); | |
632 | pci_read_config_dword(pdev, MC_SAG_CH_3, &value[3]); | |
633 | pci_read_config_dword(pdev, MC_SAG_CH_4, &value[4]); | |
634 | pci_read_config_dword(pdev, MC_SAG_CH_5, &value[5]); | |
635 | pci_read_config_dword(pdev, MC_SAG_CH_6, &value[6]); | |
636 | pci_read_config_dword(pdev, MC_SAG_CH_7, &value[7]); | |
956b9ba1 | 637 | edac_dbg(1, "\t[%i] DIVBY3\tREMOVED\tOFFSET\n", i); |
854d3349 | 638 | for (j = 0; j < 8; j++) |
956b9ba1 JP |
639 | edac_dbg(1, "\t\t%#x\t%#x\t%#x\n", |
640 | (value[j] >> 27) & 0x1, | |
641 | (value[j] >> 24) & 0x7, | |
642 | (value[j] & ((1 << 24) - 1))); | |
0b2b7b7e MCC |
643 | } |
644 | ||
a0c36a1f MCC |
645 | return 0; |
646 | } | |
647 | ||
194a40fe MCC |
648 | /**************************************************************************** |
649 | Error insertion routines | |
650 | ****************************************************************************/ | |
651 | ||
5c4cdb5a MCC |
652 | #define to_mci(k) container_of(k, struct mem_ctl_info, dev) |
653 | ||
194a40fe MCC |
654 | /* The i7core has independent error injection features per channel. |
655 | However, to have a simpler code, we don't allow enabling error injection | |
656 | on more than one channel. | |
657 | Also, since a change at an inject parameter will be applied only at enable, | |
658 | we're disabling error injection on all write calls to the sysfs nodes that | |
659 | controls the error code injection. | |
660 | */ | |
1288c18f | 661 | static int disable_inject(const struct mem_ctl_info *mci) |
194a40fe MCC |
662 | { |
663 | struct i7core_pvt *pvt = mci->pvt_info; | |
664 | ||
665 | pvt->inject.enable = 0; | |
666 | ||
f4742949 | 667 | if (!pvt->pci_ch[pvt->inject.channel][0]) |
8f331907 MCC |
668 | return -ENODEV; |
669 | ||
f4742949 | 670 | pci_write_config_dword(pvt->pci_ch[pvt->inject.channel][0], |
4157d9f5 | 671 | MC_CHANNEL_ERROR_INJECT, 0); |
8f331907 MCC |
672 | |
673 | return 0; | |
194a40fe MCC |
674 | } |
675 | ||
676 | /* | |
677 | * i7core inject inject.section | |
678 | * | |
679 | * accept and store error injection inject.section value | |
680 | * bit 0 - refers to the lower 32-byte half cacheline | |
681 | * bit 1 - refers to the upper 32-byte half cacheline | |
682 | */ | |
5c4cdb5a MCC |
683 | static ssize_t i7core_inject_section_store(struct device *dev, |
684 | struct device_attribute *mattr, | |
194a40fe MCC |
685 | const char *data, size_t count) |
686 | { | |
5c4cdb5a | 687 | struct mem_ctl_info *mci = to_mci(dev); |
194a40fe MCC |
688 | struct i7core_pvt *pvt = mci->pvt_info; |
689 | unsigned long value; | |
690 | int rc; | |
691 | ||
692 | if (pvt->inject.enable) | |
41fcb7fe | 693 | disable_inject(mci); |
194a40fe | 694 | |
c7f62fc8 | 695 | rc = kstrtoul(data, 10, &value); |
194a40fe | 696 | if ((rc < 0) || (value > 3)) |
2068def5 | 697 | return -EIO; |
194a40fe MCC |
698 | |
699 | pvt->inject.section = (u32) value; | |
700 | return count; | |
701 | } | |
702 | ||
5c4cdb5a MCC |
703 | static ssize_t i7core_inject_section_show(struct device *dev, |
704 | struct device_attribute *mattr, | |
705 | char *data) | |
194a40fe | 706 | { |
5c4cdb5a | 707 | struct mem_ctl_info *mci = to_mci(dev); |
194a40fe MCC |
708 | struct i7core_pvt *pvt = mci->pvt_info; |
709 | return sprintf(data, "0x%08x\n", pvt->inject.section); | |
710 | } | |
711 | ||
712 | /* | |
713 | * i7core inject.type | |
714 | * | |
715 | * accept and store error injection inject.section value | |
716 | * bit 0 - repeat enable - Enable error repetition | |
717 | * bit 1 - inject ECC error | |
718 | * bit 2 - inject parity error | |
719 | */ | |
5c4cdb5a MCC |
720 | static ssize_t i7core_inject_type_store(struct device *dev, |
721 | struct device_attribute *mattr, | |
194a40fe MCC |
722 | const char *data, size_t count) |
723 | { | |
5c4cdb5a | 724 | struct mem_ctl_info *mci = to_mci(dev); |
1722bc0e | 725 | struct i7core_pvt *pvt = mci->pvt_info; |
194a40fe MCC |
726 | unsigned long value; |
727 | int rc; | |
728 | ||
729 | if (pvt->inject.enable) | |
41fcb7fe | 730 | disable_inject(mci); |
194a40fe | 731 | |
c7f62fc8 | 732 | rc = kstrtoul(data, 10, &value); |
194a40fe | 733 | if ((rc < 0) || (value > 7)) |
2068def5 | 734 | return -EIO; |
194a40fe MCC |
735 | |
736 | pvt->inject.type = (u32) value; | |
737 | return count; | |
738 | } | |
739 | ||
5c4cdb5a MCC |
740 | static ssize_t i7core_inject_type_show(struct device *dev, |
741 | struct device_attribute *mattr, | |
742 | char *data) | |
194a40fe | 743 | { |
5c4cdb5a | 744 | struct mem_ctl_info *mci = to_mci(dev); |
194a40fe | 745 | struct i7core_pvt *pvt = mci->pvt_info; |
5c4cdb5a | 746 | |
194a40fe MCC |
747 | return sprintf(data, "0x%08x\n", pvt->inject.type); |
748 | } | |
749 | ||
750 | /* | |
751 | * i7core_inject_inject.eccmask_store | |
752 | * | |
753 | * The type of error (UE/CE) will depend on the inject.eccmask value: | |
754 | * Any bits set to a 1 will flip the corresponding ECC bit | |
755 | * Correctable errors can be injected by flipping 1 bit or the bits within | |
756 | * a symbol pair (2 consecutive aligned 8-bit pairs - i.e. 7:0 and 15:8 or | |
757 | * 23:16 and 31:24). Flipping bits in two symbol pairs will cause an | |
758 | * uncorrectable error to be injected. | |
759 | */ | |
5c4cdb5a MCC |
760 | static ssize_t i7core_inject_eccmask_store(struct device *dev, |
761 | struct device_attribute *mattr, | |
762 | const char *data, size_t count) | |
194a40fe | 763 | { |
5c4cdb5a | 764 | struct mem_ctl_info *mci = to_mci(dev); |
194a40fe MCC |
765 | struct i7core_pvt *pvt = mci->pvt_info; |
766 | unsigned long value; | |
767 | int rc; | |
768 | ||
769 | if (pvt->inject.enable) | |
41fcb7fe | 770 | disable_inject(mci); |
194a40fe | 771 | |
c7f62fc8 | 772 | rc = kstrtoul(data, 10, &value); |
194a40fe | 773 | if (rc < 0) |
2068def5 | 774 | return -EIO; |
194a40fe MCC |
775 | |
776 | pvt->inject.eccmask = (u32) value; | |
777 | return count; | |
778 | } | |
779 | ||
5c4cdb5a MCC |
780 | static ssize_t i7core_inject_eccmask_show(struct device *dev, |
781 | struct device_attribute *mattr, | |
782 | char *data) | |
194a40fe | 783 | { |
5c4cdb5a | 784 | struct mem_ctl_info *mci = to_mci(dev); |
194a40fe | 785 | struct i7core_pvt *pvt = mci->pvt_info; |
5c4cdb5a | 786 | |
194a40fe MCC |
787 | return sprintf(data, "0x%08x\n", pvt->inject.eccmask); |
788 | } | |
789 | ||
790 | /* | |
791 | * i7core_addrmatch | |
792 | * | |
793 | * The type of error (UE/CE) will depend on the inject.eccmask value: | |
794 | * Any bits set to a 1 will flip the corresponding ECC bit | |
795 | * Correctable errors can be injected by flipping 1 bit or the bits within | |
796 | * a symbol pair (2 consecutive aligned 8-bit pairs - i.e. 7:0 and 15:8 or | |
797 | * 23:16 and 31:24). Flipping bits in two symbol pairs will cause an | |
798 | * uncorrectable error to be injected. | |
799 | */ | |
194a40fe | 800 | |
a5538e53 MCC |
801 | #define DECLARE_ADDR_MATCH(param, limit) \ |
802 | static ssize_t i7core_inject_store_##param( \ | |
5c4cdb5a MCC |
803 | struct device *dev, \ |
804 | struct device_attribute *mattr, \ | |
805 | const char *data, size_t count) \ | |
a5538e53 | 806 | { \ |
42709efb | 807 | struct mem_ctl_info *mci = dev_get_drvdata(dev); \ |
cc301b3a | 808 | struct i7core_pvt *pvt; \ |
a5538e53 MCC |
809 | long value; \ |
810 | int rc; \ | |
811 | \ | |
956b9ba1 | 812 | edac_dbg(1, "\n"); \ |
cc301b3a MCC |
813 | pvt = mci->pvt_info; \ |
814 | \ | |
a5538e53 MCC |
815 | if (pvt->inject.enable) \ |
816 | disable_inject(mci); \ | |
817 | \ | |
4f87fad1 | 818 | if (!strcasecmp(data, "any") || !strcasecmp(data, "any\n"))\ |
a5538e53 MCC |
819 | value = -1; \ |
820 | else { \ | |
c7f62fc8 | 821 | rc = kstrtoul(data, 10, &value); \ |
a5538e53 MCC |
822 | if ((rc < 0) || (value >= limit)) \ |
823 | return -EIO; \ | |
824 | } \ | |
825 | \ | |
826 | pvt->inject.param = value; \ | |
827 | \ | |
828 | return count; \ | |
829 | } \ | |
830 | \ | |
831 | static ssize_t i7core_inject_show_##param( \ | |
5c4cdb5a MCC |
832 | struct device *dev, \ |
833 | struct device_attribute *mattr, \ | |
834 | char *data) \ | |
a5538e53 | 835 | { \ |
42709efb | 836 | struct mem_ctl_info *mci = dev_get_drvdata(dev); \ |
cc301b3a MCC |
837 | struct i7core_pvt *pvt; \ |
838 | \ | |
839 | pvt = mci->pvt_info; \ | |
956b9ba1 | 840 | edac_dbg(1, "pvt=%p\n", pvt); \ |
a5538e53 MCC |
841 | if (pvt->inject.param < 0) \ |
842 | return sprintf(data, "any\n"); \ | |
843 | else \ | |
844 | return sprintf(data, "%d\n", pvt->inject.param);\ | |
194a40fe MCC |
845 | } |
846 | ||
a5538e53 | 847 | #define ATTR_ADDR_MATCH(param) \ |
5c4cdb5a MCC |
848 | static DEVICE_ATTR(param, S_IRUGO | S_IWUSR, \ |
849 | i7core_inject_show_##param, \ | |
850 | i7core_inject_store_##param) | |
194a40fe | 851 | |
a5538e53 MCC |
852 | DECLARE_ADDR_MATCH(channel, 3); |
853 | DECLARE_ADDR_MATCH(dimm, 3); | |
854 | DECLARE_ADDR_MATCH(rank, 4); | |
855 | DECLARE_ADDR_MATCH(bank, 32); | |
856 | DECLARE_ADDR_MATCH(page, 0x10000); | |
857 | DECLARE_ADDR_MATCH(col, 0x4000); | |
194a40fe | 858 | |
5c4cdb5a MCC |
859 | ATTR_ADDR_MATCH(channel); |
860 | ATTR_ADDR_MATCH(dimm); | |
861 | ATTR_ADDR_MATCH(rank); | |
862 | ATTR_ADDR_MATCH(bank); | |
863 | ATTR_ADDR_MATCH(page); | |
864 | ATTR_ADDR_MATCH(col); | |
865 | ||
1288c18f | 866 | static int write_and_test(struct pci_dev *dev, const int where, const u32 val) |
276b824c MCC |
867 | { |
868 | u32 read; | |
869 | int count; | |
870 | ||
956b9ba1 JP |
871 | edac_dbg(0, "setting pci %02x:%02x.%x reg=%02x value=%08x\n", |
872 | dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn), | |
873 | where, val); | |
4157d9f5 | 874 | |
276b824c MCC |
875 | for (count = 0; count < 10; count++) { |
876 | if (count) | |
b990538a | 877 | msleep(100); |
276b824c MCC |
878 | pci_write_config_dword(dev, where, val); |
879 | pci_read_config_dword(dev, where, &read); | |
880 | ||
881 | if (read == val) | |
882 | return 0; | |
883 | } | |
884 | ||
4157d9f5 MCC |
885 | i7core_printk(KERN_ERR, "Error during set pci %02x:%02x.%x reg=%02x " |
886 | "write=%08x. Read=%08x\n", | |
887 | dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn), | |
888 | where, val, read); | |
276b824c MCC |
889 | |
890 | return -EINVAL; | |
891 | } | |
892 | ||
194a40fe MCC |
893 | /* |
894 | * This routine prepares the Memory Controller for error injection. | |
895 | * The error will be injected when some process tries to write to the | |
896 | * memory that matches the given criteria. | |
897 | * The criteria can be set in terms of a mask where dimm, rank, bank, page | |
898 | * and col can be specified. | |
899 | * A -1 value for any of the mask items will make the MCU to ignore | |
900 | * that matching criteria for error injection. | |
901 | * | |
902 | * It should be noticed that the error will only happen after a write operation | |
903 | * on a memory that matches the condition. if REPEAT_EN is not enabled at | |
904 | * inject mask, then it will produce just one error. Otherwise, it will repeat | |
905 | * until the injectmask would be cleaned. | |
906 | * | |
907 | * FIXME: This routine assumes that MAXNUMDIMMS value of MC_MAX_DOD | |
908 | * is reliable enough to check if the MC is using the | |
909 | * three channels. However, this is not clear at the datasheet. | |
910 | */ | |
5c4cdb5a MCC |
911 | static ssize_t i7core_inject_enable_store(struct device *dev, |
912 | struct device_attribute *mattr, | |
913 | const char *data, size_t count) | |
194a40fe | 914 | { |
5c4cdb5a | 915 | struct mem_ctl_info *mci = to_mci(dev); |
194a40fe MCC |
916 | struct i7core_pvt *pvt = mci->pvt_info; |
917 | u32 injectmask; | |
918 | u64 mask = 0; | |
919 | int rc; | |
920 | long enable; | |
921 | ||
f4742949 | 922 | if (!pvt->pci_ch[pvt->inject.channel][0]) |
8f331907 MCC |
923 | return 0; |
924 | ||
c7f62fc8 | 925 | rc = kstrtoul(data, 10, &enable); |
194a40fe MCC |
926 | if ((rc < 0)) |
927 | return 0; | |
928 | ||
929 | if (enable) { | |
930 | pvt->inject.enable = 1; | |
931 | } else { | |
932 | disable_inject(mci); | |
933 | return count; | |
934 | } | |
935 | ||
936 | /* Sets pvt->inject.dimm mask */ | |
937 | if (pvt->inject.dimm < 0) | |
486dd09f | 938 | mask |= 1LL << 41; |
194a40fe | 939 | else { |
f4742949 | 940 | if (pvt->channel[pvt->inject.channel].dimms > 2) |
486dd09f | 941 | mask |= (pvt->inject.dimm & 0x3LL) << 35; |
194a40fe | 942 | else |
486dd09f | 943 | mask |= (pvt->inject.dimm & 0x1LL) << 36; |
194a40fe MCC |
944 | } |
945 | ||
946 | /* Sets pvt->inject.rank mask */ | |
947 | if (pvt->inject.rank < 0) | |
486dd09f | 948 | mask |= 1LL << 40; |
194a40fe | 949 | else { |
f4742949 | 950 | if (pvt->channel[pvt->inject.channel].dimms > 2) |
486dd09f | 951 | mask |= (pvt->inject.rank & 0x1LL) << 34; |
194a40fe | 952 | else |
486dd09f | 953 | mask |= (pvt->inject.rank & 0x3LL) << 34; |
194a40fe MCC |
954 | } |
955 | ||
956 | /* Sets pvt->inject.bank mask */ | |
957 | if (pvt->inject.bank < 0) | |
486dd09f | 958 | mask |= 1LL << 39; |
194a40fe | 959 | else |
486dd09f | 960 | mask |= (pvt->inject.bank & 0x15LL) << 30; |
194a40fe MCC |
961 | |
962 | /* Sets pvt->inject.page mask */ | |
963 | if (pvt->inject.page < 0) | |
486dd09f | 964 | mask |= 1LL << 38; |
194a40fe | 965 | else |
486dd09f | 966 | mask |= (pvt->inject.page & 0xffff) << 14; |
194a40fe MCC |
967 | |
968 | /* Sets pvt->inject.column mask */ | |
969 | if (pvt->inject.col < 0) | |
486dd09f | 970 | mask |= 1LL << 37; |
194a40fe | 971 | else |
486dd09f | 972 | mask |= (pvt->inject.col & 0x3fff); |
194a40fe | 973 | |
276b824c MCC |
974 | /* |
975 | * bit 0: REPEAT_EN | |
976 | * bits 1-2: MASK_HALF_CACHELINE | |
977 | * bit 3: INJECT_ECC | |
978 | * bit 4: INJECT_ADDR_PARITY | |
979 | */ | |
980 | ||
981 | injectmask = (pvt->inject.type & 1) | | |
982 | (pvt->inject.section & 0x3) << 1 | | |
983 | (pvt->inject.type & 0x6) << (3 - 1); | |
984 | ||
985 | /* Unlock writes to registers - this register is write only */ | |
f4742949 | 986 | pci_write_config_dword(pvt->pci_noncore, |
67166af4 | 987 | MC_CFG_CONTROL, 0x2); |
e9bd2e73 | 988 | |
f4742949 | 989 | write_and_test(pvt->pci_ch[pvt->inject.channel][0], |
194a40fe | 990 | MC_CHANNEL_ADDR_MATCH, mask); |
f4742949 | 991 | write_and_test(pvt->pci_ch[pvt->inject.channel][0], |
7b029d03 | 992 | MC_CHANNEL_ADDR_MATCH + 4, mask >> 32L); |
7b029d03 | 993 | |
f4742949 | 994 | write_and_test(pvt->pci_ch[pvt->inject.channel][0], |
194a40fe MCC |
995 | MC_CHANNEL_ERROR_MASK, pvt->inject.eccmask); |
996 | ||
f4742949 | 997 | write_and_test(pvt->pci_ch[pvt->inject.channel][0], |
4157d9f5 | 998 | MC_CHANNEL_ERROR_INJECT, injectmask); |
276b824c | 999 | |
194a40fe | 1000 | /* |
276b824c MCC |
1001 | * This is something undocumented, based on my tests |
1002 | * Without writing 8 to this register, errors aren't injected. Not sure | |
1003 | * why. | |
194a40fe | 1004 | */ |
f4742949 | 1005 | pci_write_config_dword(pvt->pci_noncore, |
276b824c | 1006 | MC_CFG_CONTROL, 8); |
194a40fe | 1007 | |
956b9ba1 JP |
1008 | edac_dbg(0, "Error inject addr match 0x%016llx, ecc 0x%08x, inject 0x%08x\n", |
1009 | mask, pvt->inject.eccmask, injectmask); | |
194a40fe | 1010 | |
7b029d03 | 1011 | |
194a40fe MCC |
1012 | return count; |
1013 | } | |
1014 | ||
5c4cdb5a MCC |
1015 | static ssize_t i7core_inject_enable_show(struct device *dev, |
1016 | struct device_attribute *mattr, | |
1017 | char *data) | |
194a40fe | 1018 | { |
5c4cdb5a | 1019 | struct mem_ctl_info *mci = to_mci(dev); |
194a40fe | 1020 | struct i7core_pvt *pvt = mci->pvt_info; |
7b029d03 MCC |
1021 | u32 injectmask; |
1022 | ||
52a2e4fc MCC |
1023 | if (!pvt->pci_ch[pvt->inject.channel][0]) |
1024 | return 0; | |
1025 | ||
f4742949 | 1026 | pci_read_config_dword(pvt->pci_ch[pvt->inject.channel][0], |
4157d9f5 | 1027 | MC_CHANNEL_ERROR_INJECT, &injectmask); |
7b029d03 | 1028 | |
956b9ba1 | 1029 | edac_dbg(0, "Inject error read: 0x%018x\n", injectmask); |
7b029d03 MCC |
1030 | |
1031 | if (injectmask & 0x0c) | |
1032 | pvt->inject.enable = 1; | |
1033 | ||
194a40fe MCC |
1034 | return sprintf(data, "%d\n", pvt->inject.enable); |
1035 | } | |
1036 | ||
f338d736 MCC |
1037 | #define DECLARE_COUNTER(param) \ |
1038 | static ssize_t i7core_show_counter_##param( \ | |
5c4cdb5a MCC |
1039 | struct device *dev, \ |
1040 | struct device_attribute *mattr, \ | |
1041 | char *data) \ | |
f338d736 | 1042 | { \ |
42709efb | 1043 | struct mem_ctl_info *mci = dev_get_drvdata(dev); \ |
f338d736 MCC |
1044 | struct i7core_pvt *pvt = mci->pvt_info; \ |
1045 | \ | |
956b9ba1 | 1046 | edac_dbg(1, "\n"); \ |
f338d736 MCC |
1047 | if (!pvt->ce_count_available || (pvt->is_registered)) \ |
1048 | return sprintf(data, "data unavailable\n"); \ | |
1049 | return sprintf(data, "%lu\n", \ | |
1050 | pvt->udimm_ce_count[param]); \ | |
1051 | } | |
442305b1 | 1052 | |
f338d736 | 1053 | #define ATTR_COUNTER(param) \ |
5c4cdb5a MCC |
1054 | static DEVICE_ATTR(udimm##param, S_IRUGO | S_IWUSR, \ |
1055 | i7core_show_counter_##param, \ | |
1056 | NULL) | |
442305b1 | 1057 | |
f338d736 MCC |
1058 | DECLARE_COUNTER(0); |
1059 | DECLARE_COUNTER(1); | |
1060 | DECLARE_COUNTER(2); | |
442305b1 | 1061 | |
5c4cdb5a MCC |
1062 | ATTR_COUNTER(0); |
1063 | ATTR_COUNTER(1); | |
1064 | ATTR_COUNTER(2); | |
1065 | ||
194a40fe | 1066 | /* |
5c4cdb5a | 1067 | * inject_addrmatch device sysfs struct |
194a40fe | 1068 | */ |
a5538e53 | 1069 | |
5c4cdb5a MCC |
1070 | static struct attribute *i7core_addrmatch_attrs[] = { |
1071 | &dev_attr_channel.attr, | |
1072 | &dev_attr_dimm.attr, | |
1073 | &dev_attr_rank.attr, | |
1074 | &dev_attr_bank.attr, | |
1075 | &dev_attr_page.attr, | |
1076 | &dev_attr_col.attr, | |
1077 | NULL | |
a5538e53 MCC |
1078 | }; |
1079 | ||
1c18be5a | 1080 | static const struct attribute_group addrmatch_grp = { |
5c4cdb5a | 1081 | .attrs = i7core_addrmatch_attrs, |
a5538e53 MCC |
1082 | }; |
1083 | ||
5c4cdb5a MCC |
1084 | static const struct attribute_group *addrmatch_groups[] = { |
1085 | &addrmatch_grp, | |
1086 | NULL | |
f338d736 MCC |
1087 | }; |
1088 | ||
5c4cdb5a MCC |
1089 | static void addrmatch_release(struct device *device) |
1090 | { | |
956b9ba1 | 1091 | edac_dbg(1, "Releasing device %s\n", dev_name(device)); |
356f0a30 | 1092 | kfree(device); |
5c4cdb5a MCC |
1093 | } |
1094 | ||
b2b3e736 | 1095 | static const struct device_type addrmatch_type = { |
5c4cdb5a MCC |
1096 | .groups = addrmatch_groups, |
1097 | .release = addrmatch_release, | |
f338d736 MCC |
1098 | }; |
1099 | ||
5c4cdb5a MCC |
1100 | /* |
1101 | * all_channel_counts sysfs struct | |
1102 | */ | |
1103 | ||
1104 | static struct attribute *i7core_udimm_counters_attrs[] = { | |
1105 | &dev_attr_udimm0.attr, | |
1106 | &dev_attr_udimm1.attr, | |
1107 | &dev_attr_udimm2.attr, | |
1108 | NULL | |
1288c18f MCC |
1109 | }; |
1110 | ||
1c18be5a | 1111 | static const struct attribute_group all_channel_counts_grp = { |
5c4cdb5a | 1112 | .attrs = i7core_udimm_counters_attrs, |
194a40fe MCC |
1113 | }; |
1114 | ||
5c4cdb5a MCC |
1115 | static const struct attribute_group *all_channel_counts_groups[] = { |
1116 | &all_channel_counts_grp, | |
1117 | NULL | |
194a40fe MCC |
1118 | }; |
1119 | ||
5c4cdb5a MCC |
1120 | static void all_channel_counts_release(struct device *device) |
1121 | { | |
956b9ba1 | 1122 | edac_dbg(1, "Releasing device %s\n", dev_name(device)); |
356f0a30 | 1123 | kfree(device); |
5c4cdb5a MCC |
1124 | } |
1125 | ||
b2b3e736 | 1126 | static const struct device_type all_channel_counts_type = { |
5c4cdb5a MCC |
1127 | .groups = all_channel_counts_groups, |
1128 | .release = all_channel_counts_release, | |
1129 | }; | |
1130 | ||
1131 | /* | |
1132 | * inject sysfs attributes | |
1133 | */ | |
1134 | ||
1135 | static DEVICE_ATTR(inject_section, S_IRUGO | S_IWUSR, | |
1136 | i7core_inject_section_show, i7core_inject_section_store); | |
1137 | ||
1138 | static DEVICE_ATTR(inject_type, S_IRUGO | S_IWUSR, | |
1139 | i7core_inject_type_show, i7core_inject_type_store); | |
1140 | ||
1141 | ||
1142 | static DEVICE_ATTR(inject_eccmask, S_IRUGO | S_IWUSR, | |
1143 | i7core_inject_eccmask_show, i7core_inject_eccmask_store); | |
1144 | ||
1145 | static DEVICE_ATTR(inject_enable, S_IRUGO | S_IWUSR, | |
1146 | i7core_inject_enable_show, i7core_inject_enable_store); | |
1147 | ||
2eace188 TI |
1148 | static struct attribute *i7core_dev_attrs[] = { |
1149 | &dev_attr_inject_section.attr, | |
1150 | &dev_attr_inject_type.attr, | |
1151 | &dev_attr_inject_eccmask.attr, | |
1152 | &dev_attr_inject_enable.attr, | |
1153 | NULL | |
1154 | }; | |
1155 | ||
1156 | ATTRIBUTE_GROUPS(i7core_dev); | |
1157 | ||
5c4cdb5a MCC |
1158 | static int i7core_create_sysfs_devices(struct mem_ctl_info *mci) |
1159 | { | |
1160 | struct i7core_pvt *pvt = mci->pvt_info; | |
1161 | int rc; | |
1162 | ||
356f0a30 MCC |
1163 | pvt->addrmatch_dev = kzalloc(sizeof(*pvt->addrmatch_dev), GFP_KERNEL); |
1164 | if (!pvt->addrmatch_dev) | |
e97d7e38 | 1165 | return -ENOMEM; |
356f0a30 MCC |
1166 | |
1167 | pvt->addrmatch_dev->type = &addrmatch_type; | |
1168 | pvt->addrmatch_dev->bus = mci->dev.bus; | |
1169 | device_initialize(pvt->addrmatch_dev); | |
1170 | pvt->addrmatch_dev->parent = &mci->dev; | |
1171 | dev_set_name(pvt->addrmatch_dev, "inject_addrmatch"); | |
1172 | dev_set_drvdata(pvt->addrmatch_dev, mci); | |
5c4cdb5a | 1173 | |
956b9ba1 | 1174 | edac_dbg(1, "creating %s\n", dev_name(pvt->addrmatch_dev)); |
5c4cdb5a | 1175 | |
356f0a30 | 1176 | rc = device_add(pvt->addrmatch_dev); |
5c4cdb5a | 1177 | if (rc < 0) |
6c974d4d | 1178 | goto err_put_addrmatch; |
5c4cdb5a MCC |
1179 | |
1180 | if (!pvt->is_registered) { | |
356f0a30 MCC |
1181 | pvt->chancounts_dev = kzalloc(sizeof(*pvt->chancounts_dev), |
1182 | GFP_KERNEL); | |
1183 | if (!pvt->chancounts_dev) { | |
6c974d4d JH |
1184 | rc = -ENOMEM; |
1185 | goto err_del_addrmatch; | |
356f0a30 MCC |
1186 | } |
1187 | ||
1188 | pvt->chancounts_dev->type = &all_channel_counts_type; | |
1189 | pvt->chancounts_dev->bus = mci->dev.bus; | |
1190 | device_initialize(pvt->chancounts_dev); | |
1191 | pvt->chancounts_dev->parent = &mci->dev; | |
1192 | dev_set_name(pvt->chancounts_dev, "all_channel_counts"); | |
1193 | dev_set_drvdata(pvt->chancounts_dev, mci); | |
5c4cdb5a | 1194 | |
956b9ba1 | 1195 | edac_dbg(1, "creating %s\n", dev_name(pvt->chancounts_dev)); |
5c4cdb5a | 1196 | |
356f0a30 | 1197 | rc = device_add(pvt->chancounts_dev); |
5c4cdb5a | 1198 | if (rc < 0) |
6c974d4d | 1199 | goto err_put_chancounts; |
5c4cdb5a MCC |
1200 | } |
1201 | return 0; | |
6c974d4d JH |
1202 | |
1203 | err_put_chancounts: | |
1204 | put_device(pvt->chancounts_dev); | |
1205 | err_del_addrmatch: | |
1206 | device_del(pvt->addrmatch_dev); | |
1207 | err_put_addrmatch: | |
1208 | put_device(pvt->addrmatch_dev); | |
1209 | ||
1210 | return rc; | |
5c4cdb5a MCC |
1211 | } |
1212 | ||
1213 | static void i7core_delete_sysfs_devices(struct mem_ctl_info *mci) | |
1214 | { | |
1215 | struct i7core_pvt *pvt = mci->pvt_info; | |
1216 | ||
956b9ba1 | 1217 | edac_dbg(1, "\n"); |
5c4cdb5a | 1218 | |
5c4cdb5a | 1219 | if (!pvt->is_registered) { |
356f0a30 | 1220 | device_del(pvt->chancounts_dev); |
6c974d4d | 1221 | put_device(pvt->chancounts_dev); |
5c4cdb5a | 1222 | } |
356f0a30 | 1223 | device_del(pvt->addrmatch_dev); |
6c974d4d | 1224 | put_device(pvt->addrmatch_dev); |
5c4cdb5a MCC |
1225 | } |
1226 | ||
a0c36a1f MCC |
1227 | /**************************************************************************** |
1228 | Device initialization routines: put/get, init/exit | |
1229 | ****************************************************************************/ | |
1230 | ||
1231 | /* | |
64c10f6e | 1232 | * i7core_put_all_devices 'put' all the devices that we have |
a0c36a1f MCC |
1233 | * reserved via 'get' |
1234 | */ | |
13d6e9b6 | 1235 | static void i7core_put_devices(struct i7core_dev *i7core_dev) |
a0c36a1f | 1236 | { |
13d6e9b6 | 1237 | int i; |
a0c36a1f | 1238 | |
956b9ba1 | 1239 | edac_dbg(0, "\n"); |
de06eeef | 1240 | for (i = 0; i < i7core_dev->n_devs; i++) { |
22e6bcbd MCC |
1241 | struct pci_dev *pdev = i7core_dev->pdev[i]; |
1242 | if (!pdev) | |
1243 | continue; | |
956b9ba1 JP |
1244 | edac_dbg(0, "Removing dev %02x:%02x.%d\n", |
1245 | pdev->bus->number, | |
1246 | PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn)); | |
22e6bcbd MCC |
1247 | pci_dev_put(pdev); |
1248 | } | |
13d6e9b6 | 1249 | } |
66607706 | 1250 | |
13d6e9b6 MCC |
1251 | static void i7core_put_all_devices(void) |
1252 | { | |
42538680 | 1253 | struct i7core_dev *i7core_dev, *tmp; |
13d6e9b6 | 1254 | |
39300e71 | 1255 | list_for_each_entry_safe(i7core_dev, tmp, &i7core_edac_list, list) { |
13d6e9b6 | 1256 | i7core_put_devices(i7core_dev); |
2aa9be44 | 1257 | free_i7core_dev(i7core_dev); |
39300e71 | 1258 | } |
a0c36a1f MCC |
1259 | } |
1260 | ||
1288c18f | 1261 | static void __init i7core_xeon_pci_fixup(const struct pci_id_table *table) |
bc2d7245 KM |
1262 | { |
1263 | struct pci_dev *pdev = NULL; | |
1264 | int i; | |
54a08ab1 | 1265 | |
bc2d7245 | 1266 | /* |
e7bf068a | 1267 | * On Xeon 55xx, the Intel Quick Path Arch Generic Non-core pci buses |
bc2d7245 KM |
1268 | * aren't announced by acpi. So, we need to use a legacy scan probing |
1269 | * to detect them | |
1270 | */ | |
bd9e19ca VM |
1271 | while (table && table->descr) { |
1272 | pdev = pci_get_device(PCI_VENDOR_ID_INTEL, table->descr[0].dev_id, NULL); | |
1273 | if (unlikely(!pdev)) { | |
1274 | for (i = 0; i < MAX_SOCKET_BUSES; i++) | |
1275 | pcibios_scan_specific_bus(255-i); | |
1276 | } | |
bda14289 | 1277 | pci_dev_put(pdev); |
bd9e19ca | 1278 | table++; |
bc2d7245 KM |
1279 | } |
1280 | } | |
1281 | ||
bda14289 MCC |
1282 | static unsigned i7core_pci_lastbus(void) |
1283 | { | |
1284 | int last_bus = 0, bus; | |
1285 | struct pci_bus *b = NULL; | |
1286 | ||
1287 | while ((b = pci_find_next_bus(b)) != NULL) { | |
1288 | bus = b->number; | |
956b9ba1 | 1289 | edac_dbg(0, "Found bus %d\n", bus); |
bda14289 MCC |
1290 | if (bus > last_bus) |
1291 | last_bus = bus; | |
1292 | } | |
1293 | ||
956b9ba1 | 1294 | edac_dbg(0, "Last bus %d\n", last_bus); |
bda14289 MCC |
1295 | |
1296 | return last_bus; | |
1297 | } | |
1298 | ||
a0c36a1f | 1299 | /* |
64c10f6e | 1300 | * i7core_get_all_devices Find and perform 'get' operation on the MCH's |
a0c36a1f MCC |
1301 | * device/functions we want to reference for this driver |
1302 | * | |
1303 | * Need to 'get' device 16 func 1 and func 2 | |
1304 | */ | |
b197cba0 HS |
1305 | static int i7core_get_onedevice(struct pci_dev **prev, |
1306 | const struct pci_id_table *table, | |
1307 | const unsigned devno, | |
1308 | const unsigned last_bus) | |
a0c36a1f | 1309 | { |
66607706 | 1310 | struct i7core_dev *i7core_dev; |
b197cba0 | 1311 | const struct pci_id_descr *dev_descr = &table->descr[devno]; |
66607706 | 1312 | |
8f331907 | 1313 | struct pci_dev *pdev = NULL; |
67166af4 MCC |
1314 | u8 bus = 0; |
1315 | u8 socket = 0; | |
a0c36a1f | 1316 | |
c77720b9 | 1317 | pdev = pci_get_device(PCI_VENDOR_ID_INTEL, |
de06eeef | 1318 | dev_descr->dev_id, *prev); |
c77720b9 | 1319 | |
224e871f | 1320 | /* |
15ed103a | 1321 | * On Xeon 55xx, the Intel QuickPath Arch Generic Non-core regs |
224e871f MCC |
1322 | * is at addr 8086:2c40, instead of 8086:2c41. So, we need |
1323 | * to probe for the alternate address in case of failure | |
1324 | */ | |
c0f5eeed JD |
1325 | if (dev_descr->dev_id == PCI_DEVICE_ID_INTEL_I7_NONCORE && !pdev) { |
1326 | pci_dev_get(*prev); /* pci_get_device will put it */ | |
224e871f MCC |
1327 | pdev = pci_get_device(PCI_VENDOR_ID_INTEL, |
1328 | PCI_DEVICE_ID_INTEL_I7_NONCORE_ALT, *prev); | |
c0f5eeed | 1329 | } |
224e871f | 1330 | |
c0f5eeed JD |
1331 | if (dev_descr->dev_id == PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE && |
1332 | !pdev) { | |
1333 | pci_dev_get(*prev); /* pci_get_device will put it */ | |
224e871f MCC |
1334 | pdev = pci_get_device(PCI_VENDOR_ID_INTEL, |
1335 | PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE_ALT, | |
1336 | *prev); | |
c0f5eeed | 1337 | } |
224e871f | 1338 | |
c77720b9 MCC |
1339 | if (!pdev) { |
1340 | if (*prev) { | |
1341 | *prev = pdev; | |
1342 | return 0; | |
d1fd4fb6 MCC |
1343 | } |
1344 | ||
de06eeef | 1345 | if (dev_descr->optional) |
c77720b9 | 1346 | return 0; |
310cbb72 | 1347 | |
bd9e19ca VM |
1348 | if (devno == 0) |
1349 | return -ENODEV; | |
1350 | ||
ab089374 | 1351 | i7core_printk(KERN_INFO, |
c77720b9 | 1352 | "Device not found: dev %02x.%d PCI ID %04x:%04x\n", |
de06eeef MCC |
1353 | dev_descr->dev, dev_descr->func, |
1354 | PCI_VENDOR_ID_INTEL, dev_descr->dev_id); | |
67166af4 | 1355 | |
c77720b9 MCC |
1356 | /* End of list, leave */ |
1357 | return -ENODEV; | |
1358 | } | |
1359 | bus = pdev->bus->number; | |
67166af4 | 1360 | |
bda14289 | 1361 | socket = last_bus - bus; |
c77720b9 | 1362 | |
66607706 MCC |
1363 | i7core_dev = get_i7core_dev(socket); |
1364 | if (!i7core_dev) { | |
848b2f7e | 1365 | i7core_dev = alloc_i7core_dev(socket, table); |
2896637b HS |
1366 | if (!i7core_dev) { |
1367 | pci_dev_put(pdev); | |
66607706 | 1368 | return -ENOMEM; |
2896637b | 1369 | } |
c77720b9 | 1370 | } |
67166af4 | 1371 | |
66607706 | 1372 | if (i7core_dev->pdev[devno]) { |
c77720b9 MCC |
1373 | i7core_printk(KERN_ERR, |
1374 | "Duplicated device for " | |
1375 | "dev %02x:%02x.%d PCI ID %04x:%04x\n", | |
de06eeef MCC |
1376 | bus, dev_descr->dev, dev_descr->func, |
1377 | PCI_VENDOR_ID_INTEL, dev_descr->dev_id); | |
c77720b9 MCC |
1378 | pci_dev_put(pdev); |
1379 | return -ENODEV; | |
1380 | } | |
67166af4 | 1381 | |
66607706 | 1382 | i7core_dev->pdev[devno] = pdev; |
c77720b9 MCC |
1383 | |
1384 | /* Sanity check */ | |
de06eeef MCC |
1385 | if (unlikely(PCI_SLOT(pdev->devfn) != dev_descr->dev || |
1386 | PCI_FUNC(pdev->devfn) != dev_descr->func)) { | |
c77720b9 MCC |
1387 | i7core_printk(KERN_ERR, |
1388 | "Device PCI ID %04x:%04x " | |
1389 | "has dev %02x:%02x.%d instead of dev %02x:%02x.%d\n", | |
de06eeef | 1390 | PCI_VENDOR_ID_INTEL, dev_descr->dev_id, |
c77720b9 | 1391 | bus, PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), |
de06eeef | 1392 | bus, dev_descr->dev, dev_descr->func); |
c77720b9 MCC |
1393 | return -ENODEV; |
1394 | } | |
ef708b53 | 1395 | |
c77720b9 MCC |
1396 | /* Be sure that the device is enabled */ |
1397 | if (unlikely(pci_enable_device(pdev) < 0)) { | |
1398 | i7core_printk(KERN_ERR, | |
1399 | "Couldn't enable " | |
1400 | "dev %02x:%02x.%d PCI ID %04x:%04x\n", | |
de06eeef MCC |
1401 | bus, dev_descr->dev, dev_descr->func, |
1402 | PCI_VENDOR_ID_INTEL, dev_descr->dev_id); | |
c77720b9 MCC |
1403 | return -ENODEV; |
1404 | } | |
ef708b53 | 1405 | |
956b9ba1 JP |
1406 | edac_dbg(0, "Detected socket %d dev %02x:%02x.%d PCI ID %04x:%04x\n", |
1407 | socket, bus, dev_descr->dev, | |
1408 | dev_descr->func, | |
1409 | PCI_VENDOR_ID_INTEL, dev_descr->dev_id); | |
8f331907 | 1410 | |
a3e15416 MCC |
1411 | /* |
1412 | * As stated on drivers/pci/search.c, the reference count for | |
1413 | * @from is always decremented if it is not %NULL. So, as we need | |
1414 | * to get all devices up to null, we need to do a get for the device | |
1415 | */ | |
1416 | pci_dev_get(pdev); | |
1417 | ||
c77720b9 | 1418 | *prev = pdev; |
ef708b53 | 1419 | |
c77720b9 MCC |
1420 | return 0; |
1421 | } | |
a0c36a1f | 1422 | |
64c10f6e | 1423 | static int i7core_get_all_devices(void) |
c77720b9 | 1424 | { |
3c52cc57 | 1425 | int i, rc, last_bus; |
c77720b9 | 1426 | struct pci_dev *pdev = NULL; |
3c52cc57 | 1427 | const struct pci_id_table *table = pci_dev_table; |
bd9e19ca | 1428 | |
bda14289 MCC |
1429 | last_bus = i7core_pci_lastbus(); |
1430 | ||
3c52cc57 | 1431 | while (table && table->descr) { |
bd9e19ca VM |
1432 | for (i = 0; i < table->n_devs; i++) { |
1433 | pdev = NULL; | |
1434 | do { | |
b197cba0 | 1435 | rc = i7core_get_onedevice(&pdev, table, i, |
bda14289 | 1436 | last_bus); |
bd9e19ca VM |
1437 | if (rc < 0) { |
1438 | if (i == 0) { | |
1439 | i = table->n_devs; | |
1440 | break; | |
1441 | } | |
1442 | i7core_put_all_devices(); | |
1443 | return -ENODEV; | |
1444 | } | |
1445 | } while (pdev); | |
1446 | } | |
3c52cc57 | 1447 | table++; |
c77720b9 | 1448 | } |
66607706 | 1449 | |
ef708b53 | 1450 | return 0; |
ef708b53 MCC |
1451 | } |
1452 | ||
f4742949 MCC |
1453 | static int mci_bind_devs(struct mem_ctl_info *mci, |
1454 | struct i7core_dev *i7core_dev) | |
ef708b53 MCC |
1455 | { |
1456 | struct i7core_pvt *pvt = mci->pvt_info; | |
1457 | struct pci_dev *pdev; | |
f4742949 | 1458 | int i, func, slot; |
27100db0 | 1459 | char *family; |
ef708b53 | 1460 | |
27100db0 MCC |
1461 | pvt->is_registered = false; |
1462 | pvt->enable_scrub = false; | |
de06eeef | 1463 | for (i = 0; i < i7core_dev->n_devs; i++) { |
f4742949 MCC |
1464 | pdev = i7core_dev->pdev[i]; |
1465 | if (!pdev) | |
66607706 MCC |
1466 | continue; |
1467 | ||
f4742949 MCC |
1468 | func = PCI_FUNC(pdev->devfn); |
1469 | slot = PCI_SLOT(pdev->devfn); | |
1470 | if (slot == 3) { | |
1471 | if (unlikely(func > MAX_MCR_FUNC)) | |
1472 | goto error; | |
1473 | pvt->pci_mcr[func] = pdev; | |
1474 | } else if (likely(slot >= 4 && slot < 4 + NUM_CHANS)) { | |
1475 | if (unlikely(func > MAX_CHAN_FUNC)) | |
ef708b53 | 1476 | goto error; |
f4742949 | 1477 | pvt->pci_ch[slot - 4][func] = pdev; |
27100db0 | 1478 | } else if (!slot && !func) { |
f4742949 | 1479 | pvt->pci_noncore = pdev; |
27100db0 MCC |
1480 | |
1481 | /* Detect the processor family */ | |
1482 | switch (pdev->device) { | |
1483 | case PCI_DEVICE_ID_INTEL_I7_NONCORE: | |
1484 | family = "Xeon 35xx/ i7core"; | |
1485 | pvt->enable_scrub = false; | |
1486 | break; | |
1487 | case PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE_ALT: | |
1488 | family = "i7-800/i5-700"; | |
1489 | pvt->enable_scrub = false; | |
1490 | break; | |
1491 | case PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE: | |
1492 | family = "Xeon 34xx"; | |
1493 | pvt->enable_scrub = false; | |
1494 | break; | |
1495 | case PCI_DEVICE_ID_INTEL_I7_NONCORE_ALT: | |
1496 | family = "Xeon 55xx"; | |
1497 | pvt->enable_scrub = true; | |
1498 | break; | |
1499 | case PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE_REV2: | |
1500 | family = "Xeon 56xx / i7-900"; | |
1501 | pvt->enable_scrub = true; | |
1502 | break; | |
1503 | default: | |
1504 | family = "unknown"; | |
1505 | pvt->enable_scrub = false; | |
1506 | } | |
956b9ba1 | 1507 | edac_dbg(0, "Detected a processor type %s\n", family); |
27100db0 | 1508 | } else |
f4742949 | 1509 | goto error; |
ef708b53 | 1510 | |
956b9ba1 JP |
1511 | edac_dbg(0, "Associated fn %d.%d, dev = %p, socket %d\n", |
1512 | PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), | |
1513 | pdev, i7core_dev->socket); | |
14d2c083 | 1514 | |
f4742949 MCC |
1515 | if (PCI_SLOT(pdev->devfn) == 3 && |
1516 | PCI_FUNC(pdev->devfn) == 2) | |
27100db0 | 1517 | pvt->is_registered = true; |
a0c36a1f | 1518 | } |
e9bd2e73 | 1519 | |
a0c36a1f | 1520 | return 0; |
ef708b53 MCC |
1521 | |
1522 | error: | |
1523 | i7core_printk(KERN_ERR, "Device %d, function %d " | |
1524 | "is out of the expected range\n", | |
1525 | slot, func); | |
1526 | return -EINVAL; | |
a0c36a1f MCC |
1527 | } |
1528 | ||
442305b1 MCC |
1529 | /**************************************************************************** |
1530 | Error check routines | |
1531 | ****************************************************************************/ | |
b4e8f0b6 MCC |
1532 | |
1533 | static void i7core_rdimm_update_ce_count(struct mem_ctl_info *mci, | |
1288c18f MCC |
1534 | const int chan, |
1535 | const int new0, | |
1536 | const int new1, | |
1537 | const int new2) | |
b4e8f0b6 MCC |
1538 | { |
1539 | struct i7core_pvt *pvt = mci->pvt_info; | |
1540 | int add0 = 0, add1 = 0, add2 = 0; | |
1541 | /* Updates CE counters if it is not the first time here */ | |
f4742949 | 1542 | if (pvt->ce_count_available) { |
b4e8f0b6 MCC |
1543 | /* Updates CE counters */ |
1544 | ||
f4742949 MCC |
1545 | add2 = new2 - pvt->rdimm_last_ce_count[chan][2]; |
1546 | add1 = new1 - pvt->rdimm_last_ce_count[chan][1]; | |
1547 | add0 = new0 - pvt->rdimm_last_ce_count[chan][0]; | |
b4e8f0b6 MCC |
1548 | |
1549 | if (add2 < 0) | |
1550 | add2 += 0x7fff; | |
f4742949 | 1551 | pvt->rdimm_ce_count[chan][2] += add2; |
b4e8f0b6 MCC |
1552 | |
1553 | if (add1 < 0) | |
1554 | add1 += 0x7fff; | |
f4742949 | 1555 | pvt->rdimm_ce_count[chan][1] += add1; |
b4e8f0b6 MCC |
1556 | |
1557 | if (add0 < 0) | |
1558 | add0 += 0x7fff; | |
f4742949 | 1559 | pvt->rdimm_ce_count[chan][0] += add0; |
b4e8f0b6 | 1560 | } else |
f4742949 | 1561 | pvt->ce_count_available = 1; |
b4e8f0b6 MCC |
1562 | |
1563 | /* Store the new values */ | |
f4742949 MCC |
1564 | pvt->rdimm_last_ce_count[chan][2] = new2; |
1565 | pvt->rdimm_last_ce_count[chan][1] = new1; | |
1566 | pvt->rdimm_last_ce_count[chan][0] = new0; | |
b4e8f0b6 MCC |
1567 | |
1568 | /*updated the edac core */ | |
1569 | if (add0 != 0) | |
00d18339 MCC |
1570 | edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, add0, |
1571 | 0, 0, 0, | |
1572 | chan, 0, -1, "error", ""); | |
b4e8f0b6 | 1573 | if (add1 != 0) |
00d18339 MCC |
1574 | edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, add1, |
1575 | 0, 0, 0, | |
1576 | chan, 1, -1, "error", ""); | |
b4e8f0b6 | 1577 | if (add2 != 0) |
00d18339 MCC |
1578 | edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, add2, |
1579 | 0, 0, 0, | |
1580 | chan, 2, -1, "error", ""); | |
b4e8f0b6 MCC |
1581 | } |
1582 | ||
f4742949 | 1583 | static void i7core_rdimm_check_mc_ecc_err(struct mem_ctl_info *mci) |
b4e8f0b6 MCC |
1584 | { |
1585 | struct i7core_pvt *pvt = mci->pvt_info; | |
1586 | u32 rcv[3][2]; | |
1587 | int i, new0, new1, new2; | |
1588 | ||
1589 | /*Read DEV 3: FUN 2: MC_COR_ECC_CNT regs directly*/ | |
f4742949 | 1590 | pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_0, |
b4e8f0b6 | 1591 | &rcv[0][0]); |
f4742949 | 1592 | pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_1, |
b4e8f0b6 | 1593 | &rcv[0][1]); |
f4742949 | 1594 | pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_2, |
b4e8f0b6 | 1595 | &rcv[1][0]); |
f4742949 | 1596 | pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_3, |
b4e8f0b6 | 1597 | &rcv[1][1]); |
f4742949 | 1598 | pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_4, |
b4e8f0b6 | 1599 | &rcv[2][0]); |
f4742949 | 1600 | pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_5, |
b4e8f0b6 MCC |
1601 | &rcv[2][1]); |
1602 | for (i = 0 ; i < 3; i++) { | |
956b9ba1 JP |
1603 | edac_dbg(3, "MC_COR_ECC_CNT%d = 0x%x; MC_COR_ECC_CNT%d = 0x%x\n", |
1604 | (i * 2), rcv[i][0], (i * 2) + 1, rcv[i][1]); | |
b4e8f0b6 | 1605 | /*if the channel has 3 dimms*/ |
f4742949 | 1606 | if (pvt->channel[i].dimms > 2) { |
b4e8f0b6 MCC |
1607 | new0 = DIMM_BOT_COR_ERR(rcv[i][0]); |
1608 | new1 = DIMM_TOP_COR_ERR(rcv[i][0]); | |
1609 | new2 = DIMM_BOT_COR_ERR(rcv[i][1]); | |
1610 | } else { | |
1611 | new0 = DIMM_TOP_COR_ERR(rcv[i][0]) + | |
1612 | DIMM_BOT_COR_ERR(rcv[i][0]); | |
1613 | new1 = DIMM_TOP_COR_ERR(rcv[i][1]) + | |
1614 | DIMM_BOT_COR_ERR(rcv[i][1]); | |
1615 | new2 = 0; | |
1616 | } | |
1617 | ||
f4742949 | 1618 | i7core_rdimm_update_ce_count(mci, i, new0, new1, new2); |
b4e8f0b6 MCC |
1619 | } |
1620 | } | |
442305b1 MCC |
1621 | |
1622 | /* This function is based on the device 3 function 4 registers as described on: | |
1623 | * Intel Xeon Processor 5500 Series Datasheet Volume 2 | |
1624 | * http://www.intel.com/Assets/PDF/datasheet/321322.pdf | |
1625 | * also available at: | |
1626 | * http://www.arrownac.com/manufacturers/intel/s/nehalem/5500-datasheet-v2.pdf | |
1627 | */ | |
f4742949 | 1628 | static void i7core_udimm_check_mc_ecc_err(struct mem_ctl_info *mci) |
442305b1 MCC |
1629 | { |
1630 | struct i7core_pvt *pvt = mci->pvt_info; | |
1631 | u32 rcv1, rcv0; | |
1632 | int new0, new1, new2; | |
1633 | ||
f4742949 | 1634 | if (!pvt->pci_mcr[4]) { |
956b9ba1 | 1635 | edac_dbg(0, "MCR registers not found\n"); |
442305b1 MCC |
1636 | return; |
1637 | } | |
1638 | ||
b4e8f0b6 | 1639 | /* Corrected test errors */ |
f4742949 MCC |
1640 | pci_read_config_dword(pvt->pci_mcr[4], MC_TEST_ERR_RCV1, &rcv1); |
1641 | pci_read_config_dword(pvt->pci_mcr[4], MC_TEST_ERR_RCV0, &rcv0); | |
442305b1 MCC |
1642 | |
1643 | /* Store the new values */ | |
1644 | new2 = DIMM2_COR_ERR(rcv1); | |
1645 | new1 = DIMM1_COR_ERR(rcv0); | |
1646 | new0 = DIMM0_COR_ERR(rcv0); | |
1647 | ||
442305b1 | 1648 | /* Updates CE counters if it is not the first time here */ |
f4742949 | 1649 | if (pvt->ce_count_available) { |
442305b1 MCC |
1650 | /* Updates CE counters */ |
1651 | int add0, add1, add2; | |
1652 | ||
f4742949 MCC |
1653 | add2 = new2 - pvt->udimm_last_ce_count[2]; |
1654 | add1 = new1 - pvt->udimm_last_ce_count[1]; | |
1655 | add0 = new0 - pvt->udimm_last_ce_count[0]; | |
442305b1 MCC |
1656 | |
1657 | if (add2 < 0) | |
1658 | add2 += 0x7fff; | |
f4742949 | 1659 | pvt->udimm_ce_count[2] += add2; |
442305b1 MCC |
1660 | |
1661 | if (add1 < 0) | |
1662 | add1 += 0x7fff; | |
f4742949 | 1663 | pvt->udimm_ce_count[1] += add1; |
442305b1 MCC |
1664 | |
1665 | if (add0 < 0) | |
1666 | add0 += 0x7fff; | |
f4742949 | 1667 | pvt->udimm_ce_count[0] += add0; |
b4e8f0b6 MCC |
1668 | |
1669 | if (add0 | add1 | add2) | |
1670 | i7core_printk(KERN_ERR, "New Corrected error(s): " | |
1671 | "dimm0: +%d, dimm1: +%d, dimm2 +%d\n", | |
1672 | add0, add1, add2); | |
442305b1 | 1673 | } else |
f4742949 | 1674 | pvt->ce_count_available = 1; |
442305b1 MCC |
1675 | |
1676 | /* Store the new values */ | |
f4742949 MCC |
1677 | pvt->udimm_last_ce_count[2] = new2; |
1678 | pvt->udimm_last_ce_count[1] = new1; | |
1679 | pvt->udimm_last_ce_count[0] = new0; | |
442305b1 MCC |
1680 | } |
1681 | ||
8a2f118e MCC |
1682 | /* |
1683 | * According with tables E-11 and E-12 of chapter E.3.3 of Intel 64 and IA-32 | |
1684 | * Architectures Software Developer’s Manual Volume 3B. | |
f237fcf2 MCC |
1685 | * Nehalem are defined as family 0x06, model 0x1a |
1686 | * | |
1687 | * The MCA registers used here are the following ones: | |
8a2f118e | 1688 | * struct mce field MCA Register |
f237fcf2 MCC |
1689 | * m->status MSR_IA32_MC8_STATUS |
1690 | * m->addr MSR_IA32_MC8_ADDR | |
1691 | * m->misc MSR_IA32_MC8_MISC | |
8a2f118e MCC |
1692 | * In the case of Nehalem, the error information is masked at .status and .misc |
1693 | * fields | |
1694 | */ | |
d5381642 | 1695 | static void i7core_mce_output_error(struct mem_ctl_info *mci, |
1288c18f | 1696 | const struct mce *m) |
d5381642 | 1697 | { |
b4e8f0b6 | 1698 | struct i7core_pvt *pvt = mci->pvt_info; |
f118920b | 1699 | char *optype, *err; |
0975c16f | 1700 | enum hw_event_mc_err_type tp_event; |
8a2f118e | 1701 | unsigned long error = m->status & 0x1ff0000l; |
0975c16f MCC |
1702 | bool uncorrected_error = m->mcgstatus & 1ll << 61; |
1703 | bool ripv = m->mcgstatus & 1; | |
a639539f | 1704 | u32 optypenum = (m->status >> 4) & 0x07; |
8cf2d239 | 1705 | u32 core_err_cnt = (m->status >> 38) & 0x7fff; |
8a2f118e MCC |
1706 | u32 dimm = (m->misc >> 16) & 0x3; |
1707 | u32 channel = (m->misc >> 18) & 0x3; | |
1708 | u32 syndrome = m->misc >> 32; | |
1709 | u32 errnum = find_first_bit(&error, 32); | |
1710 | ||
0975c16f | 1711 | if (uncorrected_error) { |
432de7fd | 1712 | core_err_cnt = 1; |
f118920b | 1713 | if (ripv) |
0975c16f | 1714 | tp_event = HW_EVENT_ERR_FATAL; |
f118920b | 1715 | else |
0975c16f | 1716 | tp_event = HW_EVENT_ERR_UNCORRECTED; |
0975c16f | 1717 | } else { |
0975c16f MCC |
1718 | tp_event = HW_EVENT_ERR_CORRECTED; |
1719 | } | |
c5d34528 | 1720 | |
a639539f | 1721 | switch (optypenum) { |
b990538a MCC |
1722 | case 0: |
1723 | optype = "generic undef request"; | |
1724 | break; | |
1725 | case 1: | |
1726 | optype = "read error"; | |
1727 | break; | |
1728 | case 2: | |
1729 | optype = "write error"; | |
1730 | break; | |
1731 | case 3: | |
1732 | optype = "addr/cmd error"; | |
1733 | break; | |
1734 | case 4: | |
1735 | optype = "scrubbing error"; | |
1736 | break; | |
1737 | default: | |
1738 | optype = "reserved"; | |
1739 | break; | |
a639539f MCC |
1740 | } |
1741 | ||
8a2f118e MCC |
1742 | switch (errnum) { |
1743 | case 16: | |
1744 | err = "read ECC error"; | |
1745 | break; | |
1746 | case 17: | |
1747 | err = "RAS ECC error"; | |
1748 | break; | |
1749 | case 18: | |
1750 | err = "write parity error"; | |
1751 | break; | |
1752 | case 19: | |
83e548be | 1753 | err = "redundancy loss"; |
8a2f118e MCC |
1754 | break; |
1755 | case 20: | |
1756 | err = "reserved"; | |
1757 | break; | |
1758 | case 21: | |
1759 | err = "memory range error"; | |
1760 | break; | |
1761 | case 22: | |
1762 | err = "RTID out of range"; | |
1763 | break; | |
1764 | case 23: | |
1765 | err = "address parity error"; | |
1766 | break; | |
1767 | case 24: | |
1768 | err = "byte enable parity error"; | |
1769 | break; | |
1770 | default: | |
1771 | err = "unknown"; | |
d5381642 | 1772 | } |
d5381642 | 1773 | |
0975c16f MCC |
1774 | /* |
1775 | * Call the helper to output message | |
1776 | * FIXME: what to do if core_err_cnt > 1? Currently, it generates | |
1777 | * only one event | |
1778 | */ | |
1779 | if (uncorrected_error || !pvt->is_registered) | |
00d18339 | 1780 | edac_mc_handle_error(tp_event, mci, core_err_cnt, |
0975c16f MCC |
1781 | m->addr >> PAGE_SHIFT, |
1782 | m->addr & ~PAGE_MASK, | |
1783 | syndrome, | |
1784 | channel, dimm, -1, | |
00d18339 | 1785 | err, optype); |
d5381642 MCC |
1786 | } |
1787 | ||
87d1d272 MCC |
1788 | /* |
1789 | * i7core_check_error Retrieve and process errors reported by the | |
1790 | * hardware. Called by the Core module. | |
1791 | */ | |
53595345 | 1792 | static void i7core_check_error(struct mem_ctl_info *mci, struct mce *m) |
87d1d272 | 1793 | { |
d5381642 | 1794 | struct i7core_pvt *pvt = mci->pvt_info; |
d5381642 | 1795 | |
53595345 | 1796 | i7core_mce_output_error(mci, m); |
d5381642 | 1797 | |
ca9c90ba MCC |
1798 | /* |
1799 | * Now, let's increment CE error counts | |
1800 | */ | |
f4742949 MCC |
1801 | if (!pvt->is_registered) |
1802 | i7core_udimm_check_mc_ecc_err(mci); | |
1803 | else | |
1804 | i7core_rdimm_check_mc_ecc_err(mci); | |
87d1d272 MCC |
1805 | } |
1806 | ||
d5381642 | 1807 | /* |
53595345 TL |
1808 | * Check that logging is enabled and that this is the right type |
1809 | * of error for us to handle. | |
d5381642 | 1810 | */ |
4140c542 BP |
1811 | static int i7core_mce_check_error(struct notifier_block *nb, unsigned long val, |
1812 | void *data) | |
d5381642 | 1813 | { |
4140c542 BP |
1814 | struct mce *mce = (struct mce *)data; |
1815 | struct i7core_dev *i7_dev; | |
1816 | struct mem_ctl_info *mci; | |
4140c542 BP |
1817 | |
1818 | i7_dev = get_i7core_dev(mce->socketid); | |
1819 | if (!i7_dev) | |
c4fc1956 | 1820 | return NOTIFY_DONE; |
4140c542 BP |
1821 | |
1822 | mci = i7_dev->mci; | |
d5381642 | 1823 | |
8a2f118e MCC |
1824 | /* |
1825 | * Just let mcelog handle it if the error is | |
1826 | * outside the memory controller | |
1827 | */ | |
1828 | if (((mce->status & 0xffff) >> 7) != 1) | |
4140c542 | 1829 | return NOTIFY_DONE; |
8a2f118e | 1830 | |
f237fcf2 MCC |
1831 | /* Bank 8 registers are the only ones that we know how to handle */ |
1832 | if (mce->bank != 8) | |
4140c542 | 1833 | return NOTIFY_DONE; |
f237fcf2 | 1834 | |
53595345 | 1835 | i7core_check_error(mci, mce); |
c5d34528 | 1836 | |
e7bf068a | 1837 | /* Advise mcelog that the errors were handled */ |
4140c542 | 1838 | return NOTIFY_STOP; |
d5381642 MCC |
1839 | } |
1840 | ||
4140c542 BP |
1841 | static struct notifier_block i7_mce_dec = { |
1842 | .notifier_call = i7core_mce_check_error, | |
9026cc82 | 1843 | .priority = MCE_PRIO_EDAC, |
4140c542 BP |
1844 | }; |
1845 | ||
535e9c78 NC |
1846 | struct memdev_dmi_entry { |
1847 | u8 type; | |
1848 | u8 length; | |
1849 | u16 handle; | |
1850 | u16 phys_mem_array_handle; | |
1851 | u16 mem_err_info_handle; | |
1852 | u16 total_width; | |
1853 | u16 data_width; | |
1854 | u16 size; | |
1855 | u8 form; | |
1856 | u8 device_set; | |
1857 | u8 device_locator; | |
1858 | u8 bank_locator; | |
1859 | u8 memory_type; | |
1860 | u16 type_detail; | |
1861 | u16 speed; | |
1862 | u8 manufacturer; | |
1863 | u8 serial_number; | |
1864 | u8 asset_tag; | |
1865 | u8 part_number; | |
1866 | u8 attributes; | |
1867 | u32 extended_size; | |
1868 | u16 conf_mem_clk_speed; | |
1869 | } __attribute__((__packed__)); | |
1870 | ||
1871 | ||
1872 | /* | |
1873 | * Decode the DRAM Clock Frequency, be paranoid, make sure that all | |
1874 | * memory devices show the same speed, and if they don't then consider | |
1875 | * all speeds to be invalid. | |
1876 | */ | |
1877 | static void decode_dclk(const struct dmi_header *dh, void *_dclk_freq) | |
1878 | { | |
1879 | int *dclk_freq = _dclk_freq; | |
1880 | u16 dmi_mem_clk_speed; | |
1881 | ||
1882 | if (*dclk_freq == -1) | |
1883 | return; | |
1884 | ||
1885 | if (dh->type == DMI_ENTRY_MEM_DEVICE) { | |
1886 | struct memdev_dmi_entry *memdev_dmi_entry = | |
1887 | (struct memdev_dmi_entry *)dh; | |
1888 | unsigned long conf_mem_clk_speed_offset = | |
1889 | (unsigned long)&memdev_dmi_entry->conf_mem_clk_speed - | |
1890 | (unsigned long)&memdev_dmi_entry->type; | |
1891 | unsigned long speed_offset = | |
1892 | (unsigned long)&memdev_dmi_entry->speed - | |
1893 | (unsigned long)&memdev_dmi_entry->type; | |
1894 | ||
1895 | /* Check that a DIMM is present */ | |
1896 | if (memdev_dmi_entry->size == 0) | |
1897 | return; | |
1898 | ||
1899 | /* | |
1900 | * Pick the configured speed if it's available, otherwise | |
1901 | * pick the DIMM speed, or we don't have a speed. | |
1902 | */ | |
1903 | if (memdev_dmi_entry->length > conf_mem_clk_speed_offset) { | |
1904 | dmi_mem_clk_speed = | |
1905 | memdev_dmi_entry->conf_mem_clk_speed; | |
1906 | } else if (memdev_dmi_entry->length > speed_offset) { | |
1907 | dmi_mem_clk_speed = memdev_dmi_entry->speed; | |
1908 | } else { | |
1909 | *dclk_freq = -1; | |
1910 | return; | |
1911 | } | |
1912 | ||
1913 | if (*dclk_freq == 0) { | |
1914 | /* First pass, speed was 0 */ | |
1915 | if (dmi_mem_clk_speed > 0) { | |
1916 | /* Set speed if a valid speed is read */ | |
1917 | *dclk_freq = dmi_mem_clk_speed; | |
1918 | } else { | |
1919 | /* Otherwise we don't have a valid speed */ | |
1920 | *dclk_freq = -1; | |
1921 | } | |
1922 | } else if (*dclk_freq > 0 && | |
1923 | *dclk_freq != dmi_mem_clk_speed) { | |
1924 | /* | |
1925 | * If we have a speed, check that all DIMMS are the same | |
1926 | * speed, otherwise set the speed as invalid. | |
1927 | */ | |
1928 | *dclk_freq = -1; | |
1929 | } | |
1930 | } | |
1931 | } | |
1932 | ||
1933 | /* | |
1934 | * The default DCLK frequency is used as a fallback if we | |
1935 | * fail to find anything reliable in the DMI. The value | |
1936 | * is taken straight from the datasheet. | |
1937 | */ | |
1938 | #define DEFAULT_DCLK_FREQ 800 | |
1939 | ||
1940 | static int get_dclk_freq(void) | |
1941 | { | |
1942 | int dclk_freq = 0; | |
1943 | ||
1944 | dmi_walk(decode_dclk, (void *)&dclk_freq); | |
1945 | ||
1946 | if (dclk_freq < 1) | |
1947 | return DEFAULT_DCLK_FREQ; | |
1948 | ||
1949 | return dclk_freq; | |
1950 | } | |
1951 | ||
e8b6a127 SG |
1952 | /* |
1953 | * set_sdram_scrub_rate This routine sets byte/sec bandwidth scrub rate | |
1954 | * to hardware according to SCRUBINTERVAL formula | |
1955 | * found in datasheet. | |
1956 | */ | |
1957 | static int set_sdram_scrub_rate(struct mem_ctl_info *mci, u32 new_bw) | |
1958 | { | |
1959 | struct i7core_pvt *pvt = mci->pvt_info; | |
1960 | struct pci_dev *pdev; | |
e8b6a127 SG |
1961 | u32 dw_scrub; |
1962 | u32 dw_ssr; | |
1963 | ||
1964 | /* Get data from the MC register, function 2 */ | |
1965 | pdev = pvt->pci_mcr[2]; | |
1966 | if (!pdev) | |
1967 | return -ENODEV; | |
1968 | ||
1969 | pci_read_config_dword(pdev, MC_SCRUB_CONTROL, &dw_scrub); | |
1970 | ||
1971 | if (new_bw == 0) { | |
1972 | /* Prepare to disable petrol scrub */ | |
1973 | dw_scrub &= ~STARTSCRUB; | |
1974 | /* Stop the patrol scrub engine */ | |
535e9c78 NC |
1975 | write_and_test(pdev, MC_SCRUB_CONTROL, |
1976 | dw_scrub & ~SCRUBINTERVAL_MASK); | |
e8b6a127 SG |
1977 | |
1978 | /* Get current status of scrub rate and set bit to disable */ | |
1979 | pci_read_config_dword(pdev, MC_SSRCONTROL, &dw_ssr); | |
1980 | dw_ssr &= ~SSR_MODE_MASK; | |
1981 | dw_ssr |= SSR_MODE_DISABLE; | |
1982 | } else { | |
535e9c78 NC |
1983 | const int cache_line_size = 64; |
1984 | const u32 freq_dclk_mhz = pvt->dclk_freq; | |
1985 | unsigned long long scrub_interval; | |
e8b6a127 SG |
1986 | /* |
1987 | * Translate the desired scrub rate to a register value and | |
535e9c78 | 1988 | * program the corresponding register value. |
e8b6a127 | 1989 | */ |
535e9c78 | 1990 | scrub_interval = (unsigned long long)freq_dclk_mhz * |
4fad8098 SD |
1991 | cache_line_size * 1000000; |
1992 | do_div(scrub_interval, new_bw); | |
535e9c78 NC |
1993 | |
1994 | if (!scrub_interval || scrub_interval > SCRUBINTERVAL_MASK) | |
1995 | return -EINVAL; | |
1996 | ||
1997 | dw_scrub = SCRUBINTERVAL_MASK & scrub_interval; | |
e8b6a127 SG |
1998 | |
1999 | /* Start the patrol scrub engine */ | |
2000 | pci_write_config_dword(pdev, MC_SCRUB_CONTROL, | |
2001 | STARTSCRUB | dw_scrub); | |
2002 | ||
2003 | /* Get current status of scrub rate and set bit to enable */ | |
2004 | pci_read_config_dword(pdev, MC_SSRCONTROL, &dw_ssr); | |
2005 | dw_ssr &= ~SSR_MODE_MASK; | |
2006 | dw_ssr |= SSR_MODE_ENABLE; | |
2007 | } | |
2008 | /* Disable or enable scrubbing */ | |
2009 | pci_write_config_dword(pdev, MC_SSRCONTROL, dw_ssr); | |
2010 | ||
2011 | return new_bw; | |
2012 | } | |
2013 | ||
2014 | /* | |
2015 | * get_sdram_scrub_rate This routine convert current scrub rate value | |
15ed103a | 2016 | * into byte/sec bandwidth according to |
e8b6a127 SG |
2017 | * SCRUBINTERVAL formula found in datasheet. |
2018 | */ | |
2019 | static int get_sdram_scrub_rate(struct mem_ctl_info *mci) | |
2020 | { | |
2021 | struct i7core_pvt *pvt = mci->pvt_info; | |
2022 | struct pci_dev *pdev; | |
2023 | const u32 cache_line_size = 64; | |
535e9c78 NC |
2024 | const u32 freq_dclk_mhz = pvt->dclk_freq; |
2025 | unsigned long long scrub_rate; | |
e8b6a127 SG |
2026 | u32 scrubval; |
2027 | ||
2028 | /* Get data from the MC register, function 2 */ | |
2029 | pdev = pvt->pci_mcr[2]; | |
2030 | if (!pdev) | |
2031 | return -ENODEV; | |
2032 | ||
2033 | /* Get current scrub control data */ | |
2034 | pci_read_config_dword(pdev, MC_SCRUB_CONTROL, &scrubval); | |
2035 | ||
2036 | /* Mask highest 8-bits to 0 */ | |
535e9c78 | 2037 | scrubval &= SCRUBINTERVAL_MASK; |
e8b6a127 SG |
2038 | if (!scrubval) |
2039 | return 0; | |
2040 | ||
2041 | /* Calculate scrub rate value into byte/sec bandwidth */ | |
535e9c78 | 2042 | scrub_rate = (unsigned long long)freq_dclk_mhz * |
4fad8098 SD |
2043 | 1000000 * cache_line_size; |
2044 | do_div(scrub_rate, scrubval); | |
535e9c78 | 2045 | return (int)scrub_rate; |
e8b6a127 SG |
2046 | } |
2047 | ||
2048 | static void enable_sdram_scrub_setting(struct mem_ctl_info *mci) | |
2049 | { | |
2050 | struct i7core_pvt *pvt = mci->pvt_info; | |
2051 | u32 pci_lock; | |
2052 | ||
2053 | /* Unlock writes to pci registers */ | |
2054 | pci_read_config_dword(pvt->pci_noncore, MC_CFG_CONTROL, &pci_lock); | |
2055 | pci_lock &= ~0x3; | |
2056 | pci_write_config_dword(pvt->pci_noncore, MC_CFG_CONTROL, | |
2057 | pci_lock | MC_CFG_UNLOCK); | |
2058 | ||
2059 | mci->set_sdram_scrub_rate = set_sdram_scrub_rate; | |
2060 | mci->get_sdram_scrub_rate = get_sdram_scrub_rate; | |
2061 | } | |
2062 | ||
2063 | static void disable_sdram_scrub_setting(struct mem_ctl_info *mci) | |
2064 | { | |
2065 | struct i7core_pvt *pvt = mci->pvt_info; | |
2066 | u32 pci_lock; | |
2067 | ||
2068 | /* Lock writes to pci registers */ | |
2069 | pci_read_config_dword(pvt->pci_noncore, MC_CFG_CONTROL, &pci_lock); | |
2070 | pci_lock &= ~0x3; | |
2071 | pci_write_config_dword(pvt->pci_noncore, MC_CFG_CONTROL, | |
2072 | pci_lock | MC_CFG_LOCK); | |
2073 | } | |
2074 | ||
a3aa0a4a HS |
2075 | static void i7core_pci_ctl_create(struct i7core_pvt *pvt) |
2076 | { | |
2077 | pvt->i7core_pci = edac_pci_create_generic_ctl( | |
2078 | &pvt->i7core_dev->pdev[0]->dev, | |
2079 | EDAC_MOD_STR); | |
2080 | if (unlikely(!pvt->i7core_pci)) | |
f9902f24 MCC |
2081 | i7core_printk(KERN_WARNING, |
2082 | "Unable to setup PCI error report via EDAC\n"); | |
a3aa0a4a HS |
2083 | } |
2084 | ||
2085 | static void i7core_pci_ctl_release(struct i7core_pvt *pvt) | |
2086 | { | |
2087 | if (likely(pvt->i7core_pci)) | |
2088 | edac_pci_release_generic_ctl(pvt->i7core_pci); | |
2089 | else | |
2090 | i7core_printk(KERN_ERR, | |
2091 | "Couldn't find mem_ctl_info for socket %d\n", | |
2092 | pvt->i7core_dev->socket); | |
2093 | pvt->i7core_pci = NULL; | |
2094 | } | |
2095 | ||
1c6edbbe HS |
2096 | static void i7core_unregister_mci(struct i7core_dev *i7core_dev) |
2097 | { | |
2098 | struct mem_ctl_info *mci = i7core_dev->mci; | |
2099 | struct i7core_pvt *pvt; | |
2100 | ||
2101 | if (unlikely(!mci || !mci->pvt_info)) { | |
956b9ba1 | 2102 | edac_dbg(0, "MC: dev = %p\n", &i7core_dev->pdev[0]->dev); |
1c6edbbe HS |
2103 | |
2104 | i7core_printk(KERN_ERR, "Couldn't find mci handler\n"); | |
2105 | return; | |
2106 | } | |
2107 | ||
2108 | pvt = mci->pvt_info; | |
2109 | ||
956b9ba1 | 2110 | edac_dbg(0, "MC: mci = %p, dev = %p\n", mci, &i7core_dev->pdev[0]->dev); |
1c6edbbe | 2111 | |
e8b6a127 | 2112 | /* Disable scrubrate setting */ |
27100db0 MCC |
2113 | if (pvt->enable_scrub) |
2114 | disable_sdram_scrub_setting(mci); | |
e8b6a127 | 2115 | |
1c6edbbe HS |
2116 | /* Disable EDAC polling */ |
2117 | i7core_pci_ctl_release(pvt); | |
2118 | ||
2119 | /* Remove MC sysfs nodes */ | |
5c4cdb5a | 2120 | i7core_delete_sysfs_devices(mci); |
fd687502 | 2121 | edac_mc_del_mc(mci->pdev); |
1c6edbbe | 2122 | |
956b9ba1 | 2123 | edac_dbg(1, "%s: free mci struct\n", mci->ctl_name); |
1c6edbbe HS |
2124 | kfree(mci->ctl_name); |
2125 | edac_mc_free(mci); | |
2126 | i7core_dev->mci = NULL; | |
2127 | } | |
2128 | ||
aace4283 | 2129 | static int i7core_register_mci(struct i7core_dev *i7core_dev) |
a0c36a1f MCC |
2130 | { |
2131 | struct mem_ctl_info *mci; | |
2132 | struct i7core_pvt *pvt; | |
0975c16f MCC |
2133 | int rc; |
2134 | struct edac_mc_layer layers[2]; | |
a0c36a1f | 2135 | |
a0c36a1f | 2136 | /* allocate a new MC control structure */ |
0975c16f MCC |
2137 | |
2138 | layers[0].type = EDAC_MC_LAYER_CHANNEL; | |
2139 | layers[0].size = NUM_CHANS; | |
2140 | layers[0].is_virt_csrow = false; | |
2141 | layers[1].type = EDAC_MC_LAYER_SLOT; | |
2142 | layers[1].size = MAX_DIMMS; | |
2143 | layers[1].is_virt_csrow = true; | |
ca0907b9 | 2144 | mci = edac_mc_alloc(i7core_dev->socket, ARRAY_SIZE(layers), layers, |
0975c16f | 2145 | sizeof(*pvt)); |
f4742949 MCC |
2146 | if (unlikely(!mci)) |
2147 | return -ENOMEM; | |
a0c36a1f | 2148 | |
956b9ba1 | 2149 | edac_dbg(0, "MC: mci = %p, dev = %p\n", mci, &i7core_dev->pdev[0]->dev); |
a0c36a1f | 2150 | |
a0c36a1f | 2151 | pvt = mci->pvt_info; |
ef708b53 | 2152 | memset(pvt, 0, sizeof(*pvt)); |
67166af4 | 2153 | |
6d37d240 MCC |
2154 | /* Associates i7core_dev and mci for future usage */ |
2155 | pvt->i7core_dev = i7core_dev; | |
2156 | i7core_dev->mci = mci; | |
2157 | ||
41fcb7fe MCC |
2158 | /* |
2159 | * FIXME: how to handle RDDR3 at MCI level? It is possible to have | |
2160 | * Mixed RDDR3/UDDR3 with Nehalem, provided that they are on different | |
2161 | * memory channels | |
2162 | */ | |
2163 | mci->mtype_cap = MEM_FLAG_DDR3; | |
a0c36a1f MCC |
2164 | mci->edac_ctl_cap = EDAC_FLAG_NONE; |
2165 | mci->edac_cap = EDAC_FLAG_NONE; | |
2166 | mci->mod_name = "i7core_edac.c"; | |
75f029c3 AY |
2167 | |
2168 | mci->ctl_name = kasprintf(GFP_KERNEL, "i7 core #%d", i7core_dev->socket); | |
2169 | if (!mci->ctl_name) { | |
2170 | rc = -ENOMEM; | |
2171 | goto fail1; | |
2172 | } | |
2173 | ||
f4742949 | 2174 | mci->dev_name = pci_name(i7core_dev->pdev[0]); |
a0c36a1f | 2175 | mci->ctl_page_to_phys = NULL; |
1288c18f | 2176 | |
ef708b53 | 2177 | /* Store pci devices at mci for faster access */ |
f4742949 | 2178 | rc = mci_bind_devs(mci, i7core_dev); |
41fcb7fe | 2179 | if (unlikely(rc < 0)) |
628c5ddf | 2180 | goto fail0; |
ef708b53 | 2181 | |
5939813b | 2182 | |
ef708b53 | 2183 | /* Get dimm basic config */ |
2e5185f7 | 2184 | get_dimm_config(mci); |
5939813b | 2185 | /* record ptr to the generic device */ |
fd687502 | 2186 | mci->pdev = &i7core_dev->pdev[0]->dev; |
ef708b53 | 2187 | |
e8b6a127 | 2188 | /* Enable scrubrate setting */ |
27100db0 MCC |
2189 | if (pvt->enable_scrub) |
2190 | enable_sdram_scrub_setting(mci); | |
e8b6a127 | 2191 | |
a0c36a1f | 2192 | /* add this new MC control structure to EDAC's list of MCs */ |
2eace188 | 2193 | if (unlikely(edac_mc_add_mc_with_groups(mci, i7core_dev_groups))) { |
956b9ba1 | 2194 | edac_dbg(0, "MC: failed edac_mc_add_mc()\n"); |
a0c36a1f MCC |
2195 | /* FIXME: perhaps some code should go here that disables error |
2196 | * reporting if we just enabled it | |
2197 | */ | |
b7c76151 MCC |
2198 | |
2199 | rc = -EINVAL; | |
628c5ddf | 2200 | goto fail0; |
a0c36a1f | 2201 | } |
5c4cdb5a | 2202 | if (i7core_create_sysfs_devices(mci)) { |
956b9ba1 | 2203 | edac_dbg(0, "MC: failed to create sysfs nodes\n"); |
5c4cdb5a MCC |
2204 | edac_mc_del_mc(mci->pdev); |
2205 | rc = -EINVAL; | |
2206 | goto fail0; | |
2207 | } | |
a0c36a1f | 2208 | |
194a40fe | 2209 | /* Default error mask is any memory */ |
ef708b53 | 2210 | pvt->inject.channel = 0; |
194a40fe MCC |
2211 | pvt->inject.dimm = -1; |
2212 | pvt->inject.rank = -1; | |
2213 | pvt->inject.bank = -1; | |
2214 | pvt->inject.page = -1; | |
2215 | pvt->inject.col = -1; | |
2216 | ||
a3aa0a4a HS |
2217 | /* allocating generic PCI control info */ |
2218 | i7core_pci_ctl_create(pvt); | |
2219 | ||
535e9c78 NC |
2220 | /* DCLK for scrub rate setting */ |
2221 | pvt->dclk_freq = get_dclk_freq(); | |
2222 | ||
628c5ddf HS |
2223 | return 0; |
2224 | ||
628c5ddf HS |
2225 | fail0: |
2226 | kfree(mci->ctl_name); | |
75f029c3 AY |
2227 | |
2228 | fail1: | |
628c5ddf | 2229 | edac_mc_free(mci); |
1c6edbbe | 2230 | i7core_dev->mci = NULL; |
f4742949 MCC |
2231 | return rc; |
2232 | } | |
2233 | ||
2234 | /* | |
2235 | * i7core_probe Probe for ONE instance of device to see if it is | |
2236 | * present. | |
2237 | * return: | |
2238 | * 0 for FOUND a device | |
2239 | * < 0 for error code | |
2240 | */ | |
2d95d815 | 2241 | |
9b3c6e85 | 2242 | static int i7core_probe(struct pci_dev *pdev, const struct pci_device_id *id) |
f4742949 | 2243 | { |
40557591 | 2244 | int rc, count = 0; |
f4742949 MCC |
2245 | struct i7core_dev *i7core_dev; |
2246 | ||
2d95d815 MCC |
2247 | /* get the pci devices we want to reserve for our use */ |
2248 | mutex_lock(&i7core_edac_lock); | |
2249 | ||
f4742949 | 2250 | /* |
d4c27795 | 2251 | * All memory controllers are allocated at the first pass. |
f4742949 | 2252 | */ |
2d95d815 MCC |
2253 | if (unlikely(probed >= 1)) { |
2254 | mutex_unlock(&i7core_edac_lock); | |
76a7bd81 | 2255 | return -ENODEV; |
2d95d815 MCC |
2256 | } |
2257 | probed++; | |
de06eeef | 2258 | |
64c10f6e | 2259 | rc = i7core_get_all_devices(); |
f4742949 MCC |
2260 | if (unlikely(rc < 0)) |
2261 | goto fail0; | |
2262 | ||
2263 | list_for_each_entry(i7core_dev, &i7core_edac_list, list) { | |
40557591 | 2264 | count++; |
aace4283 | 2265 | rc = i7core_register_mci(i7core_dev); |
d4c27795 MCC |
2266 | if (unlikely(rc < 0)) |
2267 | goto fail1; | |
d5381642 MCC |
2268 | } |
2269 | ||
40557591 MCC |
2270 | /* |
2271 | * Nehalem-EX uses a different memory controller. However, as the | |
2272 | * memory controller is not visible on some Nehalem/Nehalem-EP, we | |
2273 | * need to indirectly probe via a X58 PCI device. The same devices | |
2274 | * are found on (some) Nehalem-EX. So, on those machines, the | |
2275 | * probe routine needs to return -ENODEV, as the actual Memory | |
2276 | * Controller registers won't be detected. | |
2277 | */ | |
2278 | if (!count) { | |
2279 | rc = -ENODEV; | |
2280 | goto fail1; | |
2281 | } | |
2282 | ||
2283 | i7core_printk(KERN_INFO, | |
2284 | "Driver loaded, %d memory controller(s) found.\n", | |
2285 | count); | |
8f331907 | 2286 | |
66607706 | 2287 | mutex_unlock(&i7core_edac_lock); |
a0c36a1f MCC |
2288 | return 0; |
2289 | ||
66607706 | 2290 | fail1: |
88ef5ea9 MCC |
2291 | list_for_each_entry(i7core_dev, &i7core_edac_list, list) |
2292 | i7core_unregister_mci(i7core_dev); | |
2293 | ||
13d6e9b6 | 2294 | i7core_put_all_devices(); |
66607706 MCC |
2295 | fail0: |
2296 | mutex_unlock(&i7core_edac_lock); | |
b7c76151 | 2297 | return rc; |
a0c36a1f MCC |
2298 | } |
2299 | ||
2300 | /* | |
2301 | * i7core_remove destructor for one instance of device | |
2302 | * | |
2303 | */ | |
9b3c6e85 | 2304 | static void i7core_remove(struct pci_dev *pdev) |
a0c36a1f | 2305 | { |
64c10f6e | 2306 | struct i7core_dev *i7core_dev; |
a0c36a1f | 2307 | |
956b9ba1 | 2308 | edac_dbg(0, "\n"); |
a0c36a1f | 2309 | |
22e6bcbd MCC |
2310 | /* |
2311 | * we have a trouble here: pdev value for removal will be wrong, since | |
2312 | * it will point to the X58 register used to detect that the machine | |
2313 | * is a Nehalem or upper design. However, due to the way several PCI | |
2314 | * devices are grouped together to provide MC functionality, we need | |
2315 | * to use a different method for releasing the devices | |
2316 | */ | |
87d1d272 | 2317 | |
66607706 | 2318 | mutex_lock(&i7core_edac_lock); |
71fe0170 HS |
2319 | |
2320 | if (unlikely(!probed)) { | |
2321 | mutex_unlock(&i7core_edac_lock); | |
2322 | return; | |
2323 | } | |
2324 | ||
88ef5ea9 MCC |
2325 | list_for_each_entry(i7core_dev, &i7core_edac_list, list) |
2326 | i7core_unregister_mci(i7core_dev); | |
64c10f6e HS |
2327 | |
2328 | /* Release PCI resources */ | |
2329 | i7core_put_all_devices(); | |
2330 | ||
2d95d815 MCC |
2331 | probed--; |
2332 | ||
66607706 | 2333 | mutex_unlock(&i7core_edac_lock); |
a0c36a1f MCC |
2334 | } |
2335 | ||
a0c36a1f MCC |
2336 | MODULE_DEVICE_TABLE(pci, i7core_pci_tbl); |
2337 | ||
2338 | /* | |
2339 | * i7core_driver pci_driver structure for this module | |
2340 | * | |
2341 | */ | |
2342 | static struct pci_driver i7core_driver = { | |
2343 | .name = "i7core_edac", | |
2344 | .probe = i7core_probe, | |
9b3c6e85 | 2345 | .remove = i7core_remove, |
a0c36a1f MCC |
2346 | .id_table = i7core_pci_tbl, |
2347 | }; | |
2348 | ||
2349 | /* | |
2350 | * i7core_init Module entry function | |
2351 | * Try to initialize this module for its devices | |
2352 | */ | |
2353 | static int __init i7core_init(void) | |
2354 | { | |
2355 | int pci_rc; | |
2356 | ||
956b9ba1 | 2357 | edac_dbg(2, "\n"); |
a0c36a1f MCC |
2358 | |
2359 | /* Ensure that the OPSTATE is set correctly for POLL or NMI */ | |
2360 | opstate_init(); | |
2361 | ||
54a08ab1 MCC |
2362 | if (use_pci_fixup) |
2363 | i7core_xeon_pci_fixup(pci_dev_table); | |
bc2d7245 | 2364 | |
a0c36a1f MCC |
2365 | pci_rc = pci_register_driver(&i7core_driver); |
2366 | ||
e35fca47 CG |
2367 | if (pci_rc >= 0) { |
2368 | mce_register_decode_chain(&i7_mce_dec); | |
3ef288a9 | 2369 | return 0; |
e35fca47 | 2370 | } |
3ef288a9 MCC |
2371 | |
2372 | i7core_printk(KERN_ERR, "Failed to register device with error %d.\n", | |
2373 | pci_rc); | |
2374 | ||
2375 | return pci_rc; | |
a0c36a1f MCC |
2376 | } |
2377 | ||
2378 | /* | |
2379 | * i7core_exit() Module exit function | |
2380 | * Unregister the driver | |
2381 | */ | |
2382 | static void __exit i7core_exit(void) | |
2383 | { | |
956b9ba1 | 2384 | edac_dbg(2, "\n"); |
a0c36a1f | 2385 | pci_unregister_driver(&i7core_driver); |
e35fca47 | 2386 | mce_unregister_decode_chain(&i7_mce_dec); |
a0c36a1f MCC |
2387 | } |
2388 | ||
2389 | module_init(i7core_init); | |
2390 | module_exit(i7core_exit); | |
2391 | ||
2392 | MODULE_LICENSE("GPL"); | |
37e59f87 | 2393 | MODULE_AUTHOR("Mauro Carvalho Chehab"); |
a0c36a1f MCC |
2394 | MODULE_AUTHOR("Red Hat Inc. (http://www.redhat.com)"); |
2395 | MODULE_DESCRIPTION("MC Driver for Intel i7 Core memory controllers - " | |
2396 | I7CORE_REVISION); | |
2397 | ||
2398 | module_param(edac_op_state, int, 0444); | |
2399 | MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI"); |