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420390f0 RD |
1 | /* |
2 | * Intel 82975X Memory Controller kernel module | |
3 | * (C) 2007 aCarLab (India) Pvt. Ltd. (http://acarlab.com) | |
4 | * (C) 2007 jetzbroadband (http://jetzbroadband.com) | |
5 | * This file may be distributed under the terms of the | |
6 | * GNU General Public License. | |
7 | * | |
8 | * Written by Arvind R. | |
9 | * Copied from i82875p_edac.c source: | |
10 | */ | |
11 | ||
12 | #include <linux/module.h> | |
13 | #include <linux/init.h> | |
14 | #include <linux/pci.h> | |
15 | #include <linux/pci_ids.h> | |
c3c52bce | 16 | #include <linux/edac.h> |
420390f0 RD |
17 | #include "edac_core.h" |
18 | ||
152ba394 | 19 | #define I82975X_REVISION " Ver: 1.0.0" |
420390f0 RD |
20 | #define EDAC_MOD_STR "i82975x_edac" |
21 | ||
22 | #define i82975x_printk(level, fmt, arg...) \ | |
23 | edac_printk(level, "i82975x", fmt, ##arg) | |
24 | ||
25 | #define i82975x_mc_printk(mci, level, fmt, arg...) \ | |
26 | edac_mc_chipset_printk(mci, level, "i82975x", fmt, ##arg) | |
27 | ||
28 | #ifndef PCI_DEVICE_ID_INTEL_82975_0 | |
29 | #define PCI_DEVICE_ID_INTEL_82975_0 0x277c | |
30 | #endif /* PCI_DEVICE_ID_INTEL_82975_0 */ | |
31 | ||
32 | #define I82975X_NR_CSROWS(nr_chans) (8/(nr_chans)) | |
33 | ||
34 | /* Intel 82975X register addresses - device 0 function 0 - DRAM Controller */ | |
35 | #define I82975X_EAP 0x58 /* Dram Error Address Pointer (32b) | |
36 | * | |
37 | * 31:7 128 byte cache-line address | |
38 | * 6:1 reserved | |
39 | * 0 0: CH0; 1: CH1 | |
40 | */ | |
41 | ||
42 | #define I82975X_DERRSYN 0x5c /* Dram Error SYNdrome (8b) | |
43 | * | |
44 | * 7:0 DRAM ECC Syndrome | |
45 | */ | |
46 | ||
47 | #define I82975X_DES 0x5d /* Dram ERRor DeSTination (8b) | |
48 | * 0h: Processor Memory Reads | |
49 | * 1h:7h reserved | |
50 | * More - See Page 65 of Intel DocSheet. | |
51 | */ | |
52 | ||
53 | #define I82975X_ERRSTS 0xc8 /* Error Status Register (16b) | |
54 | * | |
55 | * 15:12 reserved | |
56 | * 11 Thermal Sensor Event | |
57 | * 10 reserved | |
58 | * 9 non-DRAM lock error (ndlock) | |
59 | * 8 Refresh Timeout | |
60 | * 7:2 reserved | |
61 | * 1 ECC UE (multibit DRAM error) | |
62 | * 0 ECC CE (singlebit DRAM error) | |
63 | */ | |
64 | ||
65 | /* Error Reporting is supported by 3 mechanisms: | |
66 | 1. DMI SERR generation ( ERRCMD ) | |
67 | 2. SMI DMI generation ( SMICMD ) | |
68 | 3. SCI DMI generation ( SCICMD ) | |
69 | NOTE: Only ONE of the three must be enabled | |
70 | */ | |
71 | #define I82975X_ERRCMD 0xca /* Error Command (16b) | |
72 | * | |
73 | * 15:12 reserved | |
74 | * 11 Thermal Sensor Event | |
75 | * 10 reserved | |
76 | * 9 non-DRAM lock error (ndlock) | |
77 | * 8 Refresh Timeout | |
78 | * 7:2 reserved | |
79 | * 1 ECC UE (multibit DRAM error) | |
80 | * 0 ECC CE (singlebit DRAM error) | |
81 | */ | |
82 | ||
83 | #define I82975X_SMICMD 0xcc /* Error Command (16b) | |
84 | * | |
85 | * 15:2 reserved | |
86 | * 1 ECC UE (multibit DRAM error) | |
87 | * 0 ECC CE (singlebit DRAM error) | |
88 | */ | |
89 | ||
90 | #define I82975X_SCICMD 0xce /* Error Command (16b) | |
91 | * | |
92 | * 15:2 reserved | |
93 | * 1 ECC UE (multibit DRAM error) | |
94 | * 0 ECC CE (singlebit DRAM error) | |
95 | */ | |
96 | ||
97 | #define I82975X_XEAP 0xfc /* Extended Dram Error Address Pointer (8b) | |
98 | * | |
99 | * 7:1 reserved | |
100 | * 0 Bit32 of the Dram Error Address | |
101 | */ | |
102 | ||
103 | #define I82975X_MCHBAR 0x44 /* | |
104 | * | |
105 | * 31:14 Base Addr of 16K memory-mapped | |
106 | * configuration space | |
107 | * 13:1 reserverd | |
108 | * 0 mem-mapped config space enable | |
109 | */ | |
110 | ||
111 | /* NOTE: Following addresses have to indexed using MCHBAR offset (44h, 32b) */ | |
112 | /* Intel 82975x memory mapped register space */ | |
113 | ||
114 | #define I82975X_DRB_SHIFT 25 /* fixed 32MiB grain */ | |
115 | ||
116 | #define I82975X_DRB 0x100 /* DRAM Row Boundary (8b x 8) | |
117 | * | |
118 | * 7 set to 1 in highest DRB of | |
119 | * channel if 4GB in ch. | |
120 | * 6:2 upper boundary of rank in | |
121 | * 32MB grains | |
122 | * 1:0 set to 0 | |
123 | */ | |
124 | #define I82975X_DRB_CH0R0 0x100 | |
125 | #define I82975X_DRB_CH0R1 0x101 | |
126 | #define I82975X_DRB_CH0R2 0x102 | |
127 | #define I82975X_DRB_CH0R3 0x103 | |
128 | #define I82975X_DRB_CH1R0 0x180 | |
129 | #define I82975X_DRB_CH1R1 0x181 | |
130 | #define I82975X_DRB_CH1R2 0x182 | |
131 | #define I82975X_DRB_CH1R3 0x183 | |
132 | ||
133 | ||
134 | #define I82975X_DRA 0x108 /* DRAM Row Attribute (4b x 8) | |
135 | * defines the PAGE SIZE to be used | |
136 | * for the rank | |
137 | * 7 reserved | |
138 | * 6:4 row attr of odd rank, i.e. 1 | |
139 | * 3 reserved | |
140 | * 2:0 row attr of even rank, i.e. 0 | |
141 | * | |
142 | * 000 = unpopulated | |
143 | * 001 = reserved | |
144 | * 010 = 4KiB | |
145 | * 011 = 8KiB | |
146 | * 100 = 16KiB | |
147 | * others = reserved | |
148 | */ | |
149 | #define I82975X_DRA_CH0R01 0x108 | |
150 | #define I82975X_DRA_CH0R23 0x109 | |
151 | #define I82975X_DRA_CH1R01 0x188 | |
152 | #define I82975X_DRA_CH1R23 0x189 | |
153 | ||
154 | ||
155 | #define I82975X_BNKARC 0x10e /* Type of device in each rank - Bank Arch (16b) | |
156 | * | |
157 | * 15:8 reserved | |
158 | * 7:6 Rank 3 architecture | |
159 | * 5:4 Rank 2 architecture | |
160 | * 3:2 Rank 1 architecture | |
161 | * 1:0 Rank 0 architecture | |
162 | * | |
7ba99575 A |
163 | * 00 => 4 banks |
164 | * 01 => 8 banks | |
420390f0 RD |
165 | */ |
166 | #define I82975X_C0BNKARC 0x10e | |
167 | #define I82975X_C1BNKARC 0x18e | |
168 | ||
169 | ||
170 | ||
171 | #define I82975X_DRC 0x120 /* DRAM Controller Mode0 (32b) | |
172 | * | |
173 | * 31:30 reserved | |
174 | * 29 init complete | |
175 | * 28:11 reserved, according to Intel | |
176 | * 22:21 number of channels | |
177 | * 00=1 01=2 in 82875 | |
178 | * seems to be ECC mode | |
179 | * bits in 82975 in Asus | |
180 | * P5W | |
181 | * 19:18 Data Integ Mode | |
182 | * 00=none 01=ECC in 82875 | |
183 | * 10:8 refresh mode | |
184 | * 7 reserved | |
185 | * 6:4 mode select | |
186 | * 3:2 reserved | |
187 | * 1:0 DRAM type 10=Second Revision | |
188 | * DDR2 SDRAM | |
189 | * 00, 01, 11 reserved | |
190 | */ | |
191 | #define I82975X_DRC_CH0M0 0x120 | |
192 | #define I82975X_DRC_CH1M0 0x1A0 | |
193 | ||
194 | ||
195 | #define I82975X_DRC_M1 0x124 /* DRAM Controller Mode1 (32b) | |
196 | * 31 0=Standard Address Map | |
197 | * 1=Enhanced Address Map | |
198 | * 30:0 reserved | |
199 | */ | |
200 | ||
201 | #define I82975X_DRC_CH0M1 0x124 | |
202 | #define I82975X_DRC_CH1M1 0x1A4 | |
203 | ||
204 | enum i82975x_chips { | |
205 | I82975X = 0, | |
206 | }; | |
207 | ||
208 | struct i82975x_pvt { | |
209 | void __iomem *mch_window; | |
210 | }; | |
211 | ||
212 | struct i82975x_dev_info { | |
213 | const char *ctl_name; | |
214 | }; | |
215 | ||
216 | struct i82975x_error_info { | |
217 | u16 errsts; | |
218 | u32 eap; | |
219 | u8 des; | |
220 | u8 derrsyn; | |
221 | u16 errsts2; | |
222 | u8 chan; /* the channel is bit 0 of EAP */ | |
223 | u8 xeap; /* extended eap bit */ | |
224 | }; | |
225 | ||
226 | static const struct i82975x_dev_info i82975x_devs[] = { | |
227 | [I82975X] = { | |
228 | .ctl_name = "i82975x" | |
229 | }, | |
230 | }; | |
231 | ||
232 | static struct pci_dev *mci_pdev; /* init dev: in case that AGP code has | |
233 | * already registered driver | |
234 | */ | |
235 | ||
236 | static int i82975x_registered = 1; | |
237 | ||
238 | static void i82975x_get_error_info(struct mem_ctl_info *mci, | |
239 | struct i82975x_error_info *info) | |
240 | { | |
241 | struct pci_dev *pdev; | |
242 | ||
243 | pdev = to_pci_dev(mci->dev); | |
244 | ||
245 | /* | |
246 | * This is a mess because there is no atomic way to read all the | |
247 | * registers at once and the registers can transition from CE being | |
248 | * overwritten by UE. | |
249 | */ | |
250 | pci_read_config_word(pdev, I82975X_ERRSTS, &info->errsts); | |
251 | pci_read_config_dword(pdev, I82975X_EAP, &info->eap); | |
252 | pci_read_config_byte(pdev, I82975X_XEAP, &info->xeap); | |
253 | pci_read_config_byte(pdev, I82975X_DES, &info->des); | |
254 | pci_read_config_byte(pdev, I82975X_DERRSYN, &info->derrsyn); | |
255 | pci_read_config_word(pdev, I82975X_ERRSTS, &info->errsts2); | |
256 | ||
257 | pci_write_bits16(pdev, I82975X_ERRSTS, 0x0003, 0x0003); | |
258 | ||
259 | /* | |
260 | * If the error is the same then we can for both reads then | |
261 | * the first set of reads is valid. If there is a change then | |
262 | * there is a CE no info and the second set of reads is valid | |
263 | * and should be UE info. | |
264 | */ | |
265 | if (!(info->errsts2 & 0x0003)) | |
266 | return; | |
267 | ||
268 | if ((info->errsts ^ info->errsts2) & 0x0003) { | |
269 | pci_read_config_dword(pdev, I82975X_EAP, &info->eap); | |
270 | pci_read_config_byte(pdev, I82975X_XEAP, &info->xeap); | |
271 | pci_read_config_byte(pdev, I82975X_DES, &info->des); | |
272 | pci_read_config_byte(pdev, I82975X_DERRSYN, | |
273 | &info->derrsyn); | |
274 | } | |
275 | } | |
276 | ||
277 | static int i82975x_process_error_info(struct mem_ctl_info *mci, | |
278 | struct i82975x_error_info *info, int handle_errors) | |
279 | { | |
6099e419 | 280 | int row, chan; |
cb60a422 | 281 | unsigned long offst, page; |
420390f0 | 282 | |
420390f0 RD |
283 | if (!(info->errsts2 & 0x0003)) |
284 | return 0; | |
285 | ||
286 | if (!handle_errors) | |
287 | return 1; | |
288 | ||
289 | if ((info->errsts ^ info->errsts2) & 0x0003) { | |
290 | edac_mc_handle_ce_no_info(mci, "UE overwrote CE"); | |
291 | info->errsts = info->errsts2; | |
292 | } | |
293 | ||
cb60a422 | 294 | page = (unsigned long) info->eap; |
cb60a422 | 295 | page >>= 1; |
6099e419 A |
296 | if (info->xeap & 1) |
297 | page |= 0x80000000; | |
298 | page >>= (PAGE_SHIFT - 1); | |
cb60a422 | 299 | row = edac_mc_find_csrow_by_page(mci, page); |
420390f0 | 300 | |
6099e419 A |
301 | if (row == -1) { |
302 | i82975x_mc_printk(mci, KERN_ERR, "error processing EAP:\n" | |
303 | "\tXEAP=%u\n" | |
304 | "\t EAP=0x%08x\n" | |
305 | "\tPAGE=0x%08x\n", | |
306 | (info->xeap & 1) ? 1 : 0, info->eap, (unsigned int) page); | |
307 | return 0; | |
308 | } | |
309 | chan = (mci->csrows[row].nr_channels == 1) ? 0 : info->eap & 1; | |
310 | offst = info->eap | |
311 | & ((1 << PAGE_SHIFT) - | |
084a4fcc | 312 | (1 << mci->csrows[row].channels[chan].dimm->grain)); |
6099e419 | 313 | |
420390f0 | 314 | if (info->errsts & 0x0002) |
cb60a422 | 315 | edac_mc_handle_ue(mci, page, offst , row, "i82975x UE"); |
420390f0 | 316 | else |
cb60a422 | 317 | edac_mc_handle_ce(mci, page, offst, info->derrsyn, row, |
6099e419 | 318 | chan, "i82975x CE"); |
420390f0 RD |
319 | |
320 | return 1; | |
321 | } | |
322 | ||
323 | static void i82975x_check(struct mem_ctl_info *mci) | |
324 | { | |
325 | struct i82975x_error_info info; | |
326 | ||
327 | debugf1("MC%d: %s()\n", mci->mc_idx, __func__); | |
328 | i82975x_get_error_info(mci, &info); | |
329 | i82975x_process_error_info(mci, &info, 1); | |
330 | } | |
331 | ||
332 | /* Return 1 if dual channel mode is active. Else return 0. */ | |
333 | static int dual_channel_active(void __iomem *mch_window) | |
334 | { | |
335 | /* | |
336 | * We treat interleaved-symmetric configuration as dual-channel - EAP's | |
337 | * bit-0 giving the channel of the error location. | |
338 | * | |
339 | * All other configurations are treated as single channel - the EAP's | |
340 | * bit-0 will resolve ok in symmetric area of mixed | |
341 | * (symmetric/asymmetric) configurations | |
342 | */ | |
343 | u8 drb[4][2]; | |
344 | int row; | |
345 | int dualch; | |
346 | ||
347 | for (dualch = 1, row = 0; dualch && (row < 4); row++) { | |
348 | drb[row][0] = readb(mch_window + I82975X_DRB + row); | |
349 | drb[row][1] = readb(mch_window + I82975X_DRB + row + 0x80); | |
350 | dualch = dualch && (drb[row][0] == drb[row][1]); | |
351 | } | |
352 | return dualch; | |
353 | } | |
354 | ||
355 | static enum dev_type i82975x_dram_type(void __iomem *mch_window, int rank) | |
356 | { | |
357 | /* | |
7ba99575 | 358 | * ECC is possible on i92975x ONLY with DEV_X8 |
420390f0 RD |
359 | */ |
360 | return DEV_X8; | |
361 | } | |
362 | ||
363 | static void i82975x_init_csrows(struct mem_ctl_info *mci, | |
364 | struct pci_dev *pdev, void __iomem *mch_window) | |
365 | { | |
cb60a422 A |
366 | static const char *labels[4] = { |
367 | "DIMM A1", "DIMM A2", | |
368 | "DIMM B1", "DIMM B2" | |
369 | }; | |
420390f0 RD |
370 | struct csrow_info *csrow; |
371 | unsigned long last_cumul_size; | |
372 | u8 value; | |
a895bf8b | 373 | u32 cumul_size, nr_pages; |
cb60a422 | 374 | int index, chan; |
084a4fcc MCC |
375 | struct dimm_info *dimm; |
376 | enum dev_type dtype; | |
420390f0 RD |
377 | |
378 | last_cumul_size = 0; | |
379 | ||
380 | /* | |
381 | * 82875 comment: | |
382 | * The dram row boundary (DRB) reg values are boundary address | |
383 | * for each DRAM row with a granularity of 32 or 64MB (single/dual | |
384 | * channel operation). DRB regs are cumulative; therefore DRB7 will | |
cb60a422 | 385 | * contain the total memory contained in all rows. |
420390f0 RD |
386 | * |
387 | */ | |
388 | ||
389 | for (index = 0; index < mci->nr_csrows; index++) { | |
390 | csrow = &mci->csrows[index]; | |
391 | ||
392 | value = readb(mch_window + I82975X_DRB + index + | |
393 | ((index >= 4) ? 0x80 : 0)); | |
394 | cumul_size = value; | |
395 | cumul_size <<= (I82975X_DRB_SHIFT - PAGE_SHIFT); | |
cb60a422 A |
396 | /* |
397 | * Adjust cumul_size w.r.t number of channels | |
398 | * | |
399 | */ | |
400 | if (csrow->nr_channels > 1) | |
401 | cumul_size <<= 1; | |
420390f0 RD |
402 | debugf3("%s(): (%d) cumul_size 0x%x\n", __func__, index, |
403 | cumul_size); | |
cb60a422 | 404 | |
a895bf8b | 405 | nr_pages = cumul_size - last_cumul_size; |
cb60a422 A |
406 | /* |
407 | * Initialise dram labels | |
408 | * index values: | |
409 | * [0-7] for single-channel; i.e. csrow->nr_channels = 1 | |
410 | * [0-3] for dual-channel; i.e. csrow->nr_channels = 2 | |
411 | */ | |
084a4fcc MCC |
412 | dtype = i82975x_dram_type(mch_window, index); |
413 | for (chan = 0; chan < csrow->nr_channels; chan++) { | |
414 | dimm = mci->csrows[index].channels[chan].dimm; | |
a895bf8b MCC |
415 | |
416 | if (!nr_pages) | |
417 | continue; | |
418 | ||
419 | dimm->nr_pages = nr_pages / csrow->nr_channels; | |
a7d7d2e1 | 420 | strncpy(csrow->channels[chan].dimm->label, |
cb60a422 A |
421 | labels[(index >> 1) + (chan * 2)], |
422 | EDAC_MC_LABEL_LEN); | |
084a4fcc MCC |
423 | dimm->grain = 1 << 7; /* 128Byte cache-line resolution */ |
424 | dimm->dtype = i82975x_dram_type(mch_window, index); | |
425 | dimm->mtype = MEM_DDR2; /* I82975x supports only DDR2 */ | |
426 | dimm->edac_mode = EDAC_SECDED; /* only supported */ | |
427 | } | |
cb60a422 | 428 | |
a895bf8b | 429 | if (!nr_pages) |
420390f0 RD |
430 | continue; /* not populated */ |
431 | ||
432 | csrow->first_page = last_cumul_size; | |
433 | csrow->last_page = cumul_size - 1; | |
420390f0 | 434 | last_cumul_size = cumul_size; |
420390f0 RD |
435 | } |
436 | } | |
437 | ||
438 | /* #define i82975x_DEBUG_IOMEM */ | |
439 | ||
440 | #ifdef i82975x_DEBUG_IOMEM | |
441 | static void i82975x_print_dram_timings(void __iomem *mch_window) | |
442 | { | |
443 | /* | |
444 | * The register meanings are from Intel specs; | |
445 | * (shows 13-5-5-5 for 800-DDR2) | |
446 | * Asus P5W Bios reports 15-5-4-4 | |
447 | * What's your religion? | |
448 | */ | |
449 | static const int caslats[4] = { 5, 4, 3, 6 }; | |
450 | u32 dtreg[2]; | |
451 | ||
452 | dtreg[0] = readl(mch_window + 0x114); | |
453 | dtreg[1] = readl(mch_window + 0x194); | |
454 | i82975x_printk(KERN_INFO, "DRAM Timings : Ch0 Ch1\n" | |
455 | " RAS Active Min = %d %d\n" | |
456 | " CAS latency = %d %d\n" | |
457 | " RAS to CAS = %d %d\n" | |
458 | " RAS precharge = %d %d\n", | |
459 | (dtreg[0] >> 19 ) & 0x0f, | |
460 | (dtreg[1] >> 19) & 0x0f, | |
461 | caslats[(dtreg[0] >> 8) & 0x03], | |
462 | caslats[(dtreg[1] >> 8) & 0x03], | |
463 | ((dtreg[0] >> 4) & 0x07) + 2, | |
464 | ((dtreg[1] >> 4) & 0x07) + 2, | |
465 | (dtreg[0] & 0x07) + 2, | |
466 | (dtreg[1] & 0x07) + 2 | |
467 | ); | |
468 | ||
469 | } | |
470 | #endif | |
471 | ||
472 | static int i82975x_probe1(struct pci_dev *pdev, int dev_idx) | |
473 | { | |
474 | int rc = -ENODEV; | |
475 | struct mem_ctl_info *mci; | |
476 | struct i82975x_pvt *pvt; | |
477 | void __iomem *mch_window; | |
478 | u32 mchbar; | |
479 | u32 drc[2]; | |
480 | struct i82975x_error_info discard; | |
481 | int chans; | |
482 | #ifdef i82975x_DEBUG_IOMEM | |
483 | u8 c0drb[4]; | |
484 | u8 c1drb[4]; | |
485 | #endif | |
486 | ||
487 | debugf0("%s()\n", __func__); | |
488 | ||
489 | pci_read_config_dword(pdev, I82975X_MCHBAR, &mchbar); | |
490 | if (!(mchbar & 1)) { | |
491 | debugf3("%s(): failed, MCHBAR disabled!\n", __func__); | |
492 | goto fail0; | |
493 | } | |
494 | mchbar &= 0xffffc000; /* bits 31:14 used for 16K window */ | |
495 | mch_window = ioremap_nocache(mchbar, 0x1000); | |
496 | ||
497 | #ifdef i82975x_DEBUG_IOMEM | |
498 | i82975x_printk(KERN_INFO, "MCHBAR real = %0x, remapped = %p\n", | |
499 | mchbar, mch_window); | |
500 | ||
501 | c0drb[0] = readb(mch_window + I82975X_DRB_CH0R0); | |
502 | c0drb[1] = readb(mch_window + I82975X_DRB_CH0R1); | |
503 | c0drb[2] = readb(mch_window + I82975X_DRB_CH0R2); | |
504 | c0drb[3] = readb(mch_window + I82975X_DRB_CH0R3); | |
505 | c1drb[0] = readb(mch_window + I82975X_DRB_CH1R0); | |
506 | c1drb[1] = readb(mch_window + I82975X_DRB_CH1R1); | |
507 | c1drb[2] = readb(mch_window + I82975X_DRB_CH1R2); | |
508 | c1drb[3] = readb(mch_window + I82975X_DRB_CH1R3); | |
509 | i82975x_printk(KERN_INFO, "DRBCH0R0 = 0x%02x\n", c0drb[0]); | |
510 | i82975x_printk(KERN_INFO, "DRBCH0R1 = 0x%02x\n", c0drb[1]); | |
511 | i82975x_printk(KERN_INFO, "DRBCH0R2 = 0x%02x\n", c0drb[2]); | |
512 | i82975x_printk(KERN_INFO, "DRBCH0R3 = 0x%02x\n", c0drb[3]); | |
513 | i82975x_printk(KERN_INFO, "DRBCH1R0 = 0x%02x\n", c1drb[0]); | |
514 | i82975x_printk(KERN_INFO, "DRBCH1R1 = 0x%02x\n", c1drb[1]); | |
515 | i82975x_printk(KERN_INFO, "DRBCH1R2 = 0x%02x\n", c1drb[2]); | |
516 | i82975x_printk(KERN_INFO, "DRBCH1R3 = 0x%02x\n", c1drb[3]); | |
517 | #endif | |
518 | ||
519 | drc[0] = readl(mch_window + I82975X_DRC_CH0M0); | |
520 | drc[1] = readl(mch_window + I82975X_DRC_CH1M0); | |
521 | #ifdef i82975x_DEBUG_IOMEM | |
522 | i82975x_printk(KERN_INFO, "DRC_CH0 = %0x, %s\n", drc[0], | |
523 | ((drc[0] >> 21) & 3) == 1 ? | |
524 | "ECC enabled" : "ECC disabled"); | |
525 | i82975x_printk(KERN_INFO, "DRC_CH1 = %0x, %s\n", drc[1], | |
526 | ((drc[1] >> 21) & 3) == 1 ? | |
527 | "ECC enabled" : "ECC disabled"); | |
528 | ||
529 | i82975x_printk(KERN_INFO, "C0 BNKARC = %0x\n", | |
530 | readw(mch_window + I82975X_C0BNKARC)); | |
531 | i82975x_printk(KERN_INFO, "C1 BNKARC = %0x\n", | |
532 | readw(mch_window + I82975X_C1BNKARC)); | |
533 | i82975x_print_dram_timings(mch_window); | |
534 | goto fail1; | |
535 | #endif | |
536 | if (!(((drc[0] >> 21) & 3) == 1 || ((drc[1] >> 21) & 3) == 1)) { | |
537 | i82975x_printk(KERN_INFO, "ECC disabled on both channels.\n"); | |
538 | goto fail1; | |
539 | } | |
540 | ||
541 | chans = dual_channel_active(mch_window) + 1; | |
542 | ||
543 | /* assuming only one controller, index thus is 0 */ | |
544 | mci = edac_mc_alloc(sizeof(*pvt), I82975X_NR_CSROWS(chans), | |
545 | chans, 0); | |
546 | if (!mci) { | |
547 | rc = -ENOMEM; | |
548 | goto fail1; | |
549 | } | |
550 | ||
551 | debugf3("%s(): init mci\n", __func__); | |
552 | mci->dev = &pdev->dev; | |
da95b3d2 | 553 | mci->mtype_cap = MEM_FLAG_DDR2; |
420390f0 RD |
554 | mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED; |
555 | mci->edac_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED; | |
556 | mci->mod_name = EDAC_MOD_STR; | |
557 | mci->mod_ver = I82975X_REVISION; | |
558 | mci->ctl_name = i82975x_devs[dev_idx].ctl_name; | |
da95b3d2 | 559 | mci->dev_name = pci_name(pdev); |
420390f0 RD |
560 | mci->edac_check = i82975x_check; |
561 | mci->ctl_page_to_phys = NULL; | |
562 | debugf3("%s(): init pvt\n", __func__); | |
563 | pvt = (struct i82975x_pvt *) mci->pvt_info; | |
564 | pvt->mch_window = mch_window; | |
565 | i82975x_init_csrows(mci, pdev, mch_window); | |
da95b3d2 | 566 | mci->scrub_mode = SCRUB_HW_SRC; |
420390f0 RD |
567 | i82975x_get_error_info(mci, &discard); /* clear counters */ |
568 | ||
569 | /* finalize this instance of memory controller with edac core */ | |
570 | if (edac_mc_add_mc(mci)) { | |
571 | debugf3("%s(): failed edac_mc_add_mc()\n", __func__); | |
572 | goto fail2; | |
573 | } | |
574 | ||
575 | /* get this far and it's successful */ | |
576 | debugf3("%s(): success\n", __func__); | |
577 | return 0; | |
578 | ||
579 | fail2: | |
580 | edac_mc_free(mci); | |
581 | ||
582 | fail1: | |
583 | iounmap(mch_window); | |
584 | fail0: | |
585 | return rc; | |
586 | } | |
587 | ||
588 | /* returns count (>= 0), or negative on error */ | |
589 | static int __devinit i82975x_init_one(struct pci_dev *pdev, | |
590 | const struct pci_device_id *ent) | |
591 | { | |
592 | int rc; | |
593 | ||
594 | debugf0("%s()\n", __func__); | |
595 | ||
596 | if (pci_enable_device(pdev) < 0) | |
597 | return -EIO; | |
598 | ||
599 | rc = i82975x_probe1(pdev, ent->driver_data); | |
600 | ||
601 | if (mci_pdev == NULL) | |
602 | mci_pdev = pci_dev_get(pdev); | |
603 | ||
604 | return rc; | |
605 | } | |
606 | ||
607 | static void __devexit i82975x_remove_one(struct pci_dev *pdev) | |
608 | { | |
609 | struct mem_ctl_info *mci; | |
610 | struct i82975x_pvt *pvt; | |
611 | ||
612 | debugf0("%s()\n", __func__); | |
613 | ||
614 | mci = edac_mc_del_mc(&pdev->dev); | |
615 | if (mci == NULL) | |
616 | return; | |
617 | ||
618 | pvt = mci->pvt_info; | |
619 | if (pvt->mch_window) | |
620 | iounmap( pvt->mch_window ); | |
621 | ||
622 | edac_mc_free(mci); | |
623 | } | |
624 | ||
36c46f31 | 625 | static DEFINE_PCI_DEVICE_TABLE(i82975x_pci_tbl) = { |
420390f0 RD |
626 | { |
627 | PCI_VEND_DEV(INTEL, 82975_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
628 | I82975X | |
629 | }, | |
630 | { | |
631 | 0, | |
632 | } /* 0 terminated list. */ | |
633 | }; | |
634 | ||
635 | MODULE_DEVICE_TABLE(pci, i82975x_pci_tbl); | |
636 | ||
637 | static struct pci_driver i82975x_driver = { | |
638 | .name = EDAC_MOD_STR, | |
639 | .probe = i82975x_init_one, | |
640 | .remove = __devexit_p(i82975x_remove_one), | |
641 | .id_table = i82975x_pci_tbl, | |
642 | }; | |
643 | ||
644 | static int __init i82975x_init(void) | |
645 | { | |
646 | int pci_rc; | |
647 | ||
648 | debugf3("%s()\n", __func__); | |
649 | ||
c3c52bce HM |
650 | /* Ensure that the OPSTATE is set correctly for POLL or NMI */ |
651 | opstate_init(); | |
652 | ||
420390f0 RD |
653 | pci_rc = pci_register_driver(&i82975x_driver); |
654 | if (pci_rc < 0) | |
655 | goto fail0; | |
656 | ||
657 | if (mci_pdev == NULL) { | |
658 | mci_pdev = pci_get_device(PCI_VENDOR_ID_INTEL, | |
659 | PCI_DEVICE_ID_INTEL_82975_0, NULL); | |
660 | ||
661 | if (!mci_pdev) { | |
662 | debugf0("i82975x pci_get_device fail\n"); | |
663 | pci_rc = -ENODEV; | |
664 | goto fail1; | |
665 | } | |
666 | ||
667 | pci_rc = i82975x_init_one(mci_pdev, i82975x_pci_tbl); | |
668 | ||
669 | if (pci_rc < 0) { | |
670 | debugf0("i82975x init fail\n"); | |
671 | pci_rc = -ENODEV; | |
672 | goto fail1; | |
673 | } | |
674 | } | |
675 | ||
676 | return 0; | |
677 | ||
678 | fail1: | |
679 | pci_unregister_driver(&i82975x_driver); | |
680 | ||
681 | fail0: | |
682 | if (mci_pdev != NULL) | |
683 | pci_dev_put(mci_pdev); | |
684 | ||
685 | return pci_rc; | |
686 | } | |
687 | ||
688 | static void __exit i82975x_exit(void) | |
689 | { | |
690 | debugf3("%s()\n", __func__); | |
691 | ||
692 | pci_unregister_driver(&i82975x_driver); | |
693 | ||
694 | if (!i82975x_registered) { | |
695 | i82975x_remove_one(mci_pdev); | |
696 | pci_dev_put(mci_pdev); | |
697 | } | |
698 | } | |
699 | ||
700 | module_init(i82975x_init); | |
701 | module_exit(i82975x_exit); | |
702 | ||
703 | MODULE_LICENSE("GPL"); | |
25527885 | 704 | MODULE_AUTHOR("Arvind R. <arvino55@gmail.com>"); |
420390f0 | 705 | MODULE_DESCRIPTION("MC support for Intel 82975 memory hub controllers"); |
c3c52bce HM |
706 | |
707 | module_param(edac_op_state, int, 0444); | |
708 | MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI"); |