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Commit | Line | Data |
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9cdeb404 | 1 | /* |
fd19fcd6 BP |
2 | * A simple MCE injection facility for testing different aspects of the RAS |
3 | * code. This driver should be built as module so that it can be loaded | |
4 | * on production kernels for testing purposes. | |
9cdeb404 BP |
5 | * |
6 | * This file may be distributed under the terms of the GNU General Public | |
7 | * License version 2. | |
8 | * | |
fd19fcd6 | 9 | * Copyright (c) 2010-14: Borislav Petkov <bp@alien8.de> |
9cdeb404 BP |
10 | * Advanced Micro Devices Inc. |
11 | */ | |
12 | ||
13 | #include <linux/kobject.h> | |
fd19fcd6 | 14 | #include <linux/debugfs.h> |
51990e82 | 15 | #include <linux/device.h> |
80a2e2e3 | 16 | #include <linux/module.h> |
51756a50 | 17 | #include <linux/cpu.h> |
0451d14d AG |
18 | #include <linux/string.h> |
19 | #include <linux/uaccess.h> | |
9cdeb404 BP |
20 | #include <asm/mce.h> |
21 | ||
47ca08a4 | 22 | #include "mce_amd.h" |
9cdeb404 | 23 | |
9cdeb404 BP |
24 | /* |
25 | * Collect all the MCi_XXX settings | |
26 | */ | |
27 | static struct mce i_mce; | |
fd19fcd6 | 28 | static struct dentry *dfs_inj; |
9cdeb404 | 29 | |
685d46d7 AG |
30 | static u8 n_banks; |
31 | ||
0451d14d AG |
32 | #define MAX_FLAG_OPT_SIZE 3 |
33 | ||
34 | enum injection_type { | |
35 | SW_INJ = 0, /* SW injection, simply decode the error */ | |
36 | HW_INJ, /* Trigger a #MC */ | |
37 | N_INJ_TYPES, | |
38 | }; | |
39 | ||
40 | static const char * const flags_options[] = { | |
41 | [SW_INJ] = "sw", | |
42 | [HW_INJ] = "hw", | |
43 | NULL | |
44 | }; | |
45 | ||
46 | /* Set default injection to SW_INJ */ | |
de277678 | 47 | static enum injection_type inj_type = SW_INJ; |
0451d14d | 48 | |
fd19fcd6 BP |
49 | #define MCE_INJECT_SET(reg) \ |
50 | static int inj_##reg##_set(void *data, u64 val) \ | |
9cdeb404 | 51 | { \ |
fd19fcd6 | 52 | struct mce *m = (struct mce *)data; \ |
9cdeb404 | 53 | \ |
fd19fcd6 BP |
54 | m->reg = val; \ |
55 | return 0; \ | |
9cdeb404 BP |
56 | } |
57 | ||
fd19fcd6 BP |
58 | MCE_INJECT_SET(status); |
59 | MCE_INJECT_SET(misc); | |
60 | MCE_INJECT_SET(addr); | |
9cdeb404 | 61 | |
fd19fcd6 BP |
62 | #define MCE_INJECT_GET(reg) \ |
63 | static int inj_##reg##_get(void *data, u64 *val) \ | |
9cdeb404 | 64 | { \ |
fd19fcd6 BP |
65 | struct mce *m = (struct mce *)data; \ |
66 | \ | |
67 | *val = m->reg; \ | |
68 | return 0; \ | |
9cdeb404 BP |
69 | } |
70 | ||
fd19fcd6 BP |
71 | MCE_INJECT_GET(status); |
72 | MCE_INJECT_GET(misc); | |
73 | MCE_INJECT_GET(addr); | |
9cdeb404 | 74 | |
fd19fcd6 BP |
75 | DEFINE_SIMPLE_ATTRIBUTE(status_fops, inj_status_get, inj_status_set, "%llx\n"); |
76 | DEFINE_SIMPLE_ATTRIBUTE(misc_fops, inj_misc_get, inj_misc_set, "%llx\n"); | |
77 | DEFINE_SIMPLE_ATTRIBUTE(addr_fops, inj_addr_get, inj_addr_set, "%llx\n"); | |
9cdeb404 | 78 | |
21690934 BP |
79 | /* |
80 | * Caller needs to be make sure this cpu doesn't disappear | |
81 | * from under us, i.e.: get_cpu/put_cpu. | |
82 | */ | |
83 | static int toggle_hw_mce_inject(unsigned int cpu, bool enable) | |
84 | { | |
85 | u32 l, h; | |
86 | int err; | |
87 | ||
88 | err = rdmsr_on_cpu(cpu, MSR_K7_HWCR, &l, &h); | |
89 | if (err) { | |
90 | pr_err("%s: error reading HWCR\n", __func__); | |
91 | return err; | |
92 | } | |
93 | ||
94 | enable ? (l |= BIT(18)) : (l &= ~BIT(18)); | |
95 | ||
96 | err = wrmsr_on_cpu(cpu, MSR_K7_HWCR, l, h); | |
97 | if (err) | |
98 | pr_err("%s: error writing HWCR\n", __func__); | |
99 | ||
100 | return err; | |
101 | } | |
102 | ||
0451d14d | 103 | static int __set_inj(const char *buf) |
b18f3864 | 104 | { |
0451d14d AG |
105 | int i; |
106 | ||
107 | for (i = 0; i < N_INJ_TYPES; i++) { | |
108 | if (!strncmp(flags_options[i], buf, strlen(flags_options[i]))) { | |
109 | inj_type = i; | |
110 | return 0; | |
111 | } | |
112 | } | |
113 | return -EINVAL; | |
114 | } | |
115 | ||
116 | static ssize_t flags_read(struct file *filp, char __user *ubuf, | |
117 | size_t cnt, loff_t *ppos) | |
118 | { | |
119 | char buf[MAX_FLAG_OPT_SIZE]; | |
120 | int n; | |
b18f3864 | 121 | |
0451d14d | 122 | n = sprintf(buf, "%s\n", flags_options[inj_type]); |
b18f3864 | 123 | |
0451d14d | 124 | return simple_read_from_buffer(ubuf, cnt, ppos, buf, n); |
b18f3864 BP |
125 | } |
126 | ||
0451d14d AG |
127 | static ssize_t flags_write(struct file *filp, const char __user *ubuf, |
128 | size_t cnt, loff_t *ppos) | |
b18f3864 | 129 | { |
0451d14d AG |
130 | char buf[MAX_FLAG_OPT_SIZE], *__buf; |
131 | int err; | |
132 | size_t ret; | |
b18f3864 | 133 | |
0451d14d AG |
134 | if (cnt > MAX_FLAG_OPT_SIZE) |
135 | cnt = MAX_FLAG_OPT_SIZE; | |
136 | ||
137 | ret = cnt; | |
138 | ||
139 | if (copy_from_user(&buf, ubuf, cnt)) | |
140 | return -EFAULT; | |
141 | ||
142 | buf[cnt - 1] = 0; | |
143 | ||
144 | /* strip whitespace */ | |
145 | __buf = strstrip(buf); | |
146 | ||
147 | err = __set_inj(__buf); | |
148 | if (err) { | |
149 | pr_err("%s: Invalid flags value: %s\n", __func__, __buf); | |
150 | return err; | |
151 | } | |
152 | ||
153 | *ppos += ret; | |
154 | ||
155 | return ret; | |
b18f3864 BP |
156 | } |
157 | ||
0451d14d AG |
158 | static const struct file_operations flags_fops = { |
159 | .read = flags_read, | |
160 | .write = flags_write, | |
161 | .llseek = generic_file_llseek, | |
162 | }; | |
b18f3864 BP |
163 | |
164 | /* | |
165 | * On which CPU to inject? | |
166 | */ | |
167 | MCE_INJECT_GET(extcpu); | |
168 | ||
169 | static int inj_extcpu_set(void *data, u64 val) | |
170 | { | |
171 | struct mce *m = (struct mce *)data; | |
172 | ||
173 | if (val >= nr_cpu_ids || !cpu_online(val)) { | |
174 | pr_err("%s: Invalid CPU: %llu\n", __func__, val); | |
175 | return -EINVAL; | |
176 | } | |
177 | m->extcpu = val; | |
178 | return 0; | |
179 | } | |
180 | ||
181 | DEFINE_SIMPLE_ATTRIBUTE(extcpu_fops, inj_extcpu_get, inj_extcpu_set, "%llu\n"); | |
182 | ||
51756a50 BP |
183 | static void trigger_mce(void *info) |
184 | { | |
185 | asm volatile("int $18"); | |
186 | } | |
187 | ||
188 | static void do_inject(void) | |
189 | { | |
190 | u64 mcg_status = 0; | |
191 | unsigned int cpu = i_mce.extcpu; | |
192 | u8 b = i_mce.bank; | |
193 | ||
cda9459d BP |
194 | if (i_mce.misc) |
195 | i_mce.status |= MCI_STATUS_MISCV; | |
196 | ||
0451d14d | 197 | if (inj_type == SW_INJ) { |
51756a50 BP |
198 | amd_decode_mce(NULL, 0, &i_mce); |
199 | return; | |
200 | } | |
201 | ||
51756a50 BP |
202 | /* prep MCE global settings for the injection */ |
203 | mcg_status = MCG_STATUS_MCIP | MCG_STATUS_EIPV; | |
204 | ||
205 | if (!(i_mce.status & MCI_STATUS_PCC)) | |
206 | mcg_status |= MCG_STATUS_RIPV; | |
207 | ||
6d1e9bf5 BP |
208 | get_online_cpus(); |
209 | if (!cpu_online(cpu)) | |
210 | goto err; | |
211 | ||
51756a50 BP |
212 | toggle_hw_mce_inject(cpu, true); |
213 | ||
214 | wrmsr_on_cpu(cpu, MSR_IA32_MCG_STATUS, | |
215 | (u32)mcg_status, (u32)(mcg_status >> 32)); | |
216 | ||
217 | wrmsr_on_cpu(cpu, MSR_IA32_MCx_STATUS(b), | |
218 | (u32)i_mce.status, (u32)(i_mce.status >> 32)); | |
219 | ||
220 | wrmsr_on_cpu(cpu, MSR_IA32_MCx_ADDR(b), | |
221 | (u32)i_mce.addr, (u32)(i_mce.addr >> 32)); | |
222 | ||
223 | wrmsr_on_cpu(cpu, MSR_IA32_MCx_MISC(b), | |
224 | (u32)i_mce.misc, (u32)(i_mce.misc >> 32)); | |
225 | ||
226 | toggle_hw_mce_inject(cpu, false); | |
227 | ||
228 | smp_call_function_single(cpu, trigger_mce, NULL, 0); | |
229 | ||
230 | err: | |
231 | put_online_cpus(); | |
232 | ||
233 | } | |
234 | ||
9cdeb404 BP |
235 | /* |
236 | * This denotes into which bank we're injecting and triggers | |
237 | * the injection, at the same time. | |
238 | */ | |
fd19fcd6 | 239 | static int inj_bank_set(void *data, u64 val) |
9cdeb404 | 240 | { |
fd19fcd6 | 241 | struct mce *m = (struct mce *)data; |
9cdeb404 | 242 | |
685d46d7 AG |
243 | if (val >= n_banks) { |
244 | pr_err("Non-existent MCE bank: %llu\n", val); | |
245 | return -EINVAL; | |
fd19fcd6 | 246 | } |
9cdeb404 | 247 | |
fd19fcd6 | 248 | m->bank = val; |
51756a50 | 249 | do_inject(); |
9cdeb404 | 250 | |
fd19fcd6 | 251 | return 0; |
9cdeb404 BP |
252 | } |
253 | ||
e7f2ea1d | 254 | MCE_INJECT_GET(bank); |
9cdeb404 | 255 | |
fd19fcd6 BP |
256 | DEFINE_SIMPLE_ATTRIBUTE(bank_fops, inj_bank_get, inj_bank_set, "%llu\n"); |
257 | ||
99e21fea | 258 | static const char readme_msg[] = |
f2f3dca1 BP |
259 | "Description of the files and their usages:\n" |
260 | "\n" | |
261 | "Note1: i refers to the bank number below.\n" | |
262 | "Note2: See respective BKDGs for the exact bit definitions of the files below\n" | |
263 | "as they mirror the hardware registers.\n" | |
264 | "\n" | |
265 | "status:\t Set MCi_STATUS: the bits in that MSR control the error type and\n" | |
266 | "\t attributes of the error which caused the MCE.\n" | |
267 | "\n" | |
268 | "misc:\t Set MCi_MISC: provide auxiliary info about the error. It is mostly\n" | |
269 | "\t used for error thresholding purposes and its validity is indicated by\n" | |
270 | "\t MCi_STATUS[MiscV].\n" | |
271 | "\n" | |
272 | "addr:\t Error address value to be written to MCi_ADDR. Log address information\n" | |
273 | "\t associated with the error.\n" | |
274 | "\n" | |
275 | "cpu:\t The CPU to inject the error on.\n" | |
276 | "\n" | |
277 | "bank:\t Specify the bank you want to inject the error into: the number of\n" | |
278 | "\t banks in a processor varies and is family/model-specific, therefore, the\n" | |
279 | "\t supplied value is sanity-checked. Setting the bank value also triggers the\n" | |
280 | "\t injection.\n" | |
281 | "\n" | |
282 | "flags:\t Injection type to be performed. Writing to this file will trigger a\n" | |
283 | "\t real machine check, an APIC interrupt or invoke the error decoder routines\n" | |
284 | "\t for AMD processors.\n" | |
285 | "\n" | |
286 | "\t Allowed error injection types:\n" | |
287 | "\t - \"sw\": Software error injection. Decode error to a human-readable \n" | |
288 | "\t format only. Safe to use.\n" | |
289 | "\t - \"hw\": Hardware error injection. Causes the #MC exception handler to \n" | |
290 | "\t handle the error. Be warned: might cause system panic if MCi_STATUS[PCC] \n" | |
291 | "\t is set. Therefore, consider setting (debugfs_mountpoint)/mce/fake_panic \n" | |
292 | "\t before injecting.\n" | |
293 | "\n"; | |
99e21fea AG |
294 | |
295 | static ssize_t | |
296 | inj_readme_read(struct file *filp, char __user *ubuf, | |
297 | size_t cnt, loff_t *ppos) | |
298 | { | |
299 | return simple_read_from_buffer(ubuf, cnt, ppos, | |
300 | readme_msg, strlen(readme_msg)); | |
301 | } | |
302 | ||
303 | static const struct file_operations readme_fops = { | |
304 | .read = inj_readme_read, | |
305 | }; | |
306 | ||
8c2b117f | 307 | static struct dfs_node { |
fd19fcd6 BP |
308 | char *name; |
309 | struct dentry *d; | |
310 | const struct file_operations *fops; | |
4c6034e8 | 311 | umode_t perm; |
fd19fcd6 | 312 | } dfs_fls[] = { |
4c6034e8 AG |
313 | { .name = "status", .fops = &status_fops, .perm = S_IRUSR | S_IWUSR }, |
314 | { .name = "misc", .fops = &misc_fops, .perm = S_IRUSR | S_IWUSR }, | |
315 | { .name = "addr", .fops = &addr_fops, .perm = S_IRUSR | S_IWUSR }, | |
316 | { .name = "bank", .fops = &bank_fops, .perm = S_IRUSR | S_IWUSR }, | |
317 | { .name = "flags", .fops = &flags_fops, .perm = S_IRUSR | S_IWUSR }, | |
318 | { .name = "cpu", .fops = &extcpu_fops, .perm = S_IRUSR | S_IWUSR }, | |
99e21fea | 319 | { .name = "README", .fops = &readme_fops, .perm = S_IRUSR | S_IRGRP | S_IROTH }, |
9cdeb404 BP |
320 | }; |
321 | ||
fd19fcd6 | 322 | static int __init init_mce_inject(void) |
9cdeb404 | 323 | { |
fd19fcd6 | 324 | int i; |
685d46d7 AG |
325 | u64 cap; |
326 | ||
327 | rdmsrl(MSR_IA32_MCG_CAP, cap); | |
328 | n_banks = cap & MCG_BANKCNT_MASK; | |
9cdeb404 | 329 | |
fd19fcd6 BP |
330 | dfs_inj = debugfs_create_dir("mce-inject", NULL); |
331 | if (!dfs_inj) | |
9cdeb404 BP |
332 | return -EINVAL; |
333 | ||
fd19fcd6 BP |
334 | for (i = 0; i < ARRAY_SIZE(dfs_fls); i++) { |
335 | dfs_fls[i].d = debugfs_create_file(dfs_fls[i].name, | |
4c6034e8 | 336 | dfs_fls[i].perm, |
fd19fcd6 BP |
337 | dfs_inj, |
338 | &i_mce, | |
339 | dfs_fls[i].fops); | |
9cdeb404 | 340 | |
fd19fcd6 BP |
341 | if (!dfs_fls[i].d) |
342 | goto err_dfs_add; | |
9cdeb404 | 343 | } |
fd19fcd6 | 344 | |
9cdeb404 BP |
345 | return 0; |
346 | ||
fd19fcd6 | 347 | err_dfs_add: |
df4b2a30 | 348 | while (--i >= 0) |
fd19fcd6 | 349 | debugfs_remove(dfs_fls[i].d); |
9cdeb404 | 350 | |
fd19fcd6 BP |
351 | debugfs_remove(dfs_inj); |
352 | dfs_inj = NULL; | |
9cdeb404 | 353 | |
fd19fcd6 | 354 | return -ENOMEM; |
9cdeb404 BP |
355 | } |
356 | ||
fd19fcd6 | 357 | static void __exit exit_mce_inject(void) |
9cdeb404 BP |
358 | { |
359 | int i; | |
360 | ||
fd19fcd6 BP |
361 | for (i = 0; i < ARRAY_SIZE(dfs_fls); i++) |
362 | debugfs_remove(dfs_fls[i].d); | |
9cdeb404 | 363 | |
fd19fcd6 | 364 | memset(&dfs_fls, 0, sizeof(dfs_fls)); |
9cdeb404 | 365 | |
fd19fcd6 BP |
366 | debugfs_remove(dfs_inj); |
367 | dfs_inj = NULL; | |
9cdeb404 | 368 | } |
fd19fcd6 BP |
369 | module_init(init_mce_inject); |
370 | module_exit(exit_mce_inject); | |
9cdeb404 BP |
371 | |
372 | MODULE_LICENSE("GPL"); | |
43aff26c | 373 | MODULE_AUTHOR("Borislav Petkov <bp@alien8.de>"); |
9cdeb404 | 374 | MODULE_AUTHOR("AMD Inc."); |
fd19fcd6 | 375 | MODULE_DESCRIPTION("MCE injection facility for RAS testing"); |