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EDAC, mpc85xx: Drop setting/clearing RFXE bit in HID1
[mirror_ubuntu-artful-kernel.git] / drivers / edac / mpc85xx_edac.c
CommitLineData
a9a753d5 1/*
775c503f 2 * Freescale MPC85xx Memory Controller kernel module
a9a753d5 3 *
c92132f5
CL		 4 * Parts Copyrighted (c) 2013 by Freescale Semiconductor, Inc.
5 *
a9a753d5
DJ		 6 * Author: Dave Jiang <djiang@mvista.com>
7 *
8 * 2006-2007 (c) MontaVista Software, Inc. This file is licensed under
9 * the terms of the GNU General Public License version 2. This program
10 * is licensed "as is" without any warranty of any kind, whether express
11 * or implied.
12 *
13 */
14#include <linux/module.h>
15#include <linux/init.h>
a9a753d5
DJ		 16#include <linux/interrupt.h>
17#include <linux/ctype.h>
18#include <linux/io.h>
19#include <linux/mod_devicetable.h>
20#include <linux/edac.h>
60be7551 21#include <linux/smp.h>
5a0e3ad6 22#include <linux/gfp.h>
666db563 23#include <linux/fsl/edac.h>
a9a753d5
DJ		 24
25#include <linux/of_platform.h>
26#include <linux/of_device.h>
a9a753d5
DJ		 27#include "edac_module.h"
28#include "edac_core.h"
29#include "mpc85xx_edac.h"
30
31static int edac_dev_idx;
0616fb00 32#ifdef CONFIG_PCI
a9a753d5 33static int edac_pci_idx;
0616fb00 34#endif
a9a753d5
DJ		 35static int edac_mc_idx;
36
37static u32 orig_ddr_err_disable;
38static u32 orig_ddr_err_sbe;
39
40/*
41 * PCI Err defines
42 */
43#ifdef CONFIG_PCI
44static u32 orig_pci_err_cap_dr;
45static u32 orig_pci_err_en;
46#endif
47
48static u32 orig_l2_err_disable;
a9a753d5 49
a9a753d5
DJ		 50/************************ MC SYSFS parts ***********************************/
51
ba004239
MCC		 52#define to_mci(k) container_of(k, struct mem_ctl_info, dev)
53
54static ssize_t mpc85xx_mc_inject_data_hi_show(struct device *dev,
55 struct device_attribute *mattr,
a9a753d5
DJ		 56 char *data)
57{
ba004239 58 struct mem_ctl_info *mci = to_mci(dev);
a9a753d5
DJ		 59 struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
60 return sprintf(data, "0x%08x",
61 in_be32(pdata->mc_vbase +
62 MPC85XX_MC_DATA_ERR_INJECT_HI));
63}
64
ba004239
MCC		 65static ssize_t mpc85xx_mc_inject_data_lo_show(struct device *dev,
66 struct device_attribute *mattr,
a9a753d5
DJ		 67 char *data)
68{
ba004239 69 struct mem_ctl_info *mci = to_mci(dev);
a9a753d5
DJ		 70 struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
71 return sprintf(data, "0x%08x",
72 in_be32(pdata->mc_vbase +
73 MPC85XX_MC_DATA_ERR_INJECT_LO));
74}
75
ba004239
MCC		 76static ssize_t mpc85xx_mc_inject_ctrl_show(struct device *dev,
77 struct device_attribute *mattr,
78 char *data)
a9a753d5 79{
ba004239 80 struct mem_ctl_info *mci = to_mci(dev);
a9a753d5
DJ		 81 struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
82 return sprintf(data, "0x%08x",
83 in_be32(pdata->mc_vbase + MPC85XX_MC_ECC_ERR_INJECT));
84}
85
ba004239
MCC		 86static ssize_t mpc85xx_mc_inject_data_hi_store(struct device *dev,
87 struct device_attribute *mattr,
a9a753d5
DJ		 88 const char *data, size_t count)
89{
ba004239 90 struct mem_ctl_info *mci = to_mci(dev);
a9a753d5
DJ		 91 struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
92 if (isdigit(*data)) {
93 out_be32(pdata->mc_vbase + MPC85XX_MC_DATA_ERR_INJECT_HI,
94 simple_strtoul(data, NULL, 0));
95 return count;
96 }
97 return 0;
98}
99
ba004239
MCC		 100static ssize_t mpc85xx_mc_inject_data_lo_store(struct device *dev,
101 struct device_attribute *mattr,
a9a753d5
DJ		 102 const char *data, size_t count)
103{
ba004239 104 struct mem_ctl_info *mci = to_mci(dev);
a9a753d5
DJ		 105 struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
106 if (isdigit(*data)) {
107 out_be32(pdata->mc_vbase + MPC85XX_MC_DATA_ERR_INJECT_LO,
108 simple_strtoul(data, NULL, 0));
109 return count;
110 }
111 return 0;
112}
113
ba004239
MCC		 114static ssize_t mpc85xx_mc_inject_ctrl_store(struct device *dev,
115 struct device_attribute *mattr,
116 const char *data, size_t count)
a9a753d5 117{
ba004239 118 struct mem_ctl_info *mci = to_mci(dev);
a9a753d5
DJ		 119 struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
120 if (isdigit(*data)) {
121 out_be32(pdata->mc_vbase + MPC85XX_MC_ECC_ERR_INJECT,
122 simple_strtoul(data, NULL, 0));
123 return count;
124 }
125 return 0;
126}
127
ba004239
MCC		 128DEVICE_ATTR(inject_data_hi, S_IRUGO | S_IWUSR,
129 mpc85xx_mc_inject_data_hi_show, mpc85xx_mc_inject_data_hi_store);
130DEVICE_ATTR(inject_data_lo, S_IRUGO | S_IWUSR,
131 mpc85xx_mc_inject_data_lo_show, mpc85xx_mc_inject_data_lo_store);
132DEVICE_ATTR(inject_ctrl, S_IRUGO | S_IWUSR,
133 mpc85xx_mc_inject_ctrl_show, mpc85xx_mc_inject_ctrl_store);
a9a753d5 134
917c85b5
TI		 135static struct attribute *mpc85xx_dev_attrs[] = {
136 &dev_attr_inject_data_hi.attr,
137 &dev_attr_inject_data_lo.attr,
138 &dev_attr_inject_ctrl.attr,
139 NULL
140};
a9a753d5 141
917c85b5 142ATTRIBUTE_GROUPS(mpc85xx_dev);
a9a753d5
DJ		 143
144/**************************** PCI Err device ***************************/
145#ifdef CONFIG_PCI
146
147static void mpc85xx_pci_check(struct edac_pci_ctl_info *pci)
148{
149 struct mpc85xx_pci_pdata *pdata = pci->pvt_info;
150 u32 err_detect;
151
152 err_detect = in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR);
153
154 /* master aborts can happen during PCI config cycles */
155 if (!(err_detect & ~(PCI_EDE_MULTI_ERR | PCI_EDE_MST_ABRT))) {
156 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, err_detect);
157 return;
158 }
159
160 printk(KERN_ERR "PCI error(s) detected\n");
161 printk(KERN_ERR "PCI/X ERR_DR register: %#08x\n", err_detect);
162
163 printk(KERN_ERR "PCI/X ERR_ATTRIB register: %#08x\n",
164 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ATTRIB));
165 printk(KERN_ERR "PCI/X ERR_ADDR register: %#08x\n",
166 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ADDR));
167 printk(KERN_ERR "PCI/X ERR_EXT_ADDR register: %#08x\n",
168 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EXT_ADDR));
169 printk(KERN_ERR "PCI/X ERR_DL register: %#08x\n",
170 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DL));
171 printk(KERN_ERR "PCI/X ERR_DH register: %#08x\n",
172 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DH));
173
174 /* clear error bits */
175 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, err_detect);
176
177 if (err_detect & PCI_EDE_PERR_MASK)
178 edac_pci_handle_pe(pci, pci->ctl_name);
179
180 if ((err_detect & ~PCI_EDE_MULTI_ERR) & ~PCI_EDE_PERR_MASK)
181 edac_pci_handle_npe(pci, pci->ctl_name);
182}
183
c92132f5
CL		 184static void mpc85xx_pcie_check(struct edac_pci_ctl_info *pci)
185{
186 struct mpc85xx_pci_pdata *pdata = pci->pvt_info;
6fa06b0d 187 u32 err_detect, err_cap_stat;
c92132f5
CL		 188
189 err_detect = in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR);
6fa06b0d 190 err_cap_stat = in_be32(pdata->pci_vbase + MPC85XX_PCI_GAS_TIMR);
c92132f5
CL		 191
192 pr_err("PCIe error(s) detected\n");
193 pr_err("PCIe ERR_DR register: 0x%08x\n", err_detect);
6fa06b0d 194 pr_err("PCIe ERR_CAP_STAT register: 0x%08x\n", err_cap_stat);
c92132f5
CL		 195 pr_err("PCIe ERR_CAP_R0 register: 0x%08x\n",
196 in_be32(pdata->pci_vbase + MPC85XX_PCIE_ERR_CAP_R0));
197 pr_err("PCIe ERR_CAP_R1 register: 0x%08x\n",
198 in_be32(pdata->pci_vbase + MPC85XX_PCIE_ERR_CAP_R1));
199 pr_err("PCIe ERR_CAP_R2 register: 0x%08x\n",
200 in_be32(pdata->pci_vbase + MPC85XX_PCIE_ERR_CAP_R2));
201 pr_err("PCIe ERR_CAP_R3 register: 0x%08x\n",
202 in_be32(pdata->pci_vbase + MPC85XX_PCIE_ERR_CAP_R3));
203
204 /* clear error bits */
205 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, err_detect);
6fa06b0d
TH		 206
207 /* reset error capture */
208 out_be32(pdata->pci_vbase + MPC85XX_PCI_GAS_TIMR, err_cap_stat | 0x1);
c92132f5
CL		 209}
210
211static int mpc85xx_pcie_find_capability(struct device_node *np)
212{
213 struct pci_controller *hose;
214
215 if (!np)
216 return -EINVAL;
217
218 hose = pci_find_hose_for_OF_device(np);
219
220 return early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP);
221}
222
a9a753d5
DJ		 223static irqreturn_t mpc85xx_pci_isr(int irq, void *dev_id)
224{
225 struct edac_pci_ctl_info *pci = dev_id;
226 struct mpc85xx_pci_pdata *pdata = pci->pvt_info;
227 u32 err_detect;
228
229 err_detect = in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR);
230
231 if (!err_detect)
232 return IRQ_NONE;
233
c92132f5
CL		 234 if (pdata->is_pcie)
235 mpc85xx_pcie_check(pci);
236 else
237 mpc85xx_pci_check(pci);
a9a753d5
DJ		 238
239 return IRQ_HANDLED;
240}
241
666db563 242static int mpc85xx_pci_err_probe(struct platform_device *op)
a9a753d5
DJ		 243{
244 struct edac_pci_ctl_info *pci;
245 struct mpc85xx_pci_pdata *pdata;
666db563
SW		 246 struct mpc85xx_edac_pci_plat_data *plat_data;
247 struct device_node *of_node;
f87bd330 248 struct resource r;
a9a753d5
DJ		 249 int res = 0;
250
f87bd330 251 if (!devres_open_group(&op->dev, mpc85xx_pci_err_probe, GFP_KERNEL))
a9a753d5
DJ		 252 return -ENOMEM;
253
254 pci = edac_pci_alloc_ctl_info(sizeof(*pdata), "mpc85xx_pci_err");
255 if (!pci)
256 return -ENOMEM;
257
905e75c4
JH		 258 /* make sure error reporting method is sane */
259 switch (edac_op_state) {
260 case EDAC_OPSTATE_POLL:
261 case EDAC_OPSTATE_INT:
262 break;
263 default:
264 edac_op_state = EDAC_OPSTATE_INT;
265 break;
266 }
267
a9a753d5
DJ		 268 pdata = pci->pvt_info;
269 pdata->name = "mpc85xx_pci_err";
270 pdata->irq = NO_IRQ;
c92132f5 271
666db563
SW		 272 plat_data = op->dev.platform_data;
273 if (!plat_data) {
274 dev_err(&op->dev, "no platform data");
275 res = -ENXIO;
276 goto err;
277 }
278 of_node = plat_data->of_node;
279
280 if (mpc85xx_pcie_find_capability(of_node) > 0)
c92132f5
CL		 281 pdata->is_pcie = true;
282
f87bd330
DJ		 283 dev_set_drvdata(&op->dev, pci);
284 pci->dev = &op->dev;
a9a753d5
DJ		 285 pci->mod_name = EDAC_MOD_STR;
286 pci->ctl_name = pdata->name;
031d5518 287 pci->dev_name = dev_name(&op->dev);
a9a753d5 288
c92132f5
CL		 289 if (edac_op_state == EDAC_OPSTATE_POLL) {
290 if (pdata->is_pcie)
291 pci->edac_check = mpc85xx_pcie_check;
292 else
293 pci->edac_check = mpc85xx_pci_check;
294 }
a9a753d5
DJ		 295
296 pdata->edac_idx = edac_pci_idx++;
297
666db563 298 res = of_address_to_resource(of_node, 0, &r);
f87bd330 299 if (res) {
a9a753d5
DJ		 300 printk(KERN_ERR "%s: Unable to get resource for "
301 "PCI err regs\n", __func__);
302 goto err;
303 }
304
f87bd330
DJ		 305 /* we only need the error registers */
306 r.start += 0xe00;
307
66ed3f75
HS		 308 if (!devm_request_mem_region(&op->dev, r.start, resource_size(&r),
309 pdata->name)) {
a9a753d5
DJ		 310 printk(KERN_ERR "%s: Error while requesting mem region\n",
311 __func__);
312 res = -EBUSY;
313 goto err;
314 }
315
66ed3f75 316 pdata->pci_vbase = devm_ioremap(&op->dev, r.start, resource_size(&r));
a9a753d5
DJ		 317 if (!pdata->pci_vbase) {
318 printk(KERN_ERR "%s: Unable to setup PCI err regs\n", __func__);
319 res = -ENOMEM;
320 goto err;
321 }
322
c92132f5
CL		 323 if (pdata->is_pcie) {
324 orig_pci_err_cap_dr =
325 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ADDR);
326 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ADDR, ~0);
327 orig_pci_err_en =
328 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN);
329 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN, 0);
330 } else {
331 orig_pci_err_cap_dr =
332 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_CAP_DR);
333
334 /* PCI master abort is expected during config cycles */
335 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_CAP_DR, 0x40);
336
337 orig_pci_err_en =
338 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN);
339
340 /* disable master abort reporting */
341 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN, ~0x40);
342 }
a9a753d5
DJ		 343
344 /* clear error bits */
345 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, ~0);
346
6fa06b0d
TH		 347 /* reset error capture */
348 out_be32(pdata->pci_vbase + MPC85XX_PCI_GAS_TIMR, 0x1);
349
a9a753d5 350 if (edac_pci_add_device(pci, pdata->edac_idx) > 0) {
956b9ba1 351 edac_dbg(3, "failed edac_pci_add_device()\n");
a9a753d5
DJ		 352 goto err;
353 }
354
355 if (edac_op_state == EDAC_OPSTATE_INT) {
666db563 356 pdata->irq = irq_of_parse_and_map(of_node, 0);
f87bd330 357 res = devm_request_irq(&op->dev, pdata->irq,
c92132f5 358 mpc85xx_pci_isr,
e245e3b2 359 IRQF_SHARED,
a9a753d5
DJ		 360 "[EDAC] PCI err", pci);
361 if (res < 0) {
362 printk(KERN_ERR
e7d2c215 363 "%s: Unable to request irq %d for "
a9a753d5 364 "MPC85xx PCI err\n", __func__, pdata->irq);
f87bd330 365 irq_dispose_mapping(pdata->irq);
a9a753d5
DJ		 366 res = -ENODEV;
367 goto err2;
368 }
369
370 printk(KERN_INFO EDAC_MOD_STR " acquired irq %d for PCI Err\n",
371 pdata->irq);
372 }
373
c92132f5
CL		 374 if (pdata->is_pcie) {
375 /*
376 * Enable all PCIe error interrupt & error detect except invalid
377 * PEX_CONFIG_ADDR/PEX_CONFIG_DATA access interrupt generation
378 * enable bit and invalid PEX_CONFIG_ADDR/PEX_CONFIG_DATA access
379 * detection enable bit. Because PCIe bus code to initialize and
380 * configure these PCIe devices on booting will use some invalid
381 * PEX_CONFIG_ADDR/PEX_CONFIG_DATA, edac driver prints the much
382 * notice information. So disable this detect to fix ugly print.
383 */
384 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN, ~0
385 & ~PEX_ERR_ICCAIE_EN_BIT);
386 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ADDR, 0
387 | PEX_ERR_ICCAD_DISR_BIT);
388 }
389
f87bd330 390 devres_remove_group(&op->dev, mpc85xx_pci_err_probe);
956b9ba1 391 edac_dbg(3, "success\n");
a9a753d5
DJ		 392 printk(KERN_INFO EDAC_MOD_STR " PCI err registered\n");
393
394 return 0;
395
396err2:
f87bd330 397 edac_pci_del_device(&op->dev);
a9a753d5
DJ		 398err:
399 edac_pci_free_ctl_info(pci);
f87bd330 400 devres_release_group(&op->dev, mpc85xx_pci_err_probe);
a9a753d5
DJ		 401 return res;
402}
403
666db563
SW		 404static const struct platform_device_id mpc85xx_pci_err_match[] = {
405 {
406 .name = "mpc85xx-pci-edac"
407 },
408 {}
409};
410
411static struct platform_driver mpc85xx_pci_err_driver = {
412 .probe = mpc85xx_pci_err_probe,
413 .id_table = mpc85xx_pci_err_match,
414 .driver = {
415 .name = "mpc85xx_pci_err",
416 .suppress_bind_attrs = true,
417 },
418};
a9a753d5
DJ		 419#endif /* CONFIG_PCI */
420
421/**************************** L2 Err device ***************************/
422
423/************************ L2 SYSFS parts ***********************************/
424
425static ssize_t mpc85xx_l2_inject_data_hi_show(struct edac_device_ctl_info
426 *edac_dev, char *data)
427{
428 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
429 return sprintf(data, "0x%08x",
430 in_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJHI));
431}
432
433static ssize_t mpc85xx_l2_inject_data_lo_show(struct edac_device_ctl_info
434 *edac_dev, char *data)
435{
436 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
437 return sprintf(data, "0x%08x",
438 in_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJLO));
439}
440
441static ssize_t mpc85xx_l2_inject_ctrl_show(struct edac_device_ctl_info
442 *edac_dev, char *data)
443{
444 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
445 return sprintf(data, "0x%08x",
446 in_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJCTL));
447}
448
449static ssize_t mpc85xx_l2_inject_data_hi_store(struct edac_device_ctl_info
450 *edac_dev, const char *data,
451 size_t count)
452{
453 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
454 if (isdigit(*data)) {
455 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJHI,
456 simple_strtoul(data, NULL, 0));
457 return count;
458 }
459 return 0;
460}
461
462static ssize_t mpc85xx_l2_inject_data_lo_store(struct edac_device_ctl_info
463 *edac_dev, const char *data,
464 size_t count)
465{
466 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
467 if (isdigit(*data)) {
468 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJLO,
469 simple_strtoul(data, NULL, 0));
470 return count;
471 }
472 return 0;
473}
474
475static ssize_t mpc85xx_l2_inject_ctrl_store(struct edac_device_ctl_info
476 *edac_dev, const char *data,
477 size_t count)
478{
479 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
480 if (isdigit(*data)) {
481 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJCTL,
482 simple_strtoul(data, NULL, 0));
483 return count;
484 }
485 return 0;
486}
487
488static struct edac_dev_sysfs_attribute mpc85xx_l2_sysfs_attributes[] = {
489 {
490 .attr = {
491 .name = "inject_data_hi",
492 .mode = (S_IRUGO | S_IWUSR)
493 },
494 .show = mpc85xx_l2_inject_data_hi_show,
495 .store = mpc85xx_l2_inject_data_hi_store},
496 {
497 .attr = {
498 .name = "inject_data_lo",
499 .mode = (S_IRUGO | S_IWUSR)
500 },
501 .show = mpc85xx_l2_inject_data_lo_show,
502 .store = mpc85xx_l2_inject_data_lo_store},
503 {
504 .attr = {
505 .name = "inject_ctrl",
506 .mode = (S_IRUGO | S_IWUSR)
507 },
508 .show = mpc85xx_l2_inject_ctrl_show,
509 .store = mpc85xx_l2_inject_ctrl_store},
510
511 /* End of list */
512 {
513 .attr = {.name = NULL}
514 }
515};
516
517static void mpc85xx_set_l2_sysfs_attributes(struct edac_device_ctl_info
518 *edac_dev)
519{
520 edac_dev->sysfs_attributes = mpc85xx_l2_sysfs_attributes;
521}
522
523/***************************** L2 ops ***********************************/
524
525static void mpc85xx_l2_check(struct edac_device_ctl_info *edac_dev)
526{
527 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
528 u32 err_detect;
529
530 err_detect = in_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET);
531
532 if (!(err_detect & L2_EDE_MASK))
533 return;
534
535 printk(KERN_ERR "ECC Error in CPU L2 cache\n");
536 printk(KERN_ERR "L2 Error Detect Register: 0x%08x\n", err_detect);
537 printk(KERN_ERR "L2 Error Capture Data High Register: 0x%08x\n",
538 in_be32(pdata->l2_vbase + MPC85XX_L2_CAPTDATAHI));
539 printk(KERN_ERR "L2 Error Capture Data Lo Register: 0x%08x\n",
540 in_be32(pdata->l2_vbase + MPC85XX_L2_CAPTDATALO));
541 printk(KERN_ERR "L2 Error Syndrome Register: 0x%08x\n",
542 in_be32(pdata->l2_vbase + MPC85XX_L2_CAPTECC));
543 printk(KERN_ERR "L2 Error Attributes Capture Register: 0x%08x\n",
544 in_be32(pdata->l2_vbase + MPC85XX_L2_ERRATTR));
545 printk(KERN_ERR "L2 Error Address Capture Register: 0x%08x\n",
546 in_be32(pdata->l2_vbase + MPC85XX_L2_ERRADDR));
547
548 /* clear error detect register */
549 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET, err_detect);
550
551 if (err_detect & L2_EDE_CE_MASK)
552 edac_device_handle_ce(edac_dev, 0, 0, edac_dev->ctl_name);
553
554 if (err_detect & L2_EDE_UE_MASK)
555 edac_device_handle_ue(edac_dev, 0, 0, edac_dev->ctl_name);
556}
557
558static irqreturn_t mpc85xx_l2_isr(int irq, void *dev_id)
559{
560 struct edac_device_ctl_info *edac_dev = dev_id;
561 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
562 u32 err_detect;
563
564 err_detect = in_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET);
565
566 if (!(err_detect & L2_EDE_MASK))
567 return IRQ_NONE;
568
569 mpc85xx_l2_check(edac_dev);
570
571 return IRQ_HANDLED;
572}
573
9b3c6e85 574static int mpc85xx_l2_err_probe(struct platform_device *op)
a9a753d5
DJ		 575{
576 struct edac_device_ctl_info *edac_dev;
577 struct mpc85xx_l2_pdata *pdata;
578 struct resource r;
579 int res;
580
581 if (!devres_open_group(&op->dev, mpc85xx_l2_err_probe, GFP_KERNEL))
582 return -ENOMEM;
583
584 edac_dev = edac_device_alloc_ctl_info(sizeof(*pdata),
585 "cpu", 1, "L", 1, 2, NULL, 0,
586 edac_dev_idx);
587 if (!edac_dev) {
588 devres_release_group(&op->dev, mpc85xx_l2_err_probe);
589 return -ENOMEM;
590 }
591
592 pdata = edac_dev->pvt_info;
593 pdata->name = "mpc85xx_l2_err";
594 pdata->irq = NO_IRQ;
595 edac_dev->dev = &op->dev;
596 dev_set_drvdata(edac_dev->dev, edac_dev);
597 edac_dev->ctl_name = pdata->name;
598 edac_dev->dev_name = pdata->name;
599
a26f95fe 600 res = of_address_to_resource(op->dev.of_node, 0, &r);
a9a753d5
DJ		 601 if (res) {
602 printk(KERN_ERR "%s: Unable to get resource for "
603 "L2 err regs\n", __func__);
604 goto err;
605 }
606
607 /* we only need the error registers */
608 r.start += 0xe00;
609
28f65c11
JP		 610 if (!devm_request_mem_region(&op->dev, r.start, resource_size(&r),
611 pdata->name)) {
a9a753d5
DJ		 612 printk(KERN_ERR "%s: Error while requesting mem region\n",
613 __func__);
614 res = -EBUSY;
615 goto err;
616 }
617
28f65c11 618 pdata->l2_vbase = devm_ioremap(&op->dev, r.start, resource_size(&r));
a9a753d5
DJ		 619 if (!pdata->l2_vbase) {
620 printk(KERN_ERR "%s: Unable to setup L2 err regs\n", __func__);
621 res = -ENOMEM;
622 goto err;
623 }
624
625 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET, ~0);
626
627 orig_l2_err_disable = in_be32(pdata->l2_vbase + MPC85XX_L2_ERRDIS);
628
629 /* clear the err_dis */
630 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDIS, 0);
631
632 edac_dev->mod_name = EDAC_MOD_STR;
633
634 if (edac_op_state == EDAC_OPSTATE_POLL)
635 edac_dev->edac_check = mpc85xx_l2_check;
636
637 mpc85xx_set_l2_sysfs_attributes(edac_dev);
638
639 pdata->edac_idx = edac_dev_idx++;
640
641 if (edac_device_add_device(edac_dev) > 0) {
956b9ba1 642 edac_dbg(3, "failed edac_device_add_device()\n");
a9a753d5
DJ		 643 goto err;
644 }
645
646 if (edac_op_state == EDAC_OPSTATE_INT) {
a26f95fe 647 pdata->irq = irq_of_parse_and_map(op->dev.of_node, 0);
a9a753d5 648 res = devm_request_irq(&op->dev, pdata->irq,
a18c3f16 649 mpc85xx_l2_isr, IRQF_SHARED,
a9a753d5
DJ		 650 "[EDAC] L2 err", edac_dev);
651 if (res < 0) {
652 printk(KERN_ERR
e7d2c215 653 "%s: Unable to request irq %d for "
a9a753d5
DJ		 654 "MPC85xx L2 err\n", __func__, pdata->irq);
655 irq_dispose_mapping(pdata->irq);
656 res = -ENODEV;
657 goto err2;
658 }
659
660 printk(KERN_INFO EDAC_MOD_STR " acquired irq %d for L2 Err\n",
661 pdata->irq);
662
663 edac_dev->op_state = OP_RUNNING_INTERRUPT;
664
665 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINTEN, L2_EIE_MASK);
666 }
667
668 devres_remove_group(&op->dev, mpc85xx_l2_err_probe);
669
956b9ba1 670 edac_dbg(3, "success\n");
a9a753d5
DJ		 671 printk(KERN_INFO EDAC_MOD_STR " L2 err registered\n");
672
673 return 0;
674
675err2:
676 edac_device_del_device(&op->dev);
677err:
678 devres_release_group(&op->dev, mpc85xx_l2_err_probe);
679 edac_device_free_ctl_info(edac_dev);
680 return res;
681}
682
2dc11581 683static int mpc85xx_l2_err_remove(struct platform_device *op)
a9a753d5
DJ		 684{
685 struct edac_device_ctl_info *edac_dev = dev_get_drvdata(&op->dev);
686 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
687
956b9ba1 688 edac_dbg(0, "\n");
a9a753d5
DJ		 689
690 if (edac_op_state == EDAC_OPSTATE_INT) {
691 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINTEN, 0);
692 irq_dispose_mapping(pdata->irq);
693 }
694
695 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDIS, orig_l2_err_disable);
696 edac_device_del_device(&op->dev);
697 edac_device_free_ctl_info(edac_dev);
698 return 0;
699}
700
1afaa055 701static const struct of_device_id mpc85xx_l2_err_of_match[] = {
29d6cf26
KG		 702/* deprecate the fsl,85.. forms in the future, 2.6.30? */
703 { .compatible = "fsl,8540-l2-cache-controller", },
704 { .compatible = "fsl,8541-l2-cache-controller", },
705 { .compatible = "fsl,8544-l2-cache-controller", },
706 { .compatible = "fsl,8548-l2-cache-controller", },
707 { .compatible = "fsl,8555-l2-cache-controller", },
708 { .compatible = "fsl,8568-l2-cache-controller", },
709 { .compatible = "fsl,mpc8536-l2-cache-controller", },
710 { .compatible = "fsl,mpc8540-l2-cache-controller", },
711 { .compatible = "fsl,mpc8541-l2-cache-controller", },
712 { .compatible = "fsl,mpc8544-l2-cache-controller", },
713 { .compatible = "fsl,mpc8548-l2-cache-controller", },
714 { .compatible = "fsl,mpc8555-l2-cache-controller", },
715 { .compatible = "fsl,mpc8560-l2-cache-controller", },
716 { .compatible = "fsl,mpc8568-l2-cache-controller", },
cd1542c8 717 { .compatible = "fsl,mpc8569-l2-cache-controller", },
29d6cf26 718 { .compatible = "fsl,mpc8572-l2-cache-controller", },
cd1542c8
AV		 719 { .compatible = "fsl,p1020-l2-cache-controller", },
720 { .compatible = "fsl,p1021-l2-cache-controller", },
a014554e 721 { .compatible = "fsl,p2020-l2-cache-controller", },
a9a753d5
DJ		 722 {},
723};
952e1c66 724MODULE_DEVICE_TABLE(of, mpc85xx_l2_err_of_match);
a9a753d5 725
00006124 726static struct platform_driver mpc85xx_l2_err_driver = {
a9a753d5
DJ		 727 .probe = mpc85xx_l2_err_probe,
728 .remove = mpc85xx_l2_err_remove,
729 .driver = {
4018294b 730 .name = "mpc85xx_l2_err",
4018294b
GL		 731 .of_match_table = mpc85xx_l2_err_of_match,
732 },
a9a753d5
DJ		 733};
734
735/**************************** MC Err device ***************************/
736
dcca7c3d
PT		 737/*
738 * Taken from table 8-55 in the MPC8641 User's Manual and/or 9-61 in the
739 * MPC8572 User's Manual. Each line represents a syndrome bit column as a
740 * 64-bit value, but split into an upper and lower 32-bit chunk. The labels
741 * below correspond to Freescale's manuals.
742 */
743static unsigned int ecc_table[16] = {
744 /* MSB LSB */
745 /* [0:31] [32:63] */
746 0xf00fe11e, 0xc33c0ff7, /* Syndrome bit 7 */
747 0x00ff00ff, 0x00fff0ff,
748 0x0f0f0f0f, 0x0f0fff00,
749 0x11113333, 0x7777000f,
750 0x22224444, 0x8888222f,
751 0x44448888, 0xffff4441,
752 0x8888ffff, 0x11118882,
753 0xffff1111, 0x22221114, /* Syndrome bit 0 */
754};
755
756/*
757 * Calculate the correct ECC value for a 64-bit value specified by high:low
758 */
759static u8 calculate_ecc(u32 high, u32 low)
760{
761 u32 mask_low;
762 u32 mask_high;
763 int bit_cnt;
764 u8 ecc = 0;
765 int i;
766 int j;
767
768 for (i = 0; i < 8; i++) {
769 mask_high = ecc_table[i * 2];
770 mask_low = ecc_table[i * 2 + 1];
771 bit_cnt = 0;
772
773 for (j = 0; j < 32; j++) {
774 if ((mask_high >> j) & 1)
775 bit_cnt ^= (high >> j) & 1;
776 if ((mask_low >> j) & 1)
777 bit_cnt ^= (low >> j) & 1;
778 }
779
780 ecc |= bit_cnt << i;
781 }
782
783 return ecc;
784}
785
786/*
787 * Create the syndrome code which is generated if the data line specified by
788 * 'bit' failed. Eg generate an 8-bit codes seen in Table 8-55 in the MPC8641
789 * User's Manual and 9-61 in the MPC8572 User's Manual.
790 */
791static u8 syndrome_from_bit(unsigned int bit) {
792 int i;
793 u8 syndrome = 0;
794
795 /*
796 * Cycle through the upper or lower 32-bit portion of each value in
797 * ecc_table depending on if 'bit' is in the upper or lower half of
798 * 64-bit data.
799 */
800 for (i = bit < 32; i < 16; i += 2)
801 syndrome |= ((ecc_table[i] >> (bit % 32)) & 1) << (i / 2);
802
803 return syndrome;
804}
805
806/*
807 * Decode data and ecc syndrome to determine what went wrong
808 * Note: This can only decode single-bit errors
809 */
810static void sbe_ecc_decode(u32 cap_high, u32 cap_low, u32 cap_ecc,
811 int *bad_data_bit, int *bad_ecc_bit)
812{
813 int i;
814 u8 syndrome;
815
816 *bad_data_bit = -1;
817 *bad_ecc_bit = -1;
818
819 /*
820 * Calculate the ECC of the captured data and XOR it with the captured
821 * ECC to find an ECC syndrome value we can search for
822 */
823 syndrome = calculate_ecc(cap_high, cap_low) ^ cap_ecc;
824
825 /* Check if a data line is stuck... */
826 for (i = 0; i < 64; i++) {
827 if (syndrome == syndrome_from_bit(i)) {
828 *bad_data_bit = i;
829 return;
830 }
831 }
832
833 /* If data is correct, check ECC bits for errors... */
834 for (i = 0; i < 8; i++) {
835 if ((syndrome >> i) & 0x1) {
836 *bad_ecc_bit = i;
837 return;
838 }
839 }
840}
841
2ce39109
YS		 842#define make64(high, low) (((u64)(high) << 32) | (low))
843
a9a753d5
DJ		 844static void mpc85xx_mc_check(struct mem_ctl_info *mci)
845{
846 struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
847 struct csrow_info *csrow;
21768639 848 u32 bus_width;
a9a753d5
DJ		 849 u32 err_detect;
850 u32 syndrome;
2ce39109 851 u64 err_addr;
a9a753d5
DJ		 852 u32 pfn;
853 int row_index;
dcca7c3d
PT		 854 u32 cap_high;
855 u32 cap_low;
856 int bad_data_bit;
857 int bad_ecc_bit;
a9a753d5
DJ		 858
859 err_detect = in_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT);
55e5750b 860 if (!err_detect)
a9a753d5
DJ		 861 return;
862
863 mpc85xx_mc_printk(mci, KERN_ERR, "Err Detect Register: %#8.8x\n",
864 err_detect);
865
866 /* no more processing if not ECC bit errors */
867 if (!(err_detect & (DDR_EDE_SBE | DDR_EDE_MBE))) {
868 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT, err_detect);
869 return;
870 }
871
872 syndrome = in_be32(pdata->mc_vbase + MPC85XX_MC_CAPTURE_ECC);
21768639
PT		 873
874 /* Mask off appropriate bits of syndrome based on bus width */
875 bus_width = (in_be32(pdata->mc_vbase + MPC85XX_MC_DDR_SDRAM_CFG) &
876 DSC_DBW_MASK) ? 32 : 64;
877 if (bus_width == 64)
878 syndrome &= 0xff;
879 else
880 syndrome &= 0xffff;
881
2ce39109
YS		 882 err_addr = make64(
883 in_be32(pdata->mc_vbase + MPC85XX_MC_CAPTURE_EXT_ADDRESS),
884 in_be32(pdata->mc_vbase + MPC85XX_MC_CAPTURE_ADDRESS));
a9a753d5
DJ		 885 pfn = err_addr >> PAGE_SHIFT;
886
887 for (row_index = 0; row_index < mci->nr_csrows; row_index++) {
de3910eb 888 csrow = mci->csrows[row_index];
a9a753d5
DJ		 889 if ((pfn >= csrow->first_page) && (pfn <= csrow->last_page))
890 break;
891 }
892
dcca7c3d
PT		 893 cap_high = in_be32(pdata->mc_vbase + MPC85XX_MC_CAPTURE_DATA_HI);
894 cap_low = in_be32(pdata->mc_vbase + MPC85XX_MC_CAPTURE_DATA_LO);
895
896 /*
897 * Analyze single-bit errors on 64-bit wide buses
898 * TODO: Add support for 32-bit wide buses
899 */
900 if ((err_detect & DDR_EDE_SBE) && (bus_width == 64)) {
901 sbe_ecc_decode(cap_high, cap_low, syndrome,
902 &bad_data_bit, &bad_ecc_bit);
903
904 if (bad_data_bit != -1)
905 mpc85xx_mc_printk(mci, KERN_ERR,
906 "Faulty Data bit: %d\n", bad_data_bit);
907 if (bad_ecc_bit != -1)
908 mpc85xx_mc_printk(mci, KERN_ERR,
909 "Faulty ECC bit: %d\n", bad_ecc_bit);
910
911 mpc85xx_mc_printk(mci, KERN_ERR,
912 "Expected Data / ECC:\t%#8.8x_%08x / %#2.2x\n",
913 cap_high ^ (1 << (bad_data_bit - 32)),
914 cap_low ^ (1 << bad_data_bit),
915 syndrome ^ (1 << bad_ecc_bit));
916 }
917
918 mpc85xx_mc_printk(mci, KERN_ERR,
919 "Captured Data / ECC:\t%#8.8x_%08x / %#2.2x\n",
920 cap_high, cap_low, syndrome);
2ce39109 921 mpc85xx_mc_printk(mci, KERN_ERR, "Err addr: %#8.8llx\n", err_addr);
a9a753d5
DJ		 922 mpc85xx_mc_printk(mci, KERN_ERR, "PFN: %#8.8x\n", pfn);
923
924 /* we are out of range */
925 if (row_index == mci->nr_csrows)
926 mpc85xx_mc_printk(mci, KERN_ERR, "PFN out of range!\n");
927
928 if (err_detect & DDR_EDE_SBE)
9eb07a7f 929 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
ad4d6e23
MCC		 930 pfn, err_addr & ~PAGE_MASK, syndrome,
931 row_index, 0, -1,
03f7eae8 932 mci->ctl_name, "");
a9a753d5
DJ		 933
934 if (err_detect & DDR_EDE_MBE)
9eb07a7f 935 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
ad4d6e23
MCC		 936 pfn, err_addr & ~PAGE_MASK, syndrome,
937 row_index, 0, -1,
03f7eae8 938 mci->ctl_name, "");
a9a753d5
DJ		 939
940 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT, err_detect);
941}
942
943static irqreturn_t mpc85xx_mc_isr(int irq, void *dev_id)
944{
945 struct mem_ctl_info *mci = dev_id;
946 struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
947 u32 err_detect;
948
949 err_detect = in_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT);
950 if (!err_detect)
951 return IRQ_NONE;
952
953 mpc85xx_mc_check(mci);
954
955 return IRQ_HANDLED;
956}
957
9b3c6e85 958static void mpc85xx_init_csrows(struct mem_ctl_info *mci)
a9a753d5
DJ		 959{
960 struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
961 struct csrow_info *csrow;
084a4fcc 962 struct dimm_info *dimm;
a9a753d5
DJ		 963 u32 sdram_ctl;
964 u32 sdtype;
965 enum mem_type mtype;
966 u32 cs_bnds;
967 int index;
968
969 sdram_ctl = in_be32(pdata->mc_vbase + MPC85XX_MC_DDR_SDRAM_CFG);
970
971 sdtype = sdram_ctl & DSC_SDTYPE_MASK;
972 if (sdram_ctl & DSC_RD_EN) {
973 switch (sdtype) {
974 case DSC_SDTYPE_DDR:
975 mtype = MEM_RDDR;
976 break;
977 case DSC_SDTYPE_DDR2:
978 mtype = MEM_RDDR2;
979 break;
b1cfebc9
YS		 980 case DSC_SDTYPE_DDR3:
981 mtype = MEM_RDDR3;
982 break;
a9a753d5
DJ		 983 default:
984 mtype = MEM_UNKNOWN;
985 break;
986 }
987 } else {
988 switch (sdtype) {
989 case DSC_SDTYPE_DDR:
990 mtype = MEM_DDR;
991 break;
992 case DSC_SDTYPE_DDR2:
993 mtype = MEM_DDR2;
994 break;
b1cfebc9
YS		 995 case DSC_SDTYPE_DDR3:
996 mtype = MEM_DDR3;
997 break;
a9a753d5
DJ		 998 default:
999 mtype = MEM_UNKNOWN;
1000 break;
1001 }
1002 }
1003
1004 for (index = 0; index < mci->nr_csrows; index++) {
1005 u32 start;
1006 u32 end;
1007
de3910eb
MCC		 1008 csrow = mci->csrows[index];
1009 dimm = csrow->channels[0]->dimm;
084a4fcc 1010
a9a753d5
DJ		 1011 cs_bnds = in_be32(pdata->mc_vbase + MPC85XX_MC_CS_BNDS_0 +
1012 (index * MPC85XX_MC_CS_BNDS_OFS));
b4846251
IS		 1013
1014 start = (cs_bnds & 0xffff0000) >> 16;
1015 end = (cs_bnds & 0x0000ffff);
a9a753d5
DJ		 1016
1017 if (start == end)
1018 continue; /* not populated */
1019
b4846251
IS		 1020 start <<= (24 - PAGE_SHIFT);
1021 end <<= (24 - PAGE_SHIFT);
1022 end |= (1 << (24 - PAGE_SHIFT)) - 1;
1023
cff9279e
PT		 1024 csrow->first_page = start;
1025 csrow->last_page = end;
a895bf8b
MCC		 1026
1027 dimm->nr_pages = end + 1 - start;
084a4fcc
MCC		 1028 dimm->grain = 8;
1029 dimm->mtype = mtype;
1030 dimm->dtype = DEV_UNKNOWN;
a9a753d5 1031 if (sdram_ctl & DSC_X32_EN)
084a4fcc
MCC		 1032 dimm->dtype = DEV_X32;
1033 dimm->edac_mode = EDAC_SECDED;
a9a753d5
DJ		 1034 }
1035}
1036
9b3c6e85 1037static int mpc85xx_mc_err_probe(struct platform_device *op)
a9a753d5
DJ		 1038{
1039 struct mem_ctl_info *mci;
ad4d6e23 1040 struct edac_mc_layer layers[2];
a9a753d5
DJ		 1041 struct mpc85xx_mc_pdata *pdata;
1042 struct resource r;
1043 u32 sdram_ctl;
1044 int res;
1045
1046 if (!devres_open_group(&op->dev, mpc85xx_mc_err_probe, GFP_KERNEL))
1047 return -ENOMEM;
1048
ad4d6e23
MCC		 1049 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
1050 layers[0].size = 4;
1051 layers[0].is_virt_csrow = true;
1052 layers[1].type = EDAC_MC_LAYER_CHANNEL;
1053 layers[1].size = 1;
1054 layers[1].is_virt_csrow = false;
b9bc5ddb
KP		 1055 mci = edac_mc_alloc(edac_mc_idx, ARRAY_SIZE(layers), layers,
1056 sizeof(*pdata));
a9a753d5
DJ		 1057 if (!mci) {
1058 devres_release_group(&op->dev, mpc85xx_mc_err_probe);
1059 return -ENOMEM;
1060 }
1061
1062 pdata = mci->pvt_info;
1063 pdata->name = "mpc85xx_mc_err";
1064 pdata->irq = NO_IRQ;
fd687502 1065 mci->pdev = &op->dev;
a9a753d5 1066 pdata->edac_idx = edac_mc_idx++;
fd687502 1067 dev_set_drvdata(mci->pdev, mci);
a9a753d5
DJ		 1068 mci->ctl_name = pdata->name;
1069 mci->dev_name = pdata->name;
1070
a26f95fe 1071 res = of_address_to_resource(op->dev.of_node, 0, &r);
a9a753d5
DJ		 1072 if (res) {
1073 printk(KERN_ERR "%s: Unable to get resource for MC err regs\n",
1074 __func__);
1075 goto err;
1076 }
1077
28f65c11
JP		 1078 if (!devm_request_mem_region(&op->dev, r.start, resource_size(&r),
1079 pdata->name)) {
a9a753d5
DJ		 1080 printk(KERN_ERR "%s: Error while requesting mem region\n",
1081 __func__);
1082 res = -EBUSY;
1083 goto err;
1084 }
1085
28f65c11 1086 pdata->mc_vbase = devm_ioremap(&op->dev, r.start, resource_size(&r));
a9a753d5
DJ		 1087 if (!pdata->mc_vbase) {
1088 printk(KERN_ERR "%s: Unable to setup MC err regs\n", __func__);
1089 res = -ENOMEM;
1090 goto err;
1091 }
1092
1093 sdram_ctl = in_be32(pdata->mc_vbase + MPC85XX_MC_DDR_SDRAM_CFG);
1094 if (!(sdram_ctl & DSC_ECC_EN)) {
1095 /* no ECC */
1096 printk(KERN_WARNING "%s: No ECC DIMMs discovered\n", __func__);
1097 res = -ENODEV;
1098 goto err;
1099 }
1100
956b9ba1 1101 edac_dbg(3, "init mci\n");
a9a753d5
DJ		 1102 mci->mtype_cap = MEM_FLAG_RDDR | MEM_FLAG_RDDR2 |
1103 MEM_FLAG_DDR | MEM_FLAG_DDR2;
1104 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
1105 mci->edac_cap = EDAC_FLAG_SECDED;
1106 mci->mod_name = EDAC_MOD_STR;
1107 mci->mod_ver = MPC85XX_REVISION;
1108
1109 if (edac_op_state == EDAC_OPSTATE_POLL)
1110 mci->edac_check = mpc85xx_mc_check;
1111
1112 mci->ctl_page_to_phys = NULL;
1113
1114 mci->scrub_mode = SCRUB_SW_SRC;
1115
a9a753d5
DJ		 1116 mpc85xx_init_csrows(mci);
1117
a9a753d5
DJ		 1118 /* store the original error disable bits */
1119 orig_ddr_err_disable =
1120 in_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DISABLE);
1121 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DISABLE, 0);
1122
1123 /* clear all error bits */
1124 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT, ~0);
1125
917c85b5 1126 if (edac_mc_add_mc_with_groups(mci, mpc85xx_dev_groups)) {
956b9ba1 1127 edac_dbg(3, "failed edac_mc_add_mc()\n");
a9a753d5
DJ		 1128 goto err;
1129 }
1130
1131 if (edac_op_state == EDAC_OPSTATE_INT) {
1132 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_INT_EN,
1133 DDR_EIE_MBEE | DDR_EIE_SBEE);
1134
1135 /* store the original error management threshold */
1136 orig_ddr_err_sbe = in_be32(pdata->mc_vbase +
1137 MPC85XX_MC_ERR_SBE) & 0xff0000;
1138
1139 /* set threshold to 1 error per interrupt */
1140 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_SBE, 0x10000);
1141
1142 /* register interrupts */
a26f95fe 1143 pdata->irq = irq_of_parse_and_map(op->dev.of_node, 0);
a9a753d5 1144 res = devm_request_irq(&op->dev, pdata->irq,
60be7551 1145 mpc85xx_mc_isr,
e245e3b2 1146 IRQF_SHARED,
a9a753d5
DJ		 1147 "[EDAC] MC err", mci);
1148 if (res < 0) {
1149 printk(KERN_ERR "%s: Unable to request irq %d for "
1150 "MPC85xx DRAM ERR\n", __func__, pdata->irq);
1151 irq_dispose_mapping(pdata->irq);
1152 res = -ENODEV;
1153 goto err2;
1154 }
1155
1156 printk(KERN_INFO EDAC_MOD_STR " acquired irq %d for MC\n",
1157 pdata->irq);
1158 }
1159
1160 devres_remove_group(&op->dev, mpc85xx_mc_err_probe);
956b9ba1 1161 edac_dbg(3, "success\n");
a9a753d5
DJ		 1162 printk(KERN_INFO EDAC_MOD_STR " MC err registered\n");
1163
1164 return 0;
1165
1166err2:
1167 edac_mc_del_mc(&op->dev);
1168err:
1169 devres_release_group(&op->dev, mpc85xx_mc_err_probe);
1170 edac_mc_free(mci);
1171 return res;
1172}
1173
2dc11581 1174static int mpc85xx_mc_err_remove(struct platform_device *op)
a9a753d5
DJ		 1175{
1176 struct mem_ctl_info *mci = dev_get_drvdata(&op->dev);
1177 struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
1178
956b9ba1 1179 edac_dbg(0, "\n");
a9a753d5
DJ		 1180
1181 if (edac_op_state == EDAC_OPSTATE_INT) {
1182 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_INT_EN, 0);
1183 irq_dispose_mapping(pdata->irq);
1184 }
1185
1186 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DISABLE,
1187 orig_ddr_err_disable);
1188 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_SBE, orig_ddr_err_sbe);
1189
1190 edac_mc_del_mc(&op->dev);
1191 edac_mc_free(mci);
1192 return 0;
1193}
1194
1afaa055 1195static const struct of_device_id mpc85xx_mc_err_of_match[] = {
29d6cf26
KG		 1196/* deprecate the fsl,85.. forms in the future, 2.6.30? */
1197 { .compatible = "fsl,8540-memory-controller", },
1198 { .compatible = "fsl,8541-memory-controller", },
1199 { .compatible = "fsl,8544-memory-controller", },
1200 { .compatible = "fsl,8548-memory-controller", },
1201 { .compatible = "fsl,8555-memory-controller", },
1202 { .compatible = "fsl,8568-memory-controller", },
1203 { .compatible = "fsl,mpc8536-memory-controller", },
1204 { .compatible = "fsl,mpc8540-memory-controller", },
1205 { .compatible = "fsl,mpc8541-memory-controller", },
1206 { .compatible = "fsl,mpc8544-memory-controller", },
1207 { .compatible = "fsl,mpc8548-memory-controller", },
1208 { .compatible = "fsl,mpc8555-memory-controller", },
1209 { .compatible = "fsl,mpc8560-memory-controller", },
1210 { .compatible = "fsl,mpc8568-memory-controller", },
5528e229 1211 { .compatible = "fsl,mpc8569-memory-controller", },
29d6cf26 1212 { .compatible = "fsl,mpc8572-memory-controller", },
b4846251 1213 { .compatible = "fsl,mpc8349-memory-controller", },
cd1542c8
AV		 1214 { .compatible = "fsl,p1020-memory-controller", },
1215 { .compatible = "fsl,p1021-memory-controller", },
a014554e 1216 { .compatible = "fsl,p2020-memory-controller", },
86f9a433 1217 { .compatible = "fsl,qoriq-memory-controller", },
a9a753d5
DJ		 1218 {},
1219};
952e1c66 1220MODULE_DEVICE_TABLE(of, mpc85xx_mc_err_of_match);
a9a753d5 1221
00006124 1222static struct platform_driver mpc85xx_mc_err_driver = {
a9a753d5
DJ		 1223 .probe = mpc85xx_mc_err_probe,
1224 .remove = mpc85xx_mc_err_remove,
1225 .driver = {
4018294b 1226 .name = "mpc85xx_mc_err",
4018294b
GL		 1227 .of_match_table = mpc85xx_mc_err_of_match,
1228 },
a9a753d5
DJ		 1229};
1230
d54051f1
TR		 1231static struct platform_driver * const drivers[] = {
1232 &mpc85xx_mc_err_driver,
1233 &mpc85xx_l2_err_driver,
666db563
SW		 1234#ifdef CONFIG_PCI
1235 &mpc85xx_pci_err_driver,
1236#endif
d54051f1
TR		 1237};
1238
a9a753d5
DJ		 1239static int __init mpc85xx_mc_init(void)
1240{
1241 int res = 0;
f2b59ac6 1242 u32 __maybe_unused pvr = 0;
a9a753d5
DJ		 1243
1244 printk(KERN_INFO "Freescale(R) MPC85xx EDAC driver, "
1245 "(C) 2006 Montavista Software\n");
1246
1247 /* make sure error reporting method is sane */
1248 switch (edac_op_state) {
1249 case EDAC_OPSTATE_POLL:
1250 case EDAC_OPSTATE_INT:
1251 break;
1252 default:
1253 edac_op_state = EDAC_OPSTATE_INT;
1254 break;
1255 }
1256
d54051f1 1257 res = platform_register_drivers(drivers, ARRAY_SIZE(drivers));
a9a753d5 1258 if (res)
d54051f1 1259 printk(KERN_WARNING EDAC_MOD_STR "drivers fail to register\n");
a9a753d5 1260
a9a753d5
DJ		 1261 return 0;
1262}
1263
1264module_init(mpc85xx_mc_init);
1265
1266static void __exit mpc85xx_mc_exit(void)
1267{
d54051f1 1268 platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
a9a753d5
DJ		 1269}
1270
1271module_exit(mpc85xx_mc_exit);
1272
1273MODULE_LICENSE("GPL");
1274MODULE_AUTHOR("Montavista Software, Inc.");
1275module_param(edac_op_state, int, 0444);
1276MODULE_PARM_DESC(edac_op_state,
1277 "EDAC Error Reporting state: 0=Poll, 2=Interrupt");
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