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a9a753d5 DJ |
1 | /* |
2 | * Freescale MPC85xx Memory Controller kenel module | |
3 | * | |
4 | * Author: Dave Jiang <djiang@mvista.com> | |
5 | * | |
6 | * 2006-2007 (c) MontaVista Software, Inc. This file is licensed under | |
7 | * the terms of the GNU General Public License version 2. This program | |
8 | * is licensed "as is" without any warranty of any kind, whether express | |
9 | * or implied. | |
10 | * | |
11 | */ | |
12 | #include <linux/module.h> | |
13 | #include <linux/init.h> | |
a9a753d5 DJ |
14 | #include <linux/interrupt.h> |
15 | #include <linux/ctype.h> | |
16 | #include <linux/io.h> | |
17 | #include <linux/mod_devicetable.h> | |
18 | #include <linux/edac.h> | |
60be7551 | 19 | #include <linux/smp.h> |
5a0e3ad6 | 20 | #include <linux/gfp.h> |
a9a753d5 DJ |
21 | |
22 | #include <linux/of_platform.h> | |
23 | #include <linux/of_device.h> | |
a9a753d5 DJ |
24 | #include "edac_module.h" |
25 | #include "edac_core.h" | |
26 | #include "mpc85xx_edac.h" | |
27 | ||
28 | static int edac_dev_idx; | |
0616fb00 | 29 | #ifdef CONFIG_PCI |
a9a753d5 | 30 | static int edac_pci_idx; |
0616fb00 | 31 | #endif |
a9a753d5 DJ |
32 | static int edac_mc_idx; |
33 | ||
34 | static u32 orig_ddr_err_disable; | |
35 | static u32 orig_ddr_err_sbe; | |
36 | ||
37 | /* | |
38 | * PCI Err defines | |
39 | */ | |
40 | #ifdef CONFIG_PCI | |
41 | static u32 orig_pci_err_cap_dr; | |
42 | static u32 orig_pci_err_en; | |
43 | #endif | |
44 | ||
45 | static u32 orig_l2_err_disable; | |
bd1688dc | 46 | #ifdef CONFIG_FSL_SOC_BOOKE |
60be7551 | 47 | static u32 orig_hid1[2]; |
b4846251 | 48 | #endif |
a9a753d5 | 49 | |
a9a753d5 DJ |
50 | /************************ MC SYSFS parts ***********************************/ |
51 | ||
52 | static ssize_t mpc85xx_mc_inject_data_hi_show(struct mem_ctl_info *mci, | |
53 | char *data) | |
54 | { | |
55 | struct mpc85xx_mc_pdata *pdata = mci->pvt_info; | |
56 | return sprintf(data, "0x%08x", | |
57 | in_be32(pdata->mc_vbase + | |
58 | MPC85XX_MC_DATA_ERR_INJECT_HI)); | |
59 | } | |
60 | ||
61 | static ssize_t mpc85xx_mc_inject_data_lo_show(struct mem_ctl_info *mci, | |
62 | char *data) | |
63 | { | |
64 | struct mpc85xx_mc_pdata *pdata = mci->pvt_info; | |
65 | return sprintf(data, "0x%08x", | |
66 | in_be32(pdata->mc_vbase + | |
67 | MPC85XX_MC_DATA_ERR_INJECT_LO)); | |
68 | } | |
69 | ||
70 | static ssize_t mpc85xx_mc_inject_ctrl_show(struct mem_ctl_info *mci, char *data) | |
71 | { | |
72 | struct mpc85xx_mc_pdata *pdata = mci->pvt_info; | |
73 | return sprintf(data, "0x%08x", | |
74 | in_be32(pdata->mc_vbase + MPC85XX_MC_ECC_ERR_INJECT)); | |
75 | } | |
76 | ||
77 | static ssize_t mpc85xx_mc_inject_data_hi_store(struct mem_ctl_info *mci, | |
78 | const char *data, size_t count) | |
79 | { | |
80 | struct mpc85xx_mc_pdata *pdata = mci->pvt_info; | |
81 | if (isdigit(*data)) { | |
82 | out_be32(pdata->mc_vbase + MPC85XX_MC_DATA_ERR_INJECT_HI, | |
83 | simple_strtoul(data, NULL, 0)); | |
84 | return count; | |
85 | } | |
86 | return 0; | |
87 | } | |
88 | ||
89 | static ssize_t mpc85xx_mc_inject_data_lo_store(struct mem_ctl_info *mci, | |
90 | const char *data, size_t count) | |
91 | { | |
92 | struct mpc85xx_mc_pdata *pdata = mci->pvt_info; | |
93 | if (isdigit(*data)) { | |
94 | out_be32(pdata->mc_vbase + MPC85XX_MC_DATA_ERR_INJECT_LO, | |
95 | simple_strtoul(data, NULL, 0)); | |
96 | return count; | |
97 | } | |
98 | return 0; | |
99 | } | |
100 | ||
101 | static ssize_t mpc85xx_mc_inject_ctrl_store(struct mem_ctl_info *mci, | |
102 | const char *data, size_t count) | |
103 | { | |
104 | struct mpc85xx_mc_pdata *pdata = mci->pvt_info; | |
105 | if (isdigit(*data)) { | |
106 | out_be32(pdata->mc_vbase + MPC85XX_MC_ECC_ERR_INJECT, | |
107 | simple_strtoul(data, NULL, 0)); | |
108 | return count; | |
109 | } | |
110 | return 0; | |
111 | } | |
112 | ||
113 | static struct mcidev_sysfs_attribute mpc85xx_mc_sysfs_attributes[] = { | |
114 | { | |
115 | .attr = { | |
116 | .name = "inject_data_hi", | |
117 | .mode = (S_IRUGO | S_IWUSR) | |
118 | }, | |
119 | .show = mpc85xx_mc_inject_data_hi_show, | |
120 | .store = mpc85xx_mc_inject_data_hi_store}, | |
121 | { | |
122 | .attr = { | |
123 | .name = "inject_data_lo", | |
124 | .mode = (S_IRUGO | S_IWUSR) | |
125 | }, | |
126 | .show = mpc85xx_mc_inject_data_lo_show, | |
127 | .store = mpc85xx_mc_inject_data_lo_store}, | |
128 | { | |
129 | .attr = { | |
130 | .name = "inject_ctrl", | |
131 | .mode = (S_IRUGO | S_IWUSR) | |
132 | }, | |
133 | .show = mpc85xx_mc_inject_ctrl_show, | |
134 | .store = mpc85xx_mc_inject_ctrl_store}, | |
135 | ||
136 | /* End of list */ | |
137 | { | |
138 | .attr = {.name = NULL} | |
139 | } | |
140 | }; | |
141 | ||
142 | static void mpc85xx_set_mc_sysfs_attributes(struct mem_ctl_info *mci) | |
143 | { | |
144 | mci->mc_driver_sysfs_attributes = mpc85xx_mc_sysfs_attributes; | |
145 | } | |
146 | ||
147 | /**************************** PCI Err device ***************************/ | |
148 | #ifdef CONFIG_PCI | |
149 | ||
150 | static void mpc85xx_pci_check(struct edac_pci_ctl_info *pci) | |
151 | { | |
152 | struct mpc85xx_pci_pdata *pdata = pci->pvt_info; | |
153 | u32 err_detect; | |
154 | ||
155 | err_detect = in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR); | |
156 | ||
157 | /* master aborts can happen during PCI config cycles */ | |
158 | if (!(err_detect & ~(PCI_EDE_MULTI_ERR | PCI_EDE_MST_ABRT))) { | |
159 | out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, err_detect); | |
160 | return; | |
161 | } | |
162 | ||
163 | printk(KERN_ERR "PCI error(s) detected\n"); | |
164 | printk(KERN_ERR "PCI/X ERR_DR register: %#08x\n", err_detect); | |
165 | ||
166 | printk(KERN_ERR "PCI/X ERR_ATTRIB register: %#08x\n", | |
167 | in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ATTRIB)); | |
168 | printk(KERN_ERR "PCI/X ERR_ADDR register: %#08x\n", | |
169 | in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ADDR)); | |
170 | printk(KERN_ERR "PCI/X ERR_EXT_ADDR register: %#08x\n", | |
171 | in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EXT_ADDR)); | |
172 | printk(KERN_ERR "PCI/X ERR_DL register: %#08x\n", | |
173 | in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DL)); | |
174 | printk(KERN_ERR "PCI/X ERR_DH register: %#08x\n", | |
175 | in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DH)); | |
176 | ||
177 | /* clear error bits */ | |
178 | out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, err_detect); | |
179 | ||
180 | if (err_detect & PCI_EDE_PERR_MASK) | |
181 | edac_pci_handle_pe(pci, pci->ctl_name); | |
182 | ||
183 | if ((err_detect & ~PCI_EDE_MULTI_ERR) & ~PCI_EDE_PERR_MASK) | |
184 | edac_pci_handle_npe(pci, pci->ctl_name); | |
185 | } | |
186 | ||
187 | static irqreturn_t mpc85xx_pci_isr(int irq, void *dev_id) | |
188 | { | |
189 | struct edac_pci_ctl_info *pci = dev_id; | |
190 | struct mpc85xx_pci_pdata *pdata = pci->pvt_info; | |
191 | u32 err_detect; | |
192 | ||
193 | err_detect = in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR); | |
194 | ||
195 | if (!err_detect) | |
196 | return IRQ_NONE; | |
197 | ||
198 | mpc85xx_pci_check(pci); | |
199 | ||
200 | return IRQ_HANDLED; | |
201 | } | |
202 | ||
00006124 | 203 | static int __devinit mpc85xx_pci_err_probe(struct platform_device *op) |
a9a753d5 DJ |
204 | { |
205 | struct edac_pci_ctl_info *pci; | |
206 | struct mpc85xx_pci_pdata *pdata; | |
f87bd330 | 207 | struct resource r; |
a9a753d5 DJ |
208 | int res = 0; |
209 | ||
f87bd330 | 210 | if (!devres_open_group(&op->dev, mpc85xx_pci_err_probe, GFP_KERNEL)) |
a9a753d5 DJ |
211 | return -ENOMEM; |
212 | ||
213 | pci = edac_pci_alloc_ctl_info(sizeof(*pdata), "mpc85xx_pci_err"); | |
214 | if (!pci) | |
215 | return -ENOMEM; | |
216 | ||
217 | pdata = pci->pvt_info; | |
218 | pdata->name = "mpc85xx_pci_err"; | |
219 | pdata->irq = NO_IRQ; | |
f87bd330 DJ |
220 | dev_set_drvdata(&op->dev, pci); |
221 | pci->dev = &op->dev; | |
a9a753d5 DJ |
222 | pci->mod_name = EDAC_MOD_STR; |
223 | pci->ctl_name = pdata->name; | |
031d5518 | 224 | pci->dev_name = dev_name(&op->dev); |
a9a753d5 DJ |
225 | |
226 | if (edac_op_state == EDAC_OPSTATE_POLL) | |
227 | pci->edac_check = mpc85xx_pci_check; | |
228 | ||
229 | pdata->edac_idx = edac_pci_idx++; | |
230 | ||
a26f95fe | 231 | res = of_address_to_resource(op->dev.of_node, 0, &r); |
f87bd330 | 232 | if (res) { |
a9a753d5 DJ |
233 | printk(KERN_ERR "%s: Unable to get resource for " |
234 | "PCI err regs\n", __func__); | |
235 | goto err; | |
236 | } | |
237 | ||
f87bd330 DJ |
238 | /* we only need the error registers */ |
239 | r.start += 0xe00; | |
240 | ||
66ed3f75 HS |
241 | if (!devm_request_mem_region(&op->dev, r.start, resource_size(&r), |
242 | pdata->name)) { | |
a9a753d5 DJ |
243 | printk(KERN_ERR "%s: Error while requesting mem region\n", |
244 | __func__); | |
245 | res = -EBUSY; | |
246 | goto err; | |
247 | } | |
248 | ||
66ed3f75 | 249 | pdata->pci_vbase = devm_ioremap(&op->dev, r.start, resource_size(&r)); |
a9a753d5 DJ |
250 | if (!pdata->pci_vbase) { |
251 | printk(KERN_ERR "%s: Unable to setup PCI err regs\n", __func__); | |
252 | res = -ENOMEM; | |
253 | goto err; | |
254 | } | |
255 | ||
256 | orig_pci_err_cap_dr = | |
257 | in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_CAP_DR); | |
258 | ||
259 | /* PCI master abort is expected during config cycles */ | |
260 | out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_CAP_DR, 0x40); | |
261 | ||
262 | orig_pci_err_en = in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN); | |
263 | ||
264 | /* disable master abort reporting */ | |
265 | out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN, ~0x40); | |
266 | ||
267 | /* clear error bits */ | |
268 | out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, ~0); | |
269 | ||
270 | if (edac_pci_add_device(pci, pdata->edac_idx) > 0) { | |
271 | debugf3("%s(): failed edac_pci_add_device()\n", __func__); | |
272 | goto err; | |
273 | } | |
274 | ||
275 | if (edac_op_state == EDAC_OPSTATE_INT) { | |
a26f95fe | 276 | pdata->irq = irq_of_parse_and_map(op->dev.of_node, 0); |
f87bd330 | 277 | res = devm_request_irq(&op->dev, pdata->irq, |
a9a753d5 DJ |
278 | mpc85xx_pci_isr, IRQF_DISABLED, |
279 | "[EDAC] PCI err", pci); | |
280 | if (res < 0) { | |
281 | printk(KERN_ERR | |
282 | "%s: Unable to requiest irq %d for " | |
283 | "MPC85xx PCI err\n", __func__, pdata->irq); | |
f87bd330 | 284 | irq_dispose_mapping(pdata->irq); |
a9a753d5 DJ |
285 | res = -ENODEV; |
286 | goto err2; | |
287 | } | |
288 | ||
289 | printk(KERN_INFO EDAC_MOD_STR " acquired irq %d for PCI Err\n", | |
290 | pdata->irq); | |
291 | } | |
292 | ||
f87bd330 | 293 | devres_remove_group(&op->dev, mpc85xx_pci_err_probe); |
a9a753d5 DJ |
294 | debugf3("%s(): success\n", __func__); |
295 | printk(KERN_INFO EDAC_MOD_STR " PCI err registered\n"); | |
296 | ||
297 | return 0; | |
298 | ||
299 | err2: | |
f87bd330 | 300 | edac_pci_del_device(&op->dev); |
a9a753d5 DJ |
301 | err: |
302 | edac_pci_free_ctl_info(pci); | |
f87bd330 | 303 | devres_release_group(&op->dev, mpc85xx_pci_err_probe); |
a9a753d5 DJ |
304 | return res; |
305 | } | |
306 | ||
2dc11581 | 307 | static int mpc85xx_pci_err_remove(struct platform_device *op) |
a9a753d5 | 308 | { |
f87bd330 | 309 | struct edac_pci_ctl_info *pci = dev_get_drvdata(&op->dev); |
a9a753d5 DJ |
310 | struct mpc85xx_pci_pdata *pdata = pci->pvt_info; |
311 | ||
312 | debugf0("%s()\n", __func__); | |
313 | ||
314 | out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_CAP_DR, | |
315 | orig_pci_err_cap_dr); | |
316 | ||
317 | out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN, orig_pci_err_en); | |
318 | ||
319 | edac_pci_del_device(pci->dev); | |
320 | ||
321 | if (edac_op_state == EDAC_OPSTATE_INT) | |
322 | irq_dispose_mapping(pdata->irq); | |
323 | ||
324 | edac_pci_free_ctl_info(pci); | |
325 | ||
326 | return 0; | |
327 | } | |
328 | ||
f87bd330 DJ |
329 | static struct of_device_id mpc85xx_pci_err_of_match[] = { |
330 | { | |
331 | .compatible = "fsl,mpc8540-pcix", | |
332 | }, | |
333 | { | |
334 | .compatible = "fsl,mpc8540-pci", | |
335 | }, | |
336 | {}, | |
337 | }; | |
952e1c66 | 338 | MODULE_DEVICE_TABLE(of, mpc85xx_pci_err_of_match); |
f87bd330 | 339 | |
00006124 | 340 | static struct platform_driver mpc85xx_pci_err_driver = { |
a9a753d5 DJ |
341 | .probe = mpc85xx_pci_err_probe, |
342 | .remove = __devexit_p(mpc85xx_pci_err_remove), | |
343 | .driver = { | |
4018294b GL |
344 | .name = "mpc85xx_pci_err", |
345 | .owner = THIS_MODULE, | |
346 | .of_match_table = mpc85xx_pci_err_of_match, | |
347 | }, | |
a9a753d5 DJ |
348 | }; |
349 | ||
350 | #endif /* CONFIG_PCI */ | |
351 | ||
352 | /**************************** L2 Err device ***************************/ | |
353 | ||
354 | /************************ L2 SYSFS parts ***********************************/ | |
355 | ||
356 | static ssize_t mpc85xx_l2_inject_data_hi_show(struct edac_device_ctl_info | |
357 | *edac_dev, char *data) | |
358 | { | |
359 | struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; | |
360 | return sprintf(data, "0x%08x", | |
361 | in_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJHI)); | |
362 | } | |
363 | ||
364 | static ssize_t mpc85xx_l2_inject_data_lo_show(struct edac_device_ctl_info | |
365 | *edac_dev, char *data) | |
366 | { | |
367 | struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; | |
368 | return sprintf(data, "0x%08x", | |
369 | in_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJLO)); | |
370 | } | |
371 | ||
372 | static ssize_t mpc85xx_l2_inject_ctrl_show(struct edac_device_ctl_info | |
373 | *edac_dev, char *data) | |
374 | { | |
375 | struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; | |
376 | return sprintf(data, "0x%08x", | |
377 | in_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJCTL)); | |
378 | } | |
379 | ||
380 | static ssize_t mpc85xx_l2_inject_data_hi_store(struct edac_device_ctl_info | |
381 | *edac_dev, const char *data, | |
382 | size_t count) | |
383 | { | |
384 | struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; | |
385 | if (isdigit(*data)) { | |
386 | out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJHI, | |
387 | simple_strtoul(data, NULL, 0)); | |
388 | return count; | |
389 | } | |
390 | return 0; | |
391 | } | |
392 | ||
393 | static ssize_t mpc85xx_l2_inject_data_lo_store(struct edac_device_ctl_info | |
394 | *edac_dev, const char *data, | |
395 | size_t count) | |
396 | { | |
397 | struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; | |
398 | if (isdigit(*data)) { | |
399 | out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJLO, | |
400 | simple_strtoul(data, NULL, 0)); | |
401 | return count; | |
402 | } | |
403 | return 0; | |
404 | } | |
405 | ||
406 | static ssize_t mpc85xx_l2_inject_ctrl_store(struct edac_device_ctl_info | |
407 | *edac_dev, const char *data, | |
408 | size_t count) | |
409 | { | |
410 | struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; | |
411 | if (isdigit(*data)) { | |
412 | out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJCTL, | |
413 | simple_strtoul(data, NULL, 0)); | |
414 | return count; | |
415 | } | |
416 | return 0; | |
417 | } | |
418 | ||
419 | static struct edac_dev_sysfs_attribute mpc85xx_l2_sysfs_attributes[] = { | |
420 | { | |
421 | .attr = { | |
422 | .name = "inject_data_hi", | |
423 | .mode = (S_IRUGO | S_IWUSR) | |
424 | }, | |
425 | .show = mpc85xx_l2_inject_data_hi_show, | |
426 | .store = mpc85xx_l2_inject_data_hi_store}, | |
427 | { | |
428 | .attr = { | |
429 | .name = "inject_data_lo", | |
430 | .mode = (S_IRUGO | S_IWUSR) | |
431 | }, | |
432 | .show = mpc85xx_l2_inject_data_lo_show, | |
433 | .store = mpc85xx_l2_inject_data_lo_store}, | |
434 | { | |
435 | .attr = { | |
436 | .name = "inject_ctrl", | |
437 | .mode = (S_IRUGO | S_IWUSR) | |
438 | }, | |
439 | .show = mpc85xx_l2_inject_ctrl_show, | |
440 | .store = mpc85xx_l2_inject_ctrl_store}, | |
441 | ||
442 | /* End of list */ | |
443 | { | |
444 | .attr = {.name = NULL} | |
445 | } | |
446 | }; | |
447 | ||
448 | static void mpc85xx_set_l2_sysfs_attributes(struct edac_device_ctl_info | |
449 | *edac_dev) | |
450 | { | |
451 | edac_dev->sysfs_attributes = mpc85xx_l2_sysfs_attributes; | |
452 | } | |
453 | ||
454 | /***************************** L2 ops ***********************************/ | |
455 | ||
456 | static void mpc85xx_l2_check(struct edac_device_ctl_info *edac_dev) | |
457 | { | |
458 | struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; | |
459 | u32 err_detect; | |
460 | ||
461 | err_detect = in_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET); | |
462 | ||
463 | if (!(err_detect & L2_EDE_MASK)) | |
464 | return; | |
465 | ||
466 | printk(KERN_ERR "ECC Error in CPU L2 cache\n"); | |
467 | printk(KERN_ERR "L2 Error Detect Register: 0x%08x\n", err_detect); | |
468 | printk(KERN_ERR "L2 Error Capture Data High Register: 0x%08x\n", | |
469 | in_be32(pdata->l2_vbase + MPC85XX_L2_CAPTDATAHI)); | |
470 | printk(KERN_ERR "L2 Error Capture Data Lo Register: 0x%08x\n", | |
471 | in_be32(pdata->l2_vbase + MPC85XX_L2_CAPTDATALO)); | |
472 | printk(KERN_ERR "L2 Error Syndrome Register: 0x%08x\n", | |
473 | in_be32(pdata->l2_vbase + MPC85XX_L2_CAPTECC)); | |
474 | printk(KERN_ERR "L2 Error Attributes Capture Register: 0x%08x\n", | |
475 | in_be32(pdata->l2_vbase + MPC85XX_L2_ERRATTR)); | |
476 | printk(KERN_ERR "L2 Error Address Capture Register: 0x%08x\n", | |
477 | in_be32(pdata->l2_vbase + MPC85XX_L2_ERRADDR)); | |
478 | ||
479 | /* clear error detect register */ | |
480 | out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET, err_detect); | |
481 | ||
482 | if (err_detect & L2_EDE_CE_MASK) | |
483 | edac_device_handle_ce(edac_dev, 0, 0, edac_dev->ctl_name); | |
484 | ||
485 | if (err_detect & L2_EDE_UE_MASK) | |
486 | edac_device_handle_ue(edac_dev, 0, 0, edac_dev->ctl_name); | |
487 | } | |
488 | ||
489 | static irqreturn_t mpc85xx_l2_isr(int irq, void *dev_id) | |
490 | { | |
491 | struct edac_device_ctl_info *edac_dev = dev_id; | |
492 | struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; | |
493 | u32 err_detect; | |
494 | ||
495 | err_detect = in_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET); | |
496 | ||
497 | if (!(err_detect & L2_EDE_MASK)) | |
498 | return IRQ_NONE; | |
499 | ||
500 | mpc85xx_l2_check(edac_dev); | |
501 | ||
502 | return IRQ_HANDLED; | |
503 | } | |
504 | ||
00006124 | 505 | static int __devinit mpc85xx_l2_err_probe(struct platform_device *op) |
a9a753d5 DJ |
506 | { |
507 | struct edac_device_ctl_info *edac_dev; | |
508 | struct mpc85xx_l2_pdata *pdata; | |
509 | struct resource r; | |
510 | int res; | |
511 | ||
512 | if (!devres_open_group(&op->dev, mpc85xx_l2_err_probe, GFP_KERNEL)) | |
513 | return -ENOMEM; | |
514 | ||
515 | edac_dev = edac_device_alloc_ctl_info(sizeof(*pdata), | |
516 | "cpu", 1, "L", 1, 2, NULL, 0, | |
517 | edac_dev_idx); | |
518 | if (!edac_dev) { | |
519 | devres_release_group(&op->dev, mpc85xx_l2_err_probe); | |
520 | return -ENOMEM; | |
521 | } | |
522 | ||
523 | pdata = edac_dev->pvt_info; | |
524 | pdata->name = "mpc85xx_l2_err"; | |
525 | pdata->irq = NO_IRQ; | |
526 | edac_dev->dev = &op->dev; | |
527 | dev_set_drvdata(edac_dev->dev, edac_dev); | |
528 | edac_dev->ctl_name = pdata->name; | |
529 | edac_dev->dev_name = pdata->name; | |
530 | ||
a26f95fe | 531 | res = of_address_to_resource(op->dev.of_node, 0, &r); |
a9a753d5 DJ |
532 | if (res) { |
533 | printk(KERN_ERR "%s: Unable to get resource for " | |
534 | "L2 err regs\n", __func__); | |
535 | goto err; | |
536 | } | |
537 | ||
538 | /* we only need the error registers */ | |
539 | r.start += 0xe00; | |
540 | ||
28f65c11 JP |
541 | if (!devm_request_mem_region(&op->dev, r.start, resource_size(&r), |
542 | pdata->name)) { | |
a9a753d5 DJ |
543 | printk(KERN_ERR "%s: Error while requesting mem region\n", |
544 | __func__); | |
545 | res = -EBUSY; | |
546 | goto err; | |
547 | } | |
548 | ||
28f65c11 | 549 | pdata->l2_vbase = devm_ioremap(&op->dev, r.start, resource_size(&r)); |
a9a753d5 DJ |
550 | if (!pdata->l2_vbase) { |
551 | printk(KERN_ERR "%s: Unable to setup L2 err regs\n", __func__); | |
552 | res = -ENOMEM; | |
553 | goto err; | |
554 | } | |
555 | ||
556 | out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET, ~0); | |
557 | ||
558 | orig_l2_err_disable = in_be32(pdata->l2_vbase + MPC85XX_L2_ERRDIS); | |
559 | ||
560 | /* clear the err_dis */ | |
561 | out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDIS, 0); | |
562 | ||
563 | edac_dev->mod_name = EDAC_MOD_STR; | |
564 | ||
565 | if (edac_op_state == EDAC_OPSTATE_POLL) | |
566 | edac_dev->edac_check = mpc85xx_l2_check; | |
567 | ||
568 | mpc85xx_set_l2_sysfs_attributes(edac_dev); | |
569 | ||
570 | pdata->edac_idx = edac_dev_idx++; | |
571 | ||
572 | if (edac_device_add_device(edac_dev) > 0) { | |
573 | debugf3("%s(): failed edac_device_add_device()\n", __func__); | |
574 | goto err; | |
575 | } | |
576 | ||
577 | if (edac_op_state == EDAC_OPSTATE_INT) { | |
a26f95fe | 578 | pdata->irq = irq_of_parse_and_map(op->dev.of_node, 0); |
a9a753d5 DJ |
579 | res = devm_request_irq(&op->dev, pdata->irq, |
580 | mpc85xx_l2_isr, IRQF_DISABLED, | |
581 | "[EDAC] L2 err", edac_dev); | |
582 | if (res < 0) { | |
583 | printk(KERN_ERR | |
584 | "%s: Unable to requiest irq %d for " | |
585 | "MPC85xx L2 err\n", __func__, pdata->irq); | |
586 | irq_dispose_mapping(pdata->irq); | |
587 | res = -ENODEV; | |
588 | goto err2; | |
589 | } | |
590 | ||
591 | printk(KERN_INFO EDAC_MOD_STR " acquired irq %d for L2 Err\n", | |
592 | pdata->irq); | |
593 | ||
594 | edac_dev->op_state = OP_RUNNING_INTERRUPT; | |
595 | ||
596 | out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINTEN, L2_EIE_MASK); | |
597 | } | |
598 | ||
599 | devres_remove_group(&op->dev, mpc85xx_l2_err_probe); | |
600 | ||
601 | debugf3("%s(): success\n", __func__); | |
602 | printk(KERN_INFO EDAC_MOD_STR " L2 err registered\n"); | |
603 | ||
604 | return 0; | |
605 | ||
606 | err2: | |
607 | edac_device_del_device(&op->dev); | |
608 | err: | |
609 | devres_release_group(&op->dev, mpc85xx_l2_err_probe); | |
610 | edac_device_free_ctl_info(edac_dev); | |
611 | return res; | |
612 | } | |
613 | ||
2dc11581 | 614 | static int mpc85xx_l2_err_remove(struct platform_device *op) |
a9a753d5 DJ |
615 | { |
616 | struct edac_device_ctl_info *edac_dev = dev_get_drvdata(&op->dev); | |
617 | struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; | |
618 | ||
619 | debugf0("%s()\n", __func__); | |
620 | ||
621 | if (edac_op_state == EDAC_OPSTATE_INT) { | |
622 | out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINTEN, 0); | |
623 | irq_dispose_mapping(pdata->irq); | |
624 | } | |
625 | ||
626 | out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDIS, orig_l2_err_disable); | |
627 | edac_device_del_device(&op->dev); | |
628 | edac_device_free_ctl_info(edac_dev); | |
629 | return 0; | |
630 | } | |
631 | ||
632 | static struct of_device_id mpc85xx_l2_err_of_match[] = { | |
29d6cf26 KG |
633 | /* deprecate the fsl,85.. forms in the future, 2.6.30? */ |
634 | { .compatible = "fsl,8540-l2-cache-controller", }, | |
635 | { .compatible = "fsl,8541-l2-cache-controller", }, | |
636 | { .compatible = "fsl,8544-l2-cache-controller", }, | |
637 | { .compatible = "fsl,8548-l2-cache-controller", }, | |
638 | { .compatible = "fsl,8555-l2-cache-controller", }, | |
639 | { .compatible = "fsl,8568-l2-cache-controller", }, | |
640 | { .compatible = "fsl,mpc8536-l2-cache-controller", }, | |
641 | { .compatible = "fsl,mpc8540-l2-cache-controller", }, | |
642 | { .compatible = "fsl,mpc8541-l2-cache-controller", }, | |
643 | { .compatible = "fsl,mpc8544-l2-cache-controller", }, | |
644 | { .compatible = "fsl,mpc8548-l2-cache-controller", }, | |
645 | { .compatible = "fsl,mpc8555-l2-cache-controller", }, | |
646 | { .compatible = "fsl,mpc8560-l2-cache-controller", }, | |
647 | { .compatible = "fsl,mpc8568-l2-cache-controller", }, | |
cd1542c8 | 648 | { .compatible = "fsl,mpc8569-l2-cache-controller", }, |
29d6cf26 | 649 | { .compatible = "fsl,mpc8572-l2-cache-controller", }, |
cd1542c8 AV |
650 | { .compatible = "fsl,p1020-l2-cache-controller", }, |
651 | { .compatible = "fsl,p1021-l2-cache-controller", }, | |
a014554e | 652 | { .compatible = "fsl,p2020-l2-cache-controller", }, |
a9a753d5 DJ |
653 | {}, |
654 | }; | |
952e1c66 | 655 | MODULE_DEVICE_TABLE(of, mpc85xx_l2_err_of_match); |
a9a753d5 | 656 | |
00006124 | 657 | static struct platform_driver mpc85xx_l2_err_driver = { |
a9a753d5 DJ |
658 | .probe = mpc85xx_l2_err_probe, |
659 | .remove = mpc85xx_l2_err_remove, | |
660 | .driver = { | |
4018294b GL |
661 | .name = "mpc85xx_l2_err", |
662 | .owner = THIS_MODULE, | |
663 | .of_match_table = mpc85xx_l2_err_of_match, | |
664 | }, | |
a9a753d5 DJ |
665 | }; |
666 | ||
667 | /**************************** MC Err device ***************************/ | |
668 | ||
dcca7c3d PT |
669 | /* |
670 | * Taken from table 8-55 in the MPC8641 User's Manual and/or 9-61 in the | |
671 | * MPC8572 User's Manual. Each line represents a syndrome bit column as a | |
672 | * 64-bit value, but split into an upper and lower 32-bit chunk. The labels | |
673 | * below correspond to Freescale's manuals. | |
674 | */ | |
675 | static unsigned int ecc_table[16] = { | |
676 | /* MSB LSB */ | |
677 | /* [0:31] [32:63] */ | |
678 | 0xf00fe11e, 0xc33c0ff7, /* Syndrome bit 7 */ | |
679 | 0x00ff00ff, 0x00fff0ff, | |
680 | 0x0f0f0f0f, 0x0f0fff00, | |
681 | 0x11113333, 0x7777000f, | |
682 | 0x22224444, 0x8888222f, | |
683 | 0x44448888, 0xffff4441, | |
684 | 0x8888ffff, 0x11118882, | |
685 | 0xffff1111, 0x22221114, /* Syndrome bit 0 */ | |
686 | }; | |
687 | ||
688 | /* | |
689 | * Calculate the correct ECC value for a 64-bit value specified by high:low | |
690 | */ | |
691 | static u8 calculate_ecc(u32 high, u32 low) | |
692 | { | |
693 | u32 mask_low; | |
694 | u32 mask_high; | |
695 | int bit_cnt; | |
696 | u8 ecc = 0; | |
697 | int i; | |
698 | int j; | |
699 | ||
700 | for (i = 0; i < 8; i++) { | |
701 | mask_high = ecc_table[i * 2]; | |
702 | mask_low = ecc_table[i * 2 + 1]; | |
703 | bit_cnt = 0; | |
704 | ||
705 | for (j = 0; j < 32; j++) { | |
706 | if ((mask_high >> j) & 1) | |
707 | bit_cnt ^= (high >> j) & 1; | |
708 | if ((mask_low >> j) & 1) | |
709 | bit_cnt ^= (low >> j) & 1; | |
710 | } | |
711 | ||
712 | ecc |= bit_cnt << i; | |
713 | } | |
714 | ||
715 | return ecc; | |
716 | } | |
717 | ||
718 | /* | |
719 | * Create the syndrome code which is generated if the data line specified by | |
720 | * 'bit' failed. Eg generate an 8-bit codes seen in Table 8-55 in the MPC8641 | |
721 | * User's Manual and 9-61 in the MPC8572 User's Manual. | |
722 | */ | |
723 | static u8 syndrome_from_bit(unsigned int bit) { | |
724 | int i; | |
725 | u8 syndrome = 0; | |
726 | ||
727 | /* | |
728 | * Cycle through the upper or lower 32-bit portion of each value in | |
729 | * ecc_table depending on if 'bit' is in the upper or lower half of | |
730 | * 64-bit data. | |
731 | */ | |
732 | for (i = bit < 32; i < 16; i += 2) | |
733 | syndrome |= ((ecc_table[i] >> (bit % 32)) & 1) << (i / 2); | |
734 | ||
735 | return syndrome; | |
736 | } | |
737 | ||
738 | /* | |
739 | * Decode data and ecc syndrome to determine what went wrong | |
740 | * Note: This can only decode single-bit errors | |
741 | */ | |
742 | static void sbe_ecc_decode(u32 cap_high, u32 cap_low, u32 cap_ecc, | |
743 | int *bad_data_bit, int *bad_ecc_bit) | |
744 | { | |
745 | int i; | |
746 | u8 syndrome; | |
747 | ||
748 | *bad_data_bit = -1; | |
749 | *bad_ecc_bit = -1; | |
750 | ||
751 | /* | |
752 | * Calculate the ECC of the captured data and XOR it with the captured | |
753 | * ECC to find an ECC syndrome value we can search for | |
754 | */ | |
755 | syndrome = calculate_ecc(cap_high, cap_low) ^ cap_ecc; | |
756 | ||
757 | /* Check if a data line is stuck... */ | |
758 | for (i = 0; i < 64; i++) { | |
759 | if (syndrome == syndrome_from_bit(i)) { | |
760 | *bad_data_bit = i; | |
761 | return; | |
762 | } | |
763 | } | |
764 | ||
765 | /* If data is correct, check ECC bits for errors... */ | |
766 | for (i = 0; i < 8; i++) { | |
767 | if ((syndrome >> i) & 0x1) { | |
768 | *bad_ecc_bit = i; | |
769 | return; | |
770 | } | |
771 | } | |
772 | } | |
773 | ||
a9a753d5 DJ |
774 | static void mpc85xx_mc_check(struct mem_ctl_info *mci) |
775 | { | |
776 | struct mpc85xx_mc_pdata *pdata = mci->pvt_info; | |
777 | struct csrow_info *csrow; | |
21768639 | 778 | u32 bus_width; |
a9a753d5 DJ |
779 | u32 err_detect; |
780 | u32 syndrome; | |
781 | u32 err_addr; | |
782 | u32 pfn; | |
783 | int row_index; | |
dcca7c3d PT |
784 | u32 cap_high; |
785 | u32 cap_low; | |
786 | int bad_data_bit; | |
787 | int bad_ecc_bit; | |
a9a753d5 DJ |
788 | |
789 | err_detect = in_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT); | |
55e5750b | 790 | if (!err_detect) |
a9a753d5 DJ |
791 | return; |
792 | ||
793 | mpc85xx_mc_printk(mci, KERN_ERR, "Err Detect Register: %#8.8x\n", | |
794 | err_detect); | |
795 | ||
796 | /* no more processing if not ECC bit errors */ | |
797 | if (!(err_detect & (DDR_EDE_SBE | DDR_EDE_MBE))) { | |
798 | out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT, err_detect); | |
799 | return; | |
800 | } | |
801 | ||
802 | syndrome = in_be32(pdata->mc_vbase + MPC85XX_MC_CAPTURE_ECC); | |
21768639 PT |
803 | |
804 | /* Mask off appropriate bits of syndrome based on bus width */ | |
805 | bus_width = (in_be32(pdata->mc_vbase + MPC85XX_MC_DDR_SDRAM_CFG) & | |
806 | DSC_DBW_MASK) ? 32 : 64; | |
807 | if (bus_width == 64) | |
808 | syndrome &= 0xff; | |
809 | else | |
810 | syndrome &= 0xffff; | |
811 | ||
a9a753d5 DJ |
812 | err_addr = in_be32(pdata->mc_vbase + MPC85XX_MC_CAPTURE_ADDRESS); |
813 | pfn = err_addr >> PAGE_SHIFT; | |
814 | ||
815 | for (row_index = 0; row_index < mci->nr_csrows; row_index++) { | |
816 | csrow = &mci->csrows[row_index]; | |
817 | if ((pfn >= csrow->first_page) && (pfn <= csrow->last_page)) | |
818 | break; | |
819 | } | |
820 | ||
dcca7c3d PT |
821 | cap_high = in_be32(pdata->mc_vbase + MPC85XX_MC_CAPTURE_DATA_HI); |
822 | cap_low = in_be32(pdata->mc_vbase + MPC85XX_MC_CAPTURE_DATA_LO); | |
823 | ||
824 | /* | |
825 | * Analyze single-bit errors on 64-bit wide buses | |
826 | * TODO: Add support for 32-bit wide buses | |
827 | */ | |
828 | if ((err_detect & DDR_EDE_SBE) && (bus_width == 64)) { | |
829 | sbe_ecc_decode(cap_high, cap_low, syndrome, | |
830 | &bad_data_bit, &bad_ecc_bit); | |
831 | ||
832 | if (bad_data_bit != -1) | |
833 | mpc85xx_mc_printk(mci, KERN_ERR, | |
834 | "Faulty Data bit: %d\n", bad_data_bit); | |
835 | if (bad_ecc_bit != -1) | |
836 | mpc85xx_mc_printk(mci, KERN_ERR, | |
837 | "Faulty ECC bit: %d\n", bad_ecc_bit); | |
838 | ||
839 | mpc85xx_mc_printk(mci, KERN_ERR, | |
840 | "Expected Data / ECC:\t%#8.8x_%08x / %#2.2x\n", | |
841 | cap_high ^ (1 << (bad_data_bit - 32)), | |
842 | cap_low ^ (1 << bad_data_bit), | |
843 | syndrome ^ (1 << bad_ecc_bit)); | |
844 | } | |
845 | ||
846 | mpc85xx_mc_printk(mci, KERN_ERR, | |
847 | "Captured Data / ECC:\t%#8.8x_%08x / %#2.2x\n", | |
848 | cap_high, cap_low, syndrome); | |
849 | mpc85xx_mc_printk(mci, KERN_ERR, "Err addr: %#8.8x\n", err_addr); | |
a9a753d5 DJ |
850 | mpc85xx_mc_printk(mci, KERN_ERR, "PFN: %#8.8x\n", pfn); |
851 | ||
852 | /* we are out of range */ | |
853 | if (row_index == mci->nr_csrows) | |
854 | mpc85xx_mc_printk(mci, KERN_ERR, "PFN out of range!\n"); | |
855 | ||
856 | if (err_detect & DDR_EDE_SBE) | |
857 | edac_mc_handle_ce(mci, pfn, err_addr & PAGE_MASK, | |
858 | syndrome, row_index, 0, mci->ctl_name); | |
859 | ||
860 | if (err_detect & DDR_EDE_MBE) | |
861 | edac_mc_handle_ue(mci, pfn, err_addr & PAGE_MASK, | |
862 | row_index, mci->ctl_name); | |
863 | ||
864 | out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT, err_detect); | |
865 | } | |
866 | ||
867 | static irqreturn_t mpc85xx_mc_isr(int irq, void *dev_id) | |
868 | { | |
869 | struct mem_ctl_info *mci = dev_id; | |
870 | struct mpc85xx_mc_pdata *pdata = mci->pvt_info; | |
871 | u32 err_detect; | |
872 | ||
873 | err_detect = in_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT); | |
874 | if (!err_detect) | |
875 | return IRQ_NONE; | |
876 | ||
877 | mpc85xx_mc_check(mci); | |
878 | ||
879 | return IRQ_HANDLED; | |
880 | } | |
881 | ||
882 | static void __devinit mpc85xx_init_csrows(struct mem_ctl_info *mci) | |
883 | { | |
884 | struct mpc85xx_mc_pdata *pdata = mci->pvt_info; | |
885 | struct csrow_info *csrow; | |
886 | u32 sdram_ctl; | |
887 | u32 sdtype; | |
888 | enum mem_type mtype; | |
889 | u32 cs_bnds; | |
890 | int index; | |
891 | ||
892 | sdram_ctl = in_be32(pdata->mc_vbase + MPC85XX_MC_DDR_SDRAM_CFG); | |
893 | ||
894 | sdtype = sdram_ctl & DSC_SDTYPE_MASK; | |
895 | if (sdram_ctl & DSC_RD_EN) { | |
896 | switch (sdtype) { | |
897 | case DSC_SDTYPE_DDR: | |
898 | mtype = MEM_RDDR; | |
899 | break; | |
900 | case DSC_SDTYPE_DDR2: | |
901 | mtype = MEM_RDDR2; | |
902 | break; | |
b1cfebc9 YS |
903 | case DSC_SDTYPE_DDR3: |
904 | mtype = MEM_RDDR3; | |
905 | break; | |
a9a753d5 DJ |
906 | default: |
907 | mtype = MEM_UNKNOWN; | |
908 | break; | |
909 | } | |
910 | } else { | |
911 | switch (sdtype) { | |
912 | case DSC_SDTYPE_DDR: | |
913 | mtype = MEM_DDR; | |
914 | break; | |
915 | case DSC_SDTYPE_DDR2: | |
916 | mtype = MEM_DDR2; | |
917 | break; | |
b1cfebc9 YS |
918 | case DSC_SDTYPE_DDR3: |
919 | mtype = MEM_DDR3; | |
920 | break; | |
a9a753d5 DJ |
921 | default: |
922 | mtype = MEM_UNKNOWN; | |
923 | break; | |
924 | } | |
925 | } | |
926 | ||
927 | for (index = 0; index < mci->nr_csrows; index++) { | |
928 | u32 start; | |
929 | u32 end; | |
930 | ||
931 | csrow = &mci->csrows[index]; | |
932 | cs_bnds = in_be32(pdata->mc_vbase + MPC85XX_MC_CS_BNDS_0 + | |
933 | (index * MPC85XX_MC_CS_BNDS_OFS)); | |
b4846251 IS |
934 | |
935 | start = (cs_bnds & 0xffff0000) >> 16; | |
936 | end = (cs_bnds & 0x0000ffff); | |
a9a753d5 DJ |
937 | |
938 | if (start == end) | |
939 | continue; /* not populated */ | |
940 | ||
b4846251 IS |
941 | start <<= (24 - PAGE_SHIFT); |
942 | end <<= (24 - PAGE_SHIFT); | |
943 | end |= (1 << (24 - PAGE_SHIFT)) - 1; | |
944 | ||
cff9279e PT |
945 | csrow->first_page = start; |
946 | csrow->last_page = end; | |
b4846251 | 947 | csrow->nr_pages = end + 1 - start; |
a9a753d5 DJ |
948 | csrow->grain = 8; |
949 | csrow->mtype = mtype; | |
950 | csrow->dtype = DEV_UNKNOWN; | |
951 | if (sdram_ctl & DSC_X32_EN) | |
952 | csrow->dtype = DEV_X32; | |
953 | csrow->edac_mode = EDAC_SECDED; | |
954 | } | |
955 | } | |
956 | ||
00006124 | 957 | static int __devinit mpc85xx_mc_err_probe(struct platform_device *op) |
a9a753d5 DJ |
958 | { |
959 | struct mem_ctl_info *mci; | |
960 | struct mpc85xx_mc_pdata *pdata; | |
961 | struct resource r; | |
962 | u32 sdram_ctl; | |
963 | int res; | |
964 | ||
965 | if (!devres_open_group(&op->dev, mpc85xx_mc_err_probe, GFP_KERNEL)) | |
966 | return -ENOMEM; | |
967 | ||
968 | mci = edac_mc_alloc(sizeof(*pdata), 4, 1, edac_mc_idx); | |
969 | if (!mci) { | |
970 | devres_release_group(&op->dev, mpc85xx_mc_err_probe); | |
971 | return -ENOMEM; | |
972 | } | |
973 | ||
974 | pdata = mci->pvt_info; | |
975 | pdata->name = "mpc85xx_mc_err"; | |
976 | pdata->irq = NO_IRQ; | |
977 | mci->dev = &op->dev; | |
978 | pdata->edac_idx = edac_mc_idx++; | |
979 | dev_set_drvdata(mci->dev, mci); | |
980 | mci->ctl_name = pdata->name; | |
981 | mci->dev_name = pdata->name; | |
982 | ||
a26f95fe | 983 | res = of_address_to_resource(op->dev.of_node, 0, &r); |
a9a753d5 DJ |
984 | if (res) { |
985 | printk(KERN_ERR "%s: Unable to get resource for MC err regs\n", | |
986 | __func__); | |
987 | goto err; | |
988 | } | |
989 | ||
28f65c11 JP |
990 | if (!devm_request_mem_region(&op->dev, r.start, resource_size(&r), |
991 | pdata->name)) { | |
a9a753d5 DJ |
992 | printk(KERN_ERR "%s: Error while requesting mem region\n", |
993 | __func__); | |
994 | res = -EBUSY; | |
995 | goto err; | |
996 | } | |
997 | ||
28f65c11 | 998 | pdata->mc_vbase = devm_ioremap(&op->dev, r.start, resource_size(&r)); |
a9a753d5 DJ |
999 | if (!pdata->mc_vbase) { |
1000 | printk(KERN_ERR "%s: Unable to setup MC err regs\n", __func__); | |
1001 | res = -ENOMEM; | |
1002 | goto err; | |
1003 | } | |
1004 | ||
1005 | sdram_ctl = in_be32(pdata->mc_vbase + MPC85XX_MC_DDR_SDRAM_CFG); | |
1006 | if (!(sdram_ctl & DSC_ECC_EN)) { | |
1007 | /* no ECC */ | |
1008 | printk(KERN_WARNING "%s: No ECC DIMMs discovered\n", __func__); | |
1009 | res = -ENODEV; | |
1010 | goto err; | |
1011 | } | |
1012 | ||
1013 | debugf3("%s(): init mci\n", __func__); | |
1014 | mci->mtype_cap = MEM_FLAG_RDDR | MEM_FLAG_RDDR2 | | |
1015 | MEM_FLAG_DDR | MEM_FLAG_DDR2; | |
1016 | mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED; | |
1017 | mci->edac_cap = EDAC_FLAG_SECDED; | |
1018 | mci->mod_name = EDAC_MOD_STR; | |
1019 | mci->mod_ver = MPC85XX_REVISION; | |
1020 | ||
1021 | if (edac_op_state == EDAC_OPSTATE_POLL) | |
1022 | mci->edac_check = mpc85xx_mc_check; | |
1023 | ||
1024 | mci->ctl_page_to_phys = NULL; | |
1025 | ||
1026 | mci->scrub_mode = SCRUB_SW_SRC; | |
1027 | ||
1028 | mpc85xx_set_mc_sysfs_attributes(mci); | |
1029 | ||
1030 | mpc85xx_init_csrows(mci); | |
1031 | ||
a9a753d5 DJ |
1032 | /* store the original error disable bits */ |
1033 | orig_ddr_err_disable = | |
1034 | in_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DISABLE); | |
1035 | out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DISABLE, 0); | |
1036 | ||
1037 | /* clear all error bits */ | |
1038 | out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT, ~0); | |
1039 | ||
1040 | if (edac_mc_add_mc(mci)) { | |
1041 | debugf3("%s(): failed edac_mc_add_mc()\n", __func__); | |
1042 | goto err; | |
1043 | } | |
1044 | ||
1045 | if (edac_op_state == EDAC_OPSTATE_INT) { | |
1046 | out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_INT_EN, | |
1047 | DDR_EIE_MBEE | DDR_EIE_SBEE); | |
1048 | ||
1049 | /* store the original error management threshold */ | |
1050 | orig_ddr_err_sbe = in_be32(pdata->mc_vbase + | |
1051 | MPC85XX_MC_ERR_SBE) & 0xff0000; | |
1052 | ||
1053 | /* set threshold to 1 error per interrupt */ | |
1054 | out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_SBE, 0x10000); | |
1055 | ||
1056 | /* register interrupts */ | |
a26f95fe | 1057 | pdata->irq = irq_of_parse_and_map(op->dev.of_node, 0); |
a9a753d5 | 1058 | res = devm_request_irq(&op->dev, pdata->irq, |
60be7551 AK |
1059 | mpc85xx_mc_isr, |
1060 | IRQF_DISABLED | IRQF_SHARED, | |
a9a753d5 DJ |
1061 | "[EDAC] MC err", mci); |
1062 | if (res < 0) { | |
1063 | printk(KERN_ERR "%s: Unable to request irq %d for " | |
1064 | "MPC85xx DRAM ERR\n", __func__, pdata->irq); | |
1065 | irq_dispose_mapping(pdata->irq); | |
1066 | res = -ENODEV; | |
1067 | goto err2; | |
1068 | } | |
1069 | ||
1070 | printk(KERN_INFO EDAC_MOD_STR " acquired irq %d for MC\n", | |
1071 | pdata->irq); | |
1072 | } | |
1073 | ||
1074 | devres_remove_group(&op->dev, mpc85xx_mc_err_probe); | |
1075 | debugf3("%s(): success\n", __func__); | |
1076 | printk(KERN_INFO EDAC_MOD_STR " MC err registered\n"); | |
1077 | ||
1078 | return 0; | |
1079 | ||
1080 | err2: | |
1081 | edac_mc_del_mc(&op->dev); | |
1082 | err: | |
1083 | devres_release_group(&op->dev, mpc85xx_mc_err_probe); | |
1084 | edac_mc_free(mci); | |
1085 | return res; | |
1086 | } | |
1087 | ||
2dc11581 | 1088 | static int mpc85xx_mc_err_remove(struct platform_device *op) |
a9a753d5 DJ |
1089 | { |
1090 | struct mem_ctl_info *mci = dev_get_drvdata(&op->dev); | |
1091 | struct mpc85xx_mc_pdata *pdata = mci->pvt_info; | |
1092 | ||
1093 | debugf0("%s()\n", __func__); | |
1094 | ||
1095 | if (edac_op_state == EDAC_OPSTATE_INT) { | |
1096 | out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_INT_EN, 0); | |
1097 | irq_dispose_mapping(pdata->irq); | |
1098 | } | |
1099 | ||
1100 | out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DISABLE, | |
1101 | orig_ddr_err_disable); | |
1102 | out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_SBE, orig_ddr_err_sbe); | |
1103 | ||
1104 | edac_mc_del_mc(&op->dev); | |
1105 | edac_mc_free(mci); | |
1106 | return 0; | |
1107 | } | |
1108 | ||
1109 | static struct of_device_id mpc85xx_mc_err_of_match[] = { | |
29d6cf26 KG |
1110 | /* deprecate the fsl,85.. forms in the future, 2.6.30? */ |
1111 | { .compatible = "fsl,8540-memory-controller", }, | |
1112 | { .compatible = "fsl,8541-memory-controller", }, | |
1113 | { .compatible = "fsl,8544-memory-controller", }, | |
1114 | { .compatible = "fsl,8548-memory-controller", }, | |
1115 | { .compatible = "fsl,8555-memory-controller", }, | |
1116 | { .compatible = "fsl,8568-memory-controller", }, | |
1117 | { .compatible = "fsl,mpc8536-memory-controller", }, | |
1118 | { .compatible = "fsl,mpc8540-memory-controller", }, | |
1119 | { .compatible = "fsl,mpc8541-memory-controller", }, | |
1120 | { .compatible = "fsl,mpc8544-memory-controller", }, | |
1121 | { .compatible = "fsl,mpc8548-memory-controller", }, | |
1122 | { .compatible = "fsl,mpc8555-memory-controller", }, | |
1123 | { .compatible = "fsl,mpc8560-memory-controller", }, | |
1124 | { .compatible = "fsl,mpc8568-memory-controller", }, | |
5528e229 | 1125 | { .compatible = "fsl,mpc8569-memory-controller", }, |
29d6cf26 | 1126 | { .compatible = "fsl,mpc8572-memory-controller", }, |
b4846251 | 1127 | { .compatible = "fsl,mpc8349-memory-controller", }, |
cd1542c8 AV |
1128 | { .compatible = "fsl,p1020-memory-controller", }, |
1129 | { .compatible = "fsl,p1021-memory-controller", }, | |
a014554e | 1130 | { .compatible = "fsl,p2020-memory-controller", }, |
cd1542c8 | 1131 | { .compatible = "fsl,p4080-memory-controller", }, |
a9a753d5 DJ |
1132 | {}, |
1133 | }; | |
952e1c66 | 1134 | MODULE_DEVICE_TABLE(of, mpc85xx_mc_err_of_match); |
a9a753d5 | 1135 | |
00006124 | 1136 | static struct platform_driver mpc85xx_mc_err_driver = { |
a9a753d5 DJ |
1137 | .probe = mpc85xx_mc_err_probe, |
1138 | .remove = mpc85xx_mc_err_remove, | |
1139 | .driver = { | |
4018294b GL |
1140 | .name = "mpc85xx_mc_err", |
1141 | .owner = THIS_MODULE, | |
1142 | .of_match_table = mpc85xx_mc_err_of_match, | |
1143 | }, | |
a9a753d5 DJ |
1144 | }; |
1145 | ||
bd1688dc | 1146 | #ifdef CONFIG_FSL_SOC_BOOKE |
60be7551 AK |
1147 | static void __init mpc85xx_mc_clear_rfxe(void *data) |
1148 | { | |
1149 | orig_hid1[smp_processor_id()] = mfspr(SPRN_HID1); | |
a94d7b35 | 1150 | mtspr(SPRN_HID1, (orig_hid1[smp_processor_id()] & ~HID1_RFXE)); |
60be7551 | 1151 | } |
b4846251 | 1152 | #endif |
60be7551 | 1153 | |
a9a753d5 DJ |
1154 | static int __init mpc85xx_mc_init(void) |
1155 | { | |
1156 | int res = 0; | |
a94d7b35 | 1157 | u32 pvr = 0; |
a9a753d5 DJ |
1158 | |
1159 | printk(KERN_INFO "Freescale(R) MPC85xx EDAC driver, " | |
1160 | "(C) 2006 Montavista Software\n"); | |
1161 | ||
1162 | /* make sure error reporting method is sane */ | |
1163 | switch (edac_op_state) { | |
1164 | case EDAC_OPSTATE_POLL: | |
1165 | case EDAC_OPSTATE_INT: | |
1166 | break; | |
1167 | default: | |
1168 | edac_op_state = EDAC_OPSTATE_INT; | |
1169 | break; | |
1170 | } | |
1171 | ||
00006124 | 1172 | res = platform_driver_register(&mpc85xx_mc_err_driver); |
a9a753d5 DJ |
1173 | if (res) |
1174 | printk(KERN_WARNING EDAC_MOD_STR "MC fails to register\n"); | |
1175 | ||
00006124 | 1176 | res = platform_driver_register(&mpc85xx_l2_err_driver); |
a9a753d5 DJ |
1177 | if (res) |
1178 | printk(KERN_WARNING EDAC_MOD_STR "L2 fails to register\n"); | |
1179 | ||
1180 | #ifdef CONFIG_PCI | |
00006124 | 1181 | res = platform_driver_register(&mpc85xx_pci_err_driver); |
a9a753d5 DJ |
1182 | if (res) |
1183 | printk(KERN_WARNING EDAC_MOD_STR "PCI fails to register\n"); | |
1184 | #endif | |
1185 | ||
bd1688dc | 1186 | #ifdef CONFIG_FSL_SOC_BOOKE |
a94d7b35 KG |
1187 | pvr = mfspr(SPRN_PVR); |
1188 | ||
1189 | if ((PVR_VER(pvr) == PVR_VER_E500V1) || | |
1190 | (PVR_VER(pvr) == PVR_VER_E500V2)) { | |
1191 | /* | |
1192 | * need to clear HID1[RFXE] to disable machine check int | |
1193 | * so we can catch it | |
1194 | */ | |
1195 | if (edac_op_state == EDAC_OPSTATE_INT) | |
1196 | on_each_cpu(mpc85xx_mc_clear_rfxe, NULL, 0); | |
1197 | } | |
b4846251 | 1198 | #endif |
a9a753d5 DJ |
1199 | |
1200 | return 0; | |
1201 | } | |
1202 | ||
1203 | module_init(mpc85xx_mc_init); | |
1204 | ||
bd1688dc | 1205 | #ifdef CONFIG_FSL_SOC_BOOKE |
60be7551 AK |
1206 | static void __exit mpc85xx_mc_restore_hid1(void *data) |
1207 | { | |
1208 | mtspr(SPRN_HID1, orig_hid1[smp_processor_id()]); | |
1209 | } | |
b4846251 | 1210 | #endif |
60be7551 | 1211 | |
a9a753d5 DJ |
1212 | static void __exit mpc85xx_mc_exit(void) |
1213 | { | |
bd1688dc | 1214 | #ifdef CONFIG_FSL_SOC_BOOKE |
a94d7b35 KG |
1215 | u32 pvr = mfspr(SPRN_PVR); |
1216 | ||
1217 | if ((PVR_VER(pvr) == PVR_VER_E500V1) || | |
1218 | (PVR_VER(pvr) == PVR_VER_E500V2)) { | |
1219 | on_each_cpu(mpc85xx_mc_restore_hid1, NULL, 0); | |
1220 | } | |
b4846251 | 1221 | #endif |
a9a753d5 | 1222 | #ifdef CONFIG_PCI |
00006124 | 1223 | platform_driver_unregister(&mpc85xx_pci_err_driver); |
a9a753d5 | 1224 | #endif |
00006124 GL |
1225 | platform_driver_unregister(&mpc85xx_l2_err_driver); |
1226 | platform_driver_unregister(&mpc85xx_mc_err_driver); | |
a9a753d5 DJ |
1227 | } |
1228 | ||
1229 | module_exit(mpc85xx_mc_exit); | |
1230 | ||
1231 | MODULE_LICENSE("GPL"); | |
1232 | MODULE_AUTHOR("Montavista Software, Inc."); | |
1233 | module_param(edac_op_state, int, 0444); | |
1234 | MODULE_PARM_DESC(edac_op_state, | |
1235 | "EDAC Error Reporting state: 0=Poll, 2=Interrupt"); |