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Commit | Line | Data |
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2f768af7 AC |
1 | /* |
2 | * Radisys 82600 Embedded chipset Memory Controller kernel module | |
3 | * (C) 2005 EADS Astrium | |
4 | * This file may be distributed under the terms of the | |
5 | * GNU General Public License. | |
6 | * | |
7 | * Written by Tim Small <tim@buttersideup.com>, based on work by Thayne | |
8 | * Harbaugh, Dan Hollis <goemon at anime dot net> and others. | |
9 | * | |
10 | * $Id: edac_r82600.c,v 1.1.2.6 2005/10/05 00:43:44 dsp_llnl Exp $ | |
11 | * | |
12 | * Written with reference to 82600 High Integration Dual PCI System | |
13 | * Controller Data Book: | |
c4192705 | 14 | * www.radisys.com/files/support_downloads/007-01277-0002.82600DataBook.pdf |
2f768af7 AC |
15 | * references to this document given in [] |
16 | */ | |
17 | ||
2f768af7 AC |
18 | #include <linux/module.h> |
19 | #include <linux/init.h> | |
2f768af7 AC |
20 | #include <linux/pci.h> |
21 | #include <linux/pci_ids.h> | |
c3c52bce | 22 | #include <linux/edac.h> |
20bcb7a8 | 23 | #include "edac_core.h" |
2f768af7 | 24 | |
152ba394 | 25 | #define R82600_REVISION " Ver: 2.0.2" |
929a40ec | 26 | #define EDAC_MOD_STR "r82600_edac" |
37f04581 | 27 | |
537fba28 | 28 | #define r82600_printk(level, fmt, arg...) \ |
e7ecd891 | 29 | edac_printk(level, "r82600", fmt, ##arg) |
537fba28 DP |
30 | |
31 | #define r82600_mc_printk(mci, level, fmt, arg...) \ | |
e7ecd891 | 32 | edac_mc_chipset_printk(mci, level, "r82600", fmt, ##arg) |
537fba28 | 33 | |
2f768af7 AC |
34 | /* Radisys say "The 82600 integrates a main memory SDRAM controller that |
35 | * supports up to four banks of memory. The four banks can support a mix of | |
36 | * sizes of 64 bit wide (72 bits with ECC) Synchronous DRAM (SDRAM) DIMMs, | |
37 | * each of which can be any size from 16MB to 512MB. Both registered (control | |
38 | * signals buffered) and unbuffered DIMM types are supported. Mixing of | |
39 | * registered and unbuffered DIMMs as well as mixing of ECC and non-ECC DIMMs | |
40 | * is not allowed. The 82600 SDRAM interface operates at the same frequency as | |
41 | * the CPU bus, 66MHz, 100MHz or 133MHz." | |
42 | */ | |
43 | ||
44 | #define R82600_NR_CSROWS 4 | |
45 | #define R82600_NR_CHANS 1 | |
46 | #define R82600_NR_DIMMS 4 | |
47 | ||
48 | #define R82600_BRIDGE_ID 0x8200 | |
49 | ||
50 | /* Radisys 82600 register addresses - device 0 function 0 - PCI bridge */ | |
51 | #define R82600_DRAMC 0x57 /* Various SDRAM related control bits | |
52 | * all bits are R/W | |
53 | * | |
54 | * 7 SDRAM ISA Hole Enable | |
55 | * 6 Flash Page Mode Enable | |
56 | * 5 ECC Enable: 1=ECC 0=noECC | |
57 | * 4 DRAM DIMM Type: 1= | |
58 | * 3 BIOS Alias Disable | |
59 | * 2 SDRAM BIOS Flash Write Enable | |
60 | * 1:0 SDRAM Refresh Rate: 00=Disabled | |
61 | * 01=7.8usec (256Mbit SDRAMs) | |
62 | * 10=15.6us 11=125usec | |
63 | */ | |
64 | ||
65 | #define R82600_SDRAMC 0x76 /* "SDRAM Control Register" | |
66 | * More SDRAM related control bits | |
67 | * all bits are R/W | |
68 | * | |
69 | * 15:8 Reserved. | |
70 | * | |
71 | * 7:5 Special SDRAM Mode Select | |
72 | * | |
73 | * 4 Force ECC | |
74 | * | |
75 | * 1=Drive ECC bits to 0 during | |
76 | * write cycles (i.e. ECC test mode) | |
77 | * | |
78 | * 0=Normal ECC functioning | |
79 | * | |
80 | * 3 Enhanced Paging Enable | |
81 | * | |
82 | * 2 CAS# Latency 0=3clks 1=2clks | |
83 | * | |
84 | * 1 RAS# to CAS# Delay 0=3 1=2 | |
85 | * | |
86 | * 0 RAS# Precharge 0=3 1=2 | |
87 | */ | |
88 | ||
89 | #define R82600_EAP 0x80 /* ECC Error Address Pointer Register | |
90 | * | |
91 | * 31 Disable Hardware Scrubbing (RW) | |
92 | * 0=Scrub on corrected read | |
93 | * 1=Don't scrub on corrected read | |
94 | * | |
95 | * 30:12 Error Address Pointer (RO) | |
96 | * Upper 19 bits of error address | |
97 | * | |
98 | * 11:4 Syndrome Bits (RO) | |
99 | * | |
100 | * 3 BSERR# on multibit error (RW) | |
101 | * 1=enable 0=disable | |
102 | * | |
103 | * 2 NMI on Single Bit Eror (RW) | |
104 | * 1=NMI triggered by SBE n.b. other | |
105 | * prerequeists | |
106 | * 0=NMI not triggered | |
107 | * | |
108 | * 1 MBE (R/WC) | |
109 | * read 1=MBE at EAP (see above) | |
110 | * read 0=no MBE, or SBE occurred first | |
111 | * write 1=Clear MBE status (must also | |
112 | * clear SBE) | |
113 | * write 0=NOP | |
114 | * | |
115 | * 1 SBE (R/WC) | |
116 | * read 1=SBE at EAP (see above) | |
117 | * read 0=no SBE, or MBE occurred first | |
118 | * write 1=Clear SBE status (must also | |
119 | * clear MBE) | |
120 | * write 0=NOP | |
121 | */ | |
122 | ||
25985edc | 123 | #define R82600_DRBA 0x60 /* + 0x60..0x63 SDRAM Row Boundary Address |
2f768af7 AC |
124 | * Registers |
125 | * | |
126 | * 7:0 Address lines 30:24 - upper limit of | |
127 | * each row [p57] | |
128 | */ | |
129 | ||
130 | struct r82600_error_info { | |
131 | u32 eapr; | |
132 | }; | |
133 | ||
90ab5ee9 | 134 | static bool disable_hardware_scrub; |
2f768af7 | 135 | |
456a2f95 DJ |
136 | static struct edac_pci_ctl_info *r82600_pci; |
137 | ||
cddbfcac | 138 | static void r82600_get_error_info(struct mem_ctl_info *mci, |
052dfb45 | 139 | struct r82600_error_info *info) |
2f768af7 | 140 | { |
37f04581 DT |
141 | struct pci_dev *pdev; |
142 | ||
143 | pdev = to_pci_dev(mci->dev); | |
144 | pci_read_config_dword(pdev, R82600_EAP, &info->eapr); | |
2f768af7 AC |
145 | |
146 | if (info->eapr & BIT(0)) | |
147 | /* Clear error to allow next error to be reported [p.62] */ | |
37f04581 | 148 | pci_write_bits32(pdev, R82600_EAP, |
cddbfcac DT |
149 | ((u32) BIT(0) & (u32) BIT(1)), |
150 | ((u32) BIT(0) & (u32) BIT(1))); | |
2f768af7 AC |
151 | |
152 | if (info->eapr & BIT(1)) | |
153 | /* Clear error to allow next error to be reported [p.62] */ | |
37f04581 | 154 | pci_write_bits32(pdev, R82600_EAP, |
cddbfcac DT |
155 | ((u32) BIT(0) & (u32) BIT(1)), |
156 | ((u32) BIT(0) & (u32) BIT(1))); | |
2f768af7 AC |
157 | } |
158 | ||
cddbfcac | 159 | static int r82600_process_error_info(struct mem_ctl_info *mci, |
052dfb45 DT |
160 | struct r82600_error_info *info, |
161 | int handle_errors) | |
2f768af7 AC |
162 | { |
163 | int error_found; | |
164 | u32 eapaddr, page; | |
165 | u32 syndrome; | |
166 | ||
167 | error_found = 0; | |
168 | ||
169 | /* bits 30:12 store the upper 19 bits of the 32 bit error address */ | |
170 | eapaddr = ((info->eapr >> 12) & 0x7FFF) << 13; | |
171 | /* Syndrome in bits 11:4 [p.62] */ | |
172 | syndrome = (info->eapr >> 4) & 0xFF; | |
173 | ||
174 | /* the R82600 reports at less than page * | |
175 | * granularity (upper 19 bits only) */ | |
176 | page = eapaddr >> PAGE_SHIFT; | |
177 | ||
cddbfcac | 178 | if (info->eapr & BIT(0)) { /* CE? */ |
2f768af7 AC |
179 | error_found = 1; |
180 | ||
181 | if (handle_errors) | |
cddbfcac | 182 | edac_mc_handle_ce(mci, page, 0, /* not avail */ |
052dfb45 DT |
183 | syndrome, |
184 | edac_mc_find_csrow_by_page(mci, page), | |
185 | 0, mci->ctl_name); | |
2f768af7 AC |
186 | } |
187 | ||
cddbfcac | 188 | if (info->eapr & BIT(1)) { /* UE? */ |
2f768af7 AC |
189 | error_found = 1; |
190 | ||
191 | if (handle_errors) | |
192 | /* 82600 doesn't give enough info */ | |
193 | edac_mc_handle_ue(mci, page, 0, | |
052dfb45 DT |
194 | edac_mc_find_csrow_by_page(mci, page), |
195 | mci->ctl_name); | |
2f768af7 AC |
196 | } |
197 | ||
198 | return error_found; | |
199 | } | |
200 | ||
201 | static void r82600_check(struct mem_ctl_info *mci) | |
202 | { | |
203 | struct r82600_error_info info; | |
204 | ||
537fba28 | 205 | debugf1("MC%d: %s()\n", mci->mc_idx, __func__); |
2f768af7 AC |
206 | r82600_get_error_info(mci, &info); |
207 | r82600_process_error_info(mci, &info, 1); | |
208 | } | |
209 | ||
13189525 | 210 | static inline int ecc_enabled(u8 dramcr) |
2f768af7 | 211 | { |
13189525 DT |
212 | return dramcr & BIT(5); |
213 | } | |
214 | ||
215 | static void r82600_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev, | |
052dfb45 | 216 | u8 dramcr) |
13189525 DT |
217 | { |
218 | struct csrow_info *csrow; | |
2f768af7 | 219 | int index; |
25985edc | 220 | u8 drbar; /* SDRAM Row Boundary Address Register */ |
13189525 DT |
221 | u32 row_high_limit, row_high_limit_last; |
222 | u32 reg_sdram, ecc_on, row_base; | |
223 | ||
224 | ecc_on = ecc_enabled(dramcr); | |
225 | reg_sdram = dramcr & BIT(4); | |
226 | row_high_limit_last = 0; | |
227 | ||
228 | for (index = 0; index < mci->nr_csrows; index++) { | |
229 | csrow = &mci->csrows[index]; | |
230 | ||
231 | /* find the DRAM Chip Select Base address and mask */ | |
232 | pci_read_config_byte(pdev, R82600_DRBA + index, &drbar); | |
233 | ||
234 | debugf1("%s() Row=%d DRBA = %#0x\n", __func__, index, drbar); | |
235 | ||
236 | row_high_limit = ((u32) drbar << 24); | |
237 | /* row_high_limit = ((u32)drbar << 24) | 0xffffffUL; */ | |
238 | ||
25985edc | 239 | debugf1("%s() Row=%d, Boundary Address=%#0x, Last = %#0x\n", |
13189525 DT |
240 | __func__, index, row_high_limit, row_high_limit_last); |
241 | ||
242 | /* Empty row [p.57] */ | |
243 | if (row_high_limit == row_high_limit_last) | |
244 | continue; | |
245 | ||
246 | row_base = row_high_limit_last; | |
247 | ||
248 | csrow->first_page = row_base >> PAGE_SHIFT; | |
249 | csrow->last_page = (row_high_limit >> PAGE_SHIFT) - 1; | |
250 | csrow->nr_pages = csrow->last_page - csrow->first_page + 1; | |
251 | /* Error address is top 19 bits - so granularity is * | |
252 | * 14 bits */ | |
253 | csrow->grain = 1 << 14; | |
254 | csrow->mtype = reg_sdram ? MEM_RDDR : MEM_DDR; | |
255 | /* FIXME - check that this is unknowable with this chipset */ | |
256 | csrow->dtype = DEV_UNKNOWN; | |
257 | ||
258 | /* Mode is global on 82600 */ | |
259 | csrow->edac_mode = ecc_on ? EDAC_SECDED : EDAC_NONE; | |
260 | row_high_limit_last = row_high_limit; | |
261 | } | |
262 | } | |
263 | ||
264 | static int r82600_probe1(struct pci_dev *pdev, int dev_idx) | |
265 | { | |
266 | struct mem_ctl_info *mci; | |
2f768af7 | 267 | u8 dramcr; |
2f768af7 AC |
268 | u32 eapr; |
269 | u32 scrub_disabled; | |
270 | u32 sdram_refresh_rate; | |
749ede57 | 271 | struct r82600_error_info discard; |
2f768af7 | 272 | |
537fba28 | 273 | debugf0("%s()\n", __func__); |
2f768af7 AC |
274 | pci_read_config_byte(pdev, R82600_DRAMC, &dramcr); |
275 | pci_read_config_dword(pdev, R82600_EAP, &eapr); | |
2f768af7 AC |
276 | scrub_disabled = eapr & BIT(31); |
277 | sdram_refresh_rate = dramcr & (BIT(0) | BIT(1)); | |
537fba28 DP |
278 | debugf2("%s(): sdram refresh rate = %#0x\n", __func__, |
279 | sdram_refresh_rate); | |
537fba28 | 280 | debugf2("%s(): DRAMC register = %#0x\n", __func__, dramcr); |
b8f6f975 | 281 | mci = edac_mc_alloc(0, R82600_NR_CSROWS, R82600_NR_CHANS, 0); |
2f768af7 | 282 | |
13189525 DT |
283 | if (mci == NULL) |
284 | return -ENOMEM; | |
2f768af7 | 285 | |
537fba28 | 286 | debugf0("%s(): mci = %p\n", __func__, mci); |
37f04581 | 287 | mci->dev = &pdev->dev; |
2f768af7 | 288 | mci->mtype_cap = MEM_FLAG_RDDR | MEM_FLAG_DDR; |
2f768af7 | 289 | mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED; |
e7ecd891 DP |
290 | /* FIXME try to work out if the chip leads have been used for COM2 |
291 | * instead on this board? [MA6?] MAYBE: | |
292 | */ | |
2f768af7 AC |
293 | |
294 | /* On the R82600, the pins for memory bits 72:65 - i.e. the * | |
295 | * EC bits are shared with the pins for COM2 (!), so if COM2 * | |
296 | * is enabled, we assume COM2 is wired up, and thus no EDAC * | |
297 | * is possible. */ | |
298 | mci->edac_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED; | |
e7ecd891 | 299 | |
13189525 | 300 | if (ecc_enabled(dramcr)) { |
2f768af7 | 301 | if (scrub_disabled) |
537fba28 DP |
302 | debugf3("%s(): mci = %p - Scrubbing disabled! EAP: " |
303 | "%#0x\n", __func__, mci, eapr); | |
2f768af7 AC |
304 | } else |
305 | mci->edac_cap = EDAC_FLAG_NONE; | |
306 | ||
680cbbbb | 307 | mci->mod_name = EDAC_MOD_STR; |
37f04581 | 308 | mci->mod_ver = R82600_REVISION; |
2f768af7 | 309 | mci->ctl_name = "R82600"; |
c4192705 | 310 | mci->dev_name = pci_name(pdev); |
2f768af7 AC |
311 | mci->edac_check = r82600_check; |
312 | mci->ctl_page_to_phys = NULL; | |
13189525 | 313 | r82600_init_csrows(mci, pdev, dramcr); |
cddbfcac | 314 | r82600_get_error_info(mci, &discard); /* clear counters */ |
2f768af7 | 315 | |
2d7bbb91 DT |
316 | /* Here we assume that we will never see multiple instances of this |
317 | * type of memory controller. The ID is therefore hardcoded to 0. | |
318 | */ | |
b8f6f975 | 319 | if (edac_mc_add_mc(mci)) { |
537fba28 | 320 | debugf3("%s(): failed edac_mc_add_mc()\n", __func__); |
2f768af7 AC |
321 | goto fail; |
322 | } | |
323 | ||
324 | /* get this far and it's successful */ | |
325 | ||
2f768af7 | 326 | if (disable_hardware_scrub) { |
537fba28 DP |
327 | debugf3("%s(): Disabling Hardware Scrub (scrub on error)\n", |
328 | __func__); | |
37f04581 | 329 | pci_write_bits32(pdev, R82600_EAP, BIT(31), BIT(31)); |
2f768af7 AC |
330 | } |
331 | ||
456a2f95 DJ |
332 | /* allocating generic PCI control info */ |
333 | r82600_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR); | |
334 | if (!r82600_pci) { | |
335 | printk(KERN_WARNING | |
336 | "%s(): Unable to create PCI control\n", | |
337 | __func__); | |
338 | printk(KERN_WARNING | |
339 | "%s(): PCI error report via EDAC not setup\n", | |
340 | __func__); | |
341 | } | |
342 | ||
537fba28 | 343 | debugf3("%s(): success\n", __func__); |
2f768af7 AC |
344 | return 0; |
345 | ||
052dfb45 | 346 | fail: |
13189525 DT |
347 | edac_mc_free(mci); |
348 | return -ENODEV; | |
2f768af7 AC |
349 | } |
350 | ||
351 | /* returns count (>= 0), or negative on error */ | |
352 | static int __devinit r82600_init_one(struct pci_dev *pdev, | |
052dfb45 | 353 | const struct pci_device_id *ent) |
2f768af7 | 354 | { |
537fba28 | 355 | debugf0("%s()\n", __func__); |
2f768af7 | 356 | |
ee6583f6 | 357 | /* don't need to call pci_enable_device() */ |
2f768af7 AC |
358 | return r82600_probe1(pdev, ent->driver_data); |
359 | } | |
360 | ||
2f768af7 AC |
361 | static void __devexit r82600_remove_one(struct pci_dev *pdev) |
362 | { | |
363 | struct mem_ctl_info *mci; | |
364 | ||
537fba28 | 365 | debugf0("%s()\n", __func__); |
2f768af7 | 366 | |
456a2f95 DJ |
367 | if (r82600_pci) |
368 | edac_pci_release_generic_ctl(r82600_pci); | |
369 | ||
37f04581 | 370 | if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL) |
18dbc337 DP |
371 | return; |
372 | ||
373 | edac_mc_free(mci); | |
2f768af7 AC |
374 | } |
375 | ||
2f768af7 | 376 | static const struct pci_device_id r82600_pci_tbl[] __devinitdata = { |
e7ecd891 | 377 | { |
cddbfcac DT |
378 | PCI_DEVICE(PCI_VENDOR_ID_RADISYS, R82600_BRIDGE_ID) |
379 | }, | |
e7ecd891 | 380 | { |
cddbfcac DT |
381 | 0, |
382 | } /* 0 terminated list. */ | |
2f768af7 AC |
383 | }; |
384 | ||
385 | MODULE_DEVICE_TABLE(pci, r82600_pci_tbl); | |
386 | ||
2f768af7 | 387 | static struct pci_driver r82600_driver = { |
680cbbbb | 388 | .name = EDAC_MOD_STR, |
2f768af7 AC |
389 | .probe = r82600_init_one, |
390 | .remove = __devexit_p(r82600_remove_one), | |
391 | .id_table = r82600_pci_tbl, | |
392 | }; | |
393 | ||
da9bb1d2 | 394 | static int __init r82600_init(void) |
2f768af7 | 395 | { |
c3c52bce HM |
396 | /* Ensure that the OPSTATE is set correctly for POLL or NMI */ |
397 | opstate_init(); | |
398 | ||
2f768af7 AC |
399 | return pci_register_driver(&r82600_driver); |
400 | } | |
401 | ||
2f768af7 AC |
402 | static void __exit r82600_exit(void) |
403 | { | |
404 | pci_unregister_driver(&r82600_driver); | |
405 | } | |
406 | ||
2f768af7 AC |
407 | module_init(r82600_init); |
408 | module_exit(r82600_exit); | |
409 | ||
2f768af7 AC |
410 | MODULE_LICENSE("GPL"); |
411 | MODULE_AUTHOR("Tim Small <tim@buttersideup.com> - WPAD Ltd. " | |
052dfb45 | 412 | "on behalf of EADS Astrium"); |
2f768af7 AC |
413 | MODULE_DESCRIPTION("MC support for Radisys 82600 memory controllers"); |
414 | ||
415 | module_param(disable_hardware_scrub, bool, 0644); | |
416 | MODULE_PARM_DESC(disable_hardware_scrub, | |
417 | "If set, disable the chipset's automatic scrub for CEs"); | |
c3c52bce HM |
418 | |
419 | module_param(edac_op_state, int, 0444); | |
420 | MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI"); |