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eebf11a0 MCC |
1 | /* Intel Sandy Bridge -EN/-EP/-EX Memory Controller kernel module |
2 | * | |
3 | * This driver supports the memory controllers found on the Intel | |
4 | * processor family Sandy Bridge. | |
5 | * | |
6 | * This file may be distributed under the terms of the | |
7 | * GNU General Public License version 2 only. | |
8 | * | |
9 | * Copyright (c) 2011 by: | |
37e59f87 | 10 | * Mauro Carvalho Chehab |
eebf11a0 MCC |
11 | */ |
12 | ||
13 | #include <linux/module.h> | |
14 | #include <linux/init.h> | |
15 | #include <linux/pci.h> | |
16 | #include <linux/pci_ids.h> | |
17 | #include <linux/slab.h> | |
18 | #include <linux/delay.h> | |
19 | #include <linux/edac.h> | |
20 | #include <linux/mmzone.h> | |
eebf11a0 MCC |
21 | #include <linux/smp.h> |
22 | #include <linux/bitmap.h> | |
5b889e37 | 23 | #include <linux/math64.h> |
eebf11a0 | 24 | #include <asm/processor.h> |
3d78c9af | 25 | #include <asm/mce.h> |
eebf11a0 MCC |
26 | |
27 | #include "edac_core.h" | |
28 | ||
29 | /* Static vars */ | |
30 | static LIST_HEAD(sbridge_edac_list); | |
31 | static DEFINE_MUTEX(sbridge_edac_lock); | |
32 | static int probed; | |
33 | ||
34 | /* | |
35 | * Alter this version for the module when modifications are made | |
36 | */ | |
4d715a80 | 37 | #define SBRIDGE_REVISION " Ver: 1.1.0 " |
eebf11a0 MCC |
38 | #define EDAC_MOD_STR "sbridge_edac" |
39 | ||
40 | /* | |
41 | * Debug macros | |
42 | */ | |
43 | #define sbridge_printk(level, fmt, arg...) \ | |
44 | edac_printk(level, "sbridge", fmt, ##arg) | |
45 | ||
46 | #define sbridge_mc_printk(mci, level, fmt, arg...) \ | |
47 | edac_mc_chipset_printk(mci, level, "sbridge", fmt, ##arg) | |
48 | ||
49 | /* | |
50 | * Get a bit field at register value <v>, from bit <lo> to bit <hi> | |
51 | */ | |
52 | #define GET_BITFIELD(v, lo, hi) \ | |
10ef6b0d | 53 | (((v) & GENMASK_ULL(hi, lo)) >> (lo)) |
eebf11a0 | 54 | |
eebf11a0 | 55 | /* Devices 12 Function 6, Offsets 0x80 to 0xcc */ |
464f1d82 | 56 | static const u32 sbridge_dram_rule[] = { |
eebf11a0 MCC |
57 | 0x80, 0x88, 0x90, 0x98, 0xa0, |
58 | 0xa8, 0xb0, 0xb8, 0xc0, 0xc8, | |
59 | }; | |
eebf11a0 | 60 | |
4d715a80 AR |
61 | static const u32 ibridge_dram_rule[] = { |
62 | 0x60, 0x68, 0x70, 0x78, 0x80, | |
63 | 0x88, 0x90, 0x98, 0xa0, 0xa8, | |
64 | 0xb0, 0xb8, 0xc0, 0xc8, 0xd0, | |
65 | 0xd8, 0xe0, 0xe8, 0xf0, 0xf8, | |
66 | }; | |
eebf11a0 MCC |
67 | |
68 | #define SAD_LIMIT(reg) ((GET_BITFIELD(reg, 6, 25) << 26) | 0x3ffffff) | |
69 | #define DRAM_ATTR(reg) GET_BITFIELD(reg, 2, 3) | |
70 | #define INTERLEAVE_MODE(reg) GET_BITFIELD(reg, 1, 1) | |
71 | #define DRAM_RULE_ENABLE(reg) GET_BITFIELD(reg, 0, 0) | |
50d1bb93 | 72 | #define A7MODE(reg) GET_BITFIELD(reg, 26, 26) |
eebf11a0 MCC |
73 | |
74 | static char *get_dram_attr(u32 reg) | |
75 | { | |
76 | switch(DRAM_ATTR(reg)) { | |
77 | case 0: | |
78 | return "DRAM"; | |
79 | case 1: | |
80 | return "MMCFG"; | |
81 | case 2: | |
82 | return "NXM"; | |
83 | default: | |
84 | return "unknown"; | |
85 | } | |
86 | } | |
87 | ||
ef1ce51e | 88 | static const u32 sbridge_interleave_list[] = { |
eebf11a0 MCC |
89 | 0x84, 0x8c, 0x94, 0x9c, 0xa4, |
90 | 0xac, 0xb4, 0xbc, 0xc4, 0xcc, | |
91 | }; | |
eebf11a0 | 92 | |
4d715a80 AR |
93 | static const u32 ibridge_interleave_list[] = { |
94 | 0x64, 0x6c, 0x74, 0x7c, 0x84, | |
95 | 0x8c, 0x94, 0x9c, 0xa4, 0xac, | |
96 | 0xb4, 0xbc, 0xc4, 0xcc, 0xd4, | |
97 | 0xdc, 0xe4, 0xec, 0xf4, 0xfc, | |
98 | }; | |
99 | ||
cc311991 AR |
100 | struct interleave_pkg { |
101 | unsigned char start; | |
102 | unsigned char end; | |
103 | }; | |
104 | ||
105 | static const struct interleave_pkg sbridge_interleave_pkg[] = { | |
106 | { 0, 2 }, | |
107 | { 3, 5 }, | |
108 | { 8, 10 }, | |
109 | { 11, 13 }, | |
110 | { 16, 18 }, | |
111 | { 19, 21 }, | |
112 | { 24, 26 }, | |
113 | { 27, 29 }, | |
114 | }; | |
115 | ||
4d715a80 AR |
116 | static const struct interleave_pkg ibridge_interleave_pkg[] = { |
117 | { 0, 3 }, | |
118 | { 4, 7 }, | |
119 | { 8, 11 }, | |
120 | { 12, 15 }, | |
121 | { 16, 19 }, | |
122 | { 20, 23 }, | |
123 | { 24, 27 }, | |
124 | { 28, 31 }, | |
125 | }; | |
126 | ||
cc311991 AR |
127 | static inline int sad_pkg(const struct interleave_pkg *table, u32 reg, |
128 | int interleave) | |
eebf11a0 | 129 | { |
cc311991 AR |
130 | return GET_BITFIELD(reg, table[interleave].start, |
131 | table[interleave].end); | |
eebf11a0 MCC |
132 | } |
133 | ||
134 | /* Devices 12 Function 7 */ | |
135 | ||
136 | #define TOLM 0x80 | |
137 | #define TOHM 0x84 | |
50d1bb93 AR |
138 | #define HASWELL_TOHM_0 0xd4 |
139 | #define HASWELL_TOHM_1 0xd8 | |
eebf11a0 MCC |
140 | |
141 | #define GET_TOLM(reg) ((GET_BITFIELD(reg, 0, 3) << 28) | 0x3ffffff) | |
142 | #define GET_TOHM(reg) ((GET_BITFIELD(reg, 0, 20) << 25) | 0x3ffffff) | |
143 | ||
144 | /* Device 13 Function 6 */ | |
145 | ||
146 | #define SAD_TARGET 0xf0 | |
147 | ||
148 | #define SOURCE_ID(reg) GET_BITFIELD(reg, 9, 11) | |
149 | ||
150 | #define SAD_CONTROL 0xf4 | |
151 | ||
eebf11a0 MCC |
152 | /* Device 14 function 0 */ |
153 | ||
154 | static const u32 tad_dram_rule[] = { | |
155 | 0x40, 0x44, 0x48, 0x4c, | |
156 | 0x50, 0x54, 0x58, 0x5c, | |
157 | 0x60, 0x64, 0x68, 0x6c, | |
158 | }; | |
159 | #define MAX_TAD ARRAY_SIZE(tad_dram_rule) | |
160 | ||
161 | #define TAD_LIMIT(reg) ((GET_BITFIELD(reg, 12, 31) << 26) | 0x3ffffff) | |
162 | #define TAD_SOCK(reg) GET_BITFIELD(reg, 10, 11) | |
163 | #define TAD_CH(reg) GET_BITFIELD(reg, 8, 9) | |
164 | #define TAD_TGT3(reg) GET_BITFIELD(reg, 6, 7) | |
165 | #define TAD_TGT2(reg) GET_BITFIELD(reg, 4, 5) | |
166 | #define TAD_TGT1(reg) GET_BITFIELD(reg, 2, 3) | |
167 | #define TAD_TGT0(reg) GET_BITFIELD(reg, 0, 1) | |
168 | ||
169 | /* Device 15, function 0 */ | |
170 | ||
171 | #define MCMTR 0x7c | |
172 | ||
173 | #define IS_ECC_ENABLED(mcmtr) GET_BITFIELD(mcmtr, 2, 2) | |
174 | #define IS_LOCKSTEP_ENABLED(mcmtr) GET_BITFIELD(mcmtr, 1, 1) | |
175 | #define IS_CLOSE_PG(mcmtr) GET_BITFIELD(mcmtr, 0, 0) | |
176 | ||
177 | /* Device 15, function 1 */ | |
178 | ||
179 | #define RASENABLES 0xac | |
180 | #define IS_MIRROR_ENABLED(reg) GET_BITFIELD(reg, 0, 0) | |
181 | ||
182 | /* Device 15, functions 2-5 */ | |
183 | ||
184 | static const int mtr_regs[] = { | |
185 | 0x80, 0x84, 0x88, | |
186 | }; | |
187 | ||
188 | #define RANK_DISABLE(mtr) GET_BITFIELD(mtr, 16, 19) | |
189 | #define IS_DIMM_PRESENT(mtr) GET_BITFIELD(mtr, 14, 14) | |
190 | #define RANK_CNT_BITS(mtr) GET_BITFIELD(mtr, 12, 13) | |
191 | #define RANK_WIDTH_BITS(mtr) GET_BITFIELD(mtr, 2, 4) | |
192 | #define COL_WIDTH_BITS(mtr) GET_BITFIELD(mtr, 0, 1) | |
193 | ||
194 | static const u32 tad_ch_nilv_offset[] = { | |
195 | 0x90, 0x94, 0x98, 0x9c, | |
196 | 0xa0, 0xa4, 0xa8, 0xac, | |
197 | 0xb0, 0xb4, 0xb8, 0xbc, | |
198 | }; | |
199 | #define CHN_IDX_OFFSET(reg) GET_BITFIELD(reg, 28, 29) | |
200 | #define TAD_OFFSET(reg) (GET_BITFIELD(reg, 6, 25) << 26) | |
201 | ||
202 | static const u32 rir_way_limit[] = { | |
203 | 0x108, 0x10c, 0x110, 0x114, 0x118, | |
204 | }; | |
205 | #define MAX_RIR_RANGES ARRAY_SIZE(rir_way_limit) | |
206 | ||
207 | #define IS_RIR_VALID(reg) GET_BITFIELD(reg, 31, 31) | |
208 | #define RIR_WAY(reg) GET_BITFIELD(reg, 28, 29) | |
eebf11a0 MCC |
209 | |
210 | #define MAX_RIR_WAY 8 | |
211 | ||
212 | static const u32 rir_offset[MAX_RIR_RANGES][MAX_RIR_WAY] = { | |
213 | { 0x120, 0x124, 0x128, 0x12c, 0x130, 0x134, 0x138, 0x13c }, | |
214 | { 0x140, 0x144, 0x148, 0x14c, 0x150, 0x154, 0x158, 0x15c }, | |
215 | { 0x160, 0x164, 0x168, 0x16c, 0x170, 0x174, 0x178, 0x17c }, | |
216 | { 0x180, 0x184, 0x188, 0x18c, 0x190, 0x194, 0x198, 0x19c }, | |
217 | { 0x1a0, 0x1a4, 0x1a8, 0x1ac, 0x1b0, 0x1b4, 0x1b8, 0x1bc }, | |
218 | }; | |
219 | ||
220 | #define RIR_RNK_TGT(reg) GET_BITFIELD(reg, 16, 19) | |
221 | #define RIR_OFFSET(reg) GET_BITFIELD(reg, 2, 14) | |
222 | ||
223 | /* Device 16, functions 2-7 */ | |
224 | ||
225 | /* | |
226 | * FIXME: Implement the error count reads directly | |
227 | */ | |
228 | ||
229 | static const u32 correrrcnt[] = { | |
230 | 0x104, 0x108, 0x10c, 0x110, | |
231 | }; | |
232 | ||
233 | #define RANK_ODD_OV(reg) GET_BITFIELD(reg, 31, 31) | |
234 | #define RANK_ODD_ERR_CNT(reg) GET_BITFIELD(reg, 16, 30) | |
235 | #define RANK_EVEN_OV(reg) GET_BITFIELD(reg, 15, 15) | |
236 | #define RANK_EVEN_ERR_CNT(reg) GET_BITFIELD(reg, 0, 14) | |
237 | ||
238 | static const u32 correrrthrsld[] = { | |
239 | 0x11c, 0x120, 0x124, 0x128, | |
240 | }; | |
241 | ||
242 | #define RANK_ODD_ERR_THRSLD(reg) GET_BITFIELD(reg, 16, 30) | |
243 | #define RANK_EVEN_ERR_THRSLD(reg) GET_BITFIELD(reg, 0, 14) | |
244 | ||
245 | ||
246 | /* Device 17, function 0 */ | |
247 | ||
ef1e8d03 | 248 | #define SB_RANK_CFG_A 0x0328 |
eebf11a0 | 249 | |
4d715a80 | 250 | #define IB_RANK_CFG_A 0x0320 |
eebf11a0 | 251 | |
eebf11a0 MCC |
252 | /* |
253 | * sbridge structs | |
254 | */ | |
255 | ||
351fc4a9 SJ |
256 | #define NUM_CHANNELS 4 |
257 | #define MAX_DIMMS 3 /* Max DIMMS per channel */ | |
258 | #define CHANNEL_UNSPECIFIED 0xf /* Intel IA32 SDM 15-14 */ | |
eebf11a0 | 259 | |
4d715a80 AR |
260 | enum type { |
261 | SANDY_BRIDGE, | |
262 | IVY_BRIDGE, | |
50d1bb93 | 263 | HASWELL, |
4d715a80 AR |
264 | }; |
265 | ||
fb79a509 | 266 | struct sbridge_pvt; |
eebf11a0 | 267 | struct sbridge_info { |
4d715a80 | 268 | enum type type; |
464f1d82 AR |
269 | u32 mcmtr; |
270 | u32 rankcfgr; | |
271 | u64 (*get_tolm)(struct sbridge_pvt *pvt); | |
272 | u64 (*get_tohm)(struct sbridge_pvt *pvt); | |
b976bcf2 | 273 | u64 (*rir_limit)(u32 reg); |
464f1d82 | 274 | const u32 *dram_rule; |
ef1ce51e | 275 | const u32 *interleave_list; |
cc311991 | 276 | const struct interleave_pkg *interleave_pkg; |
464f1d82 | 277 | u8 max_sad; |
ef1ce51e | 278 | u8 max_interleave; |
f14d6892 | 279 | u8 (*get_node_id)(struct sbridge_pvt *pvt); |
9e375446 | 280 | enum mem_type (*get_memory_type)(struct sbridge_pvt *pvt); |
50d1bb93 | 281 | struct pci_dev *pci_vtd; |
eebf11a0 MCC |
282 | }; |
283 | ||
284 | struct sbridge_channel { | |
285 | u32 ranks; | |
286 | u32 dimms; | |
287 | }; | |
288 | ||
289 | struct pci_id_descr { | |
c41afdca | 290 | int dev_id; |
eebf11a0 MCC |
291 | int optional; |
292 | }; | |
293 | ||
294 | struct pci_id_table { | |
295 | const struct pci_id_descr *descr; | |
296 | int n_devs; | |
297 | }; | |
298 | ||
299 | struct sbridge_dev { | |
300 | struct list_head list; | |
301 | u8 bus, mc; | |
302 | u8 node_id, source_id; | |
303 | struct pci_dev **pdev; | |
304 | int n_devs; | |
305 | struct mem_ctl_info *mci; | |
306 | }; | |
307 | ||
308 | struct sbridge_pvt { | |
309 | struct pci_dev *pci_ta, *pci_ddrio, *pci_ras; | |
4d715a80 AR |
310 | struct pci_dev *pci_sad0, *pci_sad1; |
311 | struct pci_dev *pci_ha0, *pci_ha1; | |
312 | struct pci_dev *pci_br0, *pci_br1; | |
50d1bb93 | 313 | struct pci_dev *pci_ha1_ta; |
eebf11a0 MCC |
314 | struct pci_dev *pci_tad[NUM_CHANNELS]; |
315 | ||
316 | struct sbridge_dev *sbridge_dev; | |
317 | ||
318 | struct sbridge_info info; | |
319 | struct sbridge_channel channel[NUM_CHANNELS]; | |
320 | ||
eebf11a0 MCC |
321 | /* Memory type detection */ |
322 | bool is_mirrored, is_lockstep, is_close_pg; | |
323 | ||
eebf11a0 MCC |
324 | /* Fifo double buffers */ |
325 | struct mce mce_entry[MCE_LOG_LEN]; | |
326 | struct mce mce_outentry[MCE_LOG_LEN]; | |
327 | ||
328 | /* Fifo in/out counters */ | |
329 | unsigned mce_in, mce_out; | |
330 | ||
331 | /* Count indicator to show errors not got */ | |
332 | unsigned mce_overrun; | |
333 | ||
334 | /* Memory description */ | |
335 | u64 tolm, tohm; | |
336 | }; | |
337 | ||
dbc954dd AR |
338 | #define PCI_DESCR(device_id, opt) \ |
339 | .dev_id = (device_id), \ | |
de4772c6 | 340 | .optional = opt |
eebf11a0 MCC |
341 | |
342 | static const struct pci_id_descr pci_dev_descr_sbridge[] = { | |
343 | /* Processor Home Agent */ | |
dbc954dd | 344 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0, 0) }, |
eebf11a0 MCC |
345 | |
346 | /* Memory controller */ | |
dbc954dd AR |
347 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA, 0) }, |
348 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_RAS, 0) }, | |
349 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0, 0) }, | |
350 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD1, 0) }, | |
351 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD2, 0) }, | |
352 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD3, 0) }, | |
353 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_DDRIO, 1) }, | |
eebf11a0 MCC |
354 | |
355 | /* System Address Decoder */ | |
dbc954dd AR |
356 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_SAD0, 0) }, |
357 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_SAD1, 0) }, | |
eebf11a0 MCC |
358 | |
359 | /* Broadcast Registers */ | |
dbc954dd | 360 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_BR, 0) }, |
eebf11a0 MCC |
361 | }; |
362 | ||
363 | #define PCI_ID_TABLE_ENTRY(A) { .descr=A, .n_devs = ARRAY_SIZE(A) } | |
364 | static const struct pci_id_table pci_dev_descr_sbridge_table[] = { | |
365 | PCI_ID_TABLE_ENTRY(pci_dev_descr_sbridge), | |
366 | {0,} /* 0 terminated list. */ | |
367 | }; | |
368 | ||
4d715a80 AR |
369 | /* This changes depending if 1HA or 2HA: |
370 | * 1HA: | |
371 | * 0x0eb8 (17.0) is DDRIO0 | |
372 | * 2HA: | |
373 | * 0x0ebc (17.4) is DDRIO0 | |
374 | */ | |
375 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_1HA_DDRIO0 0x0eb8 | |
376 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_2HA_DDRIO0 0x0ebc | |
377 | ||
378 | /* pci ids */ | |
379 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0 0x0ea0 | |
380 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA 0x0ea8 | |
381 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_RAS 0x0e71 | |
382 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0 0x0eaa | |
383 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD1 0x0eab | |
384 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD2 0x0eac | |
385 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD3 0x0ead | |
386 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_SAD 0x0ec8 | |
387 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_BR0 0x0ec9 | |
388 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_BR1 0x0eca | |
389 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1 0x0e60 | |
390 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TA 0x0e68 | |
391 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_RAS 0x0e79 | |
392 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0 0x0e6a | |
393 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD1 0x0e6b | |
394 | ||
395 | static const struct pci_id_descr pci_dev_descr_ibridge[] = { | |
396 | /* Processor Home Agent */ | |
dbc954dd | 397 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0, 0) }, |
4d715a80 AR |
398 | |
399 | /* Memory controller */ | |
dbc954dd AR |
400 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA, 0) }, |
401 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_RAS, 0) }, | |
402 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0, 0) }, | |
403 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD1, 0) }, | |
404 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD2, 0) }, | |
405 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD3, 0) }, | |
4d715a80 AR |
406 | |
407 | /* System Address Decoder */ | |
dbc954dd | 408 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_SAD, 0) }, |
4d715a80 AR |
409 | |
410 | /* Broadcast Registers */ | |
dbc954dd AR |
411 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_BR0, 1) }, |
412 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_BR1, 0) }, | |
4d715a80 AR |
413 | |
414 | /* Optional, mode 2HA */ | |
dbc954dd | 415 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1, 1) }, |
4d715a80 | 416 | #if 0 |
dbc954dd AR |
417 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TA, 1) }, |
418 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_RAS, 1) }, | |
4d715a80 | 419 | #endif |
dbc954dd AR |
420 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0, 1) }, |
421 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD1, 1) }, | |
4d715a80 | 422 | |
dbc954dd AR |
423 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_1HA_DDRIO0, 1) }, |
424 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_2HA_DDRIO0, 1) }, | |
4d715a80 AR |
425 | }; |
426 | ||
427 | static const struct pci_id_table pci_dev_descr_ibridge_table[] = { | |
428 | PCI_ID_TABLE_ENTRY(pci_dev_descr_ibridge), | |
429 | {0,} /* 0 terminated list. */ | |
430 | }; | |
431 | ||
50d1bb93 AR |
432 | /* Haswell support */ |
433 | /* EN processor: | |
434 | * - 1 IMC | |
435 | * - 3 DDR3 channels, 2 DPC per channel | |
436 | * EP processor: | |
437 | * - 1 or 2 IMC | |
438 | * - 4 DDR4 channels, 3 DPC per channel | |
439 | * EP 4S processor: | |
440 | * - 2 IMC | |
441 | * - 4 DDR4 channels, 3 DPC per channel | |
442 | * EX processor: | |
443 | * - 2 IMC | |
444 | * - each IMC interfaces with a SMI 2 channel | |
445 | * - each SMI channel interfaces with a scalable memory buffer | |
446 | * - each scalable memory buffer supports 4 DDR3/DDR4 channels, 3 DPC | |
447 | */ | |
448 | #define HASWELL_DDRCRCLKCONTROLS 0xa10 | |
449 | #define HASWELL_HASYSDEFEATURE2 0x84 | |
450 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_VTD_MISC 0x2f28 | |
451 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0 0x2fa0 | |
452 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1 0x2f60 | |
453 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA 0x2fa8 | |
454 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_THERMAL 0x2f71 | |
455 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TA 0x2f68 | |
456 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_THERMAL 0x2f79 | |
457 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD0 0x2ffc | |
458 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD1 0x2ffd | |
459 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD0 0x2faa | |
460 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD1 0x2fab | |
461 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD2 0x2fac | |
462 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD3 0x2fad | |
463 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD0 0x2f6a | |
464 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD1 0x2f6b | |
465 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD2 0x2f6c | |
466 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD3 0x2f6d | |
467 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO0 0x2fbd | |
468 | static const struct pci_id_descr pci_dev_descr_haswell[] = { | |
469 | /* first item must be the HA */ | |
470 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0, 0) }, | |
471 | ||
472 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD0, 0) }, | |
473 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD1, 0) }, | |
474 | ||
475 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1, 1) }, | |
476 | ||
477 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA, 0) }, | |
478 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_THERMAL, 0) }, | |
479 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD0, 0) }, | |
480 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD1, 0) }, | |
481 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD2, 1) }, | |
482 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD3, 1) }, | |
483 | ||
484 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO0, 1) }, | |
485 | ||
486 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TA, 1) }, | |
487 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_THERMAL, 1) }, | |
488 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD0, 1) }, | |
489 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD1, 1) }, | |
490 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD2, 1) }, | |
491 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD3, 1) }, | |
492 | }; | |
493 | ||
494 | static const struct pci_id_table pci_dev_descr_haswell_table[] = { | |
495 | PCI_ID_TABLE_ENTRY(pci_dev_descr_haswell), | |
496 | {0,} /* 0 terminated list. */ | |
497 | }; | |
498 | ||
eebf11a0 MCC |
499 | /* |
500 | * pci_device_id table for which devices we are looking for | |
501 | */ | |
ba935f40 | 502 | static const struct pci_device_id sbridge_pci_tbl[] = { |
d0585cd8 | 503 | {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0)}, |
4d715a80 | 504 | {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA)}, |
50d1bb93 | 505 | {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0)}, |
eebf11a0 MCC |
506 | {0,} /* 0 terminated list. */ |
507 | }; | |
508 | ||
509 | ||
510 | /**************************************************************************** | |
15ed103a | 511 | Ancillary status routines |
eebf11a0 MCC |
512 | ****************************************************************************/ |
513 | ||
50d1bb93 | 514 | static inline int numrank(enum type type, u32 mtr) |
eebf11a0 MCC |
515 | { |
516 | int ranks = (1 << RANK_CNT_BITS(mtr)); | |
50d1bb93 AR |
517 | int max = 4; |
518 | ||
519 | if (type == HASWELL) | |
520 | max = 8; | |
eebf11a0 | 521 | |
50d1bb93 AR |
522 | if (ranks > max) { |
523 | edac_dbg(0, "Invalid number of ranks: %d (max = %i) raw value = %x (%04x)\n", | |
524 | ranks, max, (unsigned int)RANK_CNT_BITS(mtr), mtr); | |
eebf11a0 MCC |
525 | return -EINVAL; |
526 | } | |
527 | ||
528 | return ranks; | |
529 | } | |
530 | ||
531 | static inline int numrow(u32 mtr) | |
532 | { | |
533 | int rows = (RANK_WIDTH_BITS(mtr) + 12); | |
534 | ||
535 | if (rows < 13 || rows > 18) { | |
956b9ba1 JP |
536 | edac_dbg(0, "Invalid number of rows: %d (should be between 14 and 17) raw value = %x (%04x)\n", |
537 | rows, (unsigned int)RANK_WIDTH_BITS(mtr), mtr); | |
eebf11a0 MCC |
538 | return -EINVAL; |
539 | } | |
540 | ||
541 | return 1 << rows; | |
542 | } | |
543 | ||
544 | static inline int numcol(u32 mtr) | |
545 | { | |
546 | int cols = (COL_WIDTH_BITS(mtr) + 10); | |
547 | ||
548 | if (cols > 12) { | |
956b9ba1 JP |
549 | edac_dbg(0, "Invalid number of cols: %d (max = 4) raw value = %x (%04x)\n", |
550 | cols, (unsigned int)COL_WIDTH_BITS(mtr), mtr); | |
eebf11a0 MCC |
551 | return -EINVAL; |
552 | } | |
553 | ||
554 | return 1 << cols; | |
555 | } | |
556 | ||
557 | static struct sbridge_dev *get_sbridge_dev(u8 bus) | |
558 | { | |
559 | struct sbridge_dev *sbridge_dev; | |
560 | ||
561 | list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) { | |
562 | if (sbridge_dev->bus == bus) | |
563 | return sbridge_dev; | |
564 | } | |
565 | ||
566 | return NULL; | |
567 | } | |
568 | ||
569 | static struct sbridge_dev *alloc_sbridge_dev(u8 bus, | |
570 | const struct pci_id_table *table) | |
571 | { | |
572 | struct sbridge_dev *sbridge_dev; | |
573 | ||
574 | sbridge_dev = kzalloc(sizeof(*sbridge_dev), GFP_KERNEL); | |
575 | if (!sbridge_dev) | |
576 | return NULL; | |
577 | ||
578 | sbridge_dev->pdev = kzalloc(sizeof(*sbridge_dev->pdev) * table->n_devs, | |
579 | GFP_KERNEL); | |
580 | if (!sbridge_dev->pdev) { | |
581 | kfree(sbridge_dev); | |
582 | return NULL; | |
583 | } | |
584 | ||
585 | sbridge_dev->bus = bus; | |
586 | sbridge_dev->n_devs = table->n_devs; | |
587 | list_add_tail(&sbridge_dev->list, &sbridge_edac_list); | |
588 | ||
589 | return sbridge_dev; | |
590 | } | |
591 | ||
592 | static void free_sbridge_dev(struct sbridge_dev *sbridge_dev) | |
593 | { | |
594 | list_del(&sbridge_dev->list); | |
595 | kfree(sbridge_dev->pdev); | |
596 | kfree(sbridge_dev); | |
597 | } | |
598 | ||
fb79a509 AR |
599 | static u64 sbridge_get_tolm(struct sbridge_pvt *pvt) |
600 | { | |
601 | u32 reg; | |
602 | ||
603 | /* Address range is 32:28 */ | |
604 | pci_read_config_dword(pvt->pci_sad1, TOLM, ®); | |
605 | return GET_TOLM(reg); | |
606 | } | |
607 | ||
8fd6a43a AR |
608 | static u64 sbridge_get_tohm(struct sbridge_pvt *pvt) |
609 | { | |
610 | u32 reg; | |
611 | ||
612 | pci_read_config_dword(pvt->pci_sad1, TOHM, ®); | |
613 | return GET_TOHM(reg); | |
614 | } | |
615 | ||
4d715a80 AR |
616 | static u64 ibridge_get_tolm(struct sbridge_pvt *pvt) |
617 | { | |
618 | u32 reg; | |
619 | ||
620 | pci_read_config_dword(pvt->pci_br1, TOLM, ®); | |
621 | ||
622 | return GET_TOLM(reg); | |
623 | } | |
624 | ||
625 | static u64 ibridge_get_tohm(struct sbridge_pvt *pvt) | |
626 | { | |
627 | u32 reg; | |
628 | ||
629 | pci_read_config_dword(pvt->pci_br1, TOHM, ®); | |
630 | ||
631 | return GET_TOHM(reg); | |
632 | } | |
633 | ||
b976bcf2 AR |
634 | static u64 rir_limit(u32 reg) |
635 | { | |
636 | return ((u64)GET_BITFIELD(reg, 1, 10) << 29) | 0x1fffffff; | |
637 | } | |
638 | ||
9e375446 AR |
639 | static enum mem_type get_memory_type(struct sbridge_pvt *pvt) |
640 | { | |
641 | u32 reg; | |
642 | enum mem_type mtype; | |
643 | ||
644 | if (pvt->pci_ddrio) { | |
645 | pci_read_config_dword(pvt->pci_ddrio, pvt->info.rankcfgr, | |
646 | ®); | |
647 | if (GET_BITFIELD(reg, 11, 11)) | |
648 | /* FIXME: Can also be LRDIMM */ | |
649 | mtype = MEM_RDDR3; | |
650 | else | |
651 | mtype = MEM_DDR3; | |
652 | } else | |
653 | mtype = MEM_UNKNOWN; | |
654 | ||
655 | return mtype; | |
656 | } | |
657 | ||
50d1bb93 AR |
658 | static enum mem_type haswell_get_memory_type(struct sbridge_pvt *pvt) |
659 | { | |
660 | u32 reg; | |
661 | bool registered = false; | |
662 | enum mem_type mtype = MEM_UNKNOWN; | |
663 | ||
664 | if (!pvt->pci_ddrio) | |
665 | goto out; | |
666 | ||
667 | pci_read_config_dword(pvt->pci_ddrio, | |
668 | HASWELL_DDRCRCLKCONTROLS, ®); | |
669 | /* Is_Rdimm */ | |
670 | if (GET_BITFIELD(reg, 16, 16)) | |
671 | registered = true; | |
672 | ||
673 | pci_read_config_dword(pvt->pci_ta, MCMTR, ®); | |
674 | if (GET_BITFIELD(reg, 14, 14)) { | |
675 | if (registered) | |
676 | mtype = MEM_RDDR4; | |
677 | else | |
678 | mtype = MEM_DDR4; | |
679 | } else { | |
680 | if (registered) | |
681 | mtype = MEM_RDDR3; | |
682 | else | |
683 | mtype = MEM_DDR3; | |
684 | } | |
685 | ||
686 | out: | |
687 | return mtype; | |
688 | } | |
689 | ||
f14d6892 AR |
690 | static u8 get_node_id(struct sbridge_pvt *pvt) |
691 | { | |
692 | u32 reg; | |
693 | pci_read_config_dword(pvt->pci_br0, SAD_CONTROL, ®); | |
694 | return GET_BITFIELD(reg, 0, 2); | |
695 | } | |
696 | ||
50d1bb93 AR |
697 | static u8 haswell_get_node_id(struct sbridge_pvt *pvt) |
698 | { | |
699 | u32 reg; | |
700 | ||
701 | pci_read_config_dword(pvt->pci_sad1, SAD_CONTROL, ®); | |
702 | return GET_BITFIELD(reg, 0, 3); | |
703 | } | |
704 | ||
705 | static u64 haswell_get_tolm(struct sbridge_pvt *pvt) | |
706 | { | |
707 | u32 reg; | |
708 | ||
709 | pci_read_config_dword(pvt->info.pci_vtd, TOLM, ®); | |
710 | return (GET_BITFIELD(reg, 26, 31) << 26) | 0x1ffffff; | |
711 | } | |
712 | ||
713 | static u64 haswell_get_tohm(struct sbridge_pvt *pvt) | |
714 | { | |
715 | u64 rc; | |
716 | u32 reg; | |
717 | ||
718 | pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOHM_0, ®); | |
719 | rc = GET_BITFIELD(reg, 26, 31); | |
720 | pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOHM_1, ®); | |
721 | rc = ((reg << 6) | rc) << 26; | |
722 | ||
723 | return rc | 0x1ffffff; | |
724 | } | |
725 | ||
726 | static u64 haswell_rir_limit(u32 reg) | |
727 | { | |
728 | return (((u64)GET_BITFIELD(reg, 1, 11) + 1) << 29) - 1; | |
729 | } | |
730 | ||
4d715a80 AR |
731 | static inline u8 sad_pkg_socket(u8 pkg) |
732 | { | |
733 | /* on Ivy Bridge, nodeID is SASS, where A is HA and S is node id */ | |
2ff3a308 | 734 | return ((pkg >> 3) << 2) | (pkg & 0x3); |
4d715a80 AR |
735 | } |
736 | ||
737 | static inline u8 sad_pkg_ha(u8 pkg) | |
738 | { | |
739 | return (pkg >> 2) & 0x1; | |
740 | } | |
741 | ||
eebf11a0 MCC |
742 | /**************************************************************************** |
743 | Memory check routines | |
744 | ****************************************************************************/ | |
dbc954dd | 745 | static struct pci_dev *get_pdev_same_bus(u8 bus, u32 id) |
eebf11a0 | 746 | { |
dbc954dd | 747 | struct pci_dev *pdev = NULL; |
eebf11a0 | 748 | |
dbc954dd AR |
749 | do { |
750 | pdev = pci_get_device(PCI_VENDOR_ID_INTEL, id, pdev); | |
751 | if (pdev && pdev->bus->number == bus) | |
752 | break; | |
753 | } while (pdev); | |
eebf11a0 | 754 | |
dbc954dd | 755 | return pdev; |
eebf11a0 MCC |
756 | } |
757 | ||
758 | /** | |
c36e3e77 | 759 | * check_if_ecc_is_active() - Checks if ECC is active |
50d1bb93 AR |
760 | * @bus: Device bus |
761 | * @type: Memory controller type | |
762 | * returns: 0 in case ECC is active, -ENODEV if it can't be determined or | |
763 | * disabled | |
eebf11a0 | 764 | */ |
dbc954dd | 765 | static int check_if_ecc_is_active(const u8 bus, enum type type) |
eebf11a0 MCC |
766 | { |
767 | struct pci_dev *pdev = NULL; | |
dbc954dd | 768 | u32 mcmtr, id; |
eebf11a0 | 769 | |
dbc954dd AR |
770 | if (type == IVY_BRIDGE) |
771 | id = PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA; | |
50d1bb93 AR |
772 | else if (type == HASWELL) |
773 | id = PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA; | |
dbc954dd AR |
774 | else |
775 | id = PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA; | |
776 | ||
777 | pdev = get_pdev_same_bus(bus, id); | |
eebf11a0 MCC |
778 | if (!pdev) { |
779 | sbridge_printk(KERN_ERR, "Couldn't find PCI device " | |
dbc954dd AR |
780 | "%04x:%04x! on bus %02d\n", |
781 | PCI_VENDOR_ID_INTEL, id, bus); | |
eebf11a0 MCC |
782 | return -ENODEV; |
783 | } | |
784 | ||
785 | pci_read_config_dword(pdev, MCMTR, &mcmtr); | |
786 | if (!IS_ECC_ENABLED(mcmtr)) { | |
787 | sbridge_printk(KERN_ERR, "ECC is disabled. Aborting\n"); | |
788 | return -ENODEV; | |
789 | } | |
eebf11a0 MCC |
790 | return 0; |
791 | } | |
792 | ||
084a4fcc | 793 | static int get_dimm_config(struct mem_ctl_info *mci) |
eebf11a0 MCC |
794 | { |
795 | struct sbridge_pvt *pvt = mci->pvt_info; | |
c36e3e77 | 796 | struct dimm_info *dimm; |
deb09dda MCC |
797 | unsigned i, j, banks, ranks, rows, cols, npages; |
798 | u64 size; | |
eebf11a0 MCC |
799 | u32 reg; |
800 | enum edac_type mode; | |
c6e13b52 | 801 | enum mem_type mtype; |
eebf11a0 | 802 | |
50d1bb93 AR |
803 | if (pvt->info.type == HASWELL) |
804 | pci_read_config_dword(pvt->pci_sad1, SAD_TARGET, ®); | |
805 | else | |
806 | pci_read_config_dword(pvt->pci_br0, SAD_TARGET, ®); | |
807 | ||
eebf11a0 MCC |
808 | pvt->sbridge_dev->source_id = SOURCE_ID(reg); |
809 | ||
f14d6892 | 810 | pvt->sbridge_dev->node_id = pvt->info.get_node_id(pvt); |
956b9ba1 JP |
811 | edac_dbg(0, "mc#%d: Node ID: %d, source ID: %d\n", |
812 | pvt->sbridge_dev->mc, | |
813 | pvt->sbridge_dev->node_id, | |
814 | pvt->sbridge_dev->source_id); | |
eebf11a0 MCC |
815 | |
816 | pci_read_config_dword(pvt->pci_ras, RASENABLES, ®); | |
817 | if (IS_MIRROR_ENABLED(reg)) { | |
956b9ba1 | 818 | edac_dbg(0, "Memory mirror is enabled\n"); |
eebf11a0 MCC |
819 | pvt->is_mirrored = true; |
820 | } else { | |
956b9ba1 | 821 | edac_dbg(0, "Memory mirror is disabled\n"); |
eebf11a0 MCC |
822 | pvt->is_mirrored = false; |
823 | } | |
824 | ||
825 | pci_read_config_dword(pvt->pci_ta, MCMTR, &pvt->info.mcmtr); | |
826 | if (IS_LOCKSTEP_ENABLED(pvt->info.mcmtr)) { | |
956b9ba1 | 827 | edac_dbg(0, "Lockstep is enabled\n"); |
eebf11a0 MCC |
828 | mode = EDAC_S8ECD8ED; |
829 | pvt->is_lockstep = true; | |
830 | } else { | |
956b9ba1 | 831 | edac_dbg(0, "Lockstep is disabled\n"); |
eebf11a0 MCC |
832 | mode = EDAC_S4ECD4ED; |
833 | pvt->is_lockstep = false; | |
834 | } | |
835 | if (IS_CLOSE_PG(pvt->info.mcmtr)) { | |
956b9ba1 | 836 | edac_dbg(0, "address map is on closed page mode\n"); |
eebf11a0 MCC |
837 | pvt->is_close_pg = true; |
838 | } else { | |
956b9ba1 | 839 | edac_dbg(0, "address map is on open page mode\n"); |
eebf11a0 MCC |
840 | pvt->is_close_pg = false; |
841 | } | |
842 | ||
9e375446 | 843 | mtype = pvt->info.get_memory_type(pvt); |
50d1bb93 | 844 | if (mtype == MEM_RDDR3 || mtype == MEM_RDDR4) |
9e375446 AR |
845 | edac_dbg(0, "Memory is registered\n"); |
846 | else if (mtype == MEM_UNKNOWN) | |
de4772c6 | 847 | edac_dbg(0, "Cannot determine memory type\n"); |
9e375446 AR |
848 | else |
849 | edac_dbg(0, "Memory is unregistered\n"); | |
eebf11a0 | 850 | |
50d1bb93 AR |
851 | if (mtype == MEM_DDR4 || MEM_RDDR4) |
852 | banks = 16; | |
853 | else | |
854 | banks = 8; | |
eebf11a0 MCC |
855 | |
856 | for (i = 0; i < NUM_CHANNELS; i++) { | |
857 | u32 mtr; | |
858 | ||
859 | for (j = 0; j < ARRAY_SIZE(mtr_regs); j++) { | |
c36e3e77 MCC |
860 | dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers, |
861 | i, j, 0); | |
eebf11a0 MCC |
862 | pci_read_config_dword(pvt->pci_tad[i], |
863 | mtr_regs[j], &mtr); | |
956b9ba1 | 864 | edac_dbg(4, "Channel #%d MTR%d = %x\n", i, j, mtr); |
eebf11a0 MCC |
865 | if (IS_DIMM_PRESENT(mtr)) { |
866 | pvt->channel[i].dimms++; | |
867 | ||
50d1bb93 | 868 | ranks = numrank(pvt->info.type, mtr); |
eebf11a0 MCC |
869 | rows = numrow(mtr); |
870 | cols = numcol(mtr); | |
871 | ||
deb09dda | 872 | size = ((u64)rows * cols * banks * ranks) >> (20 - 3); |
eebf11a0 MCC |
873 | npages = MiB_TO_PAGES(size); |
874 | ||
deb09dda | 875 | edac_dbg(0, "mc#%d: channel %d, dimm %d, %Ld Mb (%d pages) bank: %d, rank: %d, row: %#x, col: %#x\n", |
956b9ba1 JP |
876 | pvt->sbridge_dev->mc, i, j, |
877 | size, npages, | |
878 | banks, ranks, rows, cols); | |
eebf11a0 | 879 | |
a895bf8b | 880 | dimm->nr_pages = npages; |
084a4fcc | 881 | dimm->grain = 32; |
50d1bb93 AR |
882 | switch (banks) { |
883 | case 16: | |
884 | dimm->dtype = DEV_X16; | |
885 | break; | |
886 | case 8: | |
887 | dimm->dtype = DEV_X8; | |
888 | break; | |
889 | case 4: | |
890 | dimm->dtype = DEV_X4; | |
891 | break; | |
892 | } | |
084a4fcc MCC |
893 | dimm->mtype = mtype; |
894 | dimm->edac_mode = mode; | |
895 | snprintf(dimm->label, sizeof(dimm->label), | |
eebf11a0 MCC |
896 | "CPU_SrcID#%u_Channel#%u_DIMM#%u", |
897 | pvt->sbridge_dev->source_id, i, j); | |
eebf11a0 MCC |
898 | } |
899 | } | |
900 | } | |
901 | ||
902 | return 0; | |
903 | } | |
904 | ||
905 | static void get_memory_layout(const struct mem_ctl_info *mci) | |
906 | { | |
907 | struct sbridge_pvt *pvt = mci->pvt_info; | |
908 | int i, j, k, n_sads, n_tads, sad_interl; | |
909 | u32 reg; | |
910 | u64 limit, prv = 0; | |
911 | u64 tmp_mb; | |
8c009100 | 912 | u32 gb, mb; |
eebf11a0 MCC |
913 | u32 rir_way; |
914 | ||
915 | /* | |
916 | * Step 1) Get TOLM/TOHM ranges | |
917 | */ | |
918 | ||
fb79a509 | 919 | pvt->tolm = pvt->info.get_tolm(pvt); |
eebf11a0 MCC |
920 | tmp_mb = (1 + pvt->tolm) >> 20; |
921 | ||
8c009100 JS |
922 | gb = div_u64_rem(tmp_mb, 1024, &mb); |
923 | edac_dbg(0, "TOLM: %u.%03u GB (0x%016Lx)\n", | |
924 | gb, (mb*1000)/1024, (u64)pvt->tolm); | |
eebf11a0 MCC |
925 | |
926 | /* Address range is already 45:25 */ | |
8fd6a43a | 927 | pvt->tohm = pvt->info.get_tohm(pvt); |
eebf11a0 MCC |
928 | tmp_mb = (1 + pvt->tohm) >> 20; |
929 | ||
8c009100 JS |
930 | gb = div_u64_rem(tmp_mb, 1024, &mb); |
931 | edac_dbg(0, "TOHM: %u.%03u GB (0x%016Lx)\n", | |
932 | gb, (mb*1000)/1024, (u64)pvt->tohm); | |
eebf11a0 MCC |
933 | |
934 | /* | |
935 | * Step 2) Get SAD range and SAD Interleave list | |
936 | * TAD registers contain the interleave wayness. However, it | |
937 | * seems simpler to just discover it indirectly, with the | |
938 | * algorithm bellow. | |
939 | */ | |
940 | prv = 0; | |
464f1d82 | 941 | for (n_sads = 0; n_sads < pvt->info.max_sad; n_sads++) { |
eebf11a0 | 942 | /* SAD_LIMIT Address range is 45:26 */ |
464f1d82 | 943 | pci_read_config_dword(pvt->pci_sad0, pvt->info.dram_rule[n_sads], |
eebf11a0 MCC |
944 | ®); |
945 | limit = SAD_LIMIT(reg); | |
946 | ||
947 | if (!DRAM_RULE_ENABLE(reg)) | |
948 | continue; | |
949 | ||
950 | if (limit <= prv) | |
951 | break; | |
952 | ||
953 | tmp_mb = (limit + 1) >> 20; | |
8c009100 | 954 | gb = div_u64_rem(tmp_mb, 1024, &mb); |
956b9ba1 JP |
955 | edac_dbg(0, "SAD#%d %s up to %u.%03u GB (0x%016Lx) Interleave: %s reg=0x%08x\n", |
956 | n_sads, | |
957 | get_dram_attr(reg), | |
8c009100 | 958 | gb, (mb*1000)/1024, |
956b9ba1 JP |
959 | ((u64)tmp_mb) << 20L, |
960 | INTERLEAVE_MODE(reg) ? "8:6" : "[8:6]XOR[18:16]", | |
961 | reg); | |
eebf11a0 MCC |
962 | prv = limit; |
963 | ||
ef1ce51e | 964 | pci_read_config_dword(pvt->pci_sad0, pvt->info.interleave_list[n_sads], |
eebf11a0 | 965 | ®); |
cc311991 | 966 | sad_interl = sad_pkg(pvt->info.interleave_pkg, reg, 0); |
eebf11a0 | 967 | for (j = 0; j < 8; j++) { |
cc311991 AR |
968 | u32 pkg = sad_pkg(pvt->info.interleave_pkg, reg, j); |
969 | if (j > 0 && sad_interl == pkg) | |
eebf11a0 MCC |
970 | break; |
971 | ||
956b9ba1 | 972 | edac_dbg(0, "SAD#%d, interleave #%d: %d\n", |
cc311991 | 973 | n_sads, j, pkg); |
eebf11a0 MCC |
974 | } |
975 | } | |
976 | ||
977 | /* | |
978 | * Step 3) Get TAD range | |
979 | */ | |
980 | prv = 0; | |
981 | for (n_tads = 0; n_tads < MAX_TAD; n_tads++) { | |
982 | pci_read_config_dword(pvt->pci_ha0, tad_dram_rule[n_tads], | |
983 | ®); | |
984 | limit = TAD_LIMIT(reg); | |
985 | if (limit <= prv) | |
986 | break; | |
987 | tmp_mb = (limit + 1) >> 20; | |
988 | ||
8c009100 | 989 | gb = div_u64_rem(tmp_mb, 1024, &mb); |
956b9ba1 | 990 | edac_dbg(0, "TAD#%d: up to %u.%03u GB (0x%016Lx), socket interleave %d, memory interleave %d, TGT: %d, %d, %d, %d, reg=0x%08x\n", |
8c009100 | 991 | n_tads, gb, (mb*1000)/1024, |
956b9ba1 JP |
992 | ((u64)tmp_mb) << 20L, |
993 | (u32)TAD_SOCK(reg), | |
994 | (u32)TAD_CH(reg), | |
995 | (u32)TAD_TGT0(reg), | |
996 | (u32)TAD_TGT1(reg), | |
997 | (u32)TAD_TGT2(reg), | |
998 | (u32)TAD_TGT3(reg), | |
999 | reg); | |
7fae0db4 | 1000 | prv = limit; |
eebf11a0 MCC |
1001 | } |
1002 | ||
1003 | /* | |
1004 | * Step 4) Get TAD offsets, per each channel | |
1005 | */ | |
1006 | for (i = 0; i < NUM_CHANNELS; i++) { | |
1007 | if (!pvt->channel[i].dimms) | |
1008 | continue; | |
1009 | for (j = 0; j < n_tads; j++) { | |
1010 | pci_read_config_dword(pvt->pci_tad[i], | |
1011 | tad_ch_nilv_offset[j], | |
1012 | ®); | |
1013 | tmp_mb = TAD_OFFSET(reg) >> 20; | |
8c009100 | 1014 | gb = div_u64_rem(tmp_mb, 1024, &mb); |
956b9ba1 JP |
1015 | edac_dbg(0, "TAD CH#%d, offset #%d: %u.%03u GB (0x%016Lx), reg=0x%08x\n", |
1016 | i, j, | |
8c009100 | 1017 | gb, (mb*1000)/1024, |
956b9ba1 JP |
1018 | ((u64)tmp_mb) << 20L, |
1019 | reg); | |
eebf11a0 MCC |
1020 | } |
1021 | } | |
1022 | ||
1023 | /* | |
1024 | * Step 6) Get RIR Wayness/Limit, per each channel | |
1025 | */ | |
1026 | for (i = 0; i < NUM_CHANNELS; i++) { | |
1027 | if (!pvt->channel[i].dimms) | |
1028 | continue; | |
1029 | for (j = 0; j < MAX_RIR_RANGES; j++) { | |
1030 | pci_read_config_dword(pvt->pci_tad[i], | |
1031 | rir_way_limit[j], | |
1032 | ®); | |
1033 | ||
1034 | if (!IS_RIR_VALID(reg)) | |
1035 | continue; | |
1036 | ||
b976bcf2 | 1037 | tmp_mb = pvt->info.rir_limit(reg) >> 20; |
eebf11a0 | 1038 | rir_way = 1 << RIR_WAY(reg); |
8c009100 | 1039 | gb = div_u64_rem(tmp_mb, 1024, &mb); |
956b9ba1 JP |
1040 | edac_dbg(0, "CH#%d RIR#%d, limit: %u.%03u GB (0x%016Lx), way: %d, reg=0x%08x\n", |
1041 | i, j, | |
8c009100 | 1042 | gb, (mb*1000)/1024, |
956b9ba1 JP |
1043 | ((u64)tmp_mb) << 20L, |
1044 | rir_way, | |
1045 | reg); | |
eebf11a0 MCC |
1046 | |
1047 | for (k = 0; k < rir_way; k++) { | |
1048 | pci_read_config_dword(pvt->pci_tad[i], | |
1049 | rir_offset[j][k], | |
1050 | ®); | |
1051 | tmp_mb = RIR_OFFSET(reg) << 6; | |
1052 | ||
8c009100 | 1053 | gb = div_u64_rem(tmp_mb, 1024, &mb); |
956b9ba1 JP |
1054 | edac_dbg(0, "CH#%d RIR#%d INTL#%d, offset %u.%03u GB (0x%016Lx), tgt: %d, reg=0x%08x\n", |
1055 | i, j, k, | |
8c009100 | 1056 | gb, (mb*1000)/1024, |
956b9ba1 JP |
1057 | ((u64)tmp_mb) << 20L, |
1058 | (u32)RIR_RNK_TGT(reg), | |
1059 | reg); | |
eebf11a0 MCC |
1060 | } |
1061 | } | |
1062 | } | |
1063 | } | |
1064 | ||
8112c0cd | 1065 | static struct mem_ctl_info *get_mci_for_node_id(u8 node_id) |
eebf11a0 MCC |
1066 | { |
1067 | struct sbridge_dev *sbridge_dev; | |
1068 | ||
1069 | list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) { | |
1070 | if (sbridge_dev->node_id == node_id) | |
1071 | return sbridge_dev->mci; | |
1072 | } | |
1073 | return NULL; | |
1074 | } | |
1075 | ||
1076 | static int get_memory_error_data(struct mem_ctl_info *mci, | |
1077 | u64 addr, | |
1078 | u8 *socket, | |
1079 | long *channel_mask, | |
1080 | u8 *rank, | |
e17a2f42 | 1081 | char **area_type, char *msg) |
eebf11a0 MCC |
1082 | { |
1083 | struct mem_ctl_info *new_mci; | |
1084 | struct sbridge_pvt *pvt = mci->pvt_info; | |
4d715a80 | 1085 | struct pci_dev *pci_ha; |
c41afdca | 1086 | int n_rir, n_sads, n_tads, sad_way, sck_xch; |
eebf11a0 | 1087 | int sad_interl, idx, base_ch; |
50d1bb93 | 1088 | int interleave_mode, shiftup = 0; |
ef1ce51e | 1089 | unsigned sad_interleave[pvt->info.max_interleave]; |
50d1bb93 | 1090 | u32 reg, dram_rule; |
4d715a80 | 1091 | u8 ch_way, sck_way, pkg, sad_ha = 0; |
eebf11a0 MCC |
1092 | u32 tad_offset; |
1093 | u32 rir_way; | |
8c009100 | 1094 | u32 mb, gb; |
bd4b9683 | 1095 | u64 ch_addr, offset, limit = 0, prv = 0; |
eebf11a0 MCC |
1096 | |
1097 | ||
1098 | /* | |
1099 | * Step 0) Check if the address is at special memory ranges | |
1100 | * The check bellow is probably enough to fill all cases where | |
1101 | * the error is not inside a memory, except for the legacy | |
1102 | * range (e. g. VGA addresses). It is unlikely, however, that the | |
1103 | * memory controller would generate an error on that range. | |
1104 | */ | |
5b889e37 | 1105 | if ((addr > (u64) pvt->tolm) && (addr < (1LL << 32))) { |
eebf11a0 | 1106 | sprintf(msg, "Error at TOLM area, on addr 0x%08Lx", addr); |
eebf11a0 MCC |
1107 | return -EINVAL; |
1108 | } | |
1109 | if (addr >= (u64)pvt->tohm) { | |
1110 | sprintf(msg, "Error at MMIOH area, on addr 0x%016Lx", addr); | |
eebf11a0 MCC |
1111 | return -EINVAL; |
1112 | } | |
1113 | ||
1114 | /* | |
1115 | * Step 1) Get socket | |
1116 | */ | |
464f1d82 AR |
1117 | for (n_sads = 0; n_sads < pvt->info.max_sad; n_sads++) { |
1118 | pci_read_config_dword(pvt->pci_sad0, pvt->info.dram_rule[n_sads], | |
eebf11a0 MCC |
1119 | ®); |
1120 | ||
1121 | if (!DRAM_RULE_ENABLE(reg)) | |
1122 | continue; | |
1123 | ||
1124 | limit = SAD_LIMIT(reg); | |
1125 | if (limit <= prv) { | |
1126 | sprintf(msg, "Can't discover the memory socket"); | |
eebf11a0 MCC |
1127 | return -EINVAL; |
1128 | } | |
1129 | if (addr <= limit) | |
1130 | break; | |
1131 | prv = limit; | |
1132 | } | |
464f1d82 | 1133 | if (n_sads == pvt->info.max_sad) { |
eebf11a0 | 1134 | sprintf(msg, "Can't discover the memory socket"); |
eebf11a0 MCC |
1135 | return -EINVAL; |
1136 | } | |
50d1bb93 AR |
1137 | dram_rule = reg; |
1138 | *area_type = get_dram_attr(dram_rule); | |
1139 | interleave_mode = INTERLEAVE_MODE(dram_rule); | |
eebf11a0 | 1140 | |
ef1ce51e | 1141 | pci_read_config_dword(pvt->pci_sad0, pvt->info.interleave_list[n_sads], |
eebf11a0 | 1142 | ®); |
4d715a80 AR |
1143 | |
1144 | if (pvt->info.type == SANDY_BRIDGE) { | |
1145 | sad_interl = sad_pkg(pvt->info.interleave_pkg, reg, 0); | |
1146 | for (sad_way = 0; sad_way < 8; sad_way++) { | |
1147 | u32 pkg = sad_pkg(pvt->info.interleave_pkg, reg, sad_way); | |
1148 | if (sad_way > 0 && sad_interl == pkg) | |
1149 | break; | |
1150 | sad_interleave[sad_way] = pkg; | |
1151 | edac_dbg(0, "SAD interleave #%d: %d\n", | |
1152 | sad_way, sad_interleave[sad_way]); | |
1153 | } | |
1154 | edac_dbg(0, "mc#%d: Error detected on SAD#%d: address 0x%016Lx < 0x%016Lx, Interleave [%d:6]%s\n", | |
1155 | pvt->sbridge_dev->mc, | |
1156 | n_sads, | |
1157 | addr, | |
1158 | limit, | |
1159 | sad_way + 7, | |
1160 | !interleave_mode ? "" : "XOR[18:16]"); | |
1161 | if (interleave_mode) | |
1162 | idx = ((addr >> 6) ^ (addr >> 16)) & 7; | |
1163 | else | |
1164 | idx = (addr >> 6) & 7; | |
1165 | switch (sad_way) { | |
1166 | case 1: | |
1167 | idx = 0; | |
eebf11a0 | 1168 | break; |
4d715a80 AR |
1169 | case 2: |
1170 | idx = idx & 1; | |
1171 | break; | |
1172 | case 4: | |
1173 | idx = idx & 3; | |
1174 | break; | |
1175 | case 8: | |
1176 | break; | |
1177 | default: | |
1178 | sprintf(msg, "Can't discover socket interleave"); | |
1179 | return -EINVAL; | |
1180 | } | |
1181 | *socket = sad_interleave[idx]; | |
1182 | edac_dbg(0, "SAD interleave index: %d (wayness %d) = CPU socket %d\n", | |
1183 | idx, sad_way, *socket); | |
50d1bb93 AR |
1184 | } else if (pvt->info.type == HASWELL) { |
1185 | int bits, a7mode = A7MODE(dram_rule); | |
1186 | ||
1187 | if (a7mode) { | |
1188 | /* A7 mode swaps P9 with P6 */ | |
1189 | bits = GET_BITFIELD(addr, 7, 8) << 1; | |
1190 | bits |= GET_BITFIELD(addr, 9, 9); | |
1191 | } else | |
1192 | bits = GET_BITFIELD(addr, 7, 9); | |
1193 | ||
1194 | if (interleave_mode) { | |
1195 | /* interleave mode will XOR {8,7,6} with {18,17,16} */ | |
1196 | idx = GET_BITFIELD(addr, 16, 18); | |
1197 | idx ^= bits; | |
1198 | } else | |
1199 | idx = bits; | |
1200 | ||
1201 | pkg = sad_pkg(pvt->info.interleave_pkg, reg, idx); | |
1202 | *socket = sad_pkg_socket(pkg); | |
1203 | sad_ha = sad_pkg_ha(pkg); | |
1204 | ||
1205 | if (a7mode) { | |
1206 | /* MCChanShiftUpEnable */ | |
1207 | pci_read_config_dword(pvt->pci_ha0, | |
1208 | HASWELL_HASYSDEFEATURE2, ®); | |
1209 | shiftup = GET_BITFIELD(reg, 22, 22); | |
1210 | } | |
1211 | ||
1212 | edac_dbg(0, "SAD interleave package: %d = CPU socket %d, HA %i, shiftup: %i\n", | |
1213 | idx, *socket, sad_ha, shiftup); | |
4d715a80 AR |
1214 | } else { |
1215 | /* Ivy Bridge's SAD mode doesn't support XOR interleave mode */ | |
eebf11a0 | 1216 | idx = (addr >> 6) & 7; |
4d715a80 AR |
1217 | pkg = sad_pkg(pvt->info.interleave_pkg, reg, idx); |
1218 | *socket = sad_pkg_socket(pkg); | |
1219 | sad_ha = sad_pkg_ha(pkg); | |
1220 | edac_dbg(0, "SAD interleave package: %d = CPU socket %d, HA %d\n", | |
1221 | idx, *socket, sad_ha); | |
eebf11a0 | 1222 | } |
eebf11a0 MCC |
1223 | |
1224 | /* | |
1225 | * Move to the proper node structure, in order to access the | |
1226 | * right PCI registers | |
1227 | */ | |
1228 | new_mci = get_mci_for_node_id(*socket); | |
1229 | if (!new_mci) { | |
1230 | sprintf(msg, "Struct for socket #%u wasn't initialized", | |
1231 | *socket); | |
eebf11a0 MCC |
1232 | return -EINVAL; |
1233 | } | |
1234 | mci = new_mci; | |
1235 | pvt = mci->pvt_info; | |
1236 | ||
1237 | /* | |
1238 | * Step 2) Get memory channel | |
1239 | */ | |
1240 | prv = 0; | |
4d715a80 AR |
1241 | if (pvt->info.type == SANDY_BRIDGE) |
1242 | pci_ha = pvt->pci_ha0; | |
1243 | else { | |
1244 | if (sad_ha) | |
1245 | pci_ha = pvt->pci_ha1; | |
1246 | else | |
1247 | pci_ha = pvt->pci_ha0; | |
1248 | } | |
eebf11a0 | 1249 | for (n_tads = 0; n_tads < MAX_TAD; n_tads++) { |
4d715a80 | 1250 | pci_read_config_dword(pci_ha, tad_dram_rule[n_tads], ®); |
eebf11a0 MCC |
1251 | limit = TAD_LIMIT(reg); |
1252 | if (limit <= prv) { | |
1253 | sprintf(msg, "Can't discover the memory channel"); | |
eebf11a0 MCC |
1254 | return -EINVAL; |
1255 | } | |
1256 | if (addr <= limit) | |
1257 | break; | |
1258 | prv = limit; | |
1259 | } | |
4d715a80 AR |
1260 | if (n_tads == MAX_TAD) { |
1261 | sprintf(msg, "Can't discover the memory channel"); | |
1262 | return -EINVAL; | |
1263 | } | |
1264 | ||
eebf11a0 MCC |
1265 | ch_way = TAD_CH(reg) + 1; |
1266 | sck_way = TAD_SOCK(reg) + 1; | |
eebf11a0 MCC |
1267 | |
1268 | if (ch_way == 3) | |
1269 | idx = addr >> 6; | |
1270 | else | |
50d1bb93 | 1271 | idx = (addr >> (6 + sck_way + shiftup)) & 0x3; |
eebf11a0 MCC |
1272 | idx = idx % ch_way; |
1273 | ||
1274 | /* | |
1275 | * FIXME: Shouldn't we use CHN_IDX_OFFSET() here, when ch_way == 3 ??? | |
1276 | */ | |
1277 | switch (idx) { | |
1278 | case 0: | |
1279 | base_ch = TAD_TGT0(reg); | |
1280 | break; | |
1281 | case 1: | |
1282 | base_ch = TAD_TGT1(reg); | |
1283 | break; | |
1284 | case 2: | |
1285 | base_ch = TAD_TGT2(reg); | |
1286 | break; | |
1287 | case 3: | |
1288 | base_ch = TAD_TGT3(reg); | |
1289 | break; | |
1290 | default: | |
1291 | sprintf(msg, "Can't discover the TAD target"); | |
eebf11a0 MCC |
1292 | return -EINVAL; |
1293 | } | |
1294 | *channel_mask = 1 << base_ch; | |
1295 | ||
4d715a80 AR |
1296 | pci_read_config_dword(pvt->pci_tad[base_ch], |
1297 | tad_ch_nilv_offset[n_tads], | |
1298 | &tad_offset); | |
1299 | ||
eebf11a0 MCC |
1300 | if (pvt->is_mirrored) { |
1301 | *channel_mask |= 1 << ((base_ch + 2) % 4); | |
1302 | switch(ch_way) { | |
1303 | case 2: | |
1304 | case 4: | |
1305 | sck_xch = 1 << sck_way * (ch_way >> 1); | |
1306 | break; | |
1307 | default: | |
1308 | sprintf(msg, "Invalid mirror set. Can't decode addr"); | |
eebf11a0 MCC |
1309 | return -EINVAL; |
1310 | } | |
1311 | } else | |
1312 | sck_xch = (1 << sck_way) * ch_way; | |
1313 | ||
1314 | if (pvt->is_lockstep) | |
1315 | *channel_mask |= 1 << ((base_ch + 1) % 4); | |
1316 | ||
1317 | offset = TAD_OFFSET(tad_offset); | |
1318 | ||
956b9ba1 JP |
1319 | edac_dbg(0, "TAD#%d: address 0x%016Lx < 0x%016Lx, socket interleave %d, channel interleave %d (offset 0x%08Lx), index %d, base ch: %d, ch mask: 0x%02lx\n", |
1320 | n_tads, | |
1321 | addr, | |
1322 | limit, | |
1323 | (u32)TAD_SOCK(reg), | |
1324 | ch_way, | |
1325 | offset, | |
1326 | idx, | |
1327 | base_ch, | |
1328 | *channel_mask); | |
eebf11a0 MCC |
1329 | |
1330 | /* Calculate channel address */ | |
1331 | /* Remove the TAD offset */ | |
1332 | ||
1333 | if (offset > addr) { | |
1334 | sprintf(msg, "Can't calculate ch addr: TAD offset 0x%08Lx is too high for addr 0x%08Lx!", | |
1335 | offset, addr); | |
eebf11a0 MCC |
1336 | return -EINVAL; |
1337 | } | |
1338 | addr -= offset; | |
1339 | /* Store the low bits [0:6] of the addr */ | |
1340 | ch_addr = addr & 0x7f; | |
1341 | /* Remove socket wayness and remove 6 bits */ | |
1342 | addr >>= 6; | |
5b889e37 | 1343 | addr = div_u64(addr, sck_xch); |
eebf11a0 MCC |
1344 | #if 0 |
1345 | /* Divide by channel way */ | |
1346 | addr = addr / ch_way; | |
1347 | #endif | |
1348 | /* Recover the last 6 bits */ | |
1349 | ch_addr |= addr << 6; | |
1350 | ||
1351 | /* | |
1352 | * Step 3) Decode rank | |
1353 | */ | |
1354 | for (n_rir = 0; n_rir < MAX_RIR_RANGES; n_rir++) { | |
1355 | pci_read_config_dword(pvt->pci_tad[base_ch], | |
1356 | rir_way_limit[n_rir], | |
1357 | ®); | |
1358 | ||
1359 | if (!IS_RIR_VALID(reg)) | |
1360 | continue; | |
1361 | ||
b976bcf2 | 1362 | limit = pvt->info.rir_limit(reg); |
8c009100 | 1363 | gb = div_u64_rem(limit >> 20, 1024, &mb); |
956b9ba1 JP |
1364 | edac_dbg(0, "RIR#%d, limit: %u.%03u GB (0x%016Lx), way: %d\n", |
1365 | n_rir, | |
8c009100 | 1366 | gb, (mb*1000)/1024, |
956b9ba1 JP |
1367 | limit, |
1368 | 1 << RIR_WAY(reg)); | |
eebf11a0 MCC |
1369 | if (ch_addr <= limit) |
1370 | break; | |
1371 | } | |
1372 | if (n_rir == MAX_RIR_RANGES) { | |
1373 | sprintf(msg, "Can't discover the memory rank for ch addr 0x%08Lx", | |
1374 | ch_addr); | |
eebf11a0 MCC |
1375 | return -EINVAL; |
1376 | } | |
1377 | rir_way = RIR_WAY(reg); | |
50d1bb93 | 1378 | |
eebf11a0 MCC |
1379 | if (pvt->is_close_pg) |
1380 | idx = (ch_addr >> 6); | |
1381 | else | |
1382 | idx = (ch_addr >> 13); /* FIXME: Datasheet says to shift by 15 */ | |
1383 | idx %= 1 << rir_way; | |
1384 | ||
1385 | pci_read_config_dword(pvt->pci_tad[base_ch], | |
1386 | rir_offset[n_rir][idx], | |
1387 | ®); | |
1388 | *rank = RIR_RNK_TGT(reg); | |
1389 | ||
956b9ba1 JP |
1390 | edac_dbg(0, "RIR#%d: channel address 0x%08Lx < 0x%08Lx, RIR interleave %d, index %d\n", |
1391 | n_rir, | |
1392 | ch_addr, | |
1393 | limit, | |
1394 | rir_way, | |
1395 | idx); | |
eebf11a0 MCC |
1396 | |
1397 | return 0; | |
1398 | } | |
1399 | ||
1400 | /**************************************************************************** | |
1401 | Device initialization routines: put/get, init/exit | |
1402 | ****************************************************************************/ | |
1403 | ||
1404 | /* | |
1405 | * sbridge_put_all_devices 'put' all the devices that we have | |
1406 | * reserved via 'get' | |
1407 | */ | |
1408 | static void sbridge_put_devices(struct sbridge_dev *sbridge_dev) | |
1409 | { | |
1410 | int i; | |
1411 | ||
956b9ba1 | 1412 | edac_dbg(0, "\n"); |
eebf11a0 MCC |
1413 | for (i = 0; i < sbridge_dev->n_devs; i++) { |
1414 | struct pci_dev *pdev = sbridge_dev->pdev[i]; | |
1415 | if (!pdev) | |
1416 | continue; | |
956b9ba1 JP |
1417 | edac_dbg(0, "Removing dev %02x:%02x.%d\n", |
1418 | pdev->bus->number, | |
1419 | PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn)); | |
eebf11a0 MCC |
1420 | pci_dev_put(pdev); |
1421 | } | |
1422 | } | |
1423 | ||
1424 | static void sbridge_put_all_devices(void) | |
1425 | { | |
1426 | struct sbridge_dev *sbridge_dev, *tmp; | |
1427 | ||
1428 | list_for_each_entry_safe(sbridge_dev, tmp, &sbridge_edac_list, list) { | |
1429 | sbridge_put_devices(sbridge_dev); | |
1430 | free_sbridge_dev(sbridge_dev); | |
1431 | } | |
1432 | } | |
1433 | ||
eebf11a0 MCC |
1434 | static int sbridge_get_onedevice(struct pci_dev **prev, |
1435 | u8 *num_mc, | |
1436 | const struct pci_id_table *table, | |
1437 | const unsigned devno) | |
1438 | { | |
1439 | struct sbridge_dev *sbridge_dev; | |
1440 | const struct pci_id_descr *dev_descr = &table->descr[devno]; | |
eebf11a0 MCC |
1441 | struct pci_dev *pdev = NULL; |
1442 | u8 bus = 0; | |
1443 | ||
ec5a0b38 | 1444 | sbridge_printk(KERN_DEBUG, |
dbc954dd | 1445 | "Seeking for: PCI ID %04x:%04x\n", |
eebf11a0 MCC |
1446 | PCI_VENDOR_ID_INTEL, dev_descr->dev_id); |
1447 | ||
1448 | pdev = pci_get_device(PCI_VENDOR_ID_INTEL, | |
1449 | dev_descr->dev_id, *prev); | |
1450 | ||
1451 | if (!pdev) { | |
1452 | if (*prev) { | |
1453 | *prev = pdev; | |
1454 | return 0; | |
1455 | } | |
1456 | ||
1457 | if (dev_descr->optional) | |
1458 | return 0; | |
1459 | ||
dbc954dd | 1460 | /* if the HA wasn't found */ |
eebf11a0 MCC |
1461 | if (devno == 0) |
1462 | return -ENODEV; | |
1463 | ||
1464 | sbridge_printk(KERN_INFO, | |
dbc954dd | 1465 | "Device not found: %04x:%04x\n", |
eebf11a0 MCC |
1466 | PCI_VENDOR_ID_INTEL, dev_descr->dev_id); |
1467 | ||
1468 | /* End of list, leave */ | |
1469 | return -ENODEV; | |
1470 | } | |
1471 | bus = pdev->bus->number; | |
1472 | ||
1473 | sbridge_dev = get_sbridge_dev(bus); | |
1474 | if (!sbridge_dev) { | |
1475 | sbridge_dev = alloc_sbridge_dev(bus, table); | |
1476 | if (!sbridge_dev) { | |
1477 | pci_dev_put(pdev); | |
1478 | return -ENOMEM; | |
1479 | } | |
1480 | (*num_mc)++; | |
1481 | } | |
1482 | ||
1483 | if (sbridge_dev->pdev[devno]) { | |
1484 | sbridge_printk(KERN_ERR, | |
dbc954dd | 1485 | "Duplicated device for %04x:%04x\n", |
eebf11a0 MCC |
1486 | PCI_VENDOR_ID_INTEL, dev_descr->dev_id); |
1487 | pci_dev_put(pdev); | |
1488 | return -ENODEV; | |
1489 | } | |
1490 | ||
1491 | sbridge_dev->pdev[devno] = pdev; | |
1492 | ||
eebf11a0 MCC |
1493 | /* Be sure that the device is enabled */ |
1494 | if (unlikely(pci_enable_device(pdev) < 0)) { | |
1495 | sbridge_printk(KERN_ERR, | |
dbc954dd | 1496 | "Couldn't enable %04x:%04x\n", |
eebf11a0 MCC |
1497 | PCI_VENDOR_ID_INTEL, dev_descr->dev_id); |
1498 | return -ENODEV; | |
1499 | } | |
1500 | ||
dbc954dd | 1501 | edac_dbg(0, "Detected %04x:%04x\n", |
956b9ba1 | 1502 | PCI_VENDOR_ID_INTEL, dev_descr->dev_id); |
eebf11a0 MCC |
1503 | |
1504 | /* | |
1505 | * As stated on drivers/pci/search.c, the reference count for | |
1506 | * @from is always decremented if it is not %NULL. So, as we need | |
1507 | * to get all devices up to null, we need to do a get for the device | |
1508 | */ | |
1509 | pci_dev_get(pdev); | |
1510 | ||
1511 | *prev = pdev; | |
1512 | ||
1513 | return 0; | |
1514 | } | |
1515 | ||
5153a0f9 AR |
1516 | /* |
1517 | * sbridge_get_all_devices - Find and perform 'get' operation on the MCH's | |
dbc954dd | 1518 | * devices we want to reference for this driver. |
5153a0f9 | 1519 | * @num_mc: pointer to the memory controllers count, to be incremented in case |
c41afdca | 1520 | * of success. |
5153a0f9 AR |
1521 | * @table: model specific table |
1522 | * | |
1523 | * returns 0 in case of success or error code | |
1524 | */ | |
1525 | static int sbridge_get_all_devices(u8 *num_mc, | |
1526 | const struct pci_id_table *table) | |
eebf11a0 MCC |
1527 | { |
1528 | int i, rc; | |
1529 | struct pci_dev *pdev = NULL; | |
eebf11a0 MCC |
1530 | |
1531 | while (table && table->descr) { | |
1532 | for (i = 0; i < table->n_devs; i++) { | |
1533 | pdev = NULL; | |
1534 | do { | |
1535 | rc = sbridge_get_onedevice(&pdev, num_mc, | |
1536 | table, i); | |
1537 | if (rc < 0) { | |
1538 | if (i == 0) { | |
1539 | i = table->n_devs; | |
1540 | break; | |
1541 | } | |
1542 | sbridge_put_all_devices(); | |
1543 | return -ENODEV; | |
1544 | } | |
1545 | } while (pdev); | |
1546 | } | |
1547 | table++; | |
1548 | } | |
1549 | ||
1550 | return 0; | |
1551 | } | |
1552 | ||
ea779b5a AR |
1553 | static int sbridge_mci_bind_devs(struct mem_ctl_info *mci, |
1554 | struct sbridge_dev *sbridge_dev) | |
eebf11a0 MCC |
1555 | { |
1556 | struct sbridge_pvt *pvt = mci->pvt_info; | |
1557 | struct pci_dev *pdev; | |
dbc954dd | 1558 | int i; |
eebf11a0 MCC |
1559 | |
1560 | for (i = 0; i < sbridge_dev->n_devs; i++) { | |
1561 | pdev = sbridge_dev->pdev[i]; | |
1562 | if (!pdev) | |
1563 | continue; | |
dbc954dd AR |
1564 | |
1565 | switch (pdev->device) { | |
1566 | case PCI_DEVICE_ID_INTEL_SBRIDGE_SAD0: | |
1567 | pvt->pci_sad0 = pdev; | |
eebf11a0 | 1568 | break; |
dbc954dd AR |
1569 | case PCI_DEVICE_ID_INTEL_SBRIDGE_SAD1: |
1570 | pvt->pci_sad1 = pdev; | |
eebf11a0 | 1571 | break; |
dbc954dd AR |
1572 | case PCI_DEVICE_ID_INTEL_SBRIDGE_BR: |
1573 | pvt->pci_br0 = pdev; | |
eebf11a0 | 1574 | break; |
dbc954dd AR |
1575 | case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0: |
1576 | pvt->pci_ha0 = pdev; | |
eebf11a0 | 1577 | break; |
dbc954dd AR |
1578 | case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA: |
1579 | pvt->pci_ta = pdev; | |
1580 | break; | |
1581 | case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_RAS: | |
1582 | pvt->pci_ras = pdev; | |
1583 | break; | |
1584 | case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0: | |
1585 | case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD1: | |
1586 | case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD2: | |
1587 | case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD3: | |
1588 | { | |
1589 | int id = pdev->device - PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0; | |
1590 | pvt->pci_tad[id] = pdev; | |
1591 | } | |
1592 | break; | |
1593 | case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_DDRIO: | |
1594 | pvt->pci_ddrio = pdev; | |
eebf11a0 MCC |
1595 | break; |
1596 | default: | |
1597 | goto error; | |
1598 | } | |
1599 | ||
dbc954dd AR |
1600 | edac_dbg(0, "Associated PCI %02x:%02x, bus %d with dev = %p\n", |
1601 | pdev->vendor, pdev->device, | |
956b9ba1 | 1602 | sbridge_dev->bus, |
956b9ba1 | 1603 | pdev); |
eebf11a0 MCC |
1604 | } |
1605 | ||
1606 | /* Check if everything were registered */ | |
1607 | if (!pvt->pci_sad0 || !pvt->pci_sad1 || !pvt->pci_ha0 || | |
de4772c6 | 1608 | !pvt-> pci_tad || !pvt->pci_ras || !pvt->pci_ta) |
eebf11a0 MCC |
1609 | goto enodev; |
1610 | ||
1611 | for (i = 0; i < NUM_CHANNELS; i++) { | |
1612 | if (!pvt->pci_tad[i]) | |
1613 | goto enodev; | |
1614 | } | |
1615 | return 0; | |
1616 | ||
1617 | enodev: | |
1618 | sbridge_printk(KERN_ERR, "Some needed devices are missing\n"); | |
1619 | return -ENODEV; | |
1620 | ||
1621 | error: | |
dbc954dd AR |
1622 | sbridge_printk(KERN_ERR, "Unexpected device %02x:%02x\n", |
1623 | PCI_VENDOR_ID_INTEL, pdev->device); | |
eebf11a0 MCC |
1624 | return -EINVAL; |
1625 | } | |
1626 | ||
4d715a80 AR |
1627 | static int ibridge_mci_bind_devs(struct mem_ctl_info *mci, |
1628 | struct sbridge_dev *sbridge_dev) | |
1629 | { | |
1630 | struct sbridge_pvt *pvt = mci->pvt_info; | |
1631 | struct pci_dev *pdev, *tmp; | |
dbc954dd | 1632 | int i; |
4d715a80 AR |
1633 | bool mode_2ha = false; |
1634 | ||
1635 | tmp = pci_get_device(PCI_VENDOR_ID_INTEL, | |
1636 | PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1, NULL); | |
1637 | if (tmp) { | |
1638 | mode_2ha = true; | |
1639 | pci_dev_put(tmp); | |
1640 | } | |
1641 | ||
1642 | for (i = 0; i < sbridge_dev->n_devs; i++) { | |
1643 | pdev = sbridge_dev->pdev[i]; | |
1644 | if (!pdev) | |
1645 | continue; | |
4d715a80 | 1646 | |
dbc954dd AR |
1647 | switch (pdev->device) { |
1648 | case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0: | |
1649 | pvt->pci_ha0 = pdev; | |
1650 | break; | |
1651 | case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA: | |
1652 | pvt->pci_ta = pdev; | |
1653 | case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_RAS: | |
1654 | pvt->pci_ras = pdev; | |
1655 | break; | |
1656 | case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD2: | |
1657 | case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD3: | |
1658 | /* if we have 2 HAs active, channels 2 and 3 | |
1659 | * are in other device */ | |
1660 | if (mode_2ha) | |
4d715a80 | 1661 | break; |
dbc954dd AR |
1662 | /* fall through */ |
1663 | case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0: | |
1664 | case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD1: | |
1665 | { | |
1666 | int id = pdev->device - PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0; | |
1667 | pvt->pci_tad[id] = pdev; | |
1668 | } | |
4d715a80 | 1669 | break; |
dbc954dd AR |
1670 | case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_2HA_DDRIO0: |
1671 | pvt->pci_ddrio = pdev; | |
1672 | break; | |
1673 | case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_1HA_DDRIO0: | |
1674 | if (!mode_2ha) | |
4d715a80 | 1675 | pvt->pci_ddrio = pdev; |
4d715a80 | 1676 | break; |
dbc954dd AR |
1677 | case PCI_DEVICE_ID_INTEL_IBRIDGE_SAD: |
1678 | pvt->pci_sad0 = pdev; | |
1679 | break; | |
1680 | case PCI_DEVICE_ID_INTEL_IBRIDGE_BR0: | |
1681 | pvt->pci_br0 = pdev; | |
1682 | break; | |
1683 | case PCI_DEVICE_ID_INTEL_IBRIDGE_BR1: | |
1684 | pvt->pci_br1 = pdev; | |
1685 | break; | |
1686 | case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1: | |
1687 | pvt->pci_ha1 = pdev; | |
1688 | break; | |
1689 | case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0: | |
1690 | case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD1: | |
1691 | { | |
1692 | int id = pdev->device - PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0 + 2; | |
1693 | ||
4d715a80 AR |
1694 | /* we shouldn't have this device if we have just one |
1695 | * HA present */ | |
1696 | WARN_ON(!mode_2ha); | |
dbc954dd AR |
1697 | pvt->pci_tad[id] = pdev; |
1698 | } | |
1699 | break; | |
4d715a80 AR |
1700 | default: |
1701 | goto error; | |
1702 | } | |
1703 | ||
1704 | edac_dbg(0, "Associated PCI %02x.%02d.%d with dev = %p\n", | |
1705 | sbridge_dev->bus, | |
1706 | PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), | |
1707 | pdev); | |
1708 | } | |
1709 | ||
1710 | /* Check if everything were registered */ | |
1711 | if (!pvt->pci_sad0 || !pvt->pci_ha0 || !pvt->pci_br0 || | |
1712 | !pvt->pci_br1 || !pvt->pci_tad || !pvt->pci_ras || | |
1713 | !pvt->pci_ta) | |
1714 | goto enodev; | |
1715 | ||
1716 | for (i = 0; i < NUM_CHANNELS; i++) { | |
1717 | if (!pvt->pci_tad[i]) | |
1718 | goto enodev; | |
1719 | } | |
1720 | return 0; | |
1721 | ||
1722 | enodev: | |
1723 | sbridge_printk(KERN_ERR, "Some needed devices are missing\n"); | |
1724 | return -ENODEV; | |
1725 | ||
1726 | error: | |
1727 | sbridge_printk(KERN_ERR, | |
dbc954dd AR |
1728 | "Unexpected device %02x:%02x\n", PCI_VENDOR_ID_INTEL, |
1729 | pdev->device); | |
4d715a80 AR |
1730 | return -EINVAL; |
1731 | } | |
1732 | ||
50d1bb93 AR |
1733 | static int haswell_mci_bind_devs(struct mem_ctl_info *mci, |
1734 | struct sbridge_dev *sbridge_dev) | |
1735 | { | |
1736 | struct sbridge_pvt *pvt = mci->pvt_info; | |
1737 | struct pci_dev *pdev, *tmp; | |
1738 | int i; | |
1739 | bool mode_2ha = false; | |
1740 | ||
1741 | tmp = pci_get_device(PCI_VENDOR_ID_INTEL, | |
1742 | PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1, NULL); | |
1743 | if (tmp) { | |
1744 | mode_2ha = true; | |
1745 | pci_dev_put(tmp); | |
1746 | } | |
1747 | ||
1748 | /* there's only one device per system; not tied to any bus */ | |
1749 | if (pvt->info.pci_vtd == NULL) | |
1750 | /* result will be checked later */ | |
1751 | pvt->info.pci_vtd = pci_get_device(PCI_VENDOR_ID_INTEL, | |
1752 | PCI_DEVICE_ID_INTEL_HASWELL_IMC_VTD_MISC, | |
1753 | NULL); | |
1754 | ||
1755 | for (i = 0; i < sbridge_dev->n_devs; i++) { | |
1756 | pdev = sbridge_dev->pdev[i]; | |
1757 | if (!pdev) | |
1758 | continue; | |
1759 | ||
1760 | switch (pdev->device) { | |
1761 | case PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD0: | |
1762 | pvt->pci_sad0 = pdev; | |
1763 | break; | |
1764 | case PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD1: | |
1765 | pvt->pci_sad1 = pdev; | |
1766 | break; | |
1767 | case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0: | |
1768 | pvt->pci_ha0 = pdev; | |
1769 | break; | |
1770 | case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA: | |
1771 | pvt->pci_ta = pdev; | |
1772 | break; | |
1773 | case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_THERMAL: | |
1774 | pvt->pci_ras = pdev; | |
1775 | break; | |
1776 | case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD0: | |
1777 | pvt->pci_tad[0] = pdev; | |
1778 | break; | |
1779 | case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD1: | |
1780 | pvt->pci_tad[1] = pdev; | |
1781 | break; | |
1782 | case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD2: | |
1783 | if (!mode_2ha) | |
1784 | pvt->pci_tad[2] = pdev; | |
1785 | break; | |
1786 | case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD3: | |
1787 | if (!mode_2ha) | |
1788 | pvt->pci_tad[3] = pdev; | |
1789 | break; | |
1790 | case PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO0: | |
1791 | pvt->pci_ddrio = pdev; | |
1792 | break; | |
1793 | case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1: | |
1794 | pvt->pci_ha1 = pdev; | |
1795 | break; | |
1796 | case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TA: | |
1797 | pvt->pci_ha1_ta = pdev; | |
1798 | break; | |
1799 | case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD0: | |
1800 | if (mode_2ha) | |
1801 | pvt->pci_tad[2] = pdev; | |
1802 | break; | |
1803 | case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD1: | |
1804 | if (mode_2ha) | |
1805 | pvt->pci_tad[3] = pdev; | |
1806 | break; | |
1807 | default: | |
1808 | break; | |
1809 | } | |
1810 | ||
1811 | edac_dbg(0, "Associated PCI %02x.%02d.%d with dev = %p\n", | |
1812 | sbridge_dev->bus, | |
1813 | PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), | |
1814 | pdev); | |
1815 | } | |
1816 | ||
1817 | /* Check if everything were registered */ | |
1818 | if (!pvt->pci_sad0 || !pvt->pci_ha0 || !pvt->pci_sad1 || | |
1819 | !pvt->pci_ras || !pvt->pci_ta || !pvt->info.pci_vtd) | |
1820 | goto enodev; | |
1821 | ||
1822 | for (i = 0; i < NUM_CHANNELS; i++) { | |
1823 | if (!pvt->pci_tad[i]) | |
1824 | goto enodev; | |
1825 | } | |
1826 | return 0; | |
1827 | ||
1828 | enodev: | |
1829 | sbridge_printk(KERN_ERR, "Some needed devices are missing\n"); | |
1830 | return -ENODEV; | |
1831 | } | |
1832 | ||
eebf11a0 MCC |
1833 | /**************************************************************************** |
1834 | Error check routines | |
1835 | ****************************************************************************/ | |
1836 | ||
1837 | /* | |
1838 | * While Sandy Bridge has error count registers, SMI BIOS read values from | |
1839 | * and resets the counters. So, they are not reliable for the OS to read | |
1840 | * from them. So, we have no option but to just trust on whatever MCE is | |
1841 | * telling us about the errors. | |
1842 | */ | |
1843 | static void sbridge_mce_output_error(struct mem_ctl_info *mci, | |
1844 | const struct mce *m) | |
1845 | { | |
1846 | struct mem_ctl_info *new_mci; | |
1847 | struct sbridge_pvt *pvt = mci->pvt_info; | |
c36e3e77 | 1848 | enum hw_event_mc_err_type tp_event; |
e17a2f42 | 1849 | char *type, *optype, msg[256]; |
eebf11a0 MCC |
1850 | bool ripv = GET_BITFIELD(m->mcgstatus, 0, 0); |
1851 | bool overflow = GET_BITFIELD(m->status, 62, 62); | |
1852 | bool uncorrected_error = GET_BITFIELD(m->status, 61, 61); | |
4d715a80 | 1853 | bool recoverable; |
eebf11a0 MCC |
1854 | u32 core_err_cnt = GET_BITFIELD(m->status, 38, 52); |
1855 | u32 mscod = GET_BITFIELD(m->status, 16, 31); | |
1856 | u32 errcode = GET_BITFIELD(m->status, 0, 15); | |
1857 | u32 channel = GET_BITFIELD(m->status, 0, 3); | |
1858 | u32 optypenum = GET_BITFIELD(m->status, 4, 6); | |
1859 | long channel_mask, first_channel; | |
1860 | u8 rank, socket; | |
c36e3e77 | 1861 | int rc, dimm; |
e17a2f42 | 1862 | char *area_type = NULL; |
eebf11a0 | 1863 | |
4d715a80 AR |
1864 | if (pvt->info.type == IVY_BRIDGE) |
1865 | recoverable = true; | |
1866 | else | |
1867 | recoverable = GET_BITFIELD(m->status, 56, 56); | |
1868 | ||
c36e3e77 MCC |
1869 | if (uncorrected_error) { |
1870 | if (ripv) { | |
1871 | type = "FATAL"; | |
1872 | tp_event = HW_EVENT_ERR_FATAL; | |
1873 | } else { | |
1874 | type = "NON_FATAL"; | |
1875 | tp_event = HW_EVENT_ERR_UNCORRECTED; | |
1876 | } | |
1877 | } else { | |
1878 | type = "CORRECTED"; | |
1879 | tp_event = HW_EVENT_ERR_CORRECTED; | |
1880 | } | |
eebf11a0 MCC |
1881 | |
1882 | /* | |
15ed103a | 1883 | * According with Table 15-9 of the Intel Architecture spec vol 3A, |
eebf11a0 MCC |
1884 | * memory errors should fit in this mask: |
1885 | * 000f 0000 1mmm cccc (binary) | |
1886 | * where: | |
1887 | * f = Correction Report Filtering Bit. If 1, subsequent errors | |
1888 | * won't be shown | |
1889 | * mmm = error type | |
1890 | * cccc = channel | |
1891 | * If the mask doesn't match, report an error to the parsing logic | |
1892 | */ | |
1893 | if (! ((errcode & 0xef80) == 0x80)) { | |
1894 | optype = "Can't parse: it is not a mem"; | |
1895 | } else { | |
1896 | switch (optypenum) { | |
1897 | case 0: | |
c36e3e77 | 1898 | optype = "generic undef request error"; |
eebf11a0 MCC |
1899 | break; |
1900 | case 1: | |
c36e3e77 | 1901 | optype = "memory read error"; |
eebf11a0 MCC |
1902 | break; |
1903 | case 2: | |
c36e3e77 | 1904 | optype = "memory write error"; |
eebf11a0 MCC |
1905 | break; |
1906 | case 3: | |
c36e3e77 | 1907 | optype = "addr/cmd error"; |
eebf11a0 MCC |
1908 | break; |
1909 | case 4: | |
c36e3e77 | 1910 | optype = "memory scrubbing error"; |
eebf11a0 MCC |
1911 | break; |
1912 | default: | |
1913 | optype = "reserved"; | |
1914 | break; | |
1915 | } | |
1916 | } | |
1917 | ||
be3036d2 AR |
1918 | /* Only decode errors with an valid address (ADDRV) */ |
1919 | if (!GET_BITFIELD(m->status, 58, 58)) | |
1920 | return; | |
1921 | ||
eebf11a0 | 1922 | rc = get_memory_error_data(mci, m->addr, &socket, |
e17a2f42 | 1923 | &channel_mask, &rank, &area_type, msg); |
eebf11a0 | 1924 | if (rc < 0) |
c36e3e77 | 1925 | goto err_parsing; |
eebf11a0 MCC |
1926 | new_mci = get_mci_for_node_id(socket); |
1927 | if (!new_mci) { | |
c36e3e77 MCC |
1928 | strcpy(msg, "Error: socket got corrupted!"); |
1929 | goto err_parsing; | |
eebf11a0 MCC |
1930 | } |
1931 | mci = new_mci; | |
1932 | pvt = mci->pvt_info; | |
1933 | ||
1934 | first_channel = find_first_bit(&channel_mask, NUM_CHANNELS); | |
1935 | ||
1936 | if (rank < 4) | |
1937 | dimm = 0; | |
1938 | else if (rank < 8) | |
1939 | dimm = 1; | |
1940 | else | |
1941 | dimm = 2; | |
1942 | ||
eebf11a0 MCC |
1943 | |
1944 | /* | |
e17a2f42 MCC |
1945 | * FIXME: On some memory configurations (mirror, lockstep), the |
1946 | * Memory Controller can't point the error to a single DIMM. The | |
1947 | * EDAC core should be handling the channel mask, in order to point | |
1948 | * to the group of dimm's where the error may be happening. | |
eebf11a0 | 1949 | */ |
d7c660b7 AR |
1950 | if (!pvt->is_lockstep && !pvt->is_mirrored && !pvt->is_close_pg) |
1951 | channel = first_channel; | |
1952 | ||
c36e3e77 | 1953 | snprintf(msg, sizeof(msg), |
c1053839 | 1954 | "%s%s area:%s err_code:%04x:%04x socket:%d channel_mask:%ld rank:%d", |
e17a2f42 MCC |
1955 | overflow ? " OVERFLOW" : "", |
1956 | (uncorrected_error && recoverable) ? " recoverable" : "", | |
1957 | area_type, | |
1958 | mscod, errcode, | |
1959 | socket, | |
1960 | channel_mask, | |
1961 | rank); | |
eebf11a0 | 1962 | |
956b9ba1 | 1963 | edac_dbg(0, "%s\n", msg); |
eebf11a0 | 1964 | |
c36e3e77 MCC |
1965 | /* FIXME: need support for channel mask */ |
1966 | ||
351fc4a9 SJ |
1967 | if (channel == CHANNEL_UNSPECIFIED) |
1968 | channel = -1; | |
1969 | ||
eebf11a0 | 1970 | /* Call the helper to output message */ |
c1053839 | 1971 | edac_mc_handle_error(tp_event, mci, core_err_cnt, |
c36e3e77 MCC |
1972 | m->addr >> PAGE_SHIFT, m->addr & ~PAGE_MASK, 0, |
1973 | channel, dimm, -1, | |
03f7eae8 | 1974 | optype, msg); |
c36e3e77 MCC |
1975 | return; |
1976 | err_parsing: | |
c1053839 | 1977 | edac_mc_handle_error(tp_event, mci, core_err_cnt, 0, 0, 0, |
c36e3e77 | 1978 | -1, -1, -1, |
03f7eae8 | 1979 | msg, ""); |
eebf11a0 | 1980 | |
eebf11a0 MCC |
1981 | } |
1982 | ||
1983 | /* | |
1984 | * sbridge_check_error Retrieve and process errors reported by the | |
1985 | * hardware. Called by the Core module. | |
1986 | */ | |
1987 | static void sbridge_check_error(struct mem_ctl_info *mci) | |
1988 | { | |
1989 | struct sbridge_pvt *pvt = mci->pvt_info; | |
1990 | int i; | |
1991 | unsigned count = 0; | |
1992 | struct mce *m; | |
1993 | ||
1994 | /* | |
1995 | * MCE first step: Copy all mce errors into a temporary buffer | |
1996 | * We use a double buffering here, to reduce the risk of | |
1997 | * loosing an error. | |
1998 | */ | |
1999 | smp_rmb(); | |
2000 | count = (pvt->mce_out + MCE_LOG_LEN - pvt->mce_in) | |
2001 | % MCE_LOG_LEN; | |
2002 | if (!count) | |
2003 | return; | |
2004 | ||
2005 | m = pvt->mce_outentry; | |
2006 | if (pvt->mce_in + count > MCE_LOG_LEN) { | |
2007 | unsigned l = MCE_LOG_LEN - pvt->mce_in; | |
2008 | ||
2009 | memcpy(m, &pvt->mce_entry[pvt->mce_in], sizeof(*m) * l); | |
2010 | smp_wmb(); | |
2011 | pvt->mce_in = 0; | |
2012 | count -= l; | |
2013 | m += l; | |
2014 | } | |
2015 | memcpy(m, &pvt->mce_entry[pvt->mce_in], sizeof(*m) * count); | |
2016 | smp_wmb(); | |
2017 | pvt->mce_in += count; | |
2018 | ||
2019 | smp_rmb(); | |
2020 | if (pvt->mce_overrun) { | |
2021 | sbridge_printk(KERN_ERR, "Lost %d memory errors\n", | |
2022 | pvt->mce_overrun); | |
2023 | smp_wmb(); | |
2024 | pvt->mce_overrun = 0; | |
2025 | } | |
2026 | ||
2027 | /* | |
2028 | * MCE second step: parse errors and display | |
2029 | */ | |
2030 | for (i = 0; i < count; i++) | |
2031 | sbridge_mce_output_error(mci, &pvt->mce_outentry[i]); | |
2032 | } | |
2033 | ||
2034 | /* | |
2035 | * sbridge_mce_check_error Replicates mcelog routine to get errors | |
2036 | * This routine simply queues mcelog errors, and | |
2037 | * return. The error itself should be handled later | |
2038 | * by sbridge_check_error. | |
2039 | * WARNING: As this routine should be called at NMI time, extra care should | |
2040 | * be taken to avoid deadlocks, and to be as fast as possible. | |
2041 | */ | |
3d78c9af MCC |
2042 | static int sbridge_mce_check_error(struct notifier_block *nb, unsigned long val, |
2043 | void *data) | |
eebf11a0 | 2044 | { |
3d78c9af MCC |
2045 | struct mce *mce = (struct mce *)data; |
2046 | struct mem_ctl_info *mci; | |
2047 | struct sbridge_pvt *pvt; | |
cf40f80c | 2048 | char *type; |
3d78c9af | 2049 | |
fd521039 CG |
2050 | if (get_edac_report_status() == EDAC_REPORTING_DISABLED) |
2051 | return NOTIFY_DONE; | |
2052 | ||
3d78c9af MCC |
2053 | mci = get_mci_for_node_id(mce->socketid); |
2054 | if (!mci) | |
2055 | return NOTIFY_BAD; | |
2056 | pvt = mci->pvt_info; | |
eebf11a0 MCC |
2057 | |
2058 | /* | |
2059 | * Just let mcelog handle it if the error is | |
2060 | * outside the memory controller. A memory error | |
2061 | * is indicated by bit 7 = 1 and bits = 8-11,13-15 = 0. | |
2062 | * bit 12 has an special meaning. | |
2063 | */ | |
2064 | if ((mce->status & 0xefff) >> 7 != 1) | |
3d78c9af | 2065 | return NOTIFY_DONE; |
eebf11a0 | 2066 | |
cf40f80c AR |
2067 | if (mce->mcgstatus & MCG_STATUS_MCIP) |
2068 | type = "Exception"; | |
2069 | else | |
2070 | type = "Event"; | |
2071 | ||
49856dc9 | 2072 | sbridge_mc_printk(mci, KERN_DEBUG, "HANDLING MCE MEMORY ERROR\n"); |
eebf11a0 | 2073 | |
49856dc9 AR |
2074 | sbridge_mc_printk(mci, KERN_DEBUG, "CPU %d: Machine Check %s: %Lx " |
2075 | "Bank %d: %016Lx\n", mce->extcpu, type, | |
2076 | mce->mcgstatus, mce->bank, mce->status); | |
2077 | sbridge_mc_printk(mci, KERN_DEBUG, "TSC %llx ", mce->tsc); | |
2078 | sbridge_mc_printk(mci, KERN_DEBUG, "ADDR %llx ", mce->addr); | |
2079 | sbridge_mc_printk(mci, KERN_DEBUG, "MISC %llx ", mce->misc); | |
eebf11a0 | 2080 | |
49856dc9 AR |
2081 | sbridge_mc_printk(mci, KERN_DEBUG, "PROCESSOR %u:%x TIME %llu SOCKET " |
2082 | "%u APIC %x\n", mce->cpuvendor, mce->cpuid, | |
2083 | mce->time, mce->socketid, mce->apicid); | |
eebf11a0 | 2084 | |
eebf11a0 MCC |
2085 | smp_rmb(); |
2086 | if ((pvt->mce_out + 1) % MCE_LOG_LEN == pvt->mce_in) { | |
2087 | smp_wmb(); | |
2088 | pvt->mce_overrun++; | |
3d78c9af | 2089 | return NOTIFY_DONE; |
eebf11a0 MCC |
2090 | } |
2091 | ||
2092 | /* Copy memory error at the ringbuffer */ | |
2093 | memcpy(&pvt->mce_entry[pvt->mce_out], mce, sizeof(*mce)); | |
2094 | smp_wmb(); | |
2095 | pvt->mce_out = (pvt->mce_out + 1) % MCE_LOG_LEN; | |
2096 | ||
2097 | /* Handle fatal errors immediately */ | |
2098 | if (mce->mcgstatus & 1) | |
2099 | sbridge_check_error(mci); | |
2100 | ||
2101 | /* Advice mcelog that the error were handled */ | |
3d78c9af | 2102 | return NOTIFY_STOP; |
eebf11a0 MCC |
2103 | } |
2104 | ||
3d78c9af MCC |
2105 | static struct notifier_block sbridge_mce_dec = { |
2106 | .notifier_call = sbridge_mce_check_error, | |
2107 | }; | |
2108 | ||
eebf11a0 MCC |
2109 | /**************************************************************************** |
2110 | EDAC register/unregister logic | |
2111 | ****************************************************************************/ | |
2112 | ||
2113 | static void sbridge_unregister_mci(struct sbridge_dev *sbridge_dev) | |
2114 | { | |
2115 | struct mem_ctl_info *mci = sbridge_dev->mci; | |
2116 | struct sbridge_pvt *pvt; | |
2117 | ||
2118 | if (unlikely(!mci || !mci->pvt_info)) { | |
956b9ba1 | 2119 | edac_dbg(0, "MC: dev = %p\n", &sbridge_dev->pdev[0]->dev); |
eebf11a0 MCC |
2120 | |
2121 | sbridge_printk(KERN_ERR, "Couldn't find mci handler\n"); | |
2122 | return; | |
2123 | } | |
2124 | ||
2125 | pvt = mci->pvt_info; | |
2126 | ||
956b9ba1 JP |
2127 | edac_dbg(0, "MC: mci = %p, dev = %p\n", |
2128 | mci, &sbridge_dev->pdev[0]->dev); | |
eebf11a0 | 2129 | |
eebf11a0 | 2130 | /* Remove MC sysfs nodes */ |
fd687502 | 2131 | edac_mc_del_mc(mci->pdev); |
eebf11a0 | 2132 | |
956b9ba1 | 2133 | edac_dbg(1, "%s: free mci struct\n", mci->ctl_name); |
eebf11a0 MCC |
2134 | kfree(mci->ctl_name); |
2135 | edac_mc_free(mci); | |
2136 | sbridge_dev->mci = NULL; | |
2137 | } | |
2138 | ||
4d715a80 | 2139 | static int sbridge_register_mci(struct sbridge_dev *sbridge_dev, enum type type) |
eebf11a0 MCC |
2140 | { |
2141 | struct mem_ctl_info *mci; | |
c36e3e77 | 2142 | struct edac_mc_layer layers[2]; |
eebf11a0 | 2143 | struct sbridge_pvt *pvt; |
4d715a80 | 2144 | struct pci_dev *pdev = sbridge_dev->pdev[0]; |
c36e3e77 | 2145 | int rc; |
eebf11a0 MCC |
2146 | |
2147 | /* Check the number of active and not disabled channels */ | |
dbc954dd | 2148 | rc = check_if_ecc_is_active(sbridge_dev->bus, type); |
eebf11a0 MCC |
2149 | if (unlikely(rc < 0)) |
2150 | return rc; | |
2151 | ||
2152 | /* allocate a new MC control structure */ | |
c36e3e77 MCC |
2153 | layers[0].type = EDAC_MC_LAYER_CHANNEL; |
2154 | layers[0].size = NUM_CHANNELS; | |
2155 | layers[0].is_virt_csrow = false; | |
2156 | layers[1].type = EDAC_MC_LAYER_SLOT; | |
2157 | layers[1].size = MAX_DIMMS; | |
2158 | layers[1].is_virt_csrow = true; | |
ca0907b9 | 2159 | mci = edac_mc_alloc(sbridge_dev->mc, ARRAY_SIZE(layers), layers, |
c36e3e77 MCC |
2160 | sizeof(*pvt)); |
2161 | ||
eebf11a0 MCC |
2162 | if (unlikely(!mci)) |
2163 | return -ENOMEM; | |
2164 | ||
956b9ba1 | 2165 | edac_dbg(0, "MC: mci = %p, dev = %p\n", |
4d715a80 | 2166 | mci, &pdev->dev); |
eebf11a0 MCC |
2167 | |
2168 | pvt = mci->pvt_info; | |
2169 | memset(pvt, 0, sizeof(*pvt)); | |
2170 | ||
2171 | /* Associate sbridge_dev and mci for future usage */ | |
2172 | pvt->sbridge_dev = sbridge_dev; | |
2173 | sbridge_dev->mci = mci; | |
2174 | ||
2175 | mci->mtype_cap = MEM_FLAG_DDR3; | |
2176 | mci->edac_ctl_cap = EDAC_FLAG_NONE; | |
2177 | mci->edac_cap = EDAC_FLAG_NONE; | |
2178 | mci->mod_name = "sbridge_edac.c"; | |
2179 | mci->mod_ver = SBRIDGE_REVISION; | |
4d715a80 | 2180 | mci->dev_name = pci_name(pdev); |
eebf11a0 MCC |
2181 | mci->ctl_page_to_phys = NULL; |
2182 | ||
2183 | /* Set the function pointer to an actual operation function */ | |
2184 | mci->edac_check = sbridge_check_error; | |
2185 | ||
4d715a80 | 2186 | pvt->info.type = type; |
50d1bb93 AR |
2187 | switch (type) { |
2188 | case IVY_BRIDGE: | |
4d715a80 AR |
2189 | pvt->info.rankcfgr = IB_RANK_CFG_A; |
2190 | pvt->info.get_tolm = ibridge_get_tolm; | |
2191 | pvt->info.get_tohm = ibridge_get_tohm; | |
2192 | pvt->info.dram_rule = ibridge_dram_rule; | |
9e375446 | 2193 | pvt->info.get_memory_type = get_memory_type; |
f14d6892 | 2194 | pvt->info.get_node_id = get_node_id; |
b976bcf2 | 2195 | pvt->info.rir_limit = rir_limit; |
4d715a80 AR |
2196 | pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule); |
2197 | pvt->info.interleave_list = ibridge_interleave_list; | |
2198 | pvt->info.max_interleave = ARRAY_SIZE(ibridge_interleave_list); | |
2199 | pvt->info.interleave_pkg = ibridge_interleave_pkg; | |
2200 | mci->ctl_name = kasprintf(GFP_KERNEL, "Ivy Bridge Socket#%d", mci->mc_idx); | |
2201 | ||
2202 | /* Store pci devices at mci for faster access */ | |
2203 | rc = ibridge_mci_bind_devs(mci, sbridge_dev); | |
2204 | if (unlikely(rc < 0)) | |
2205 | goto fail0; | |
50d1bb93 AR |
2206 | break; |
2207 | case SANDY_BRIDGE: | |
4d715a80 AR |
2208 | pvt->info.rankcfgr = SB_RANK_CFG_A; |
2209 | pvt->info.get_tolm = sbridge_get_tolm; | |
2210 | pvt->info.get_tohm = sbridge_get_tohm; | |
2211 | pvt->info.dram_rule = sbridge_dram_rule; | |
9e375446 | 2212 | pvt->info.get_memory_type = get_memory_type; |
f14d6892 | 2213 | pvt->info.get_node_id = get_node_id; |
b976bcf2 | 2214 | pvt->info.rir_limit = rir_limit; |
4d715a80 AR |
2215 | pvt->info.max_sad = ARRAY_SIZE(sbridge_dram_rule); |
2216 | pvt->info.interleave_list = sbridge_interleave_list; | |
2217 | pvt->info.max_interleave = ARRAY_SIZE(sbridge_interleave_list); | |
2218 | pvt->info.interleave_pkg = sbridge_interleave_pkg; | |
2219 | mci->ctl_name = kasprintf(GFP_KERNEL, "Sandy Bridge Socket#%d", mci->mc_idx); | |
2220 | ||
2221 | /* Store pci devices at mci for faster access */ | |
2222 | rc = sbridge_mci_bind_devs(mci, sbridge_dev); | |
2223 | if (unlikely(rc < 0)) | |
2224 | goto fail0; | |
50d1bb93 AR |
2225 | break; |
2226 | case HASWELL: | |
2227 | /* rankcfgr isn't used */ | |
2228 | pvt->info.get_tolm = haswell_get_tolm; | |
2229 | pvt->info.get_tohm = haswell_get_tohm; | |
2230 | pvt->info.dram_rule = ibridge_dram_rule; | |
2231 | pvt->info.get_memory_type = haswell_get_memory_type; | |
2232 | pvt->info.get_node_id = haswell_get_node_id; | |
2233 | pvt->info.rir_limit = haswell_rir_limit; | |
2234 | pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule); | |
2235 | pvt->info.interleave_list = ibridge_interleave_list; | |
2236 | pvt->info.max_interleave = ARRAY_SIZE(ibridge_interleave_list); | |
2237 | pvt->info.interleave_pkg = ibridge_interleave_pkg; | |
2238 | mci->ctl_name = kasprintf(GFP_KERNEL, "Haswell Socket#%d", mci->mc_idx); | |
4d715a80 | 2239 | |
50d1bb93 AR |
2240 | /* Store pci devices at mci for faster access */ |
2241 | rc = haswell_mci_bind_devs(mci, sbridge_dev); | |
2242 | if (unlikely(rc < 0)) | |
2243 | goto fail0; | |
2244 | break; | |
2245 | } | |
eebf11a0 MCC |
2246 | |
2247 | /* Get dimm basic config and the memory layout */ | |
2248 | get_dimm_config(mci); | |
2249 | get_memory_layout(mci); | |
2250 | ||
2251 | /* record ptr to the generic device */ | |
4d715a80 | 2252 | mci->pdev = &pdev->dev; |
eebf11a0 MCC |
2253 | |
2254 | /* add this new MC control structure to EDAC's list of MCs */ | |
2255 | if (unlikely(edac_mc_add_mc(mci))) { | |
956b9ba1 | 2256 | edac_dbg(0, "MC: failed edac_mc_add_mc()\n"); |
eebf11a0 MCC |
2257 | rc = -EINVAL; |
2258 | goto fail0; | |
2259 | } | |
2260 | ||
eebf11a0 | 2261 | return 0; |
eebf11a0 MCC |
2262 | |
2263 | fail0: | |
2264 | kfree(mci->ctl_name); | |
2265 | edac_mc_free(mci); | |
2266 | sbridge_dev->mci = NULL; | |
2267 | return rc; | |
2268 | } | |
2269 | ||
2270 | /* | |
2271 | * sbridge_probe Probe for ONE instance of device to see if it is | |
2272 | * present. | |
2273 | * return: | |
2274 | * 0 for FOUND a device | |
2275 | * < 0 for error code | |
2276 | */ | |
2277 | ||
9b3c6e85 | 2278 | static int sbridge_probe(struct pci_dev *pdev, const struct pci_device_id *id) |
eebf11a0 | 2279 | { |
50d1bb93 | 2280 | int rc = -ENODEV; |
eebf11a0 MCC |
2281 | u8 mc, num_mc = 0; |
2282 | struct sbridge_dev *sbridge_dev; | |
50d1bb93 | 2283 | enum type type = SANDY_BRIDGE; |
eebf11a0 MCC |
2284 | |
2285 | /* get the pci devices we want to reserve for our use */ | |
2286 | mutex_lock(&sbridge_edac_lock); | |
2287 | ||
2288 | /* | |
2289 | * All memory controllers are allocated at the first pass. | |
2290 | */ | |
2291 | if (unlikely(probed >= 1)) { | |
2292 | mutex_unlock(&sbridge_edac_lock); | |
2293 | return -ENODEV; | |
2294 | } | |
2295 | probed++; | |
2296 | ||
50d1bb93 AR |
2297 | switch (pdev->device) { |
2298 | case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA: | |
4d715a80 AR |
2299 | rc = sbridge_get_all_devices(&num_mc, pci_dev_descr_ibridge_table); |
2300 | type = IVY_BRIDGE; | |
50d1bb93 AR |
2301 | break; |
2302 | case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA: | |
4d715a80 AR |
2303 | rc = sbridge_get_all_devices(&num_mc, pci_dev_descr_sbridge_table); |
2304 | type = SANDY_BRIDGE; | |
50d1bb93 AR |
2305 | break; |
2306 | case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0: | |
2307 | rc = sbridge_get_all_devices(&num_mc, pci_dev_descr_haswell_table); | |
2308 | type = HASWELL; | |
2309 | break; | |
4d715a80 | 2310 | } |
eebf11a0 MCC |
2311 | if (unlikely(rc < 0)) |
2312 | goto fail0; | |
2313 | mc = 0; | |
2314 | ||
2315 | list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) { | |
956b9ba1 JP |
2316 | edac_dbg(0, "Registering MC#%d (%d of %d)\n", |
2317 | mc, mc + 1, num_mc); | |
50d1bb93 | 2318 | |
eebf11a0 | 2319 | sbridge_dev->mc = mc++; |
4d715a80 | 2320 | rc = sbridge_register_mci(sbridge_dev, type); |
eebf11a0 MCC |
2321 | if (unlikely(rc < 0)) |
2322 | goto fail1; | |
2323 | } | |
2324 | ||
2325 | sbridge_printk(KERN_INFO, "Driver loaded.\n"); | |
2326 | ||
2327 | mutex_unlock(&sbridge_edac_lock); | |
2328 | return 0; | |
2329 | ||
2330 | fail1: | |
2331 | list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) | |
2332 | sbridge_unregister_mci(sbridge_dev); | |
2333 | ||
2334 | sbridge_put_all_devices(); | |
2335 | fail0: | |
2336 | mutex_unlock(&sbridge_edac_lock); | |
2337 | return rc; | |
2338 | } | |
2339 | ||
2340 | /* | |
2341 | * sbridge_remove destructor for one instance of device | |
2342 | * | |
2343 | */ | |
9b3c6e85 | 2344 | static void sbridge_remove(struct pci_dev *pdev) |
eebf11a0 MCC |
2345 | { |
2346 | struct sbridge_dev *sbridge_dev; | |
2347 | ||
956b9ba1 | 2348 | edac_dbg(0, "\n"); |
eebf11a0 MCC |
2349 | |
2350 | /* | |
2351 | * we have a trouble here: pdev value for removal will be wrong, since | |
2352 | * it will point to the X58 register used to detect that the machine | |
2353 | * is a Nehalem or upper design. However, due to the way several PCI | |
2354 | * devices are grouped together to provide MC functionality, we need | |
2355 | * to use a different method for releasing the devices | |
2356 | */ | |
2357 | ||
2358 | mutex_lock(&sbridge_edac_lock); | |
2359 | ||
2360 | if (unlikely(!probed)) { | |
2361 | mutex_unlock(&sbridge_edac_lock); | |
2362 | return; | |
2363 | } | |
2364 | ||
2365 | list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) | |
2366 | sbridge_unregister_mci(sbridge_dev); | |
2367 | ||
2368 | /* Release PCI resources */ | |
2369 | sbridge_put_all_devices(); | |
2370 | ||
2371 | probed--; | |
2372 | ||
2373 | mutex_unlock(&sbridge_edac_lock); | |
2374 | } | |
2375 | ||
2376 | MODULE_DEVICE_TABLE(pci, sbridge_pci_tbl); | |
2377 | ||
2378 | /* | |
2379 | * sbridge_driver pci_driver structure for this module | |
2380 | * | |
2381 | */ | |
2382 | static struct pci_driver sbridge_driver = { | |
2383 | .name = "sbridge_edac", | |
2384 | .probe = sbridge_probe, | |
9b3c6e85 | 2385 | .remove = sbridge_remove, |
eebf11a0 MCC |
2386 | .id_table = sbridge_pci_tbl, |
2387 | }; | |
2388 | ||
2389 | /* | |
2390 | * sbridge_init Module entry function | |
2391 | * Try to initialize this module for its devices | |
2392 | */ | |
2393 | static int __init sbridge_init(void) | |
2394 | { | |
2395 | int pci_rc; | |
2396 | ||
956b9ba1 | 2397 | edac_dbg(2, "\n"); |
eebf11a0 MCC |
2398 | |
2399 | /* Ensure that the OPSTATE is set correctly for POLL or NMI */ | |
2400 | opstate_init(); | |
2401 | ||
2402 | pci_rc = pci_register_driver(&sbridge_driver); | |
e35fca47 CG |
2403 | if (pci_rc >= 0) { |
2404 | mce_register_decode_chain(&sbridge_mce_dec); | |
fd521039 CG |
2405 | if (get_edac_report_status() == EDAC_REPORTING_DISABLED) |
2406 | sbridge_printk(KERN_WARNING, "Loading driver, error reporting disabled.\n"); | |
eebf11a0 | 2407 | return 0; |
e35fca47 | 2408 | } |
eebf11a0 MCC |
2409 | |
2410 | sbridge_printk(KERN_ERR, "Failed to register device with error %d.\n", | |
2411 | pci_rc); | |
2412 | ||
2413 | return pci_rc; | |
2414 | } | |
2415 | ||
2416 | /* | |
2417 | * sbridge_exit() Module exit function | |
2418 | * Unregister the driver | |
2419 | */ | |
2420 | static void __exit sbridge_exit(void) | |
2421 | { | |
956b9ba1 | 2422 | edac_dbg(2, "\n"); |
eebf11a0 | 2423 | pci_unregister_driver(&sbridge_driver); |
e35fca47 | 2424 | mce_unregister_decode_chain(&sbridge_mce_dec); |
eebf11a0 MCC |
2425 | } |
2426 | ||
2427 | module_init(sbridge_init); | |
2428 | module_exit(sbridge_exit); | |
2429 | ||
2430 | module_param(edac_op_state, int, 0444); | |
2431 | MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI"); | |
2432 | ||
2433 | MODULE_LICENSE("GPL"); | |
37e59f87 | 2434 | MODULE_AUTHOR("Mauro Carvalho Chehab"); |
eebf11a0 | 2435 | MODULE_AUTHOR("Red Hat Inc. (http://www.redhat.com)"); |
4d715a80 | 2436 | MODULE_DESCRIPTION("MC Driver for Intel Sandy Bridge and Ivy Bridge memory controllers - " |
eebf11a0 | 2437 | SBRIDGE_REVISION); |