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eebf11a0 MCC |
1 | /* Intel Sandy Bridge -EN/-EP/-EX Memory Controller kernel module |
2 | * | |
3 | * This driver supports the memory controllers found on the Intel | |
4 | * processor family Sandy Bridge. | |
5 | * | |
6 | * This file may be distributed under the terms of the | |
7 | * GNU General Public License version 2 only. | |
8 | * | |
9 | * Copyright (c) 2011 by: | |
37e59f87 | 10 | * Mauro Carvalho Chehab |
eebf11a0 MCC |
11 | */ |
12 | ||
13 | #include <linux/module.h> | |
14 | #include <linux/init.h> | |
15 | #include <linux/pci.h> | |
16 | #include <linux/pci_ids.h> | |
17 | #include <linux/slab.h> | |
18 | #include <linux/delay.h> | |
19 | #include <linux/edac.h> | |
20 | #include <linux/mmzone.h> | |
eebf11a0 MCC |
21 | #include <linux/smp.h> |
22 | #include <linux/bitmap.h> | |
5b889e37 | 23 | #include <linux/math64.h> |
eebf11a0 | 24 | #include <asm/processor.h> |
3d78c9af | 25 | #include <asm/mce.h> |
eebf11a0 MCC |
26 | |
27 | #include "edac_core.h" | |
28 | ||
29 | /* Static vars */ | |
30 | static LIST_HEAD(sbridge_edac_list); | |
31 | static DEFINE_MUTEX(sbridge_edac_lock); | |
32 | static int probed; | |
33 | ||
34 | /* | |
35 | * Alter this version for the module when modifications are made | |
36 | */ | |
7d375bff | 37 | #define SBRIDGE_REVISION " Ver: 1.1.1 " |
eebf11a0 MCC |
38 | #define EDAC_MOD_STR "sbridge_edac" |
39 | ||
40 | /* | |
41 | * Debug macros | |
42 | */ | |
43 | #define sbridge_printk(level, fmt, arg...) \ | |
44 | edac_printk(level, "sbridge", fmt, ##arg) | |
45 | ||
46 | #define sbridge_mc_printk(mci, level, fmt, arg...) \ | |
47 | edac_mc_chipset_printk(mci, level, "sbridge", fmt, ##arg) | |
48 | ||
49 | /* | |
50 | * Get a bit field at register value <v>, from bit <lo> to bit <hi> | |
51 | */ | |
52 | #define GET_BITFIELD(v, lo, hi) \ | |
10ef6b0d | 53 | (((v) & GENMASK_ULL(hi, lo)) >> (lo)) |
eebf11a0 | 54 | |
eebf11a0 | 55 | /* Devices 12 Function 6, Offsets 0x80 to 0xcc */ |
464f1d82 | 56 | static const u32 sbridge_dram_rule[] = { |
eebf11a0 MCC |
57 | 0x80, 0x88, 0x90, 0x98, 0xa0, |
58 | 0xa8, 0xb0, 0xb8, 0xc0, 0xc8, | |
59 | }; | |
eebf11a0 | 60 | |
4d715a80 AR |
61 | static const u32 ibridge_dram_rule[] = { |
62 | 0x60, 0x68, 0x70, 0x78, 0x80, | |
63 | 0x88, 0x90, 0x98, 0xa0, 0xa8, | |
64 | 0xb0, 0xb8, 0xc0, 0xc8, 0xd0, | |
65 | 0xd8, 0xe0, 0xe8, 0xf0, 0xf8, | |
66 | }; | |
eebf11a0 | 67 | |
eebf11a0 | 68 | #define DRAM_RULE_ENABLE(reg) GET_BITFIELD(reg, 0, 0) |
50d1bb93 | 69 | #define A7MODE(reg) GET_BITFIELD(reg, 26, 26) |
eebf11a0 | 70 | |
c59f9c06 | 71 | static char *show_dram_attr(u32 attr) |
eebf11a0 | 72 | { |
c59f9c06 | 73 | switch (attr) { |
eebf11a0 MCC |
74 | case 0: |
75 | return "DRAM"; | |
76 | case 1: | |
77 | return "MMCFG"; | |
78 | case 2: | |
79 | return "NXM"; | |
80 | default: | |
81 | return "unknown"; | |
82 | } | |
83 | } | |
84 | ||
ef1ce51e | 85 | static const u32 sbridge_interleave_list[] = { |
eebf11a0 MCC |
86 | 0x84, 0x8c, 0x94, 0x9c, 0xa4, |
87 | 0xac, 0xb4, 0xbc, 0xc4, 0xcc, | |
88 | }; | |
eebf11a0 | 89 | |
4d715a80 AR |
90 | static const u32 ibridge_interleave_list[] = { |
91 | 0x64, 0x6c, 0x74, 0x7c, 0x84, | |
92 | 0x8c, 0x94, 0x9c, 0xa4, 0xac, | |
93 | 0xb4, 0xbc, 0xc4, 0xcc, 0xd4, | |
94 | 0xdc, 0xe4, 0xec, 0xf4, 0xfc, | |
95 | }; | |
96 | ||
cc311991 AR |
97 | struct interleave_pkg { |
98 | unsigned char start; | |
99 | unsigned char end; | |
100 | }; | |
101 | ||
102 | static const struct interleave_pkg sbridge_interleave_pkg[] = { | |
103 | { 0, 2 }, | |
104 | { 3, 5 }, | |
105 | { 8, 10 }, | |
106 | { 11, 13 }, | |
107 | { 16, 18 }, | |
108 | { 19, 21 }, | |
109 | { 24, 26 }, | |
110 | { 27, 29 }, | |
111 | }; | |
112 | ||
4d715a80 AR |
113 | static const struct interleave_pkg ibridge_interleave_pkg[] = { |
114 | { 0, 3 }, | |
115 | { 4, 7 }, | |
116 | { 8, 11 }, | |
117 | { 12, 15 }, | |
118 | { 16, 19 }, | |
119 | { 20, 23 }, | |
120 | { 24, 27 }, | |
121 | { 28, 31 }, | |
122 | }; | |
123 | ||
cc311991 AR |
124 | static inline int sad_pkg(const struct interleave_pkg *table, u32 reg, |
125 | int interleave) | |
eebf11a0 | 126 | { |
cc311991 AR |
127 | return GET_BITFIELD(reg, table[interleave].start, |
128 | table[interleave].end); | |
eebf11a0 MCC |
129 | } |
130 | ||
131 | /* Devices 12 Function 7 */ | |
132 | ||
133 | #define TOLM 0x80 | |
134 | #define TOHM 0x84 | |
f7cf2a22 | 135 | #define HASWELL_TOLM 0xd0 |
50d1bb93 AR |
136 | #define HASWELL_TOHM_0 0xd4 |
137 | #define HASWELL_TOHM_1 0xd8 | |
eebf11a0 MCC |
138 | |
139 | #define GET_TOLM(reg) ((GET_BITFIELD(reg, 0, 3) << 28) | 0x3ffffff) | |
140 | #define GET_TOHM(reg) ((GET_BITFIELD(reg, 0, 20) << 25) | 0x3ffffff) | |
141 | ||
142 | /* Device 13 Function 6 */ | |
143 | ||
144 | #define SAD_TARGET 0xf0 | |
145 | ||
146 | #define SOURCE_ID(reg) GET_BITFIELD(reg, 9, 11) | |
147 | ||
148 | #define SAD_CONTROL 0xf4 | |
149 | ||
eebf11a0 MCC |
150 | /* Device 14 function 0 */ |
151 | ||
152 | static const u32 tad_dram_rule[] = { | |
153 | 0x40, 0x44, 0x48, 0x4c, | |
154 | 0x50, 0x54, 0x58, 0x5c, | |
155 | 0x60, 0x64, 0x68, 0x6c, | |
156 | }; | |
157 | #define MAX_TAD ARRAY_SIZE(tad_dram_rule) | |
158 | ||
159 | #define TAD_LIMIT(reg) ((GET_BITFIELD(reg, 12, 31) << 26) | 0x3ffffff) | |
160 | #define TAD_SOCK(reg) GET_BITFIELD(reg, 10, 11) | |
161 | #define TAD_CH(reg) GET_BITFIELD(reg, 8, 9) | |
162 | #define TAD_TGT3(reg) GET_BITFIELD(reg, 6, 7) | |
163 | #define TAD_TGT2(reg) GET_BITFIELD(reg, 4, 5) | |
164 | #define TAD_TGT1(reg) GET_BITFIELD(reg, 2, 3) | |
165 | #define TAD_TGT0(reg) GET_BITFIELD(reg, 0, 1) | |
166 | ||
167 | /* Device 15, function 0 */ | |
168 | ||
169 | #define MCMTR 0x7c | |
170 | ||
171 | #define IS_ECC_ENABLED(mcmtr) GET_BITFIELD(mcmtr, 2, 2) | |
172 | #define IS_LOCKSTEP_ENABLED(mcmtr) GET_BITFIELD(mcmtr, 1, 1) | |
173 | #define IS_CLOSE_PG(mcmtr) GET_BITFIELD(mcmtr, 0, 0) | |
174 | ||
175 | /* Device 15, function 1 */ | |
176 | ||
177 | #define RASENABLES 0xac | |
178 | #define IS_MIRROR_ENABLED(reg) GET_BITFIELD(reg, 0, 0) | |
179 | ||
180 | /* Device 15, functions 2-5 */ | |
181 | ||
182 | static const int mtr_regs[] = { | |
183 | 0x80, 0x84, 0x88, | |
184 | }; | |
185 | ||
186 | #define RANK_DISABLE(mtr) GET_BITFIELD(mtr, 16, 19) | |
187 | #define IS_DIMM_PRESENT(mtr) GET_BITFIELD(mtr, 14, 14) | |
188 | #define RANK_CNT_BITS(mtr) GET_BITFIELD(mtr, 12, 13) | |
189 | #define RANK_WIDTH_BITS(mtr) GET_BITFIELD(mtr, 2, 4) | |
190 | #define COL_WIDTH_BITS(mtr) GET_BITFIELD(mtr, 0, 1) | |
191 | ||
192 | static const u32 tad_ch_nilv_offset[] = { | |
193 | 0x90, 0x94, 0x98, 0x9c, | |
194 | 0xa0, 0xa4, 0xa8, 0xac, | |
195 | 0xb0, 0xb4, 0xb8, 0xbc, | |
196 | }; | |
197 | #define CHN_IDX_OFFSET(reg) GET_BITFIELD(reg, 28, 29) | |
198 | #define TAD_OFFSET(reg) (GET_BITFIELD(reg, 6, 25) << 26) | |
199 | ||
200 | static const u32 rir_way_limit[] = { | |
201 | 0x108, 0x10c, 0x110, 0x114, 0x118, | |
202 | }; | |
203 | #define MAX_RIR_RANGES ARRAY_SIZE(rir_way_limit) | |
204 | ||
205 | #define IS_RIR_VALID(reg) GET_BITFIELD(reg, 31, 31) | |
206 | #define RIR_WAY(reg) GET_BITFIELD(reg, 28, 29) | |
eebf11a0 MCC |
207 | |
208 | #define MAX_RIR_WAY 8 | |
209 | ||
210 | static const u32 rir_offset[MAX_RIR_RANGES][MAX_RIR_WAY] = { | |
211 | { 0x120, 0x124, 0x128, 0x12c, 0x130, 0x134, 0x138, 0x13c }, | |
212 | { 0x140, 0x144, 0x148, 0x14c, 0x150, 0x154, 0x158, 0x15c }, | |
213 | { 0x160, 0x164, 0x168, 0x16c, 0x170, 0x174, 0x178, 0x17c }, | |
214 | { 0x180, 0x184, 0x188, 0x18c, 0x190, 0x194, 0x198, 0x19c }, | |
215 | { 0x1a0, 0x1a4, 0x1a8, 0x1ac, 0x1b0, 0x1b4, 0x1b8, 0x1bc }, | |
216 | }; | |
217 | ||
218 | #define RIR_RNK_TGT(reg) GET_BITFIELD(reg, 16, 19) | |
219 | #define RIR_OFFSET(reg) GET_BITFIELD(reg, 2, 14) | |
220 | ||
221 | /* Device 16, functions 2-7 */ | |
222 | ||
223 | /* | |
224 | * FIXME: Implement the error count reads directly | |
225 | */ | |
226 | ||
227 | static const u32 correrrcnt[] = { | |
228 | 0x104, 0x108, 0x10c, 0x110, | |
229 | }; | |
230 | ||
231 | #define RANK_ODD_OV(reg) GET_BITFIELD(reg, 31, 31) | |
232 | #define RANK_ODD_ERR_CNT(reg) GET_BITFIELD(reg, 16, 30) | |
233 | #define RANK_EVEN_OV(reg) GET_BITFIELD(reg, 15, 15) | |
234 | #define RANK_EVEN_ERR_CNT(reg) GET_BITFIELD(reg, 0, 14) | |
235 | ||
236 | static const u32 correrrthrsld[] = { | |
237 | 0x11c, 0x120, 0x124, 0x128, | |
238 | }; | |
239 | ||
240 | #define RANK_ODD_ERR_THRSLD(reg) GET_BITFIELD(reg, 16, 30) | |
241 | #define RANK_EVEN_ERR_THRSLD(reg) GET_BITFIELD(reg, 0, 14) | |
242 | ||
243 | ||
244 | /* Device 17, function 0 */ | |
245 | ||
ef1e8d03 | 246 | #define SB_RANK_CFG_A 0x0328 |
eebf11a0 | 247 | |
4d715a80 | 248 | #define IB_RANK_CFG_A 0x0320 |
eebf11a0 | 249 | |
eebf11a0 MCC |
250 | /* |
251 | * sbridge structs | |
252 | */ | |
253 | ||
7d375bff | 254 | #define NUM_CHANNELS 8 /* 2MC per socket, four chan per MC */ |
351fc4a9 SJ |
255 | #define MAX_DIMMS 3 /* Max DIMMS per channel */ |
256 | #define CHANNEL_UNSPECIFIED 0xf /* Intel IA32 SDM 15-14 */ | |
eebf11a0 | 257 | |
4d715a80 AR |
258 | enum type { |
259 | SANDY_BRIDGE, | |
260 | IVY_BRIDGE, | |
50d1bb93 | 261 | HASWELL, |
1f39581a | 262 | BROADWELL, |
4d715a80 AR |
263 | }; |
264 | ||
fb79a509 | 265 | struct sbridge_pvt; |
eebf11a0 | 266 | struct sbridge_info { |
4d715a80 | 267 | enum type type; |
464f1d82 AR |
268 | u32 mcmtr; |
269 | u32 rankcfgr; | |
270 | u64 (*get_tolm)(struct sbridge_pvt *pvt); | |
271 | u64 (*get_tohm)(struct sbridge_pvt *pvt); | |
b976bcf2 | 272 | u64 (*rir_limit)(u32 reg); |
c59f9c06 JS |
273 | u64 (*sad_limit)(u32 reg); |
274 | u32 (*interleave_mode)(u32 reg); | |
275 | char* (*show_interleave_mode)(u32 reg); | |
276 | u32 (*dram_attr)(u32 reg); | |
464f1d82 | 277 | const u32 *dram_rule; |
ef1ce51e | 278 | const u32 *interleave_list; |
cc311991 | 279 | const struct interleave_pkg *interleave_pkg; |
464f1d82 | 280 | u8 max_sad; |
ef1ce51e | 281 | u8 max_interleave; |
f14d6892 | 282 | u8 (*get_node_id)(struct sbridge_pvt *pvt); |
9e375446 | 283 | enum mem_type (*get_memory_type)(struct sbridge_pvt *pvt); |
12f0721c | 284 | enum dev_type (*get_width)(struct sbridge_pvt *pvt, u32 mtr); |
50d1bb93 | 285 | struct pci_dev *pci_vtd; |
eebf11a0 MCC |
286 | }; |
287 | ||
288 | struct sbridge_channel { | |
289 | u32 ranks; | |
290 | u32 dimms; | |
291 | }; | |
292 | ||
293 | struct pci_id_descr { | |
c41afdca | 294 | int dev_id; |
eebf11a0 MCC |
295 | int optional; |
296 | }; | |
297 | ||
298 | struct pci_id_table { | |
299 | const struct pci_id_descr *descr; | |
300 | int n_devs; | |
301 | }; | |
302 | ||
303 | struct sbridge_dev { | |
304 | struct list_head list; | |
305 | u8 bus, mc; | |
306 | u8 node_id, source_id; | |
307 | struct pci_dev **pdev; | |
308 | int n_devs; | |
309 | struct mem_ctl_info *mci; | |
310 | }; | |
311 | ||
312 | struct sbridge_pvt { | |
313 | struct pci_dev *pci_ta, *pci_ddrio, *pci_ras; | |
4d715a80 AR |
314 | struct pci_dev *pci_sad0, *pci_sad1; |
315 | struct pci_dev *pci_ha0, *pci_ha1; | |
316 | struct pci_dev *pci_br0, *pci_br1; | |
50d1bb93 | 317 | struct pci_dev *pci_ha1_ta; |
eebf11a0 MCC |
318 | struct pci_dev *pci_tad[NUM_CHANNELS]; |
319 | ||
320 | struct sbridge_dev *sbridge_dev; | |
321 | ||
322 | struct sbridge_info info; | |
323 | struct sbridge_channel channel[NUM_CHANNELS]; | |
324 | ||
eebf11a0 MCC |
325 | /* Memory type detection */ |
326 | bool is_mirrored, is_lockstep, is_close_pg; | |
327 | ||
eebf11a0 MCC |
328 | /* Fifo double buffers */ |
329 | struct mce mce_entry[MCE_LOG_LEN]; | |
330 | struct mce mce_outentry[MCE_LOG_LEN]; | |
331 | ||
332 | /* Fifo in/out counters */ | |
333 | unsigned mce_in, mce_out; | |
334 | ||
335 | /* Count indicator to show errors not got */ | |
336 | unsigned mce_overrun; | |
337 | ||
338 | /* Memory description */ | |
339 | u64 tolm, tohm; | |
340 | }; | |
341 | ||
dbc954dd AR |
342 | #define PCI_DESCR(device_id, opt) \ |
343 | .dev_id = (device_id), \ | |
de4772c6 | 344 | .optional = opt |
eebf11a0 MCC |
345 | |
346 | static const struct pci_id_descr pci_dev_descr_sbridge[] = { | |
347 | /* Processor Home Agent */ | |
dbc954dd | 348 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0, 0) }, |
eebf11a0 MCC |
349 | |
350 | /* Memory controller */ | |
dbc954dd AR |
351 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA, 0) }, |
352 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_RAS, 0) }, | |
353 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0, 0) }, | |
354 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD1, 0) }, | |
355 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD2, 0) }, | |
356 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD3, 0) }, | |
357 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_DDRIO, 1) }, | |
eebf11a0 MCC |
358 | |
359 | /* System Address Decoder */ | |
dbc954dd AR |
360 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_SAD0, 0) }, |
361 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_SAD1, 0) }, | |
eebf11a0 MCC |
362 | |
363 | /* Broadcast Registers */ | |
dbc954dd | 364 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_BR, 0) }, |
eebf11a0 MCC |
365 | }; |
366 | ||
367 | #define PCI_ID_TABLE_ENTRY(A) { .descr=A, .n_devs = ARRAY_SIZE(A) } | |
368 | static const struct pci_id_table pci_dev_descr_sbridge_table[] = { | |
369 | PCI_ID_TABLE_ENTRY(pci_dev_descr_sbridge), | |
370 | {0,} /* 0 terminated list. */ | |
371 | }; | |
372 | ||
4d715a80 AR |
373 | /* This changes depending if 1HA or 2HA: |
374 | * 1HA: | |
375 | * 0x0eb8 (17.0) is DDRIO0 | |
376 | * 2HA: | |
377 | * 0x0ebc (17.4) is DDRIO0 | |
378 | */ | |
379 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_1HA_DDRIO0 0x0eb8 | |
380 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_2HA_DDRIO0 0x0ebc | |
381 | ||
382 | /* pci ids */ | |
383 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0 0x0ea0 | |
384 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA 0x0ea8 | |
385 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_RAS 0x0e71 | |
386 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0 0x0eaa | |
387 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD1 0x0eab | |
388 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD2 0x0eac | |
389 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD3 0x0ead | |
390 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_SAD 0x0ec8 | |
391 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_BR0 0x0ec9 | |
392 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_BR1 0x0eca | |
393 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1 0x0e60 | |
394 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TA 0x0e68 | |
395 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_RAS 0x0e79 | |
396 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0 0x0e6a | |
397 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD1 0x0e6b | |
7d375bff TL |
398 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD2 0x0e6c |
399 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD3 0x0e6d | |
4d715a80 AR |
400 | |
401 | static const struct pci_id_descr pci_dev_descr_ibridge[] = { | |
402 | /* Processor Home Agent */ | |
dbc954dd | 403 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0, 0) }, |
4d715a80 AR |
404 | |
405 | /* Memory controller */ | |
dbc954dd AR |
406 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA, 0) }, |
407 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_RAS, 0) }, | |
408 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0, 0) }, | |
409 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD1, 0) }, | |
410 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD2, 0) }, | |
411 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD3, 0) }, | |
4d715a80 AR |
412 | |
413 | /* System Address Decoder */ | |
dbc954dd | 414 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_SAD, 0) }, |
4d715a80 AR |
415 | |
416 | /* Broadcast Registers */ | |
dbc954dd AR |
417 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_BR0, 1) }, |
418 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_BR1, 0) }, | |
4d715a80 AR |
419 | |
420 | /* Optional, mode 2HA */ | |
dbc954dd | 421 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1, 1) }, |
4d715a80 | 422 | #if 0 |
dbc954dd AR |
423 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TA, 1) }, |
424 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_RAS, 1) }, | |
4d715a80 | 425 | #endif |
dbc954dd AR |
426 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0, 1) }, |
427 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD1, 1) }, | |
7d375bff TL |
428 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD2, 1) }, |
429 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD3, 1) }, | |
4d715a80 | 430 | |
dbc954dd AR |
431 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_1HA_DDRIO0, 1) }, |
432 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_2HA_DDRIO0, 1) }, | |
4d715a80 AR |
433 | }; |
434 | ||
435 | static const struct pci_id_table pci_dev_descr_ibridge_table[] = { | |
436 | PCI_ID_TABLE_ENTRY(pci_dev_descr_ibridge), | |
437 | {0,} /* 0 terminated list. */ | |
438 | }; | |
439 | ||
50d1bb93 AR |
440 | /* Haswell support */ |
441 | /* EN processor: | |
442 | * - 1 IMC | |
443 | * - 3 DDR3 channels, 2 DPC per channel | |
444 | * EP processor: | |
445 | * - 1 or 2 IMC | |
446 | * - 4 DDR4 channels, 3 DPC per channel | |
447 | * EP 4S processor: | |
448 | * - 2 IMC | |
449 | * - 4 DDR4 channels, 3 DPC per channel | |
450 | * EX processor: | |
451 | * - 2 IMC | |
452 | * - each IMC interfaces with a SMI 2 channel | |
453 | * - each SMI channel interfaces with a scalable memory buffer | |
454 | * - each scalable memory buffer supports 4 DDR3/DDR4 channels, 3 DPC | |
455 | */ | |
1f39581a | 456 | #define HASWELL_DDRCRCLKCONTROLS 0xa10 /* Ditto on Broadwell */ |
50d1bb93 AR |
457 | #define HASWELL_HASYSDEFEATURE2 0x84 |
458 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_VTD_MISC 0x2f28 | |
459 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0 0x2fa0 | |
460 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1 0x2f60 | |
461 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA 0x2fa8 | |
462 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_THERMAL 0x2f71 | |
463 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TA 0x2f68 | |
464 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_THERMAL 0x2f79 | |
465 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD0 0x2ffc | |
466 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD1 0x2ffd | |
467 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD0 0x2faa | |
468 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD1 0x2fab | |
469 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD2 0x2fac | |
470 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD3 0x2fad | |
471 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD0 0x2f6a | |
472 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD1 0x2f6b | |
473 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD2 0x2f6c | |
474 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD3 0x2f6d | |
475 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO0 0x2fbd | |
7179385a AR |
476 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO1 0x2fbf |
477 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO2 0x2fb9 | |
478 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO3 0x2fbb | |
50d1bb93 AR |
479 | static const struct pci_id_descr pci_dev_descr_haswell[] = { |
480 | /* first item must be the HA */ | |
481 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0, 0) }, | |
482 | ||
483 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD0, 0) }, | |
484 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD1, 0) }, | |
485 | ||
486 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1, 1) }, | |
487 | ||
488 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA, 0) }, | |
489 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_THERMAL, 0) }, | |
490 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD0, 0) }, | |
491 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD1, 0) }, | |
492 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD2, 1) }, | |
493 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD3, 1) }, | |
494 | ||
495 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO0, 1) }, | |
7179385a AR |
496 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO1, 1) }, |
497 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO2, 1) }, | |
498 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO3, 1) }, | |
50d1bb93 AR |
499 | |
500 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TA, 1) }, | |
501 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_THERMAL, 1) }, | |
502 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD0, 1) }, | |
503 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD1, 1) }, | |
504 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD2, 1) }, | |
505 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD3, 1) }, | |
506 | }; | |
507 | ||
508 | static const struct pci_id_table pci_dev_descr_haswell_table[] = { | |
509 | PCI_ID_TABLE_ENTRY(pci_dev_descr_haswell), | |
510 | {0,} /* 0 terminated list. */ | |
511 | }; | |
512 | ||
1f39581a TL |
513 | /* |
514 | * Broadwell support | |
515 | * | |
516 | * DE processor: | |
517 | * - 1 IMC | |
518 | * - 2 DDR3 channels, 2 DPC per channel | |
fa2ce64f TL |
519 | * EP processor: |
520 | * - 1 or 2 IMC | |
521 | * - 4 DDR4 channels, 3 DPC per channel | |
522 | * EP 4S processor: | |
523 | * - 2 IMC | |
524 | * - 4 DDR4 channels, 3 DPC per channel | |
525 | * EX processor: | |
526 | * - 2 IMC | |
527 | * - each IMC interfaces with a SMI 2 channel | |
528 | * - each SMI channel interfaces with a scalable memory buffer | |
529 | * - each scalable memory buffer supports 4 DDR3/DDR4 channels, 3 DPC | |
1f39581a TL |
530 | */ |
531 | #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_VTD_MISC 0x6f28 | |
532 | #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0 0x6fa0 | |
fa2ce64f | 533 | #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1 0x6f60 |
1f39581a TL |
534 | #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TA 0x6fa8 |
535 | #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_THERMAL 0x6f71 | |
fa2ce64f TL |
536 | #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TA 0x6f68 |
537 | #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_THERMAL 0x6f79 | |
1f39581a TL |
538 | #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD0 0x6ffc |
539 | #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD1 0x6ffd | |
540 | #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD0 0x6faa | |
541 | #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD1 0x6fab | |
542 | #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD2 0x6fac | |
543 | #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD3 0x6fad | |
fa2ce64f TL |
544 | #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD0 0x6f6a |
545 | #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD1 0x6f6b | |
546 | #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD2 0x6f6c | |
547 | #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD3 0x6f6d | |
1f39581a TL |
548 | #define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_DDRIO0 0x6faf |
549 | ||
550 | static const struct pci_id_descr pci_dev_descr_broadwell[] = { | |
551 | /* first item must be the HA */ | |
552 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0, 0) }, | |
553 | ||
554 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD0, 0) }, | |
555 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD1, 0) }, | |
556 | ||
fa2ce64f TL |
557 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1, 1) }, |
558 | ||
1f39581a TL |
559 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TA, 0) }, |
560 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_THERMAL, 0) }, | |
561 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD0, 0) }, | |
562 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD1, 0) }, | |
fa2ce64f TL |
563 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD2, 1) }, |
564 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD3, 1) }, | |
565 | ||
1f39581a | 566 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_DDRIO0, 1) }, |
fa2ce64f TL |
567 | |
568 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TA, 1) }, | |
569 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_THERMAL, 1) }, | |
570 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD0, 1) }, | |
571 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD1, 1) }, | |
572 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD2, 1) }, | |
573 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD3, 1) }, | |
1f39581a TL |
574 | }; |
575 | ||
576 | static const struct pci_id_table pci_dev_descr_broadwell_table[] = { | |
577 | PCI_ID_TABLE_ENTRY(pci_dev_descr_broadwell), | |
578 | {0,} /* 0 terminated list. */ | |
579 | }; | |
580 | ||
eebf11a0 MCC |
581 | /* |
582 | * pci_device_id table for which devices we are looking for | |
583 | */ | |
ba935f40 | 584 | static const struct pci_device_id sbridge_pci_tbl[] = { |
d0585cd8 | 585 | {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0)}, |
4d715a80 | 586 | {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA)}, |
50d1bb93 | 587 | {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0)}, |
1f39581a | 588 | {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0)}, |
eebf11a0 MCC |
589 | {0,} /* 0 terminated list. */ |
590 | }; | |
591 | ||
592 | ||
593 | /**************************************************************************** | |
15ed103a | 594 | Ancillary status routines |
eebf11a0 MCC |
595 | ****************************************************************************/ |
596 | ||
50d1bb93 | 597 | static inline int numrank(enum type type, u32 mtr) |
eebf11a0 MCC |
598 | { |
599 | int ranks = (1 << RANK_CNT_BITS(mtr)); | |
50d1bb93 AR |
600 | int max = 4; |
601 | ||
fa2ce64f | 602 | if (type == HASWELL || type == BROADWELL) |
50d1bb93 | 603 | max = 8; |
eebf11a0 | 604 | |
50d1bb93 AR |
605 | if (ranks > max) { |
606 | edac_dbg(0, "Invalid number of ranks: %d (max = %i) raw value = %x (%04x)\n", | |
607 | ranks, max, (unsigned int)RANK_CNT_BITS(mtr), mtr); | |
eebf11a0 MCC |
608 | return -EINVAL; |
609 | } | |
610 | ||
611 | return ranks; | |
612 | } | |
613 | ||
614 | static inline int numrow(u32 mtr) | |
615 | { | |
616 | int rows = (RANK_WIDTH_BITS(mtr) + 12); | |
617 | ||
618 | if (rows < 13 || rows > 18) { | |
956b9ba1 JP |
619 | edac_dbg(0, "Invalid number of rows: %d (should be between 14 and 17) raw value = %x (%04x)\n", |
620 | rows, (unsigned int)RANK_WIDTH_BITS(mtr), mtr); | |
eebf11a0 MCC |
621 | return -EINVAL; |
622 | } | |
623 | ||
624 | return 1 << rows; | |
625 | } | |
626 | ||
627 | static inline int numcol(u32 mtr) | |
628 | { | |
629 | int cols = (COL_WIDTH_BITS(mtr) + 10); | |
630 | ||
631 | if (cols > 12) { | |
956b9ba1 JP |
632 | edac_dbg(0, "Invalid number of cols: %d (max = 4) raw value = %x (%04x)\n", |
633 | cols, (unsigned int)COL_WIDTH_BITS(mtr), mtr); | |
eebf11a0 MCC |
634 | return -EINVAL; |
635 | } | |
636 | ||
637 | return 1 << cols; | |
638 | } | |
639 | ||
640 | static struct sbridge_dev *get_sbridge_dev(u8 bus) | |
641 | { | |
642 | struct sbridge_dev *sbridge_dev; | |
643 | ||
644 | list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) { | |
645 | if (sbridge_dev->bus == bus) | |
646 | return sbridge_dev; | |
647 | } | |
648 | ||
649 | return NULL; | |
650 | } | |
651 | ||
652 | static struct sbridge_dev *alloc_sbridge_dev(u8 bus, | |
653 | const struct pci_id_table *table) | |
654 | { | |
655 | struct sbridge_dev *sbridge_dev; | |
656 | ||
657 | sbridge_dev = kzalloc(sizeof(*sbridge_dev), GFP_KERNEL); | |
658 | if (!sbridge_dev) | |
659 | return NULL; | |
660 | ||
661 | sbridge_dev->pdev = kzalloc(sizeof(*sbridge_dev->pdev) * table->n_devs, | |
662 | GFP_KERNEL); | |
663 | if (!sbridge_dev->pdev) { | |
664 | kfree(sbridge_dev); | |
665 | return NULL; | |
666 | } | |
667 | ||
668 | sbridge_dev->bus = bus; | |
669 | sbridge_dev->n_devs = table->n_devs; | |
670 | list_add_tail(&sbridge_dev->list, &sbridge_edac_list); | |
671 | ||
672 | return sbridge_dev; | |
673 | } | |
674 | ||
675 | static void free_sbridge_dev(struct sbridge_dev *sbridge_dev) | |
676 | { | |
677 | list_del(&sbridge_dev->list); | |
678 | kfree(sbridge_dev->pdev); | |
679 | kfree(sbridge_dev); | |
680 | } | |
681 | ||
fb79a509 AR |
682 | static u64 sbridge_get_tolm(struct sbridge_pvt *pvt) |
683 | { | |
684 | u32 reg; | |
685 | ||
686 | /* Address range is 32:28 */ | |
687 | pci_read_config_dword(pvt->pci_sad1, TOLM, ®); | |
688 | return GET_TOLM(reg); | |
689 | } | |
690 | ||
8fd6a43a AR |
691 | static u64 sbridge_get_tohm(struct sbridge_pvt *pvt) |
692 | { | |
693 | u32 reg; | |
694 | ||
695 | pci_read_config_dword(pvt->pci_sad1, TOHM, ®); | |
696 | return GET_TOHM(reg); | |
697 | } | |
698 | ||
4d715a80 AR |
699 | static u64 ibridge_get_tolm(struct sbridge_pvt *pvt) |
700 | { | |
701 | u32 reg; | |
702 | ||
703 | pci_read_config_dword(pvt->pci_br1, TOLM, ®); | |
704 | ||
705 | return GET_TOLM(reg); | |
706 | } | |
707 | ||
708 | static u64 ibridge_get_tohm(struct sbridge_pvt *pvt) | |
709 | { | |
710 | u32 reg; | |
711 | ||
712 | pci_read_config_dword(pvt->pci_br1, TOHM, ®); | |
713 | ||
714 | return GET_TOHM(reg); | |
715 | } | |
716 | ||
b976bcf2 AR |
717 | static u64 rir_limit(u32 reg) |
718 | { | |
719 | return ((u64)GET_BITFIELD(reg, 1, 10) << 29) | 0x1fffffff; | |
720 | } | |
721 | ||
c59f9c06 JS |
722 | static u64 sad_limit(u32 reg) |
723 | { | |
724 | return (GET_BITFIELD(reg, 6, 25) << 26) | 0x3ffffff; | |
725 | } | |
726 | ||
727 | static u32 interleave_mode(u32 reg) | |
728 | { | |
729 | return GET_BITFIELD(reg, 1, 1); | |
730 | } | |
731 | ||
732 | char *show_interleave_mode(u32 reg) | |
733 | { | |
734 | return interleave_mode(reg) ? "8:6" : "[8:6]XOR[18:16]"; | |
735 | } | |
736 | ||
737 | static u32 dram_attr(u32 reg) | |
738 | { | |
739 | return GET_BITFIELD(reg, 2, 3); | |
740 | } | |
741 | ||
9e375446 AR |
742 | static enum mem_type get_memory_type(struct sbridge_pvt *pvt) |
743 | { | |
744 | u32 reg; | |
745 | enum mem_type mtype; | |
746 | ||
747 | if (pvt->pci_ddrio) { | |
748 | pci_read_config_dword(pvt->pci_ddrio, pvt->info.rankcfgr, | |
749 | ®); | |
750 | if (GET_BITFIELD(reg, 11, 11)) | |
751 | /* FIXME: Can also be LRDIMM */ | |
752 | mtype = MEM_RDDR3; | |
753 | else | |
754 | mtype = MEM_DDR3; | |
755 | } else | |
756 | mtype = MEM_UNKNOWN; | |
757 | ||
758 | return mtype; | |
759 | } | |
760 | ||
50d1bb93 AR |
761 | static enum mem_type haswell_get_memory_type(struct sbridge_pvt *pvt) |
762 | { | |
763 | u32 reg; | |
764 | bool registered = false; | |
765 | enum mem_type mtype = MEM_UNKNOWN; | |
766 | ||
767 | if (!pvt->pci_ddrio) | |
768 | goto out; | |
769 | ||
770 | pci_read_config_dword(pvt->pci_ddrio, | |
771 | HASWELL_DDRCRCLKCONTROLS, ®); | |
772 | /* Is_Rdimm */ | |
773 | if (GET_BITFIELD(reg, 16, 16)) | |
774 | registered = true; | |
775 | ||
776 | pci_read_config_dword(pvt->pci_ta, MCMTR, ®); | |
777 | if (GET_BITFIELD(reg, 14, 14)) { | |
778 | if (registered) | |
779 | mtype = MEM_RDDR4; | |
780 | else | |
781 | mtype = MEM_DDR4; | |
782 | } else { | |
783 | if (registered) | |
784 | mtype = MEM_RDDR3; | |
785 | else | |
786 | mtype = MEM_DDR3; | |
787 | } | |
788 | ||
789 | out: | |
790 | return mtype; | |
791 | } | |
792 | ||
12f0721c AR |
793 | static enum dev_type sbridge_get_width(struct sbridge_pvt *pvt, u32 mtr) |
794 | { | |
795 | /* there's no way to figure out */ | |
796 | return DEV_UNKNOWN; | |
797 | } | |
798 | ||
799 | static enum dev_type __ibridge_get_width(u32 mtr) | |
800 | { | |
801 | enum dev_type type; | |
802 | ||
803 | switch (mtr) { | |
804 | case 3: | |
805 | type = DEV_UNKNOWN; | |
806 | break; | |
807 | case 2: | |
808 | type = DEV_X16; | |
809 | break; | |
810 | case 1: | |
811 | type = DEV_X8; | |
812 | break; | |
813 | case 0: | |
814 | type = DEV_X4; | |
815 | break; | |
816 | } | |
817 | ||
818 | return type; | |
819 | } | |
820 | ||
821 | static enum dev_type ibridge_get_width(struct sbridge_pvt *pvt, u32 mtr) | |
822 | { | |
823 | /* | |
824 | * ddr3_width on the documentation but also valid for DDR4 on | |
825 | * Haswell | |
826 | */ | |
827 | return __ibridge_get_width(GET_BITFIELD(mtr, 7, 8)); | |
828 | } | |
829 | ||
830 | static enum dev_type broadwell_get_width(struct sbridge_pvt *pvt, u32 mtr) | |
831 | { | |
832 | /* ddr3_width on the documentation but also valid for DDR4 */ | |
833 | return __ibridge_get_width(GET_BITFIELD(mtr, 8, 9)); | |
834 | } | |
835 | ||
f14d6892 AR |
836 | static u8 get_node_id(struct sbridge_pvt *pvt) |
837 | { | |
838 | u32 reg; | |
839 | pci_read_config_dword(pvt->pci_br0, SAD_CONTROL, ®); | |
840 | return GET_BITFIELD(reg, 0, 2); | |
841 | } | |
842 | ||
50d1bb93 AR |
843 | static u8 haswell_get_node_id(struct sbridge_pvt *pvt) |
844 | { | |
845 | u32 reg; | |
846 | ||
847 | pci_read_config_dword(pvt->pci_sad1, SAD_CONTROL, ®); | |
848 | return GET_BITFIELD(reg, 0, 3); | |
849 | } | |
850 | ||
851 | static u64 haswell_get_tolm(struct sbridge_pvt *pvt) | |
852 | { | |
853 | u32 reg; | |
854 | ||
f7cf2a22 TL |
855 | pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOLM, ®); |
856 | return (GET_BITFIELD(reg, 26, 31) << 26) | 0x3ffffff; | |
50d1bb93 AR |
857 | } |
858 | ||
859 | static u64 haswell_get_tohm(struct sbridge_pvt *pvt) | |
860 | { | |
861 | u64 rc; | |
862 | u32 reg; | |
863 | ||
864 | pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOHM_0, ®); | |
865 | rc = GET_BITFIELD(reg, 26, 31); | |
866 | pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOHM_1, ®); | |
867 | rc = ((reg << 6) | rc) << 26; | |
868 | ||
869 | return rc | 0x1ffffff; | |
870 | } | |
871 | ||
872 | static u64 haswell_rir_limit(u32 reg) | |
873 | { | |
874 | return (((u64)GET_BITFIELD(reg, 1, 11) + 1) << 29) - 1; | |
875 | } | |
876 | ||
4d715a80 AR |
877 | static inline u8 sad_pkg_socket(u8 pkg) |
878 | { | |
879 | /* on Ivy Bridge, nodeID is SASS, where A is HA and S is node id */ | |
2ff3a308 | 880 | return ((pkg >> 3) << 2) | (pkg & 0x3); |
4d715a80 AR |
881 | } |
882 | ||
883 | static inline u8 sad_pkg_ha(u8 pkg) | |
884 | { | |
885 | return (pkg >> 2) & 0x1; | |
886 | } | |
887 | ||
eebf11a0 MCC |
888 | /**************************************************************************** |
889 | Memory check routines | |
890 | ****************************************************************************/ | |
dbc954dd | 891 | static struct pci_dev *get_pdev_same_bus(u8 bus, u32 id) |
eebf11a0 | 892 | { |
dbc954dd | 893 | struct pci_dev *pdev = NULL; |
eebf11a0 | 894 | |
dbc954dd AR |
895 | do { |
896 | pdev = pci_get_device(PCI_VENDOR_ID_INTEL, id, pdev); | |
897 | if (pdev && pdev->bus->number == bus) | |
898 | break; | |
899 | } while (pdev); | |
eebf11a0 | 900 | |
dbc954dd | 901 | return pdev; |
eebf11a0 MCC |
902 | } |
903 | ||
904 | /** | |
c36e3e77 | 905 | * check_if_ecc_is_active() - Checks if ECC is active |
50d1bb93 AR |
906 | * @bus: Device bus |
907 | * @type: Memory controller type | |
908 | * returns: 0 in case ECC is active, -ENODEV if it can't be determined or | |
909 | * disabled | |
eebf11a0 | 910 | */ |
dbc954dd | 911 | static int check_if_ecc_is_active(const u8 bus, enum type type) |
eebf11a0 MCC |
912 | { |
913 | struct pci_dev *pdev = NULL; | |
dbc954dd | 914 | u32 mcmtr, id; |
eebf11a0 | 915 | |
1f39581a TL |
916 | switch (type) { |
917 | case IVY_BRIDGE: | |
dbc954dd | 918 | id = PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA; |
1f39581a TL |
919 | break; |
920 | case HASWELL: | |
50d1bb93 | 921 | id = PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA; |
1f39581a TL |
922 | break; |
923 | case SANDY_BRIDGE: | |
dbc954dd | 924 | id = PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA; |
1f39581a TL |
925 | break; |
926 | case BROADWELL: | |
927 | id = PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TA; | |
928 | break; | |
929 | default: | |
930 | return -ENODEV; | |
931 | } | |
dbc954dd AR |
932 | |
933 | pdev = get_pdev_same_bus(bus, id); | |
eebf11a0 MCC |
934 | if (!pdev) { |
935 | sbridge_printk(KERN_ERR, "Couldn't find PCI device " | |
dbc954dd AR |
936 | "%04x:%04x! on bus %02d\n", |
937 | PCI_VENDOR_ID_INTEL, id, bus); | |
eebf11a0 MCC |
938 | return -ENODEV; |
939 | } | |
940 | ||
941 | pci_read_config_dword(pdev, MCMTR, &mcmtr); | |
942 | if (!IS_ECC_ENABLED(mcmtr)) { | |
943 | sbridge_printk(KERN_ERR, "ECC is disabled. Aborting\n"); | |
944 | return -ENODEV; | |
945 | } | |
eebf11a0 MCC |
946 | return 0; |
947 | } | |
948 | ||
084a4fcc | 949 | static int get_dimm_config(struct mem_ctl_info *mci) |
eebf11a0 MCC |
950 | { |
951 | struct sbridge_pvt *pvt = mci->pvt_info; | |
c36e3e77 | 952 | struct dimm_info *dimm; |
deb09dda MCC |
953 | unsigned i, j, banks, ranks, rows, cols, npages; |
954 | u64 size; | |
eebf11a0 MCC |
955 | u32 reg; |
956 | enum edac_type mode; | |
c6e13b52 | 957 | enum mem_type mtype; |
eebf11a0 | 958 | |
1f39581a | 959 | if (pvt->info.type == HASWELL || pvt->info.type == BROADWELL) |
50d1bb93 AR |
960 | pci_read_config_dword(pvt->pci_sad1, SAD_TARGET, ®); |
961 | else | |
962 | pci_read_config_dword(pvt->pci_br0, SAD_TARGET, ®); | |
963 | ||
eebf11a0 MCC |
964 | pvt->sbridge_dev->source_id = SOURCE_ID(reg); |
965 | ||
f14d6892 | 966 | pvt->sbridge_dev->node_id = pvt->info.get_node_id(pvt); |
956b9ba1 JP |
967 | edac_dbg(0, "mc#%d: Node ID: %d, source ID: %d\n", |
968 | pvt->sbridge_dev->mc, | |
969 | pvt->sbridge_dev->node_id, | |
970 | pvt->sbridge_dev->source_id); | |
eebf11a0 MCC |
971 | |
972 | pci_read_config_dword(pvt->pci_ras, RASENABLES, ®); | |
973 | if (IS_MIRROR_ENABLED(reg)) { | |
956b9ba1 | 974 | edac_dbg(0, "Memory mirror is enabled\n"); |
eebf11a0 MCC |
975 | pvt->is_mirrored = true; |
976 | } else { | |
956b9ba1 | 977 | edac_dbg(0, "Memory mirror is disabled\n"); |
eebf11a0 MCC |
978 | pvt->is_mirrored = false; |
979 | } | |
980 | ||
981 | pci_read_config_dword(pvt->pci_ta, MCMTR, &pvt->info.mcmtr); | |
982 | if (IS_LOCKSTEP_ENABLED(pvt->info.mcmtr)) { | |
956b9ba1 | 983 | edac_dbg(0, "Lockstep is enabled\n"); |
eebf11a0 MCC |
984 | mode = EDAC_S8ECD8ED; |
985 | pvt->is_lockstep = true; | |
986 | } else { | |
956b9ba1 | 987 | edac_dbg(0, "Lockstep is disabled\n"); |
eebf11a0 MCC |
988 | mode = EDAC_S4ECD4ED; |
989 | pvt->is_lockstep = false; | |
990 | } | |
991 | if (IS_CLOSE_PG(pvt->info.mcmtr)) { | |
956b9ba1 | 992 | edac_dbg(0, "address map is on closed page mode\n"); |
eebf11a0 MCC |
993 | pvt->is_close_pg = true; |
994 | } else { | |
956b9ba1 | 995 | edac_dbg(0, "address map is on open page mode\n"); |
eebf11a0 MCC |
996 | pvt->is_close_pg = false; |
997 | } | |
998 | ||
9e375446 | 999 | mtype = pvt->info.get_memory_type(pvt); |
50d1bb93 | 1000 | if (mtype == MEM_RDDR3 || mtype == MEM_RDDR4) |
9e375446 AR |
1001 | edac_dbg(0, "Memory is registered\n"); |
1002 | else if (mtype == MEM_UNKNOWN) | |
de4772c6 | 1003 | edac_dbg(0, "Cannot determine memory type\n"); |
9e375446 AR |
1004 | else |
1005 | edac_dbg(0, "Memory is unregistered\n"); | |
eebf11a0 | 1006 | |
fec53af5 | 1007 | if (mtype == MEM_DDR4 || mtype == MEM_RDDR4) |
50d1bb93 AR |
1008 | banks = 16; |
1009 | else | |
1010 | banks = 8; | |
eebf11a0 MCC |
1011 | |
1012 | for (i = 0; i < NUM_CHANNELS; i++) { | |
1013 | u32 mtr; | |
1014 | ||
7d375bff TL |
1015 | if (!pvt->pci_tad[i]) |
1016 | continue; | |
eebf11a0 | 1017 | for (j = 0; j < ARRAY_SIZE(mtr_regs); j++) { |
c36e3e77 MCC |
1018 | dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers, |
1019 | i, j, 0); | |
eebf11a0 MCC |
1020 | pci_read_config_dword(pvt->pci_tad[i], |
1021 | mtr_regs[j], &mtr); | |
956b9ba1 | 1022 | edac_dbg(4, "Channel #%d MTR%d = %x\n", i, j, mtr); |
eebf11a0 MCC |
1023 | if (IS_DIMM_PRESENT(mtr)) { |
1024 | pvt->channel[i].dimms++; | |
1025 | ||
50d1bb93 | 1026 | ranks = numrank(pvt->info.type, mtr); |
eebf11a0 MCC |
1027 | rows = numrow(mtr); |
1028 | cols = numcol(mtr); | |
1029 | ||
deb09dda | 1030 | size = ((u64)rows * cols * banks * ranks) >> (20 - 3); |
eebf11a0 MCC |
1031 | npages = MiB_TO_PAGES(size); |
1032 | ||
7d375bff TL |
1033 | edac_dbg(0, "mc#%d: ha %d channel %d, dimm %d, %lld Mb (%d pages) bank: %d, rank: %d, row: %#x, col: %#x\n", |
1034 | pvt->sbridge_dev->mc, i/4, i%4, j, | |
956b9ba1 JP |
1035 | size, npages, |
1036 | banks, ranks, rows, cols); | |
eebf11a0 | 1037 | |
a895bf8b | 1038 | dimm->nr_pages = npages; |
084a4fcc | 1039 | dimm->grain = 32; |
12f0721c | 1040 | dimm->dtype = pvt->info.get_width(pvt, mtr); |
084a4fcc MCC |
1041 | dimm->mtype = mtype; |
1042 | dimm->edac_mode = mode; | |
1043 | snprintf(dimm->label, sizeof(dimm->label), | |
7d375bff TL |
1044 | "CPU_SrcID#%u_Ha#%u_Chan#%u_DIMM#%u", |
1045 | pvt->sbridge_dev->source_id, i/4, i%4, j); | |
eebf11a0 MCC |
1046 | } |
1047 | } | |
1048 | } | |
1049 | ||
1050 | return 0; | |
1051 | } | |
1052 | ||
1053 | static void get_memory_layout(const struct mem_ctl_info *mci) | |
1054 | { | |
1055 | struct sbridge_pvt *pvt = mci->pvt_info; | |
1056 | int i, j, k, n_sads, n_tads, sad_interl; | |
1057 | u32 reg; | |
1058 | u64 limit, prv = 0; | |
1059 | u64 tmp_mb; | |
8c009100 | 1060 | u32 gb, mb; |
eebf11a0 MCC |
1061 | u32 rir_way; |
1062 | ||
1063 | /* | |
1064 | * Step 1) Get TOLM/TOHM ranges | |
1065 | */ | |
1066 | ||
fb79a509 | 1067 | pvt->tolm = pvt->info.get_tolm(pvt); |
eebf11a0 MCC |
1068 | tmp_mb = (1 + pvt->tolm) >> 20; |
1069 | ||
8c009100 JS |
1070 | gb = div_u64_rem(tmp_mb, 1024, &mb); |
1071 | edac_dbg(0, "TOLM: %u.%03u GB (0x%016Lx)\n", | |
1072 | gb, (mb*1000)/1024, (u64)pvt->tolm); | |
eebf11a0 MCC |
1073 | |
1074 | /* Address range is already 45:25 */ | |
8fd6a43a | 1075 | pvt->tohm = pvt->info.get_tohm(pvt); |
eebf11a0 MCC |
1076 | tmp_mb = (1 + pvt->tohm) >> 20; |
1077 | ||
8c009100 JS |
1078 | gb = div_u64_rem(tmp_mb, 1024, &mb); |
1079 | edac_dbg(0, "TOHM: %u.%03u GB (0x%016Lx)\n", | |
1080 | gb, (mb*1000)/1024, (u64)pvt->tohm); | |
eebf11a0 MCC |
1081 | |
1082 | /* | |
1083 | * Step 2) Get SAD range and SAD Interleave list | |
1084 | * TAD registers contain the interleave wayness. However, it | |
1085 | * seems simpler to just discover it indirectly, with the | |
1086 | * algorithm bellow. | |
1087 | */ | |
1088 | prv = 0; | |
464f1d82 | 1089 | for (n_sads = 0; n_sads < pvt->info.max_sad; n_sads++) { |
eebf11a0 | 1090 | /* SAD_LIMIT Address range is 45:26 */ |
464f1d82 | 1091 | pci_read_config_dword(pvt->pci_sad0, pvt->info.dram_rule[n_sads], |
eebf11a0 | 1092 | ®); |
c59f9c06 | 1093 | limit = pvt->info.sad_limit(reg); |
eebf11a0 MCC |
1094 | |
1095 | if (!DRAM_RULE_ENABLE(reg)) | |
1096 | continue; | |
1097 | ||
1098 | if (limit <= prv) | |
1099 | break; | |
1100 | ||
1101 | tmp_mb = (limit + 1) >> 20; | |
8c009100 | 1102 | gb = div_u64_rem(tmp_mb, 1024, &mb); |
956b9ba1 JP |
1103 | edac_dbg(0, "SAD#%d %s up to %u.%03u GB (0x%016Lx) Interleave: %s reg=0x%08x\n", |
1104 | n_sads, | |
c59f9c06 | 1105 | show_dram_attr(pvt->info.dram_attr(reg)), |
8c009100 | 1106 | gb, (mb*1000)/1024, |
956b9ba1 | 1107 | ((u64)tmp_mb) << 20L, |
c59f9c06 | 1108 | pvt->info.show_interleave_mode(reg), |
956b9ba1 | 1109 | reg); |
eebf11a0 MCC |
1110 | prv = limit; |
1111 | ||
ef1ce51e | 1112 | pci_read_config_dword(pvt->pci_sad0, pvt->info.interleave_list[n_sads], |
eebf11a0 | 1113 | ®); |
cc311991 | 1114 | sad_interl = sad_pkg(pvt->info.interleave_pkg, reg, 0); |
eebf11a0 | 1115 | for (j = 0; j < 8; j++) { |
cc311991 AR |
1116 | u32 pkg = sad_pkg(pvt->info.interleave_pkg, reg, j); |
1117 | if (j > 0 && sad_interl == pkg) | |
eebf11a0 MCC |
1118 | break; |
1119 | ||
956b9ba1 | 1120 | edac_dbg(0, "SAD#%d, interleave #%d: %d\n", |
cc311991 | 1121 | n_sads, j, pkg); |
eebf11a0 MCC |
1122 | } |
1123 | } | |
1124 | ||
1125 | /* | |
1126 | * Step 3) Get TAD range | |
1127 | */ | |
1128 | prv = 0; | |
1129 | for (n_tads = 0; n_tads < MAX_TAD; n_tads++) { | |
1130 | pci_read_config_dword(pvt->pci_ha0, tad_dram_rule[n_tads], | |
1131 | ®); | |
1132 | limit = TAD_LIMIT(reg); | |
1133 | if (limit <= prv) | |
1134 | break; | |
1135 | tmp_mb = (limit + 1) >> 20; | |
1136 | ||
8c009100 | 1137 | gb = div_u64_rem(tmp_mb, 1024, &mb); |
956b9ba1 | 1138 | edac_dbg(0, "TAD#%d: up to %u.%03u GB (0x%016Lx), socket interleave %d, memory interleave %d, TGT: %d, %d, %d, %d, reg=0x%08x\n", |
8c009100 | 1139 | n_tads, gb, (mb*1000)/1024, |
956b9ba1 JP |
1140 | ((u64)tmp_mb) << 20L, |
1141 | (u32)TAD_SOCK(reg), | |
1142 | (u32)TAD_CH(reg), | |
1143 | (u32)TAD_TGT0(reg), | |
1144 | (u32)TAD_TGT1(reg), | |
1145 | (u32)TAD_TGT2(reg), | |
1146 | (u32)TAD_TGT3(reg), | |
1147 | reg); | |
7fae0db4 | 1148 | prv = limit; |
eebf11a0 MCC |
1149 | } |
1150 | ||
1151 | /* | |
1152 | * Step 4) Get TAD offsets, per each channel | |
1153 | */ | |
1154 | for (i = 0; i < NUM_CHANNELS; i++) { | |
1155 | if (!pvt->channel[i].dimms) | |
1156 | continue; | |
1157 | for (j = 0; j < n_tads; j++) { | |
1158 | pci_read_config_dword(pvt->pci_tad[i], | |
1159 | tad_ch_nilv_offset[j], | |
1160 | ®); | |
1161 | tmp_mb = TAD_OFFSET(reg) >> 20; | |
8c009100 | 1162 | gb = div_u64_rem(tmp_mb, 1024, &mb); |
956b9ba1 JP |
1163 | edac_dbg(0, "TAD CH#%d, offset #%d: %u.%03u GB (0x%016Lx), reg=0x%08x\n", |
1164 | i, j, | |
8c009100 | 1165 | gb, (mb*1000)/1024, |
956b9ba1 JP |
1166 | ((u64)tmp_mb) << 20L, |
1167 | reg); | |
eebf11a0 MCC |
1168 | } |
1169 | } | |
1170 | ||
1171 | /* | |
1172 | * Step 6) Get RIR Wayness/Limit, per each channel | |
1173 | */ | |
1174 | for (i = 0; i < NUM_CHANNELS; i++) { | |
1175 | if (!pvt->channel[i].dimms) | |
1176 | continue; | |
1177 | for (j = 0; j < MAX_RIR_RANGES; j++) { | |
1178 | pci_read_config_dword(pvt->pci_tad[i], | |
1179 | rir_way_limit[j], | |
1180 | ®); | |
1181 | ||
1182 | if (!IS_RIR_VALID(reg)) | |
1183 | continue; | |
1184 | ||
b976bcf2 | 1185 | tmp_mb = pvt->info.rir_limit(reg) >> 20; |
eebf11a0 | 1186 | rir_way = 1 << RIR_WAY(reg); |
8c009100 | 1187 | gb = div_u64_rem(tmp_mb, 1024, &mb); |
956b9ba1 JP |
1188 | edac_dbg(0, "CH#%d RIR#%d, limit: %u.%03u GB (0x%016Lx), way: %d, reg=0x%08x\n", |
1189 | i, j, | |
8c009100 | 1190 | gb, (mb*1000)/1024, |
956b9ba1 JP |
1191 | ((u64)tmp_mb) << 20L, |
1192 | rir_way, | |
1193 | reg); | |
eebf11a0 MCC |
1194 | |
1195 | for (k = 0; k < rir_way; k++) { | |
1196 | pci_read_config_dword(pvt->pci_tad[i], | |
1197 | rir_offset[j][k], | |
1198 | ®); | |
1199 | tmp_mb = RIR_OFFSET(reg) << 6; | |
1200 | ||
8c009100 | 1201 | gb = div_u64_rem(tmp_mb, 1024, &mb); |
956b9ba1 JP |
1202 | edac_dbg(0, "CH#%d RIR#%d INTL#%d, offset %u.%03u GB (0x%016Lx), tgt: %d, reg=0x%08x\n", |
1203 | i, j, k, | |
8c009100 | 1204 | gb, (mb*1000)/1024, |
956b9ba1 JP |
1205 | ((u64)tmp_mb) << 20L, |
1206 | (u32)RIR_RNK_TGT(reg), | |
1207 | reg); | |
eebf11a0 MCC |
1208 | } |
1209 | } | |
1210 | } | |
1211 | } | |
1212 | ||
8112c0cd | 1213 | static struct mem_ctl_info *get_mci_for_node_id(u8 node_id) |
eebf11a0 MCC |
1214 | { |
1215 | struct sbridge_dev *sbridge_dev; | |
1216 | ||
1217 | list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) { | |
1218 | if (sbridge_dev->node_id == node_id) | |
1219 | return sbridge_dev->mci; | |
1220 | } | |
1221 | return NULL; | |
1222 | } | |
1223 | ||
1224 | static int get_memory_error_data(struct mem_ctl_info *mci, | |
1225 | u64 addr, | |
7d375bff | 1226 | u8 *socket, u8 *ha, |
eebf11a0 MCC |
1227 | long *channel_mask, |
1228 | u8 *rank, | |
e17a2f42 | 1229 | char **area_type, char *msg) |
eebf11a0 MCC |
1230 | { |
1231 | struct mem_ctl_info *new_mci; | |
1232 | struct sbridge_pvt *pvt = mci->pvt_info; | |
4d715a80 | 1233 | struct pci_dev *pci_ha; |
c41afdca | 1234 | int n_rir, n_sads, n_tads, sad_way, sck_xch; |
eebf11a0 | 1235 | int sad_interl, idx, base_ch; |
50d1bb93 | 1236 | int interleave_mode, shiftup = 0; |
ef1ce51e | 1237 | unsigned sad_interleave[pvt->info.max_interleave]; |
50d1bb93 | 1238 | u32 reg, dram_rule; |
7d375bff | 1239 | u8 ch_way, sck_way, pkg, sad_ha = 0, ch_add = 0; |
eebf11a0 MCC |
1240 | u32 tad_offset; |
1241 | u32 rir_way; | |
8c009100 | 1242 | u32 mb, gb; |
bd4b9683 | 1243 | u64 ch_addr, offset, limit = 0, prv = 0; |
eebf11a0 MCC |
1244 | |
1245 | ||
1246 | /* | |
1247 | * Step 0) Check if the address is at special memory ranges | |
1248 | * The check bellow is probably enough to fill all cases where | |
1249 | * the error is not inside a memory, except for the legacy | |
1250 | * range (e. g. VGA addresses). It is unlikely, however, that the | |
1251 | * memory controller would generate an error on that range. | |
1252 | */ | |
5b889e37 | 1253 | if ((addr > (u64) pvt->tolm) && (addr < (1LL << 32))) { |
eebf11a0 | 1254 | sprintf(msg, "Error at TOLM area, on addr 0x%08Lx", addr); |
eebf11a0 MCC |
1255 | return -EINVAL; |
1256 | } | |
1257 | if (addr >= (u64)pvt->tohm) { | |
1258 | sprintf(msg, "Error at MMIOH area, on addr 0x%016Lx", addr); | |
eebf11a0 MCC |
1259 | return -EINVAL; |
1260 | } | |
1261 | ||
1262 | /* | |
1263 | * Step 1) Get socket | |
1264 | */ | |
464f1d82 AR |
1265 | for (n_sads = 0; n_sads < pvt->info.max_sad; n_sads++) { |
1266 | pci_read_config_dword(pvt->pci_sad0, pvt->info.dram_rule[n_sads], | |
eebf11a0 MCC |
1267 | ®); |
1268 | ||
1269 | if (!DRAM_RULE_ENABLE(reg)) | |
1270 | continue; | |
1271 | ||
c59f9c06 | 1272 | limit = pvt->info.sad_limit(reg); |
eebf11a0 MCC |
1273 | if (limit <= prv) { |
1274 | sprintf(msg, "Can't discover the memory socket"); | |
eebf11a0 MCC |
1275 | return -EINVAL; |
1276 | } | |
1277 | if (addr <= limit) | |
1278 | break; | |
1279 | prv = limit; | |
1280 | } | |
464f1d82 | 1281 | if (n_sads == pvt->info.max_sad) { |
eebf11a0 | 1282 | sprintf(msg, "Can't discover the memory socket"); |
eebf11a0 MCC |
1283 | return -EINVAL; |
1284 | } | |
50d1bb93 | 1285 | dram_rule = reg; |
c59f9c06 JS |
1286 | *area_type = show_dram_attr(pvt->info.dram_attr(dram_rule)); |
1287 | interleave_mode = pvt->info.interleave_mode(dram_rule); | |
eebf11a0 | 1288 | |
ef1ce51e | 1289 | pci_read_config_dword(pvt->pci_sad0, pvt->info.interleave_list[n_sads], |
eebf11a0 | 1290 | ®); |
4d715a80 AR |
1291 | |
1292 | if (pvt->info.type == SANDY_BRIDGE) { | |
1293 | sad_interl = sad_pkg(pvt->info.interleave_pkg, reg, 0); | |
1294 | for (sad_way = 0; sad_way < 8; sad_way++) { | |
1295 | u32 pkg = sad_pkg(pvt->info.interleave_pkg, reg, sad_way); | |
1296 | if (sad_way > 0 && sad_interl == pkg) | |
1297 | break; | |
1298 | sad_interleave[sad_way] = pkg; | |
1299 | edac_dbg(0, "SAD interleave #%d: %d\n", | |
1300 | sad_way, sad_interleave[sad_way]); | |
1301 | } | |
1302 | edac_dbg(0, "mc#%d: Error detected on SAD#%d: address 0x%016Lx < 0x%016Lx, Interleave [%d:6]%s\n", | |
1303 | pvt->sbridge_dev->mc, | |
1304 | n_sads, | |
1305 | addr, | |
1306 | limit, | |
1307 | sad_way + 7, | |
1308 | !interleave_mode ? "" : "XOR[18:16]"); | |
1309 | if (interleave_mode) | |
1310 | idx = ((addr >> 6) ^ (addr >> 16)) & 7; | |
1311 | else | |
1312 | idx = (addr >> 6) & 7; | |
1313 | switch (sad_way) { | |
1314 | case 1: | |
1315 | idx = 0; | |
eebf11a0 | 1316 | break; |
4d715a80 AR |
1317 | case 2: |
1318 | idx = idx & 1; | |
1319 | break; | |
1320 | case 4: | |
1321 | idx = idx & 3; | |
1322 | break; | |
1323 | case 8: | |
1324 | break; | |
1325 | default: | |
1326 | sprintf(msg, "Can't discover socket interleave"); | |
1327 | return -EINVAL; | |
1328 | } | |
1329 | *socket = sad_interleave[idx]; | |
1330 | edac_dbg(0, "SAD interleave index: %d (wayness %d) = CPU socket %d\n", | |
1331 | idx, sad_way, *socket); | |
1f39581a | 1332 | } else if (pvt->info.type == HASWELL || pvt->info.type == BROADWELL) { |
50d1bb93 AR |
1333 | int bits, a7mode = A7MODE(dram_rule); |
1334 | ||
1335 | if (a7mode) { | |
1336 | /* A7 mode swaps P9 with P6 */ | |
1337 | bits = GET_BITFIELD(addr, 7, 8) << 1; | |
1338 | bits |= GET_BITFIELD(addr, 9, 9); | |
1339 | } else | |
bb89e714 | 1340 | bits = GET_BITFIELD(addr, 6, 8); |
50d1bb93 | 1341 | |
bb89e714 | 1342 | if (interleave_mode == 0) { |
50d1bb93 AR |
1343 | /* interleave mode will XOR {8,7,6} with {18,17,16} */ |
1344 | idx = GET_BITFIELD(addr, 16, 18); | |
1345 | idx ^= bits; | |
1346 | } else | |
1347 | idx = bits; | |
1348 | ||
1349 | pkg = sad_pkg(pvt->info.interleave_pkg, reg, idx); | |
1350 | *socket = sad_pkg_socket(pkg); | |
1351 | sad_ha = sad_pkg_ha(pkg); | |
7d375bff TL |
1352 | if (sad_ha) |
1353 | ch_add = 4; | |
50d1bb93 AR |
1354 | |
1355 | if (a7mode) { | |
1356 | /* MCChanShiftUpEnable */ | |
1357 | pci_read_config_dword(pvt->pci_ha0, | |
1358 | HASWELL_HASYSDEFEATURE2, ®); | |
1359 | shiftup = GET_BITFIELD(reg, 22, 22); | |
1360 | } | |
1361 | ||
1362 | edac_dbg(0, "SAD interleave package: %d = CPU socket %d, HA %i, shiftup: %i\n", | |
1363 | idx, *socket, sad_ha, shiftup); | |
4d715a80 AR |
1364 | } else { |
1365 | /* Ivy Bridge's SAD mode doesn't support XOR interleave mode */ | |
eebf11a0 | 1366 | idx = (addr >> 6) & 7; |
4d715a80 AR |
1367 | pkg = sad_pkg(pvt->info.interleave_pkg, reg, idx); |
1368 | *socket = sad_pkg_socket(pkg); | |
1369 | sad_ha = sad_pkg_ha(pkg); | |
7d375bff TL |
1370 | if (sad_ha) |
1371 | ch_add = 4; | |
4d715a80 AR |
1372 | edac_dbg(0, "SAD interleave package: %d = CPU socket %d, HA %d\n", |
1373 | idx, *socket, sad_ha); | |
eebf11a0 | 1374 | } |
eebf11a0 | 1375 | |
7d375bff TL |
1376 | *ha = sad_ha; |
1377 | ||
eebf11a0 MCC |
1378 | /* |
1379 | * Move to the proper node structure, in order to access the | |
1380 | * right PCI registers | |
1381 | */ | |
1382 | new_mci = get_mci_for_node_id(*socket); | |
1383 | if (!new_mci) { | |
1384 | sprintf(msg, "Struct for socket #%u wasn't initialized", | |
1385 | *socket); | |
eebf11a0 MCC |
1386 | return -EINVAL; |
1387 | } | |
1388 | mci = new_mci; | |
1389 | pvt = mci->pvt_info; | |
1390 | ||
1391 | /* | |
1392 | * Step 2) Get memory channel | |
1393 | */ | |
1394 | prv = 0; | |
4d715a80 AR |
1395 | if (pvt->info.type == SANDY_BRIDGE) |
1396 | pci_ha = pvt->pci_ha0; | |
1397 | else { | |
1398 | if (sad_ha) | |
1399 | pci_ha = pvt->pci_ha1; | |
1400 | else | |
1401 | pci_ha = pvt->pci_ha0; | |
1402 | } | |
eebf11a0 | 1403 | for (n_tads = 0; n_tads < MAX_TAD; n_tads++) { |
4d715a80 | 1404 | pci_read_config_dword(pci_ha, tad_dram_rule[n_tads], ®); |
eebf11a0 MCC |
1405 | limit = TAD_LIMIT(reg); |
1406 | if (limit <= prv) { | |
1407 | sprintf(msg, "Can't discover the memory channel"); | |
eebf11a0 MCC |
1408 | return -EINVAL; |
1409 | } | |
1410 | if (addr <= limit) | |
1411 | break; | |
1412 | prv = limit; | |
1413 | } | |
4d715a80 AR |
1414 | if (n_tads == MAX_TAD) { |
1415 | sprintf(msg, "Can't discover the memory channel"); | |
1416 | return -EINVAL; | |
1417 | } | |
1418 | ||
eebf11a0 MCC |
1419 | ch_way = TAD_CH(reg) + 1; |
1420 | sck_way = TAD_SOCK(reg) + 1; | |
eebf11a0 MCC |
1421 | |
1422 | if (ch_way == 3) | |
1423 | idx = addr >> 6; | |
1424 | else | |
50d1bb93 | 1425 | idx = (addr >> (6 + sck_way + shiftup)) & 0x3; |
eebf11a0 MCC |
1426 | idx = idx % ch_way; |
1427 | ||
1428 | /* | |
1429 | * FIXME: Shouldn't we use CHN_IDX_OFFSET() here, when ch_way == 3 ??? | |
1430 | */ | |
1431 | switch (idx) { | |
1432 | case 0: | |
1433 | base_ch = TAD_TGT0(reg); | |
1434 | break; | |
1435 | case 1: | |
1436 | base_ch = TAD_TGT1(reg); | |
1437 | break; | |
1438 | case 2: | |
1439 | base_ch = TAD_TGT2(reg); | |
1440 | break; | |
1441 | case 3: | |
1442 | base_ch = TAD_TGT3(reg); | |
1443 | break; | |
1444 | default: | |
1445 | sprintf(msg, "Can't discover the TAD target"); | |
eebf11a0 MCC |
1446 | return -EINVAL; |
1447 | } | |
1448 | *channel_mask = 1 << base_ch; | |
1449 | ||
7d375bff | 1450 | pci_read_config_dword(pvt->pci_tad[ch_add + base_ch], |
4d715a80 AR |
1451 | tad_ch_nilv_offset[n_tads], |
1452 | &tad_offset); | |
1453 | ||
eebf11a0 MCC |
1454 | if (pvt->is_mirrored) { |
1455 | *channel_mask |= 1 << ((base_ch + 2) % 4); | |
1456 | switch(ch_way) { | |
1457 | case 2: | |
1458 | case 4: | |
1459 | sck_xch = 1 << sck_way * (ch_way >> 1); | |
1460 | break; | |
1461 | default: | |
1462 | sprintf(msg, "Invalid mirror set. Can't decode addr"); | |
eebf11a0 MCC |
1463 | return -EINVAL; |
1464 | } | |
1465 | } else | |
1466 | sck_xch = (1 << sck_way) * ch_way; | |
1467 | ||
1468 | if (pvt->is_lockstep) | |
1469 | *channel_mask |= 1 << ((base_ch + 1) % 4); | |
1470 | ||
1471 | offset = TAD_OFFSET(tad_offset); | |
1472 | ||
956b9ba1 JP |
1473 | edac_dbg(0, "TAD#%d: address 0x%016Lx < 0x%016Lx, socket interleave %d, channel interleave %d (offset 0x%08Lx), index %d, base ch: %d, ch mask: 0x%02lx\n", |
1474 | n_tads, | |
1475 | addr, | |
1476 | limit, | |
1477 | (u32)TAD_SOCK(reg), | |
1478 | ch_way, | |
1479 | offset, | |
1480 | idx, | |
1481 | base_ch, | |
1482 | *channel_mask); | |
eebf11a0 MCC |
1483 | |
1484 | /* Calculate channel address */ | |
1485 | /* Remove the TAD offset */ | |
1486 | ||
1487 | if (offset > addr) { | |
1488 | sprintf(msg, "Can't calculate ch addr: TAD offset 0x%08Lx is too high for addr 0x%08Lx!", | |
1489 | offset, addr); | |
eebf11a0 MCC |
1490 | return -EINVAL; |
1491 | } | |
1492 | addr -= offset; | |
1493 | /* Store the low bits [0:6] of the addr */ | |
1494 | ch_addr = addr & 0x7f; | |
1495 | /* Remove socket wayness and remove 6 bits */ | |
1496 | addr >>= 6; | |
5b889e37 | 1497 | addr = div_u64(addr, sck_xch); |
eebf11a0 MCC |
1498 | #if 0 |
1499 | /* Divide by channel way */ | |
1500 | addr = addr / ch_way; | |
1501 | #endif | |
1502 | /* Recover the last 6 bits */ | |
1503 | ch_addr |= addr << 6; | |
1504 | ||
1505 | /* | |
1506 | * Step 3) Decode rank | |
1507 | */ | |
1508 | for (n_rir = 0; n_rir < MAX_RIR_RANGES; n_rir++) { | |
7d375bff | 1509 | pci_read_config_dword(pvt->pci_tad[ch_add + base_ch], |
eebf11a0 MCC |
1510 | rir_way_limit[n_rir], |
1511 | ®); | |
1512 | ||
1513 | if (!IS_RIR_VALID(reg)) | |
1514 | continue; | |
1515 | ||
b976bcf2 | 1516 | limit = pvt->info.rir_limit(reg); |
8c009100 | 1517 | gb = div_u64_rem(limit >> 20, 1024, &mb); |
956b9ba1 JP |
1518 | edac_dbg(0, "RIR#%d, limit: %u.%03u GB (0x%016Lx), way: %d\n", |
1519 | n_rir, | |
8c009100 | 1520 | gb, (mb*1000)/1024, |
956b9ba1 JP |
1521 | limit, |
1522 | 1 << RIR_WAY(reg)); | |
eebf11a0 MCC |
1523 | if (ch_addr <= limit) |
1524 | break; | |
1525 | } | |
1526 | if (n_rir == MAX_RIR_RANGES) { | |
1527 | sprintf(msg, "Can't discover the memory rank for ch addr 0x%08Lx", | |
1528 | ch_addr); | |
eebf11a0 MCC |
1529 | return -EINVAL; |
1530 | } | |
1531 | rir_way = RIR_WAY(reg); | |
50d1bb93 | 1532 | |
eebf11a0 MCC |
1533 | if (pvt->is_close_pg) |
1534 | idx = (ch_addr >> 6); | |
1535 | else | |
1536 | idx = (ch_addr >> 13); /* FIXME: Datasheet says to shift by 15 */ | |
1537 | idx %= 1 << rir_way; | |
1538 | ||
7d375bff | 1539 | pci_read_config_dword(pvt->pci_tad[ch_add + base_ch], |
eebf11a0 MCC |
1540 | rir_offset[n_rir][idx], |
1541 | ®); | |
1542 | *rank = RIR_RNK_TGT(reg); | |
1543 | ||
956b9ba1 JP |
1544 | edac_dbg(0, "RIR#%d: channel address 0x%08Lx < 0x%08Lx, RIR interleave %d, index %d\n", |
1545 | n_rir, | |
1546 | ch_addr, | |
1547 | limit, | |
1548 | rir_way, | |
1549 | idx); | |
eebf11a0 MCC |
1550 | |
1551 | return 0; | |
1552 | } | |
1553 | ||
1554 | /**************************************************************************** | |
1555 | Device initialization routines: put/get, init/exit | |
1556 | ****************************************************************************/ | |
1557 | ||
1558 | /* | |
1559 | * sbridge_put_all_devices 'put' all the devices that we have | |
1560 | * reserved via 'get' | |
1561 | */ | |
1562 | static void sbridge_put_devices(struct sbridge_dev *sbridge_dev) | |
1563 | { | |
1564 | int i; | |
1565 | ||
956b9ba1 | 1566 | edac_dbg(0, "\n"); |
eebf11a0 MCC |
1567 | for (i = 0; i < sbridge_dev->n_devs; i++) { |
1568 | struct pci_dev *pdev = sbridge_dev->pdev[i]; | |
1569 | if (!pdev) | |
1570 | continue; | |
956b9ba1 JP |
1571 | edac_dbg(0, "Removing dev %02x:%02x.%d\n", |
1572 | pdev->bus->number, | |
1573 | PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn)); | |
eebf11a0 MCC |
1574 | pci_dev_put(pdev); |
1575 | } | |
1576 | } | |
1577 | ||
1578 | static void sbridge_put_all_devices(void) | |
1579 | { | |
1580 | struct sbridge_dev *sbridge_dev, *tmp; | |
1581 | ||
1582 | list_for_each_entry_safe(sbridge_dev, tmp, &sbridge_edac_list, list) { | |
1583 | sbridge_put_devices(sbridge_dev); | |
1584 | free_sbridge_dev(sbridge_dev); | |
1585 | } | |
1586 | } | |
1587 | ||
eebf11a0 MCC |
1588 | static int sbridge_get_onedevice(struct pci_dev **prev, |
1589 | u8 *num_mc, | |
1590 | const struct pci_id_table *table, | |
1591 | const unsigned devno) | |
1592 | { | |
1593 | struct sbridge_dev *sbridge_dev; | |
1594 | const struct pci_id_descr *dev_descr = &table->descr[devno]; | |
eebf11a0 MCC |
1595 | struct pci_dev *pdev = NULL; |
1596 | u8 bus = 0; | |
1597 | ||
ec5a0b38 | 1598 | sbridge_printk(KERN_DEBUG, |
dbc954dd | 1599 | "Seeking for: PCI ID %04x:%04x\n", |
eebf11a0 MCC |
1600 | PCI_VENDOR_ID_INTEL, dev_descr->dev_id); |
1601 | ||
1602 | pdev = pci_get_device(PCI_VENDOR_ID_INTEL, | |
1603 | dev_descr->dev_id, *prev); | |
1604 | ||
1605 | if (!pdev) { | |
1606 | if (*prev) { | |
1607 | *prev = pdev; | |
1608 | return 0; | |
1609 | } | |
1610 | ||
1611 | if (dev_descr->optional) | |
1612 | return 0; | |
1613 | ||
dbc954dd | 1614 | /* if the HA wasn't found */ |
eebf11a0 MCC |
1615 | if (devno == 0) |
1616 | return -ENODEV; | |
1617 | ||
1618 | sbridge_printk(KERN_INFO, | |
dbc954dd | 1619 | "Device not found: %04x:%04x\n", |
eebf11a0 MCC |
1620 | PCI_VENDOR_ID_INTEL, dev_descr->dev_id); |
1621 | ||
1622 | /* End of list, leave */ | |
1623 | return -ENODEV; | |
1624 | } | |
1625 | bus = pdev->bus->number; | |
1626 | ||
1627 | sbridge_dev = get_sbridge_dev(bus); | |
1628 | if (!sbridge_dev) { | |
1629 | sbridge_dev = alloc_sbridge_dev(bus, table); | |
1630 | if (!sbridge_dev) { | |
1631 | pci_dev_put(pdev); | |
1632 | return -ENOMEM; | |
1633 | } | |
1634 | (*num_mc)++; | |
1635 | } | |
1636 | ||
1637 | if (sbridge_dev->pdev[devno]) { | |
1638 | sbridge_printk(KERN_ERR, | |
dbc954dd | 1639 | "Duplicated device for %04x:%04x\n", |
eebf11a0 MCC |
1640 | PCI_VENDOR_ID_INTEL, dev_descr->dev_id); |
1641 | pci_dev_put(pdev); | |
1642 | return -ENODEV; | |
1643 | } | |
1644 | ||
1645 | sbridge_dev->pdev[devno] = pdev; | |
1646 | ||
eebf11a0 MCC |
1647 | /* Be sure that the device is enabled */ |
1648 | if (unlikely(pci_enable_device(pdev) < 0)) { | |
1649 | sbridge_printk(KERN_ERR, | |
dbc954dd | 1650 | "Couldn't enable %04x:%04x\n", |
eebf11a0 MCC |
1651 | PCI_VENDOR_ID_INTEL, dev_descr->dev_id); |
1652 | return -ENODEV; | |
1653 | } | |
1654 | ||
dbc954dd | 1655 | edac_dbg(0, "Detected %04x:%04x\n", |
956b9ba1 | 1656 | PCI_VENDOR_ID_INTEL, dev_descr->dev_id); |
eebf11a0 MCC |
1657 | |
1658 | /* | |
1659 | * As stated on drivers/pci/search.c, the reference count for | |
1660 | * @from is always decremented if it is not %NULL. So, as we need | |
1661 | * to get all devices up to null, we need to do a get for the device | |
1662 | */ | |
1663 | pci_dev_get(pdev); | |
1664 | ||
1665 | *prev = pdev; | |
1666 | ||
1667 | return 0; | |
1668 | } | |
1669 | ||
5153a0f9 AR |
1670 | /* |
1671 | * sbridge_get_all_devices - Find and perform 'get' operation on the MCH's | |
dbc954dd | 1672 | * devices we want to reference for this driver. |
5153a0f9 | 1673 | * @num_mc: pointer to the memory controllers count, to be incremented in case |
c41afdca | 1674 | * of success. |
5153a0f9 AR |
1675 | * @table: model specific table |
1676 | * | |
1677 | * returns 0 in case of success or error code | |
1678 | */ | |
1679 | static int sbridge_get_all_devices(u8 *num_mc, | |
1680 | const struct pci_id_table *table) | |
eebf11a0 MCC |
1681 | { |
1682 | int i, rc; | |
1683 | struct pci_dev *pdev = NULL; | |
eebf11a0 MCC |
1684 | |
1685 | while (table && table->descr) { | |
1686 | for (i = 0; i < table->n_devs; i++) { | |
1687 | pdev = NULL; | |
1688 | do { | |
1689 | rc = sbridge_get_onedevice(&pdev, num_mc, | |
1690 | table, i); | |
1691 | if (rc < 0) { | |
1692 | if (i == 0) { | |
1693 | i = table->n_devs; | |
1694 | break; | |
1695 | } | |
1696 | sbridge_put_all_devices(); | |
1697 | return -ENODEV; | |
1698 | } | |
1699 | } while (pdev); | |
1700 | } | |
1701 | table++; | |
1702 | } | |
1703 | ||
1704 | return 0; | |
1705 | } | |
1706 | ||
ea779b5a AR |
1707 | static int sbridge_mci_bind_devs(struct mem_ctl_info *mci, |
1708 | struct sbridge_dev *sbridge_dev) | |
eebf11a0 MCC |
1709 | { |
1710 | struct sbridge_pvt *pvt = mci->pvt_info; | |
1711 | struct pci_dev *pdev; | |
2900ea60 | 1712 | u8 saw_chan_mask = 0; |
dbc954dd | 1713 | int i; |
eebf11a0 MCC |
1714 | |
1715 | for (i = 0; i < sbridge_dev->n_devs; i++) { | |
1716 | pdev = sbridge_dev->pdev[i]; | |
1717 | if (!pdev) | |
1718 | continue; | |
dbc954dd AR |
1719 | |
1720 | switch (pdev->device) { | |
1721 | case PCI_DEVICE_ID_INTEL_SBRIDGE_SAD0: | |
1722 | pvt->pci_sad0 = pdev; | |
eebf11a0 | 1723 | break; |
dbc954dd AR |
1724 | case PCI_DEVICE_ID_INTEL_SBRIDGE_SAD1: |
1725 | pvt->pci_sad1 = pdev; | |
eebf11a0 | 1726 | break; |
dbc954dd AR |
1727 | case PCI_DEVICE_ID_INTEL_SBRIDGE_BR: |
1728 | pvt->pci_br0 = pdev; | |
eebf11a0 | 1729 | break; |
dbc954dd AR |
1730 | case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0: |
1731 | pvt->pci_ha0 = pdev; | |
eebf11a0 | 1732 | break; |
dbc954dd AR |
1733 | case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA: |
1734 | pvt->pci_ta = pdev; | |
1735 | break; | |
1736 | case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_RAS: | |
1737 | pvt->pci_ras = pdev; | |
1738 | break; | |
1739 | case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0: | |
1740 | case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD1: | |
1741 | case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD2: | |
1742 | case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD3: | |
1743 | { | |
1744 | int id = pdev->device - PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0; | |
1745 | pvt->pci_tad[id] = pdev; | |
2900ea60 | 1746 | saw_chan_mask |= 1 << id; |
dbc954dd AR |
1747 | } |
1748 | break; | |
1749 | case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_DDRIO: | |
1750 | pvt->pci_ddrio = pdev; | |
eebf11a0 MCC |
1751 | break; |
1752 | default: | |
1753 | goto error; | |
1754 | } | |
1755 | ||
dbc954dd AR |
1756 | edac_dbg(0, "Associated PCI %02x:%02x, bus %d with dev = %p\n", |
1757 | pdev->vendor, pdev->device, | |
956b9ba1 | 1758 | sbridge_dev->bus, |
956b9ba1 | 1759 | pdev); |
eebf11a0 MCC |
1760 | } |
1761 | ||
1762 | /* Check if everything were registered */ | |
1763 | if (!pvt->pci_sad0 || !pvt->pci_sad1 || !pvt->pci_ha0 || | |
de4772c6 | 1764 | !pvt-> pci_tad || !pvt->pci_ras || !pvt->pci_ta) |
eebf11a0 MCC |
1765 | goto enodev; |
1766 | ||
2900ea60 SJ |
1767 | if (saw_chan_mask != 0x0f) |
1768 | goto enodev; | |
eebf11a0 MCC |
1769 | return 0; |
1770 | ||
1771 | enodev: | |
1772 | sbridge_printk(KERN_ERR, "Some needed devices are missing\n"); | |
1773 | return -ENODEV; | |
1774 | ||
1775 | error: | |
dbc954dd AR |
1776 | sbridge_printk(KERN_ERR, "Unexpected device %02x:%02x\n", |
1777 | PCI_VENDOR_ID_INTEL, pdev->device); | |
eebf11a0 MCC |
1778 | return -EINVAL; |
1779 | } | |
1780 | ||
4d715a80 AR |
1781 | static int ibridge_mci_bind_devs(struct mem_ctl_info *mci, |
1782 | struct sbridge_dev *sbridge_dev) | |
1783 | { | |
1784 | struct sbridge_pvt *pvt = mci->pvt_info; | |
7d375bff TL |
1785 | struct pci_dev *pdev; |
1786 | u8 saw_chan_mask = 0; | |
dbc954dd | 1787 | int i; |
4d715a80 AR |
1788 | |
1789 | for (i = 0; i < sbridge_dev->n_devs; i++) { | |
1790 | pdev = sbridge_dev->pdev[i]; | |
1791 | if (!pdev) | |
1792 | continue; | |
4d715a80 | 1793 | |
dbc954dd AR |
1794 | switch (pdev->device) { |
1795 | case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0: | |
1796 | pvt->pci_ha0 = pdev; | |
1797 | break; | |
1798 | case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA: | |
1799 | pvt->pci_ta = pdev; | |
1800 | case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_RAS: | |
1801 | pvt->pci_ras = pdev; | |
1802 | break; | |
dbc954dd AR |
1803 | case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0: |
1804 | case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD1: | |
7d375bff TL |
1805 | case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD2: |
1806 | case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD3: | |
dbc954dd AR |
1807 | { |
1808 | int id = pdev->device - PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0; | |
1809 | pvt->pci_tad[id] = pdev; | |
7d375bff | 1810 | saw_chan_mask |= 1 << id; |
dbc954dd | 1811 | } |
4d715a80 | 1812 | break; |
dbc954dd AR |
1813 | case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_2HA_DDRIO0: |
1814 | pvt->pci_ddrio = pdev; | |
1815 | break; | |
1816 | case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_1HA_DDRIO0: | |
7d375bff | 1817 | pvt->pci_ddrio = pdev; |
4d715a80 | 1818 | break; |
dbc954dd AR |
1819 | case PCI_DEVICE_ID_INTEL_IBRIDGE_SAD: |
1820 | pvt->pci_sad0 = pdev; | |
1821 | break; | |
1822 | case PCI_DEVICE_ID_INTEL_IBRIDGE_BR0: | |
1823 | pvt->pci_br0 = pdev; | |
1824 | break; | |
1825 | case PCI_DEVICE_ID_INTEL_IBRIDGE_BR1: | |
1826 | pvt->pci_br1 = pdev; | |
1827 | break; | |
1828 | case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1: | |
1829 | pvt->pci_ha1 = pdev; | |
1830 | break; | |
1831 | case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0: | |
1832 | case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD1: | |
7d375bff TL |
1833 | case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD2: |
1834 | case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD3: | |
dbc954dd | 1835 | { |
7d375bff | 1836 | int id = pdev->device - PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0 + 4; |
dbc954dd | 1837 | pvt->pci_tad[id] = pdev; |
7d375bff | 1838 | saw_chan_mask |= 1 << id; |
dbc954dd AR |
1839 | } |
1840 | break; | |
4d715a80 AR |
1841 | default: |
1842 | goto error; | |
1843 | } | |
1844 | ||
1845 | edac_dbg(0, "Associated PCI %02x.%02d.%d with dev = %p\n", | |
1846 | sbridge_dev->bus, | |
1847 | PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), | |
1848 | pdev); | |
1849 | } | |
1850 | ||
1851 | /* Check if everything were registered */ | |
1852 | if (!pvt->pci_sad0 || !pvt->pci_ha0 || !pvt->pci_br0 || | |
1853 | !pvt->pci_br1 || !pvt->pci_tad || !pvt->pci_ras || | |
1854 | !pvt->pci_ta) | |
1855 | goto enodev; | |
1856 | ||
7d375bff TL |
1857 | if (saw_chan_mask != 0x0f && /* -EN */ |
1858 | saw_chan_mask != 0x33 && /* -EP */ | |
1859 | saw_chan_mask != 0xff) /* -EX */ | |
1860 | goto enodev; | |
4d715a80 AR |
1861 | return 0; |
1862 | ||
1863 | enodev: | |
1864 | sbridge_printk(KERN_ERR, "Some needed devices are missing\n"); | |
1865 | return -ENODEV; | |
1866 | ||
1867 | error: | |
1868 | sbridge_printk(KERN_ERR, | |
dbc954dd AR |
1869 | "Unexpected device %02x:%02x\n", PCI_VENDOR_ID_INTEL, |
1870 | pdev->device); | |
4d715a80 AR |
1871 | return -EINVAL; |
1872 | } | |
1873 | ||
50d1bb93 AR |
1874 | static int haswell_mci_bind_devs(struct mem_ctl_info *mci, |
1875 | struct sbridge_dev *sbridge_dev) | |
1876 | { | |
1877 | struct sbridge_pvt *pvt = mci->pvt_info; | |
7d375bff TL |
1878 | struct pci_dev *pdev; |
1879 | u8 saw_chan_mask = 0; | |
50d1bb93 | 1880 | int i; |
50d1bb93 AR |
1881 | |
1882 | /* there's only one device per system; not tied to any bus */ | |
1883 | if (pvt->info.pci_vtd == NULL) | |
1884 | /* result will be checked later */ | |
1885 | pvt->info.pci_vtd = pci_get_device(PCI_VENDOR_ID_INTEL, | |
1886 | PCI_DEVICE_ID_INTEL_HASWELL_IMC_VTD_MISC, | |
1887 | NULL); | |
1888 | ||
1889 | for (i = 0; i < sbridge_dev->n_devs; i++) { | |
1890 | pdev = sbridge_dev->pdev[i]; | |
1891 | if (!pdev) | |
1892 | continue; | |
1893 | ||
1894 | switch (pdev->device) { | |
1895 | case PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD0: | |
1896 | pvt->pci_sad0 = pdev; | |
1897 | break; | |
1898 | case PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD1: | |
1899 | pvt->pci_sad1 = pdev; | |
1900 | break; | |
1901 | case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0: | |
1902 | pvt->pci_ha0 = pdev; | |
1903 | break; | |
1904 | case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA: | |
1905 | pvt->pci_ta = pdev; | |
1906 | break; | |
1907 | case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_THERMAL: | |
1908 | pvt->pci_ras = pdev; | |
1909 | break; | |
1910 | case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD0: | |
50d1bb93 | 1911 | case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD1: |
50d1bb93 | 1912 | case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD2: |
50d1bb93 | 1913 | case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD3: |
7d375bff TL |
1914 | { |
1915 | int id = pdev->device - PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD0; | |
1916 | ||
1917 | pvt->pci_tad[id] = pdev; | |
1918 | saw_chan_mask |= 1 << id; | |
1919 | } | |
1920 | break; | |
1921 | case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD0: | |
1922 | case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD1: | |
1923 | case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD2: | |
1924 | case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD3: | |
1925 | { | |
1926 | int id = pdev->device - PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD0 + 4; | |
1927 | ||
1928 | pvt->pci_tad[id] = pdev; | |
1929 | saw_chan_mask |= 1 << id; | |
1930 | } | |
50d1bb93 AR |
1931 | break; |
1932 | case PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO0: | |
7179385a AR |
1933 | case PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO1: |
1934 | case PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO2: | |
1935 | case PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO3: | |
1936 | if (!pvt->pci_ddrio) | |
1937 | pvt->pci_ddrio = pdev; | |
50d1bb93 AR |
1938 | break; |
1939 | case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1: | |
1940 | pvt->pci_ha1 = pdev; | |
1941 | break; | |
1942 | case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TA: | |
1943 | pvt->pci_ha1_ta = pdev; | |
1944 | break; | |
50d1bb93 AR |
1945 | default: |
1946 | break; | |
1947 | } | |
1948 | ||
1949 | edac_dbg(0, "Associated PCI %02x.%02d.%d with dev = %p\n", | |
1950 | sbridge_dev->bus, | |
1951 | PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), | |
1952 | pdev); | |
1953 | } | |
1954 | ||
1955 | /* Check if everything were registered */ | |
1956 | if (!pvt->pci_sad0 || !pvt->pci_ha0 || !pvt->pci_sad1 || | |
1957 | !pvt->pci_ras || !pvt->pci_ta || !pvt->info.pci_vtd) | |
1958 | goto enodev; | |
1959 | ||
7d375bff TL |
1960 | if (saw_chan_mask != 0x0f && /* -EN */ |
1961 | saw_chan_mask != 0x33 && /* -EP */ | |
1962 | saw_chan_mask != 0xff) /* -EX */ | |
1963 | goto enodev; | |
50d1bb93 AR |
1964 | return 0; |
1965 | ||
1966 | enodev: | |
1967 | sbridge_printk(KERN_ERR, "Some needed devices are missing\n"); | |
1968 | return -ENODEV; | |
1969 | } | |
1970 | ||
1f39581a TL |
1971 | static int broadwell_mci_bind_devs(struct mem_ctl_info *mci, |
1972 | struct sbridge_dev *sbridge_dev) | |
1973 | { | |
1974 | struct sbridge_pvt *pvt = mci->pvt_info; | |
1975 | struct pci_dev *pdev; | |
fa2ce64f | 1976 | u8 saw_chan_mask = 0; |
1f39581a TL |
1977 | int i; |
1978 | ||
1979 | /* there's only one device per system; not tied to any bus */ | |
1980 | if (pvt->info.pci_vtd == NULL) | |
1981 | /* result will be checked later */ | |
1982 | pvt->info.pci_vtd = pci_get_device(PCI_VENDOR_ID_INTEL, | |
1983 | PCI_DEVICE_ID_INTEL_BROADWELL_IMC_VTD_MISC, | |
1984 | NULL); | |
1985 | ||
1986 | for (i = 0; i < sbridge_dev->n_devs; i++) { | |
1987 | pdev = sbridge_dev->pdev[i]; | |
1988 | if (!pdev) | |
1989 | continue; | |
1990 | ||
1991 | switch (pdev->device) { | |
1992 | case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD0: | |
1993 | pvt->pci_sad0 = pdev; | |
1994 | break; | |
1995 | case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD1: | |
1996 | pvt->pci_sad1 = pdev; | |
1997 | break; | |
1998 | case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0: | |
1999 | pvt->pci_ha0 = pdev; | |
2000 | break; | |
2001 | case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TA: | |
2002 | pvt->pci_ta = pdev; | |
2003 | break; | |
2004 | case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_THERMAL: | |
2005 | pvt->pci_ras = pdev; | |
2006 | break; | |
2007 | case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD0: | |
1f39581a | 2008 | case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD1: |
1f39581a | 2009 | case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD2: |
1f39581a | 2010 | case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD3: |
fa2ce64f TL |
2011 | { |
2012 | int id = pdev->device - PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD0; | |
2013 | pvt->pci_tad[id] = pdev; | |
2014 | saw_chan_mask |= 1 << id; | |
2015 | } | |
2016 | break; | |
2017 | case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD0: | |
2018 | case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD1: | |
2019 | case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD2: | |
2020 | case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD3: | |
2021 | { | |
2022 | int id = pdev->device - PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD0 + 4; | |
2023 | pvt->pci_tad[id] = pdev; | |
2024 | saw_chan_mask |= 1 << id; | |
2025 | } | |
1f39581a TL |
2026 | break; |
2027 | case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_DDRIO0: | |
2028 | pvt->pci_ddrio = pdev; | |
2029 | break; | |
fa2ce64f TL |
2030 | case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1: |
2031 | pvt->pci_ha1 = pdev; | |
2032 | break; | |
2033 | case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TA: | |
2034 | pvt->pci_ha1_ta = pdev; | |
2035 | break; | |
1f39581a TL |
2036 | default: |
2037 | break; | |
2038 | } | |
2039 | ||
2040 | edac_dbg(0, "Associated PCI %02x.%02d.%d with dev = %p\n", | |
2041 | sbridge_dev->bus, | |
2042 | PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), | |
2043 | pdev); | |
2044 | } | |
2045 | ||
2046 | /* Check if everything were registered */ | |
2047 | if (!pvt->pci_sad0 || !pvt->pci_ha0 || !pvt->pci_sad1 || | |
2048 | !pvt->pci_ras || !pvt->pci_ta || !pvt->info.pci_vtd) | |
2049 | goto enodev; | |
2050 | ||
fa2ce64f TL |
2051 | if (saw_chan_mask != 0x0f && /* -EN */ |
2052 | saw_chan_mask != 0x33 && /* -EP */ | |
2053 | saw_chan_mask != 0xff) /* -EX */ | |
2054 | goto enodev; | |
1f39581a TL |
2055 | return 0; |
2056 | ||
2057 | enodev: | |
2058 | sbridge_printk(KERN_ERR, "Some needed devices are missing\n"); | |
2059 | return -ENODEV; | |
2060 | } | |
2061 | ||
eebf11a0 MCC |
2062 | /**************************************************************************** |
2063 | Error check routines | |
2064 | ****************************************************************************/ | |
2065 | ||
2066 | /* | |
2067 | * While Sandy Bridge has error count registers, SMI BIOS read values from | |
2068 | * and resets the counters. So, they are not reliable for the OS to read | |
2069 | * from them. So, we have no option but to just trust on whatever MCE is | |
2070 | * telling us about the errors. | |
2071 | */ | |
2072 | static void sbridge_mce_output_error(struct mem_ctl_info *mci, | |
2073 | const struct mce *m) | |
2074 | { | |
2075 | struct mem_ctl_info *new_mci; | |
2076 | struct sbridge_pvt *pvt = mci->pvt_info; | |
c36e3e77 | 2077 | enum hw_event_mc_err_type tp_event; |
e17a2f42 | 2078 | char *type, *optype, msg[256]; |
eebf11a0 MCC |
2079 | bool ripv = GET_BITFIELD(m->mcgstatus, 0, 0); |
2080 | bool overflow = GET_BITFIELD(m->status, 62, 62); | |
2081 | bool uncorrected_error = GET_BITFIELD(m->status, 61, 61); | |
4d715a80 | 2082 | bool recoverable; |
eebf11a0 MCC |
2083 | u32 core_err_cnt = GET_BITFIELD(m->status, 38, 52); |
2084 | u32 mscod = GET_BITFIELD(m->status, 16, 31); | |
2085 | u32 errcode = GET_BITFIELD(m->status, 0, 15); | |
2086 | u32 channel = GET_BITFIELD(m->status, 0, 3); | |
2087 | u32 optypenum = GET_BITFIELD(m->status, 4, 6); | |
2088 | long channel_mask, first_channel; | |
7d375bff | 2089 | u8 rank, socket, ha; |
c36e3e77 | 2090 | int rc, dimm; |
e17a2f42 | 2091 | char *area_type = NULL; |
eebf11a0 | 2092 | |
fa2ce64f | 2093 | if (pvt->info.type != SANDY_BRIDGE) |
4d715a80 AR |
2094 | recoverable = true; |
2095 | else | |
2096 | recoverable = GET_BITFIELD(m->status, 56, 56); | |
2097 | ||
c36e3e77 MCC |
2098 | if (uncorrected_error) { |
2099 | if (ripv) { | |
2100 | type = "FATAL"; | |
2101 | tp_event = HW_EVENT_ERR_FATAL; | |
2102 | } else { | |
2103 | type = "NON_FATAL"; | |
2104 | tp_event = HW_EVENT_ERR_UNCORRECTED; | |
2105 | } | |
2106 | } else { | |
2107 | type = "CORRECTED"; | |
2108 | tp_event = HW_EVENT_ERR_CORRECTED; | |
2109 | } | |
eebf11a0 MCC |
2110 | |
2111 | /* | |
15ed103a | 2112 | * According with Table 15-9 of the Intel Architecture spec vol 3A, |
eebf11a0 MCC |
2113 | * memory errors should fit in this mask: |
2114 | * 000f 0000 1mmm cccc (binary) | |
2115 | * where: | |
2116 | * f = Correction Report Filtering Bit. If 1, subsequent errors | |
2117 | * won't be shown | |
2118 | * mmm = error type | |
2119 | * cccc = channel | |
2120 | * If the mask doesn't match, report an error to the parsing logic | |
2121 | */ | |
2122 | if (! ((errcode & 0xef80) == 0x80)) { | |
2123 | optype = "Can't parse: it is not a mem"; | |
2124 | } else { | |
2125 | switch (optypenum) { | |
2126 | case 0: | |
c36e3e77 | 2127 | optype = "generic undef request error"; |
eebf11a0 MCC |
2128 | break; |
2129 | case 1: | |
c36e3e77 | 2130 | optype = "memory read error"; |
eebf11a0 MCC |
2131 | break; |
2132 | case 2: | |
c36e3e77 | 2133 | optype = "memory write error"; |
eebf11a0 MCC |
2134 | break; |
2135 | case 3: | |
c36e3e77 | 2136 | optype = "addr/cmd error"; |
eebf11a0 MCC |
2137 | break; |
2138 | case 4: | |
c36e3e77 | 2139 | optype = "memory scrubbing error"; |
eebf11a0 MCC |
2140 | break; |
2141 | default: | |
2142 | optype = "reserved"; | |
2143 | break; | |
2144 | } | |
2145 | } | |
2146 | ||
be3036d2 AR |
2147 | /* Only decode errors with an valid address (ADDRV) */ |
2148 | if (!GET_BITFIELD(m->status, 58, 58)) | |
2149 | return; | |
2150 | ||
7d375bff | 2151 | rc = get_memory_error_data(mci, m->addr, &socket, &ha, |
e17a2f42 | 2152 | &channel_mask, &rank, &area_type, msg); |
eebf11a0 | 2153 | if (rc < 0) |
c36e3e77 | 2154 | goto err_parsing; |
eebf11a0 MCC |
2155 | new_mci = get_mci_for_node_id(socket); |
2156 | if (!new_mci) { | |
c36e3e77 MCC |
2157 | strcpy(msg, "Error: socket got corrupted!"); |
2158 | goto err_parsing; | |
eebf11a0 MCC |
2159 | } |
2160 | mci = new_mci; | |
2161 | pvt = mci->pvt_info; | |
2162 | ||
2163 | first_channel = find_first_bit(&channel_mask, NUM_CHANNELS); | |
2164 | ||
2165 | if (rank < 4) | |
2166 | dimm = 0; | |
2167 | else if (rank < 8) | |
2168 | dimm = 1; | |
2169 | else | |
2170 | dimm = 2; | |
2171 | ||
eebf11a0 MCC |
2172 | |
2173 | /* | |
e17a2f42 MCC |
2174 | * FIXME: On some memory configurations (mirror, lockstep), the |
2175 | * Memory Controller can't point the error to a single DIMM. The | |
2176 | * EDAC core should be handling the channel mask, in order to point | |
2177 | * to the group of dimm's where the error may be happening. | |
eebf11a0 | 2178 | */ |
d7c660b7 AR |
2179 | if (!pvt->is_lockstep && !pvt->is_mirrored && !pvt->is_close_pg) |
2180 | channel = first_channel; | |
2181 | ||
c36e3e77 | 2182 | snprintf(msg, sizeof(msg), |
7d375bff | 2183 | "%s%s area:%s err_code:%04x:%04x socket:%d ha:%d channel_mask:%ld rank:%d", |
e17a2f42 MCC |
2184 | overflow ? " OVERFLOW" : "", |
2185 | (uncorrected_error && recoverable) ? " recoverable" : "", | |
2186 | area_type, | |
2187 | mscod, errcode, | |
7d375bff | 2188 | socket, ha, |
e17a2f42 MCC |
2189 | channel_mask, |
2190 | rank); | |
eebf11a0 | 2191 | |
956b9ba1 | 2192 | edac_dbg(0, "%s\n", msg); |
eebf11a0 | 2193 | |
c36e3e77 MCC |
2194 | /* FIXME: need support for channel mask */ |
2195 | ||
351fc4a9 SJ |
2196 | if (channel == CHANNEL_UNSPECIFIED) |
2197 | channel = -1; | |
2198 | ||
eebf11a0 | 2199 | /* Call the helper to output message */ |
c1053839 | 2200 | edac_mc_handle_error(tp_event, mci, core_err_cnt, |
c36e3e77 | 2201 | m->addr >> PAGE_SHIFT, m->addr & ~PAGE_MASK, 0, |
7d375bff | 2202 | 4*ha+channel, dimm, -1, |
03f7eae8 | 2203 | optype, msg); |
c36e3e77 MCC |
2204 | return; |
2205 | err_parsing: | |
c1053839 | 2206 | edac_mc_handle_error(tp_event, mci, core_err_cnt, 0, 0, 0, |
c36e3e77 | 2207 | -1, -1, -1, |
03f7eae8 | 2208 | msg, ""); |
eebf11a0 | 2209 | |
eebf11a0 MCC |
2210 | } |
2211 | ||
2212 | /* | |
2213 | * sbridge_check_error Retrieve and process errors reported by the | |
2214 | * hardware. Called by the Core module. | |
2215 | */ | |
2216 | static void sbridge_check_error(struct mem_ctl_info *mci) | |
2217 | { | |
2218 | struct sbridge_pvt *pvt = mci->pvt_info; | |
2219 | int i; | |
2220 | unsigned count = 0; | |
2221 | struct mce *m; | |
2222 | ||
2223 | /* | |
2224 | * MCE first step: Copy all mce errors into a temporary buffer | |
2225 | * We use a double buffering here, to reduce the risk of | |
2226 | * loosing an error. | |
2227 | */ | |
2228 | smp_rmb(); | |
2229 | count = (pvt->mce_out + MCE_LOG_LEN - pvt->mce_in) | |
2230 | % MCE_LOG_LEN; | |
2231 | if (!count) | |
2232 | return; | |
2233 | ||
2234 | m = pvt->mce_outentry; | |
2235 | if (pvt->mce_in + count > MCE_LOG_LEN) { | |
2236 | unsigned l = MCE_LOG_LEN - pvt->mce_in; | |
2237 | ||
2238 | memcpy(m, &pvt->mce_entry[pvt->mce_in], sizeof(*m) * l); | |
2239 | smp_wmb(); | |
2240 | pvt->mce_in = 0; | |
2241 | count -= l; | |
2242 | m += l; | |
2243 | } | |
2244 | memcpy(m, &pvt->mce_entry[pvt->mce_in], sizeof(*m) * count); | |
2245 | smp_wmb(); | |
2246 | pvt->mce_in += count; | |
2247 | ||
2248 | smp_rmb(); | |
2249 | if (pvt->mce_overrun) { | |
2250 | sbridge_printk(KERN_ERR, "Lost %d memory errors\n", | |
2251 | pvt->mce_overrun); | |
2252 | smp_wmb(); | |
2253 | pvt->mce_overrun = 0; | |
2254 | } | |
2255 | ||
2256 | /* | |
2257 | * MCE second step: parse errors and display | |
2258 | */ | |
2259 | for (i = 0; i < count; i++) | |
2260 | sbridge_mce_output_error(mci, &pvt->mce_outentry[i]); | |
2261 | } | |
2262 | ||
2263 | /* | |
2264 | * sbridge_mce_check_error Replicates mcelog routine to get errors | |
2265 | * This routine simply queues mcelog errors, and | |
2266 | * return. The error itself should be handled later | |
2267 | * by sbridge_check_error. | |
2268 | * WARNING: As this routine should be called at NMI time, extra care should | |
2269 | * be taken to avoid deadlocks, and to be as fast as possible. | |
2270 | */ | |
3d78c9af MCC |
2271 | static int sbridge_mce_check_error(struct notifier_block *nb, unsigned long val, |
2272 | void *data) | |
eebf11a0 | 2273 | { |
3d78c9af MCC |
2274 | struct mce *mce = (struct mce *)data; |
2275 | struct mem_ctl_info *mci; | |
2276 | struct sbridge_pvt *pvt; | |
cf40f80c | 2277 | char *type; |
3d78c9af | 2278 | |
fd521039 CG |
2279 | if (get_edac_report_status() == EDAC_REPORTING_DISABLED) |
2280 | return NOTIFY_DONE; | |
2281 | ||
3d78c9af MCC |
2282 | mci = get_mci_for_node_id(mce->socketid); |
2283 | if (!mci) | |
2284 | return NOTIFY_BAD; | |
2285 | pvt = mci->pvt_info; | |
eebf11a0 MCC |
2286 | |
2287 | /* | |
2288 | * Just let mcelog handle it if the error is | |
2289 | * outside the memory controller. A memory error | |
2290 | * is indicated by bit 7 = 1 and bits = 8-11,13-15 = 0. | |
2291 | * bit 12 has an special meaning. | |
2292 | */ | |
2293 | if ((mce->status & 0xefff) >> 7 != 1) | |
3d78c9af | 2294 | return NOTIFY_DONE; |
eebf11a0 | 2295 | |
cf40f80c AR |
2296 | if (mce->mcgstatus & MCG_STATUS_MCIP) |
2297 | type = "Exception"; | |
2298 | else | |
2299 | type = "Event"; | |
2300 | ||
49856dc9 | 2301 | sbridge_mc_printk(mci, KERN_DEBUG, "HANDLING MCE MEMORY ERROR\n"); |
eebf11a0 | 2302 | |
49856dc9 AR |
2303 | sbridge_mc_printk(mci, KERN_DEBUG, "CPU %d: Machine Check %s: %Lx " |
2304 | "Bank %d: %016Lx\n", mce->extcpu, type, | |
2305 | mce->mcgstatus, mce->bank, mce->status); | |
2306 | sbridge_mc_printk(mci, KERN_DEBUG, "TSC %llx ", mce->tsc); | |
2307 | sbridge_mc_printk(mci, KERN_DEBUG, "ADDR %llx ", mce->addr); | |
2308 | sbridge_mc_printk(mci, KERN_DEBUG, "MISC %llx ", mce->misc); | |
eebf11a0 | 2309 | |
49856dc9 AR |
2310 | sbridge_mc_printk(mci, KERN_DEBUG, "PROCESSOR %u:%x TIME %llu SOCKET " |
2311 | "%u APIC %x\n", mce->cpuvendor, mce->cpuid, | |
2312 | mce->time, mce->socketid, mce->apicid); | |
eebf11a0 | 2313 | |
eebf11a0 MCC |
2314 | smp_rmb(); |
2315 | if ((pvt->mce_out + 1) % MCE_LOG_LEN == pvt->mce_in) { | |
2316 | smp_wmb(); | |
2317 | pvt->mce_overrun++; | |
3d78c9af | 2318 | return NOTIFY_DONE; |
eebf11a0 MCC |
2319 | } |
2320 | ||
2321 | /* Copy memory error at the ringbuffer */ | |
2322 | memcpy(&pvt->mce_entry[pvt->mce_out], mce, sizeof(*mce)); | |
2323 | smp_wmb(); | |
2324 | pvt->mce_out = (pvt->mce_out + 1) % MCE_LOG_LEN; | |
2325 | ||
2326 | /* Handle fatal errors immediately */ | |
2327 | if (mce->mcgstatus & 1) | |
2328 | sbridge_check_error(mci); | |
2329 | ||
2330 | /* Advice mcelog that the error were handled */ | |
3d78c9af | 2331 | return NOTIFY_STOP; |
eebf11a0 MCC |
2332 | } |
2333 | ||
3d78c9af MCC |
2334 | static struct notifier_block sbridge_mce_dec = { |
2335 | .notifier_call = sbridge_mce_check_error, | |
2336 | }; | |
2337 | ||
eebf11a0 MCC |
2338 | /**************************************************************************** |
2339 | EDAC register/unregister logic | |
2340 | ****************************************************************************/ | |
2341 | ||
2342 | static void sbridge_unregister_mci(struct sbridge_dev *sbridge_dev) | |
2343 | { | |
2344 | struct mem_ctl_info *mci = sbridge_dev->mci; | |
2345 | struct sbridge_pvt *pvt; | |
2346 | ||
2347 | if (unlikely(!mci || !mci->pvt_info)) { | |
956b9ba1 | 2348 | edac_dbg(0, "MC: dev = %p\n", &sbridge_dev->pdev[0]->dev); |
eebf11a0 MCC |
2349 | |
2350 | sbridge_printk(KERN_ERR, "Couldn't find mci handler\n"); | |
2351 | return; | |
2352 | } | |
2353 | ||
2354 | pvt = mci->pvt_info; | |
2355 | ||
956b9ba1 JP |
2356 | edac_dbg(0, "MC: mci = %p, dev = %p\n", |
2357 | mci, &sbridge_dev->pdev[0]->dev); | |
eebf11a0 | 2358 | |
eebf11a0 | 2359 | /* Remove MC sysfs nodes */ |
fd687502 | 2360 | edac_mc_del_mc(mci->pdev); |
eebf11a0 | 2361 | |
956b9ba1 | 2362 | edac_dbg(1, "%s: free mci struct\n", mci->ctl_name); |
eebf11a0 MCC |
2363 | kfree(mci->ctl_name); |
2364 | edac_mc_free(mci); | |
2365 | sbridge_dev->mci = NULL; | |
2366 | } | |
2367 | ||
4d715a80 | 2368 | static int sbridge_register_mci(struct sbridge_dev *sbridge_dev, enum type type) |
eebf11a0 MCC |
2369 | { |
2370 | struct mem_ctl_info *mci; | |
c36e3e77 | 2371 | struct edac_mc_layer layers[2]; |
eebf11a0 | 2372 | struct sbridge_pvt *pvt; |
4d715a80 | 2373 | struct pci_dev *pdev = sbridge_dev->pdev[0]; |
c36e3e77 | 2374 | int rc; |
eebf11a0 MCC |
2375 | |
2376 | /* Check the number of active and not disabled channels */ | |
dbc954dd | 2377 | rc = check_if_ecc_is_active(sbridge_dev->bus, type); |
eebf11a0 MCC |
2378 | if (unlikely(rc < 0)) |
2379 | return rc; | |
2380 | ||
2381 | /* allocate a new MC control structure */ | |
c36e3e77 MCC |
2382 | layers[0].type = EDAC_MC_LAYER_CHANNEL; |
2383 | layers[0].size = NUM_CHANNELS; | |
2384 | layers[0].is_virt_csrow = false; | |
2385 | layers[1].type = EDAC_MC_LAYER_SLOT; | |
2386 | layers[1].size = MAX_DIMMS; | |
2387 | layers[1].is_virt_csrow = true; | |
ca0907b9 | 2388 | mci = edac_mc_alloc(sbridge_dev->mc, ARRAY_SIZE(layers), layers, |
c36e3e77 MCC |
2389 | sizeof(*pvt)); |
2390 | ||
eebf11a0 MCC |
2391 | if (unlikely(!mci)) |
2392 | return -ENOMEM; | |
2393 | ||
956b9ba1 | 2394 | edac_dbg(0, "MC: mci = %p, dev = %p\n", |
4d715a80 | 2395 | mci, &pdev->dev); |
eebf11a0 MCC |
2396 | |
2397 | pvt = mci->pvt_info; | |
2398 | memset(pvt, 0, sizeof(*pvt)); | |
2399 | ||
2400 | /* Associate sbridge_dev and mci for future usage */ | |
2401 | pvt->sbridge_dev = sbridge_dev; | |
2402 | sbridge_dev->mci = mci; | |
2403 | ||
2404 | mci->mtype_cap = MEM_FLAG_DDR3; | |
2405 | mci->edac_ctl_cap = EDAC_FLAG_NONE; | |
2406 | mci->edac_cap = EDAC_FLAG_NONE; | |
2407 | mci->mod_name = "sbridge_edac.c"; | |
2408 | mci->mod_ver = SBRIDGE_REVISION; | |
4d715a80 | 2409 | mci->dev_name = pci_name(pdev); |
eebf11a0 MCC |
2410 | mci->ctl_page_to_phys = NULL; |
2411 | ||
2412 | /* Set the function pointer to an actual operation function */ | |
2413 | mci->edac_check = sbridge_check_error; | |
2414 | ||
4d715a80 | 2415 | pvt->info.type = type; |
50d1bb93 AR |
2416 | switch (type) { |
2417 | case IVY_BRIDGE: | |
4d715a80 AR |
2418 | pvt->info.rankcfgr = IB_RANK_CFG_A; |
2419 | pvt->info.get_tolm = ibridge_get_tolm; | |
2420 | pvt->info.get_tohm = ibridge_get_tohm; | |
2421 | pvt->info.dram_rule = ibridge_dram_rule; | |
9e375446 | 2422 | pvt->info.get_memory_type = get_memory_type; |
f14d6892 | 2423 | pvt->info.get_node_id = get_node_id; |
b976bcf2 | 2424 | pvt->info.rir_limit = rir_limit; |
c59f9c06 JS |
2425 | pvt->info.sad_limit = sad_limit; |
2426 | pvt->info.interleave_mode = interleave_mode; | |
2427 | pvt->info.show_interleave_mode = show_interleave_mode; | |
2428 | pvt->info.dram_attr = dram_attr; | |
4d715a80 AR |
2429 | pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule); |
2430 | pvt->info.interleave_list = ibridge_interleave_list; | |
2431 | pvt->info.max_interleave = ARRAY_SIZE(ibridge_interleave_list); | |
2432 | pvt->info.interleave_pkg = ibridge_interleave_pkg; | |
12f0721c | 2433 | pvt->info.get_width = ibridge_get_width; |
4d715a80 AR |
2434 | mci->ctl_name = kasprintf(GFP_KERNEL, "Ivy Bridge Socket#%d", mci->mc_idx); |
2435 | ||
2436 | /* Store pci devices at mci for faster access */ | |
2437 | rc = ibridge_mci_bind_devs(mci, sbridge_dev); | |
2438 | if (unlikely(rc < 0)) | |
2439 | goto fail0; | |
50d1bb93 AR |
2440 | break; |
2441 | case SANDY_BRIDGE: | |
4d715a80 AR |
2442 | pvt->info.rankcfgr = SB_RANK_CFG_A; |
2443 | pvt->info.get_tolm = sbridge_get_tolm; | |
2444 | pvt->info.get_tohm = sbridge_get_tohm; | |
2445 | pvt->info.dram_rule = sbridge_dram_rule; | |
9e375446 | 2446 | pvt->info.get_memory_type = get_memory_type; |
f14d6892 | 2447 | pvt->info.get_node_id = get_node_id; |
b976bcf2 | 2448 | pvt->info.rir_limit = rir_limit; |
c59f9c06 JS |
2449 | pvt->info.sad_limit = sad_limit; |
2450 | pvt->info.interleave_mode = interleave_mode; | |
2451 | pvt->info.show_interleave_mode = show_interleave_mode; | |
2452 | pvt->info.dram_attr = dram_attr; | |
4d715a80 AR |
2453 | pvt->info.max_sad = ARRAY_SIZE(sbridge_dram_rule); |
2454 | pvt->info.interleave_list = sbridge_interleave_list; | |
2455 | pvt->info.max_interleave = ARRAY_SIZE(sbridge_interleave_list); | |
2456 | pvt->info.interleave_pkg = sbridge_interleave_pkg; | |
12f0721c | 2457 | pvt->info.get_width = sbridge_get_width; |
4d715a80 AR |
2458 | mci->ctl_name = kasprintf(GFP_KERNEL, "Sandy Bridge Socket#%d", mci->mc_idx); |
2459 | ||
2460 | /* Store pci devices at mci for faster access */ | |
2461 | rc = sbridge_mci_bind_devs(mci, sbridge_dev); | |
2462 | if (unlikely(rc < 0)) | |
2463 | goto fail0; | |
50d1bb93 AR |
2464 | break; |
2465 | case HASWELL: | |
2466 | /* rankcfgr isn't used */ | |
2467 | pvt->info.get_tolm = haswell_get_tolm; | |
2468 | pvt->info.get_tohm = haswell_get_tohm; | |
2469 | pvt->info.dram_rule = ibridge_dram_rule; | |
2470 | pvt->info.get_memory_type = haswell_get_memory_type; | |
2471 | pvt->info.get_node_id = haswell_get_node_id; | |
2472 | pvt->info.rir_limit = haswell_rir_limit; | |
c59f9c06 JS |
2473 | pvt->info.sad_limit = sad_limit; |
2474 | pvt->info.interleave_mode = interleave_mode; | |
2475 | pvt->info.show_interleave_mode = show_interleave_mode; | |
2476 | pvt->info.dram_attr = dram_attr; | |
50d1bb93 AR |
2477 | pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule); |
2478 | pvt->info.interleave_list = ibridge_interleave_list; | |
2479 | pvt->info.max_interleave = ARRAY_SIZE(ibridge_interleave_list); | |
2480 | pvt->info.interleave_pkg = ibridge_interleave_pkg; | |
12f0721c | 2481 | pvt->info.get_width = ibridge_get_width; |
50d1bb93 | 2482 | mci->ctl_name = kasprintf(GFP_KERNEL, "Haswell Socket#%d", mci->mc_idx); |
4d715a80 | 2483 | |
50d1bb93 AR |
2484 | /* Store pci devices at mci for faster access */ |
2485 | rc = haswell_mci_bind_devs(mci, sbridge_dev); | |
2486 | if (unlikely(rc < 0)) | |
2487 | goto fail0; | |
2488 | break; | |
1f39581a TL |
2489 | case BROADWELL: |
2490 | /* rankcfgr isn't used */ | |
2491 | pvt->info.get_tolm = haswell_get_tolm; | |
2492 | pvt->info.get_tohm = haswell_get_tohm; | |
2493 | pvt->info.dram_rule = ibridge_dram_rule; | |
2494 | pvt->info.get_memory_type = haswell_get_memory_type; | |
2495 | pvt->info.get_node_id = haswell_get_node_id; | |
2496 | pvt->info.rir_limit = haswell_rir_limit; | |
c59f9c06 JS |
2497 | pvt->info.sad_limit = sad_limit; |
2498 | pvt->info.interleave_mode = interleave_mode; | |
2499 | pvt->info.show_interleave_mode = show_interleave_mode; | |
2500 | pvt->info.dram_attr = dram_attr; | |
1f39581a TL |
2501 | pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule); |
2502 | pvt->info.interleave_list = ibridge_interleave_list; | |
2503 | pvt->info.max_interleave = ARRAY_SIZE(ibridge_interleave_list); | |
2504 | pvt->info.interleave_pkg = ibridge_interleave_pkg; | |
12f0721c | 2505 | pvt->info.get_width = broadwell_get_width; |
1f39581a TL |
2506 | mci->ctl_name = kasprintf(GFP_KERNEL, "Broadwell Socket#%d", mci->mc_idx); |
2507 | ||
2508 | /* Store pci devices at mci for faster access */ | |
2509 | rc = broadwell_mci_bind_devs(mci, sbridge_dev); | |
2510 | if (unlikely(rc < 0)) | |
2511 | goto fail0; | |
2512 | break; | |
50d1bb93 | 2513 | } |
eebf11a0 MCC |
2514 | |
2515 | /* Get dimm basic config and the memory layout */ | |
2516 | get_dimm_config(mci); | |
2517 | get_memory_layout(mci); | |
2518 | ||
2519 | /* record ptr to the generic device */ | |
4d715a80 | 2520 | mci->pdev = &pdev->dev; |
eebf11a0 MCC |
2521 | |
2522 | /* add this new MC control structure to EDAC's list of MCs */ | |
2523 | if (unlikely(edac_mc_add_mc(mci))) { | |
956b9ba1 | 2524 | edac_dbg(0, "MC: failed edac_mc_add_mc()\n"); |
eebf11a0 MCC |
2525 | rc = -EINVAL; |
2526 | goto fail0; | |
2527 | } | |
2528 | ||
eebf11a0 | 2529 | return 0; |
eebf11a0 MCC |
2530 | |
2531 | fail0: | |
2532 | kfree(mci->ctl_name); | |
2533 | edac_mc_free(mci); | |
2534 | sbridge_dev->mci = NULL; | |
2535 | return rc; | |
2536 | } | |
2537 | ||
2538 | /* | |
2539 | * sbridge_probe Probe for ONE instance of device to see if it is | |
2540 | * present. | |
2541 | * return: | |
2542 | * 0 for FOUND a device | |
2543 | * < 0 for error code | |
2544 | */ | |
2545 | ||
9b3c6e85 | 2546 | static int sbridge_probe(struct pci_dev *pdev, const struct pci_device_id *id) |
eebf11a0 | 2547 | { |
50d1bb93 | 2548 | int rc = -ENODEV; |
eebf11a0 MCC |
2549 | u8 mc, num_mc = 0; |
2550 | struct sbridge_dev *sbridge_dev; | |
50d1bb93 | 2551 | enum type type = SANDY_BRIDGE; |
eebf11a0 MCC |
2552 | |
2553 | /* get the pci devices we want to reserve for our use */ | |
2554 | mutex_lock(&sbridge_edac_lock); | |
2555 | ||
2556 | /* | |
2557 | * All memory controllers are allocated at the first pass. | |
2558 | */ | |
2559 | if (unlikely(probed >= 1)) { | |
2560 | mutex_unlock(&sbridge_edac_lock); | |
2561 | return -ENODEV; | |
2562 | } | |
2563 | probed++; | |
2564 | ||
50d1bb93 AR |
2565 | switch (pdev->device) { |
2566 | case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA: | |
4d715a80 AR |
2567 | rc = sbridge_get_all_devices(&num_mc, pci_dev_descr_ibridge_table); |
2568 | type = IVY_BRIDGE; | |
50d1bb93 | 2569 | break; |
11249e73 | 2570 | case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0: |
4d715a80 AR |
2571 | rc = sbridge_get_all_devices(&num_mc, pci_dev_descr_sbridge_table); |
2572 | type = SANDY_BRIDGE; | |
50d1bb93 AR |
2573 | break; |
2574 | case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0: | |
2575 | rc = sbridge_get_all_devices(&num_mc, pci_dev_descr_haswell_table); | |
2576 | type = HASWELL; | |
2577 | break; | |
1f39581a TL |
2578 | case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0: |
2579 | rc = sbridge_get_all_devices(&num_mc, pci_dev_descr_broadwell_table); | |
2580 | type = BROADWELL; | |
2581 | break; | |
4d715a80 | 2582 | } |
11249e73 BP |
2583 | if (unlikely(rc < 0)) { |
2584 | edac_dbg(0, "couldn't get all devices for 0x%x\n", pdev->device); | |
eebf11a0 | 2585 | goto fail0; |
11249e73 BP |
2586 | } |
2587 | ||
eebf11a0 MCC |
2588 | mc = 0; |
2589 | ||
2590 | list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) { | |
956b9ba1 JP |
2591 | edac_dbg(0, "Registering MC#%d (%d of %d)\n", |
2592 | mc, mc + 1, num_mc); | |
50d1bb93 | 2593 | |
eebf11a0 | 2594 | sbridge_dev->mc = mc++; |
4d715a80 | 2595 | rc = sbridge_register_mci(sbridge_dev, type); |
eebf11a0 MCC |
2596 | if (unlikely(rc < 0)) |
2597 | goto fail1; | |
2598 | } | |
2599 | ||
11249e73 | 2600 | sbridge_printk(KERN_INFO, "%s\n", SBRIDGE_REVISION); |
eebf11a0 MCC |
2601 | |
2602 | mutex_unlock(&sbridge_edac_lock); | |
2603 | return 0; | |
2604 | ||
2605 | fail1: | |
2606 | list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) | |
2607 | sbridge_unregister_mci(sbridge_dev); | |
2608 | ||
2609 | sbridge_put_all_devices(); | |
2610 | fail0: | |
2611 | mutex_unlock(&sbridge_edac_lock); | |
2612 | return rc; | |
2613 | } | |
2614 | ||
2615 | /* | |
2616 | * sbridge_remove destructor for one instance of device | |
2617 | * | |
2618 | */ | |
9b3c6e85 | 2619 | static void sbridge_remove(struct pci_dev *pdev) |
eebf11a0 MCC |
2620 | { |
2621 | struct sbridge_dev *sbridge_dev; | |
2622 | ||
956b9ba1 | 2623 | edac_dbg(0, "\n"); |
eebf11a0 MCC |
2624 | |
2625 | /* | |
2626 | * we have a trouble here: pdev value for removal will be wrong, since | |
2627 | * it will point to the X58 register used to detect that the machine | |
2628 | * is a Nehalem or upper design. However, due to the way several PCI | |
2629 | * devices are grouped together to provide MC functionality, we need | |
2630 | * to use a different method for releasing the devices | |
2631 | */ | |
2632 | ||
2633 | mutex_lock(&sbridge_edac_lock); | |
2634 | ||
2635 | if (unlikely(!probed)) { | |
2636 | mutex_unlock(&sbridge_edac_lock); | |
2637 | return; | |
2638 | } | |
2639 | ||
2640 | list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) | |
2641 | sbridge_unregister_mci(sbridge_dev); | |
2642 | ||
2643 | /* Release PCI resources */ | |
2644 | sbridge_put_all_devices(); | |
2645 | ||
2646 | probed--; | |
2647 | ||
2648 | mutex_unlock(&sbridge_edac_lock); | |
2649 | } | |
2650 | ||
2651 | MODULE_DEVICE_TABLE(pci, sbridge_pci_tbl); | |
2652 | ||
2653 | /* | |
2654 | * sbridge_driver pci_driver structure for this module | |
2655 | * | |
2656 | */ | |
2657 | static struct pci_driver sbridge_driver = { | |
2658 | .name = "sbridge_edac", | |
2659 | .probe = sbridge_probe, | |
9b3c6e85 | 2660 | .remove = sbridge_remove, |
eebf11a0 MCC |
2661 | .id_table = sbridge_pci_tbl, |
2662 | }; | |
2663 | ||
2664 | /* | |
2665 | * sbridge_init Module entry function | |
2666 | * Try to initialize this module for its devices | |
2667 | */ | |
2668 | static int __init sbridge_init(void) | |
2669 | { | |
2670 | int pci_rc; | |
2671 | ||
956b9ba1 | 2672 | edac_dbg(2, "\n"); |
eebf11a0 MCC |
2673 | |
2674 | /* Ensure that the OPSTATE is set correctly for POLL or NMI */ | |
2675 | opstate_init(); | |
2676 | ||
2677 | pci_rc = pci_register_driver(&sbridge_driver); | |
e35fca47 CG |
2678 | if (pci_rc >= 0) { |
2679 | mce_register_decode_chain(&sbridge_mce_dec); | |
fd521039 CG |
2680 | if (get_edac_report_status() == EDAC_REPORTING_DISABLED) |
2681 | sbridge_printk(KERN_WARNING, "Loading driver, error reporting disabled.\n"); | |
eebf11a0 | 2682 | return 0; |
e35fca47 | 2683 | } |
eebf11a0 MCC |
2684 | |
2685 | sbridge_printk(KERN_ERR, "Failed to register device with error %d.\n", | |
2686 | pci_rc); | |
2687 | ||
2688 | return pci_rc; | |
2689 | } | |
2690 | ||
2691 | /* | |
2692 | * sbridge_exit() Module exit function | |
2693 | * Unregister the driver | |
2694 | */ | |
2695 | static void __exit sbridge_exit(void) | |
2696 | { | |
956b9ba1 | 2697 | edac_dbg(2, "\n"); |
eebf11a0 | 2698 | pci_unregister_driver(&sbridge_driver); |
e35fca47 | 2699 | mce_unregister_decode_chain(&sbridge_mce_dec); |
eebf11a0 MCC |
2700 | } |
2701 | ||
2702 | module_init(sbridge_init); | |
2703 | module_exit(sbridge_exit); | |
2704 | ||
2705 | module_param(edac_op_state, int, 0444); | |
2706 | MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI"); | |
2707 | ||
2708 | MODULE_LICENSE("GPL"); | |
37e59f87 | 2709 | MODULE_AUTHOR("Mauro Carvalho Chehab"); |
eebf11a0 | 2710 | MODULE_AUTHOR("Red Hat Inc. (http://www.redhat.com)"); |
4d715a80 | 2711 | MODULE_DESCRIPTION("MC Driver for Intel Sandy Bridge and Ivy Bridge memory controllers - " |
eebf11a0 | 2712 | SBRIDGE_REVISION); |