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eebf11a0 MCC |
1 | /* Intel Sandy Bridge -EN/-EP/-EX Memory Controller kernel module |
2 | * | |
3 | * This driver supports the memory controllers found on the Intel | |
4 | * processor family Sandy Bridge. | |
5 | * | |
6 | * This file may be distributed under the terms of the | |
7 | * GNU General Public License version 2 only. | |
8 | * | |
9 | * Copyright (c) 2011 by: | |
37e59f87 | 10 | * Mauro Carvalho Chehab |
eebf11a0 MCC |
11 | */ |
12 | ||
13 | #include <linux/module.h> | |
14 | #include <linux/init.h> | |
15 | #include <linux/pci.h> | |
16 | #include <linux/pci_ids.h> | |
17 | #include <linux/slab.h> | |
18 | #include <linux/delay.h> | |
19 | #include <linux/edac.h> | |
20 | #include <linux/mmzone.h> | |
eebf11a0 MCC |
21 | #include <linux/smp.h> |
22 | #include <linux/bitmap.h> | |
5b889e37 | 23 | #include <linux/math64.h> |
eebf11a0 | 24 | #include <asm/processor.h> |
3d78c9af | 25 | #include <asm/mce.h> |
eebf11a0 MCC |
26 | |
27 | #include "edac_core.h" | |
28 | ||
29 | /* Static vars */ | |
30 | static LIST_HEAD(sbridge_edac_list); | |
31 | static DEFINE_MUTEX(sbridge_edac_lock); | |
32 | static int probed; | |
33 | ||
34 | /* | |
35 | * Alter this version for the module when modifications are made | |
36 | */ | |
4d715a80 | 37 | #define SBRIDGE_REVISION " Ver: 1.1.0 " |
eebf11a0 MCC |
38 | #define EDAC_MOD_STR "sbridge_edac" |
39 | ||
40 | /* | |
41 | * Debug macros | |
42 | */ | |
43 | #define sbridge_printk(level, fmt, arg...) \ | |
44 | edac_printk(level, "sbridge", fmt, ##arg) | |
45 | ||
46 | #define sbridge_mc_printk(mci, level, fmt, arg...) \ | |
47 | edac_mc_chipset_printk(mci, level, "sbridge", fmt, ##arg) | |
48 | ||
49 | /* | |
50 | * Get a bit field at register value <v>, from bit <lo> to bit <hi> | |
51 | */ | |
52 | #define GET_BITFIELD(v, lo, hi) \ | |
10ef6b0d | 53 | (((v) & GENMASK_ULL(hi, lo)) >> (lo)) |
eebf11a0 | 54 | |
eebf11a0 | 55 | /* Devices 12 Function 6, Offsets 0x80 to 0xcc */ |
464f1d82 | 56 | static const u32 sbridge_dram_rule[] = { |
eebf11a0 MCC |
57 | 0x80, 0x88, 0x90, 0x98, 0xa0, |
58 | 0xa8, 0xb0, 0xb8, 0xc0, 0xc8, | |
59 | }; | |
eebf11a0 | 60 | |
4d715a80 AR |
61 | static const u32 ibridge_dram_rule[] = { |
62 | 0x60, 0x68, 0x70, 0x78, 0x80, | |
63 | 0x88, 0x90, 0x98, 0xa0, 0xa8, | |
64 | 0xb0, 0xb8, 0xc0, 0xc8, 0xd0, | |
65 | 0xd8, 0xe0, 0xe8, 0xf0, 0xf8, | |
66 | }; | |
eebf11a0 MCC |
67 | |
68 | #define SAD_LIMIT(reg) ((GET_BITFIELD(reg, 6, 25) << 26) | 0x3ffffff) | |
69 | #define DRAM_ATTR(reg) GET_BITFIELD(reg, 2, 3) | |
70 | #define INTERLEAVE_MODE(reg) GET_BITFIELD(reg, 1, 1) | |
71 | #define DRAM_RULE_ENABLE(reg) GET_BITFIELD(reg, 0, 0) | |
50d1bb93 | 72 | #define A7MODE(reg) GET_BITFIELD(reg, 26, 26) |
eebf11a0 MCC |
73 | |
74 | static char *get_dram_attr(u32 reg) | |
75 | { | |
76 | switch(DRAM_ATTR(reg)) { | |
77 | case 0: | |
78 | return "DRAM"; | |
79 | case 1: | |
80 | return "MMCFG"; | |
81 | case 2: | |
82 | return "NXM"; | |
83 | default: | |
84 | return "unknown"; | |
85 | } | |
86 | } | |
87 | ||
ef1ce51e | 88 | static const u32 sbridge_interleave_list[] = { |
eebf11a0 MCC |
89 | 0x84, 0x8c, 0x94, 0x9c, 0xa4, |
90 | 0xac, 0xb4, 0xbc, 0xc4, 0xcc, | |
91 | }; | |
eebf11a0 | 92 | |
4d715a80 AR |
93 | static const u32 ibridge_interleave_list[] = { |
94 | 0x64, 0x6c, 0x74, 0x7c, 0x84, | |
95 | 0x8c, 0x94, 0x9c, 0xa4, 0xac, | |
96 | 0xb4, 0xbc, 0xc4, 0xcc, 0xd4, | |
97 | 0xdc, 0xe4, 0xec, 0xf4, 0xfc, | |
98 | }; | |
99 | ||
cc311991 AR |
100 | struct interleave_pkg { |
101 | unsigned char start; | |
102 | unsigned char end; | |
103 | }; | |
104 | ||
105 | static const struct interleave_pkg sbridge_interleave_pkg[] = { | |
106 | { 0, 2 }, | |
107 | { 3, 5 }, | |
108 | { 8, 10 }, | |
109 | { 11, 13 }, | |
110 | { 16, 18 }, | |
111 | { 19, 21 }, | |
112 | { 24, 26 }, | |
113 | { 27, 29 }, | |
114 | }; | |
115 | ||
4d715a80 AR |
116 | static const struct interleave_pkg ibridge_interleave_pkg[] = { |
117 | { 0, 3 }, | |
118 | { 4, 7 }, | |
119 | { 8, 11 }, | |
120 | { 12, 15 }, | |
121 | { 16, 19 }, | |
122 | { 20, 23 }, | |
123 | { 24, 27 }, | |
124 | { 28, 31 }, | |
125 | }; | |
126 | ||
cc311991 AR |
127 | static inline int sad_pkg(const struct interleave_pkg *table, u32 reg, |
128 | int interleave) | |
eebf11a0 | 129 | { |
cc311991 AR |
130 | return GET_BITFIELD(reg, table[interleave].start, |
131 | table[interleave].end); | |
eebf11a0 MCC |
132 | } |
133 | ||
134 | /* Devices 12 Function 7 */ | |
135 | ||
136 | #define TOLM 0x80 | |
137 | #define TOHM 0x84 | |
f7cf2a22 | 138 | #define HASWELL_TOLM 0xd0 |
50d1bb93 AR |
139 | #define HASWELL_TOHM_0 0xd4 |
140 | #define HASWELL_TOHM_1 0xd8 | |
eebf11a0 MCC |
141 | |
142 | #define GET_TOLM(reg) ((GET_BITFIELD(reg, 0, 3) << 28) | 0x3ffffff) | |
143 | #define GET_TOHM(reg) ((GET_BITFIELD(reg, 0, 20) << 25) | 0x3ffffff) | |
144 | ||
145 | /* Device 13 Function 6 */ | |
146 | ||
147 | #define SAD_TARGET 0xf0 | |
148 | ||
149 | #define SOURCE_ID(reg) GET_BITFIELD(reg, 9, 11) | |
150 | ||
151 | #define SAD_CONTROL 0xf4 | |
152 | ||
eebf11a0 MCC |
153 | /* Device 14 function 0 */ |
154 | ||
155 | static const u32 tad_dram_rule[] = { | |
156 | 0x40, 0x44, 0x48, 0x4c, | |
157 | 0x50, 0x54, 0x58, 0x5c, | |
158 | 0x60, 0x64, 0x68, 0x6c, | |
159 | }; | |
160 | #define MAX_TAD ARRAY_SIZE(tad_dram_rule) | |
161 | ||
162 | #define TAD_LIMIT(reg) ((GET_BITFIELD(reg, 12, 31) << 26) | 0x3ffffff) | |
163 | #define TAD_SOCK(reg) GET_BITFIELD(reg, 10, 11) | |
164 | #define TAD_CH(reg) GET_BITFIELD(reg, 8, 9) | |
165 | #define TAD_TGT3(reg) GET_BITFIELD(reg, 6, 7) | |
166 | #define TAD_TGT2(reg) GET_BITFIELD(reg, 4, 5) | |
167 | #define TAD_TGT1(reg) GET_BITFIELD(reg, 2, 3) | |
168 | #define TAD_TGT0(reg) GET_BITFIELD(reg, 0, 1) | |
169 | ||
170 | /* Device 15, function 0 */ | |
171 | ||
172 | #define MCMTR 0x7c | |
173 | ||
174 | #define IS_ECC_ENABLED(mcmtr) GET_BITFIELD(mcmtr, 2, 2) | |
175 | #define IS_LOCKSTEP_ENABLED(mcmtr) GET_BITFIELD(mcmtr, 1, 1) | |
176 | #define IS_CLOSE_PG(mcmtr) GET_BITFIELD(mcmtr, 0, 0) | |
177 | ||
178 | /* Device 15, function 1 */ | |
179 | ||
180 | #define RASENABLES 0xac | |
181 | #define IS_MIRROR_ENABLED(reg) GET_BITFIELD(reg, 0, 0) | |
182 | ||
183 | /* Device 15, functions 2-5 */ | |
184 | ||
185 | static const int mtr_regs[] = { | |
186 | 0x80, 0x84, 0x88, | |
187 | }; | |
188 | ||
189 | #define RANK_DISABLE(mtr) GET_BITFIELD(mtr, 16, 19) | |
190 | #define IS_DIMM_PRESENT(mtr) GET_BITFIELD(mtr, 14, 14) | |
191 | #define RANK_CNT_BITS(mtr) GET_BITFIELD(mtr, 12, 13) | |
192 | #define RANK_WIDTH_BITS(mtr) GET_BITFIELD(mtr, 2, 4) | |
193 | #define COL_WIDTH_BITS(mtr) GET_BITFIELD(mtr, 0, 1) | |
194 | ||
195 | static const u32 tad_ch_nilv_offset[] = { | |
196 | 0x90, 0x94, 0x98, 0x9c, | |
197 | 0xa0, 0xa4, 0xa8, 0xac, | |
198 | 0xb0, 0xb4, 0xb8, 0xbc, | |
199 | }; | |
200 | #define CHN_IDX_OFFSET(reg) GET_BITFIELD(reg, 28, 29) | |
201 | #define TAD_OFFSET(reg) (GET_BITFIELD(reg, 6, 25) << 26) | |
202 | ||
203 | static const u32 rir_way_limit[] = { | |
204 | 0x108, 0x10c, 0x110, 0x114, 0x118, | |
205 | }; | |
206 | #define MAX_RIR_RANGES ARRAY_SIZE(rir_way_limit) | |
207 | ||
208 | #define IS_RIR_VALID(reg) GET_BITFIELD(reg, 31, 31) | |
209 | #define RIR_WAY(reg) GET_BITFIELD(reg, 28, 29) | |
eebf11a0 MCC |
210 | |
211 | #define MAX_RIR_WAY 8 | |
212 | ||
213 | static const u32 rir_offset[MAX_RIR_RANGES][MAX_RIR_WAY] = { | |
214 | { 0x120, 0x124, 0x128, 0x12c, 0x130, 0x134, 0x138, 0x13c }, | |
215 | { 0x140, 0x144, 0x148, 0x14c, 0x150, 0x154, 0x158, 0x15c }, | |
216 | { 0x160, 0x164, 0x168, 0x16c, 0x170, 0x174, 0x178, 0x17c }, | |
217 | { 0x180, 0x184, 0x188, 0x18c, 0x190, 0x194, 0x198, 0x19c }, | |
218 | { 0x1a0, 0x1a4, 0x1a8, 0x1ac, 0x1b0, 0x1b4, 0x1b8, 0x1bc }, | |
219 | }; | |
220 | ||
221 | #define RIR_RNK_TGT(reg) GET_BITFIELD(reg, 16, 19) | |
222 | #define RIR_OFFSET(reg) GET_BITFIELD(reg, 2, 14) | |
223 | ||
224 | /* Device 16, functions 2-7 */ | |
225 | ||
226 | /* | |
227 | * FIXME: Implement the error count reads directly | |
228 | */ | |
229 | ||
230 | static const u32 correrrcnt[] = { | |
231 | 0x104, 0x108, 0x10c, 0x110, | |
232 | }; | |
233 | ||
234 | #define RANK_ODD_OV(reg) GET_BITFIELD(reg, 31, 31) | |
235 | #define RANK_ODD_ERR_CNT(reg) GET_BITFIELD(reg, 16, 30) | |
236 | #define RANK_EVEN_OV(reg) GET_BITFIELD(reg, 15, 15) | |
237 | #define RANK_EVEN_ERR_CNT(reg) GET_BITFIELD(reg, 0, 14) | |
238 | ||
239 | static const u32 correrrthrsld[] = { | |
240 | 0x11c, 0x120, 0x124, 0x128, | |
241 | }; | |
242 | ||
243 | #define RANK_ODD_ERR_THRSLD(reg) GET_BITFIELD(reg, 16, 30) | |
244 | #define RANK_EVEN_ERR_THRSLD(reg) GET_BITFIELD(reg, 0, 14) | |
245 | ||
246 | ||
247 | /* Device 17, function 0 */ | |
248 | ||
ef1e8d03 | 249 | #define SB_RANK_CFG_A 0x0328 |
eebf11a0 | 250 | |
4d715a80 | 251 | #define IB_RANK_CFG_A 0x0320 |
eebf11a0 | 252 | |
eebf11a0 MCC |
253 | /* |
254 | * sbridge structs | |
255 | */ | |
256 | ||
351fc4a9 SJ |
257 | #define NUM_CHANNELS 4 |
258 | #define MAX_DIMMS 3 /* Max DIMMS per channel */ | |
259 | #define CHANNEL_UNSPECIFIED 0xf /* Intel IA32 SDM 15-14 */ | |
eebf11a0 | 260 | |
4d715a80 AR |
261 | enum type { |
262 | SANDY_BRIDGE, | |
263 | IVY_BRIDGE, | |
50d1bb93 | 264 | HASWELL, |
4d715a80 AR |
265 | }; |
266 | ||
fb79a509 | 267 | struct sbridge_pvt; |
eebf11a0 | 268 | struct sbridge_info { |
4d715a80 | 269 | enum type type; |
464f1d82 AR |
270 | u32 mcmtr; |
271 | u32 rankcfgr; | |
272 | u64 (*get_tolm)(struct sbridge_pvt *pvt); | |
273 | u64 (*get_tohm)(struct sbridge_pvt *pvt); | |
b976bcf2 | 274 | u64 (*rir_limit)(u32 reg); |
464f1d82 | 275 | const u32 *dram_rule; |
ef1ce51e | 276 | const u32 *interleave_list; |
cc311991 | 277 | const struct interleave_pkg *interleave_pkg; |
464f1d82 | 278 | u8 max_sad; |
ef1ce51e | 279 | u8 max_interleave; |
f14d6892 | 280 | u8 (*get_node_id)(struct sbridge_pvt *pvt); |
9e375446 | 281 | enum mem_type (*get_memory_type)(struct sbridge_pvt *pvt); |
50d1bb93 | 282 | struct pci_dev *pci_vtd; |
eebf11a0 MCC |
283 | }; |
284 | ||
285 | struct sbridge_channel { | |
286 | u32 ranks; | |
287 | u32 dimms; | |
288 | }; | |
289 | ||
290 | struct pci_id_descr { | |
c41afdca | 291 | int dev_id; |
eebf11a0 MCC |
292 | int optional; |
293 | }; | |
294 | ||
295 | struct pci_id_table { | |
296 | const struct pci_id_descr *descr; | |
297 | int n_devs; | |
298 | }; | |
299 | ||
300 | struct sbridge_dev { | |
301 | struct list_head list; | |
302 | u8 bus, mc; | |
303 | u8 node_id, source_id; | |
304 | struct pci_dev **pdev; | |
305 | int n_devs; | |
306 | struct mem_ctl_info *mci; | |
307 | }; | |
308 | ||
309 | struct sbridge_pvt { | |
310 | struct pci_dev *pci_ta, *pci_ddrio, *pci_ras; | |
4d715a80 AR |
311 | struct pci_dev *pci_sad0, *pci_sad1; |
312 | struct pci_dev *pci_ha0, *pci_ha1; | |
313 | struct pci_dev *pci_br0, *pci_br1; | |
50d1bb93 | 314 | struct pci_dev *pci_ha1_ta; |
eebf11a0 MCC |
315 | struct pci_dev *pci_tad[NUM_CHANNELS]; |
316 | ||
317 | struct sbridge_dev *sbridge_dev; | |
318 | ||
319 | struct sbridge_info info; | |
320 | struct sbridge_channel channel[NUM_CHANNELS]; | |
321 | ||
eebf11a0 MCC |
322 | /* Memory type detection */ |
323 | bool is_mirrored, is_lockstep, is_close_pg; | |
324 | ||
eebf11a0 MCC |
325 | /* Fifo double buffers */ |
326 | struct mce mce_entry[MCE_LOG_LEN]; | |
327 | struct mce mce_outentry[MCE_LOG_LEN]; | |
328 | ||
329 | /* Fifo in/out counters */ | |
330 | unsigned mce_in, mce_out; | |
331 | ||
332 | /* Count indicator to show errors not got */ | |
333 | unsigned mce_overrun; | |
334 | ||
335 | /* Memory description */ | |
336 | u64 tolm, tohm; | |
337 | }; | |
338 | ||
dbc954dd AR |
339 | #define PCI_DESCR(device_id, opt) \ |
340 | .dev_id = (device_id), \ | |
de4772c6 | 341 | .optional = opt |
eebf11a0 MCC |
342 | |
343 | static const struct pci_id_descr pci_dev_descr_sbridge[] = { | |
344 | /* Processor Home Agent */ | |
dbc954dd | 345 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0, 0) }, |
eebf11a0 MCC |
346 | |
347 | /* Memory controller */ | |
dbc954dd AR |
348 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA, 0) }, |
349 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_RAS, 0) }, | |
350 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0, 0) }, | |
351 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD1, 0) }, | |
352 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD2, 0) }, | |
353 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD3, 0) }, | |
354 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_DDRIO, 1) }, | |
eebf11a0 MCC |
355 | |
356 | /* System Address Decoder */ | |
dbc954dd AR |
357 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_SAD0, 0) }, |
358 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_SAD1, 0) }, | |
eebf11a0 MCC |
359 | |
360 | /* Broadcast Registers */ | |
dbc954dd | 361 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_BR, 0) }, |
eebf11a0 MCC |
362 | }; |
363 | ||
364 | #define PCI_ID_TABLE_ENTRY(A) { .descr=A, .n_devs = ARRAY_SIZE(A) } | |
365 | static const struct pci_id_table pci_dev_descr_sbridge_table[] = { | |
366 | PCI_ID_TABLE_ENTRY(pci_dev_descr_sbridge), | |
367 | {0,} /* 0 terminated list. */ | |
368 | }; | |
369 | ||
4d715a80 AR |
370 | /* This changes depending if 1HA or 2HA: |
371 | * 1HA: | |
372 | * 0x0eb8 (17.0) is DDRIO0 | |
373 | * 2HA: | |
374 | * 0x0ebc (17.4) is DDRIO0 | |
375 | */ | |
376 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_1HA_DDRIO0 0x0eb8 | |
377 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_2HA_DDRIO0 0x0ebc | |
378 | ||
379 | /* pci ids */ | |
380 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0 0x0ea0 | |
381 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA 0x0ea8 | |
382 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_RAS 0x0e71 | |
383 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0 0x0eaa | |
384 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD1 0x0eab | |
385 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD2 0x0eac | |
386 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD3 0x0ead | |
387 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_SAD 0x0ec8 | |
388 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_BR0 0x0ec9 | |
389 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_BR1 0x0eca | |
390 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1 0x0e60 | |
391 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TA 0x0e68 | |
392 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_RAS 0x0e79 | |
393 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0 0x0e6a | |
394 | #define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD1 0x0e6b | |
395 | ||
396 | static const struct pci_id_descr pci_dev_descr_ibridge[] = { | |
397 | /* Processor Home Agent */ | |
dbc954dd | 398 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0, 0) }, |
4d715a80 AR |
399 | |
400 | /* Memory controller */ | |
dbc954dd AR |
401 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA, 0) }, |
402 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_RAS, 0) }, | |
403 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0, 0) }, | |
404 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD1, 0) }, | |
405 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD2, 0) }, | |
406 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD3, 0) }, | |
4d715a80 AR |
407 | |
408 | /* System Address Decoder */ | |
dbc954dd | 409 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_SAD, 0) }, |
4d715a80 AR |
410 | |
411 | /* Broadcast Registers */ | |
dbc954dd AR |
412 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_BR0, 1) }, |
413 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_BR1, 0) }, | |
4d715a80 AR |
414 | |
415 | /* Optional, mode 2HA */ | |
dbc954dd | 416 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1, 1) }, |
4d715a80 | 417 | #if 0 |
dbc954dd AR |
418 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TA, 1) }, |
419 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_RAS, 1) }, | |
4d715a80 | 420 | #endif |
dbc954dd AR |
421 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0, 1) }, |
422 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD1, 1) }, | |
4d715a80 | 423 | |
dbc954dd AR |
424 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_1HA_DDRIO0, 1) }, |
425 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_2HA_DDRIO0, 1) }, | |
4d715a80 AR |
426 | }; |
427 | ||
428 | static const struct pci_id_table pci_dev_descr_ibridge_table[] = { | |
429 | PCI_ID_TABLE_ENTRY(pci_dev_descr_ibridge), | |
430 | {0,} /* 0 terminated list. */ | |
431 | }; | |
432 | ||
50d1bb93 AR |
433 | /* Haswell support */ |
434 | /* EN processor: | |
435 | * - 1 IMC | |
436 | * - 3 DDR3 channels, 2 DPC per channel | |
437 | * EP processor: | |
438 | * - 1 or 2 IMC | |
439 | * - 4 DDR4 channels, 3 DPC per channel | |
440 | * EP 4S processor: | |
441 | * - 2 IMC | |
442 | * - 4 DDR4 channels, 3 DPC per channel | |
443 | * EX processor: | |
444 | * - 2 IMC | |
445 | * - each IMC interfaces with a SMI 2 channel | |
446 | * - each SMI channel interfaces with a scalable memory buffer | |
447 | * - each scalable memory buffer supports 4 DDR3/DDR4 channels, 3 DPC | |
448 | */ | |
449 | #define HASWELL_DDRCRCLKCONTROLS 0xa10 | |
450 | #define HASWELL_HASYSDEFEATURE2 0x84 | |
451 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_VTD_MISC 0x2f28 | |
452 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0 0x2fa0 | |
453 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1 0x2f60 | |
454 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA 0x2fa8 | |
455 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_THERMAL 0x2f71 | |
456 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TA 0x2f68 | |
457 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_THERMAL 0x2f79 | |
458 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD0 0x2ffc | |
459 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD1 0x2ffd | |
460 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD0 0x2faa | |
461 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD1 0x2fab | |
462 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD2 0x2fac | |
463 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD3 0x2fad | |
464 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD0 0x2f6a | |
465 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD1 0x2f6b | |
466 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD2 0x2f6c | |
467 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD3 0x2f6d | |
468 | #define PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO0 0x2fbd | |
469 | static const struct pci_id_descr pci_dev_descr_haswell[] = { | |
470 | /* first item must be the HA */ | |
471 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0, 0) }, | |
472 | ||
473 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD0, 0) }, | |
474 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD1, 0) }, | |
475 | ||
476 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1, 1) }, | |
477 | ||
478 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA, 0) }, | |
479 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_THERMAL, 0) }, | |
480 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD0, 0) }, | |
481 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD1, 0) }, | |
482 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD2, 1) }, | |
483 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD3, 1) }, | |
484 | ||
485 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO0, 1) }, | |
486 | ||
487 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TA, 1) }, | |
488 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_THERMAL, 1) }, | |
489 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD0, 1) }, | |
490 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD1, 1) }, | |
491 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD2, 1) }, | |
492 | { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD3, 1) }, | |
493 | }; | |
494 | ||
495 | static const struct pci_id_table pci_dev_descr_haswell_table[] = { | |
496 | PCI_ID_TABLE_ENTRY(pci_dev_descr_haswell), | |
497 | {0,} /* 0 terminated list. */ | |
498 | }; | |
499 | ||
eebf11a0 MCC |
500 | /* |
501 | * pci_device_id table for which devices we are looking for | |
502 | */ | |
ba935f40 | 503 | static const struct pci_device_id sbridge_pci_tbl[] = { |
d0585cd8 | 504 | {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0)}, |
4d715a80 | 505 | {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA)}, |
50d1bb93 | 506 | {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0)}, |
eebf11a0 MCC |
507 | {0,} /* 0 terminated list. */ |
508 | }; | |
509 | ||
510 | ||
511 | /**************************************************************************** | |
15ed103a | 512 | Ancillary status routines |
eebf11a0 MCC |
513 | ****************************************************************************/ |
514 | ||
50d1bb93 | 515 | static inline int numrank(enum type type, u32 mtr) |
eebf11a0 MCC |
516 | { |
517 | int ranks = (1 << RANK_CNT_BITS(mtr)); | |
50d1bb93 AR |
518 | int max = 4; |
519 | ||
520 | if (type == HASWELL) | |
521 | max = 8; | |
eebf11a0 | 522 | |
50d1bb93 AR |
523 | if (ranks > max) { |
524 | edac_dbg(0, "Invalid number of ranks: %d (max = %i) raw value = %x (%04x)\n", | |
525 | ranks, max, (unsigned int)RANK_CNT_BITS(mtr), mtr); | |
eebf11a0 MCC |
526 | return -EINVAL; |
527 | } | |
528 | ||
529 | return ranks; | |
530 | } | |
531 | ||
532 | static inline int numrow(u32 mtr) | |
533 | { | |
534 | int rows = (RANK_WIDTH_BITS(mtr) + 12); | |
535 | ||
536 | if (rows < 13 || rows > 18) { | |
956b9ba1 JP |
537 | edac_dbg(0, "Invalid number of rows: %d (should be between 14 and 17) raw value = %x (%04x)\n", |
538 | rows, (unsigned int)RANK_WIDTH_BITS(mtr), mtr); | |
eebf11a0 MCC |
539 | return -EINVAL; |
540 | } | |
541 | ||
542 | return 1 << rows; | |
543 | } | |
544 | ||
545 | static inline int numcol(u32 mtr) | |
546 | { | |
547 | int cols = (COL_WIDTH_BITS(mtr) + 10); | |
548 | ||
549 | if (cols > 12) { | |
956b9ba1 JP |
550 | edac_dbg(0, "Invalid number of cols: %d (max = 4) raw value = %x (%04x)\n", |
551 | cols, (unsigned int)COL_WIDTH_BITS(mtr), mtr); | |
eebf11a0 MCC |
552 | return -EINVAL; |
553 | } | |
554 | ||
555 | return 1 << cols; | |
556 | } | |
557 | ||
558 | static struct sbridge_dev *get_sbridge_dev(u8 bus) | |
559 | { | |
560 | struct sbridge_dev *sbridge_dev; | |
561 | ||
562 | list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) { | |
563 | if (sbridge_dev->bus == bus) | |
564 | return sbridge_dev; | |
565 | } | |
566 | ||
567 | return NULL; | |
568 | } | |
569 | ||
570 | static struct sbridge_dev *alloc_sbridge_dev(u8 bus, | |
571 | const struct pci_id_table *table) | |
572 | { | |
573 | struct sbridge_dev *sbridge_dev; | |
574 | ||
575 | sbridge_dev = kzalloc(sizeof(*sbridge_dev), GFP_KERNEL); | |
576 | if (!sbridge_dev) | |
577 | return NULL; | |
578 | ||
579 | sbridge_dev->pdev = kzalloc(sizeof(*sbridge_dev->pdev) * table->n_devs, | |
580 | GFP_KERNEL); | |
581 | if (!sbridge_dev->pdev) { | |
582 | kfree(sbridge_dev); | |
583 | return NULL; | |
584 | } | |
585 | ||
586 | sbridge_dev->bus = bus; | |
587 | sbridge_dev->n_devs = table->n_devs; | |
588 | list_add_tail(&sbridge_dev->list, &sbridge_edac_list); | |
589 | ||
590 | return sbridge_dev; | |
591 | } | |
592 | ||
593 | static void free_sbridge_dev(struct sbridge_dev *sbridge_dev) | |
594 | { | |
595 | list_del(&sbridge_dev->list); | |
596 | kfree(sbridge_dev->pdev); | |
597 | kfree(sbridge_dev); | |
598 | } | |
599 | ||
fb79a509 AR |
600 | static u64 sbridge_get_tolm(struct sbridge_pvt *pvt) |
601 | { | |
602 | u32 reg; | |
603 | ||
604 | /* Address range is 32:28 */ | |
605 | pci_read_config_dword(pvt->pci_sad1, TOLM, ®); | |
606 | return GET_TOLM(reg); | |
607 | } | |
608 | ||
8fd6a43a AR |
609 | static u64 sbridge_get_tohm(struct sbridge_pvt *pvt) |
610 | { | |
611 | u32 reg; | |
612 | ||
613 | pci_read_config_dword(pvt->pci_sad1, TOHM, ®); | |
614 | return GET_TOHM(reg); | |
615 | } | |
616 | ||
4d715a80 AR |
617 | static u64 ibridge_get_tolm(struct sbridge_pvt *pvt) |
618 | { | |
619 | u32 reg; | |
620 | ||
621 | pci_read_config_dword(pvt->pci_br1, TOLM, ®); | |
622 | ||
623 | return GET_TOLM(reg); | |
624 | } | |
625 | ||
626 | static u64 ibridge_get_tohm(struct sbridge_pvt *pvt) | |
627 | { | |
628 | u32 reg; | |
629 | ||
630 | pci_read_config_dword(pvt->pci_br1, TOHM, ®); | |
631 | ||
632 | return GET_TOHM(reg); | |
633 | } | |
634 | ||
b976bcf2 AR |
635 | static u64 rir_limit(u32 reg) |
636 | { | |
637 | return ((u64)GET_BITFIELD(reg, 1, 10) << 29) | 0x1fffffff; | |
638 | } | |
639 | ||
9e375446 AR |
640 | static enum mem_type get_memory_type(struct sbridge_pvt *pvt) |
641 | { | |
642 | u32 reg; | |
643 | enum mem_type mtype; | |
644 | ||
645 | if (pvt->pci_ddrio) { | |
646 | pci_read_config_dword(pvt->pci_ddrio, pvt->info.rankcfgr, | |
647 | ®); | |
648 | if (GET_BITFIELD(reg, 11, 11)) | |
649 | /* FIXME: Can also be LRDIMM */ | |
650 | mtype = MEM_RDDR3; | |
651 | else | |
652 | mtype = MEM_DDR3; | |
653 | } else | |
654 | mtype = MEM_UNKNOWN; | |
655 | ||
656 | return mtype; | |
657 | } | |
658 | ||
50d1bb93 AR |
659 | static enum mem_type haswell_get_memory_type(struct sbridge_pvt *pvt) |
660 | { | |
661 | u32 reg; | |
662 | bool registered = false; | |
663 | enum mem_type mtype = MEM_UNKNOWN; | |
664 | ||
665 | if (!pvt->pci_ddrio) | |
666 | goto out; | |
667 | ||
668 | pci_read_config_dword(pvt->pci_ddrio, | |
669 | HASWELL_DDRCRCLKCONTROLS, ®); | |
670 | /* Is_Rdimm */ | |
671 | if (GET_BITFIELD(reg, 16, 16)) | |
672 | registered = true; | |
673 | ||
674 | pci_read_config_dword(pvt->pci_ta, MCMTR, ®); | |
675 | if (GET_BITFIELD(reg, 14, 14)) { | |
676 | if (registered) | |
677 | mtype = MEM_RDDR4; | |
678 | else | |
679 | mtype = MEM_DDR4; | |
680 | } else { | |
681 | if (registered) | |
682 | mtype = MEM_RDDR3; | |
683 | else | |
684 | mtype = MEM_DDR3; | |
685 | } | |
686 | ||
687 | out: | |
688 | return mtype; | |
689 | } | |
690 | ||
f14d6892 AR |
691 | static u8 get_node_id(struct sbridge_pvt *pvt) |
692 | { | |
693 | u32 reg; | |
694 | pci_read_config_dword(pvt->pci_br0, SAD_CONTROL, ®); | |
695 | return GET_BITFIELD(reg, 0, 2); | |
696 | } | |
697 | ||
50d1bb93 AR |
698 | static u8 haswell_get_node_id(struct sbridge_pvt *pvt) |
699 | { | |
700 | u32 reg; | |
701 | ||
702 | pci_read_config_dword(pvt->pci_sad1, SAD_CONTROL, ®); | |
703 | return GET_BITFIELD(reg, 0, 3); | |
704 | } | |
705 | ||
706 | static u64 haswell_get_tolm(struct sbridge_pvt *pvt) | |
707 | { | |
708 | u32 reg; | |
709 | ||
f7cf2a22 TL |
710 | pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOLM, ®); |
711 | return (GET_BITFIELD(reg, 26, 31) << 26) | 0x3ffffff; | |
50d1bb93 AR |
712 | } |
713 | ||
714 | static u64 haswell_get_tohm(struct sbridge_pvt *pvt) | |
715 | { | |
716 | u64 rc; | |
717 | u32 reg; | |
718 | ||
719 | pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOHM_0, ®); | |
720 | rc = GET_BITFIELD(reg, 26, 31); | |
721 | pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOHM_1, ®); | |
722 | rc = ((reg << 6) | rc) << 26; | |
723 | ||
724 | return rc | 0x1ffffff; | |
725 | } | |
726 | ||
727 | static u64 haswell_rir_limit(u32 reg) | |
728 | { | |
729 | return (((u64)GET_BITFIELD(reg, 1, 11) + 1) << 29) - 1; | |
730 | } | |
731 | ||
4d715a80 AR |
732 | static inline u8 sad_pkg_socket(u8 pkg) |
733 | { | |
734 | /* on Ivy Bridge, nodeID is SASS, where A is HA and S is node id */ | |
2ff3a308 | 735 | return ((pkg >> 3) << 2) | (pkg & 0x3); |
4d715a80 AR |
736 | } |
737 | ||
738 | static inline u8 sad_pkg_ha(u8 pkg) | |
739 | { | |
740 | return (pkg >> 2) & 0x1; | |
741 | } | |
742 | ||
eebf11a0 MCC |
743 | /**************************************************************************** |
744 | Memory check routines | |
745 | ****************************************************************************/ | |
dbc954dd | 746 | static struct pci_dev *get_pdev_same_bus(u8 bus, u32 id) |
eebf11a0 | 747 | { |
dbc954dd | 748 | struct pci_dev *pdev = NULL; |
eebf11a0 | 749 | |
dbc954dd AR |
750 | do { |
751 | pdev = pci_get_device(PCI_VENDOR_ID_INTEL, id, pdev); | |
752 | if (pdev && pdev->bus->number == bus) | |
753 | break; | |
754 | } while (pdev); | |
eebf11a0 | 755 | |
dbc954dd | 756 | return pdev; |
eebf11a0 MCC |
757 | } |
758 | ||
759 | /** | |
c36e3e77 | 760 | * check_if_ecc_is_active() - Checks if ECC is active |
50d1bb93 AR |
761 | * @bus: Device bus |
762 | * @type: Memory controller type | |
763 | * returns: 0 in case ECC is active, -ENODEV if it can't be determined or | |
764 | * disabled | |
eebf11a0 | 765 | */ |
dbc954dd | 766 | static int check_if_ecc_is_active(const u8 bus, enum type type) |
eebf11a0 MCC |
767 | { |
768 | struct pci_dev *pdev = NULL; | |
dbc954dd | 769 | u32 mcmtr, id; |
eebf11a0 | 770 | |
dbc954dd AR |
771 | if (type == IVY_BRIDGE) |
772 | id = PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA; | |
50d1bb93 AR |
773 | else if (type == HASWELL) |
774 | id = PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA; | |
dbc954dd AR |
775 | else |
776 | id = PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA; | |
777 | ||
778 | pdev = get_pdev_same_bus(bus, id); | |
eebf11a0 MCC |
779 | if (!pdev) { |
780 | sbridge_printk(KERN_ERR, "Couldn't find PCI device " | |
dbc954dd AR |
781 | "%04x:%04x! on bus %02d\n", |
782 | PCI_VENDOR_ID_INTEL, id, bus); | |
eebf11a0 MCC |
783 | return -ENODEV; |
784 | } | |
785 | ||
786 | pci_read_config_dword(pdev, MCMTR, &mcmtr); | |
787 | if (!IS_ECC_ENABLED(mcmtr)) { | |
788 | sbridge_printk(KERN_ERR, "ECC is disabled. Aborting\n"); | |
789 | return -ENODEV; | |
790 | } | |
eebf11a0 MCC |
791 | return 0; |
792 | } | |
793 | ||
084a4fcc | 794 | static int get_dimm_config(struct mem_ctl_info *mci) |
eebf11a0 MCC |
795 | { |
796 | struct sbridge_pvt *pvt = mci->pvt_info; | |
c36e3e77 | 797 | struct dimm_info *dimm; |
deb09dda MCC |
798 | unsigned i, j, banks, ranks, rows, cols, npages; |
799 | u64 size; | |
eebf11a0 MCC |
800 | u32 reg; |
801 | enum edac_type mode; | |
c6e13b52 | 802 | enum mem_type mtype; |
eebf11a0 | 803 | |
50d1bb93 AR |
804 | if (pvt->info.type == HASWELL) |
805 | pci_read_config_dword(pvt->pci_sad1, SAD_TARGET, ®); | |
806 | else | |
807 | pci_read_config_dword(pvt->pci_br0, SAD_TARGET, ®); | |
808 | ||
eebf11a0 MCC |
809 | pvt->sbridge_dev->source_id = SOURCE_ID(reg); |
810 | ||
f14d6892 | 811 | pvt->sbridge_dev->node_id = pvt->info.get_node_id(pvt); |
956b9ba1 JP |
812 | edac_dbg(0, "mc#%d: Node ID: %d, source ID: %d\n", |
813 | pvt->sbridge_dev->mc, | |
814 | pvt->sbridge_dev->node_id, | |
815 | pvt->sbridge_dev->source_id); | |
eebf11a0 MCC |
816 | |
817 | pci_read_config_dword(pvt->pci_ras, RASENABLES, ®); | |
818 | if (IS_MIRROR_ENABLED(reg)) { | |
956b9ba1 | 819 | edac_dbg(0, "Memory mirror is enabled\n"); |
eebf11a0 MCC |
820 | pvt->is_mirrored = true; |
821 | } else { | |
956b9ba1 | 822 | edac_dbg(0, "Memory mirror is disabled\n"); |
eebf11a0 MCC |
823 | pvt->is_mirrored = false; |
824 | } | |
825 | ||
826 | pci_read_config_dword(pvt->pci_ta, MCMTR, &pvt->info.mcmtr); | |
827 | if (IS_LOCKSTEP_ENABLED(pvt->info.mcmtr)) { | |
956b9ba1 | 828 | edac_dbg(0, "Lockstep is enabled\n"); |
eebf11a0 MCC |
829 | mode = EDAC_S8ECD8ED; |
830 | pvt->is_lockstep = true; | |
831 | } else { | |
956b9ba1 | 832 | edac_dbg(0, "Lockstep is disabled\n"); |
eebf11a0 MCC |
833 | mode = EDAC_S4ECD4ED; |
834 | pvt->is_lockstep = false; | |
835 | } | |
836 | if (IS_CLOSE_PG(pvt->info.mcmtr)) { | |
956b9ba1 | 837 | edac_dbg(0, "address map is on closed page mode\n"); |
eebf11a0 MCC |
838 | pvt->is_close_pg = true; |
839 | } else { | |
956b9ba1 | 840 | edac_dbg(0, "address map is on open page mode\n"); |
eebf11a0 MCC |
841 | pvt->is_close_pg = false; |
842 | } | |
843 | ||
9e375446 | 844 | mtype = pvt->info.get_memory_type(pvt); |
50d1bb93 | 845 | if (mtype == MEM_RDDR3 || mtype == MEM_RDDR4) |
9e375446 AR |
846 | edac_dbg(0, "Memory is registered\n"); |
847 | else if (mtype == MEM_UNKNOWN) | |
de4772c6 | 848 | edac_dbg(0, "Cannot determine memory type\n"); |
9e375446 AR |
849 | else |
850 | edac_dbg(0, "Memory is unregistered\n"); | |
eebf11a0 | 851 | |
50d1bb93 AR |
852 | if (mtype == MEM_DDR4 || MEM_RDDR4) |
853 | banks = 16; | |
854 | else | |
855 | banks = 8; | |
eebf11a0 MCC |
856 | |
857 | for (i = 0; i < NUM_CHANNELS; i++) { | |
858 | u32 mtr; | |
859 | ||
860 | for (j = 0; j < ARRAY_SIZE(mtr_regs); j++) { | |
c36e3e77 MCC |
861 | dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers, |
862 | i, j, 0); | |
eebf11a0 MCC |
863 | pci_read_config_dword(pvt->pci_tad[i], |
864 | mtr_regs[j], &mtr); | |
956b9ba1 | 865 | edac_dbg(4, "Channel #%d MTR%d = %x\n", i, j, mtr); |
eebf11a0 MCC |
866 | if (IS_DIMM_PRESENT(mtr)) { |
867 | pvt->channel[i].dimms++; | |
868 | ||
50d1bb93 | 869 | ranks = numrank(pvt->info.type, mtr); |
eebf11a0 MCC |
870 | rows = numrow(mtr); |
871 | cols = numcol(mtr); | |
872 | ||
deb09dda | 873 | size = ((u64)rows * cols * banks * ranks) >> (20 - 3); |
eebf11a0 MCC |
874 | npages = MiB_TO_PAGES(size); |
875 | ||
deb09dda | 876 | edac_dbg(0, "mc#%d: channel %d, dimm %d, %Ld Mb (%d pages) bank: %d, rank: %d, row: %#x, col: %#x\n", |
956b9ba1 JP |
877 | pvt->sbridge_dev->mc, i, j, |
878 | size, npages, | |
879 | banks, ranks, rows, cols); | |
eebf11a0 | 880 | |
a895bf8b | 881 | dimm->nr_pages = npages; |
084a4fcc | 882 | dimm->grain = 32; |
50d1bb93 AR |
883 | switch (banks) { |
884 | case 16: | |
885 | dimm->dtype = DEV_X16; | |
886 | break; | |
887 | case 8: | |
888 | dimm->dtype = DEV_X8; | |
889 | break; | |
890 | case 4: | |
891 | dimm->dtype = DEV_X4; | |
892 | break; | |
893 | } | |
084a4fcc MCC |
894 | dimm->mtype = mtype; |
895 | dimm->edac_mode = mode; | |
896 | snprintf(dimm->label, sizeof(dimm->label), | |
eebf11a0 MCC |
897 | "CPU_SrcID#%u_Channel#%u_DIMM#%u", |
898 | pvt->sbridge_dev->source_id, i, j); | |
eebf11a0 MCC |
899 | } |
900 | } | |
901 | } | |
902 | ||
903 | return 0; | |
904 | } | |
905 | ||
906 | static void get_memory_layout(const struct mem_ctl_info *mci) | |
907 | { | |
908 | struct sbridge_pvt *pvt = mci->pvt_info; | |
909 | int i, j, k, n_sads, n_tads, sad_interl; | |
910 | u32 reg; | |
911 | u64 limit, prv = 0; | |
912 | u64 tmp_mb; | |
8c009100 | 913 | u32 gb, mb; |
eebf11a0 MCC |
914 | u32 rir_way; |
915 | ||
916 | /* | |
917 | * Step 1) Get TOLM/TOHM ranges | |
918 | */ | |
919 | ||
fb79a509 | 920 | pvt->tolm = pvt->info.get_tolm(pvt); |
eebf11a0 MCC |
921 | tmp_mb = (1 + pvt->tolm) >> 20; |
922 | ||
8c009100 JS |
923 | gb = div_u64_rem(tmp_mb, 1024, &mb); |
924 | edac_dbg(0, "TOLM: %u.%03u GB (0x%016Lx)\n", | |
925 | gb, (mb*1000)/1024, (u64)pvt->tolm); | |
eebf11a0 MCC |
926 | |
927 | /* Address range is already 45:25 */ | |
8fd6a43a | 928 | pvt->tohm = pvt->info.get_tohm(pvt); |
eebf11a0 MCC |
929 | tmp_mb = (1 + pvt->tohm) >> 20; |
930 | ||
8c009100 JS |
931 | gb = div_u64_rem(tmp_mb, 1024, &mb); |
932 | edac_dbg(0, "TOHM: %u.%03u GB (0x%016Lx)\n", | |
933 | gb, (mb*1000)/1024, (u64)pvt->tohm); | |
eebf11a0 MCC |
934 | |
935 | /* | |
936 | * Step 2) Get SAD range and SAD Interleave list | |
937 | * TAD registers contain the interleave wayness. However, it | |
938 | * seems simpler to just discover it indirectly, with the | |
939 | * algorithm bellow. | |
940 | */ | |
941 | prv = 0; | |
464f1d82 | 942 | for (n_sads = 0; n_sads < pvt->info.max_sad; n_sads++) { |
eebf11a0 | 943 | /* SAD_LIMIT Address range is 45:26 */ |
464f1d82 | 944 | pci_read_config_dword(pvt->pci_sad0, pvt->info.dram_rule[n_sads], |
eebf11a0 MCC |
945 | ®); |
946 | limit = SAD_LIMIT(reg); | |
947 | ||
948 | if (!DRAM_RULE_ENABLE(reg)) | |
949 | continue; | |
950 | ||
951 | if (limit <= prv) | |
952 | break; | |
953 | ||
954 | tmp_mb = (limit + 1) >> 20; | |
8c009100 | 955 | gb = div_u64_rem(tmp_mb, 1024, &mb); |
956b9ba1 JP |
956 | edac_dbg(0, "SAD#%d %s up to %u.%03u GB (0x%016Lx) Interleave: %s reg=0x%08x\n", |
957 | n_sads, | |
958 | get_dram_attr(reg), | |
8c009100 | 959 | gb, (mb*1000)/1024, |
956b9ba1 JP |
960 | ((u64)tmp_mb) << 20L, |
961 | INTERLEAVE_MODE(reg) ? "8:6" : "[8:6]XOR[18:16]", | |
962 | reg); | |
eebf11a0 MCC |
963 | prv = limit; |
964 | ||
ef1ce51e | 965 | pci_read_config_dword(pvt->pci_sad0, pvt->info.interleave_list[n_sads], |
eebf11a0 | 966 | ®); |
cc311991 | 967 | sad_interl = sad_pkg(pvt->info.interleave_pkg, reg, 0); |
eebf11a0 | 968 | for (j = 0; j < 8; j++) { |
cc311991 AR |
969 | u32 pkg = sad_pkg(pvt->info.interleave_pkg, reg, j); |
970 | if (j > 0 && sad_interl == pkg) | |
eebf11a0 MCC |
971 | break; |
972 | ||
956b9ba1 | 973 | edac_dbg(0, "SAD#%d, interleave #%d: %d\n", |
cc311991 | 974 | n_sads, j, pkg); |
eebf11a0 MCC |
975 | } |
976 | } | |
977 | ||
978 | /* | |
979 | * Step 3) Get TAD range | |
980 | */ | |
981 | prv = 0; | |
982 | for (n_tads = 0; n_tads < MAX_TAD; n_tads++) { | |
983 | pci_read_config_dword(pvt->pci_ha0, tad_dram_rule[n_tads], | |
984 | ®); | |
985 | limit = TAD_LIMIT(reg); | |
986 | if (limit <= prv) | |
987 | break; | |
988 | tmp_mb = (limit + 1) >> 20; | |
989 | ||
8c009100 | 990 | gb = div_u64_rem(tmp_mb, 1024, &mb); |
956b9ba1 | 991 | edac_dbg(0, "TAD#%d: up to %u.%03u GB (0x%016Lx), socket interleave %d, memory interleave %d, TGT: %d, %d, %d, %d, reg=0x%08x\n", |
8c009100 | 992 | n_tads, gb, (mb*1000)/1024, |
956b9ba1 JP |
993 | ((u64)tmp_mb) << 20L, |
994 | (u32)TAD_SOCK(reg), | |
995 | (u32)TAD_CH(reg), | |
996 | (u32)TAD_TGT0(reg), | |
997 | (u32)TAD_TGT1(reg), | |
998 | (u32)TAD_TGT2(reg), | |
999 | (u32)TAD_TGT3(reg), | |
1000 | reg); | |
7fae0db4 | 1001 | prv = limit; |
eebf11a0 MCC |
1002 | } |
1003 | ||
1004 | /* | |
1005 | * Step 4) Get TAD offsets, per each channel | |
1006 | */ | |
1007 | for (i = 0; i < NUM_CHANNELS; i++) { | |
1008 | if (!pvt->channel[i].dimms) | |
1009 | continue; | |
1010 | for (j = 0; j < n_tads; j++) { | |
1011 | pci_read_config_dword(pvt->pci_tad[i], | |
1012 | tad_ch_nilv_offset[j], | |
1013 | ®); | |
1014 | tmp_mb = TAD_OFFSET(reg) >> 20; | |
8c009100 | 1015 | gb = div_u64_rem(tmp_mb, 1024, &mb); |
956b9ba1 JP |
1016 | edac_dbg(0, "TAD CH#%d, offset #%d: %u.%03u GB (0x%016Lx), reg=0x%08x\n", |
1017 | i, j, | |
8c009100 | 1018 | gb, (mb*1000)/1024, |
956b9ba1 JP |
1019 | ((u64)tmp_mb) << 20L, |
1020 | reg); | |
eebf11a0 MCC |
1021 | } |
1022 | } | |
1023 | ||
1024 | /* | |
1025 | * Step 6) Get RIR Wayness/Limit, per each channel | |
1026 | */ | |
1027 | for (i = 0; i < NUM_CHANNELS; i++) { | |
1028 | if (!pvt->channel[i].dimms) | |
1029 | continue; | |
1030 | for (j = 0; j < MAX_RIR_RANGES; j++) { | |
1031 | pci_read_config_dword(pvt->pci_tad[i], | |
1032 | rir_way_limit[j], | |
1033 | ®); | |
1034 | ||
1035 | if (!IS_RIR_VALID(reg)) | |
1036 | continue; | |
1037 | ||
b976bcf2 | 1038 | tmp_mb = pvt->info.rir_limit(reg) >> 20; |
eebf11a0 | 1039 | rir_way = 1 << RIR_WAY(reg); |
8c009100 | 1040 | gb = div_u64_rem(tmp_mb, 1024, &mb); |
956b9ba1 JP |
1041 | edac_dbg(0, "CH#%d RIR#%d, limit: %u.%03u GB (0x%016Lx), way: %d, reg=0x%08x\n", |
1042 | i, j, | |
8c009100 | 1043 | gb, (mb*1000)/1024, |
956b9ba1 JP |
1044 | ((u64)tmp_mb) << 20L, |
1045 | rir_way, | |
1046 | reg); | |
eebf11a0 MCC |
1047 | |
1048 | for (k = 0; k < rir_way; k++) { | |
1049 | pci_read_config_dword(pvt->pci_tad[i], | |
1050 | rir_offset[j][k], | |
1051 | ®); | |
1052 | tmp_mb = RIR_OFFSET(reg) << 6; | |
1053 | ||
8c009100 | 1054 | gb = div_u64_rem(tmp_mb, 1024, &mb); |
956b9ba1 JP |
1055 | edac_dbg(0, "CH#%d RIR#%d INTL#%d, offset %u.%03u GB (0x%016Lx), tgt: %d, reg=0x%08x\n", |
1056 | i, j, k, | |
8c009100 | 1057 | gb, (mb*1000)/1024, |
956b9ba1 JP |
1058 | ((u64)tmp_mb) << 20L, |
1059 | (u32)RIR_RNK_TGT(reg), | |
1060 | reg); | |
eebf11a0 MCC |
1061 | } |
1062 | } | |
1063 | } | |
1064 | } | |
1065 | ||
8112c0cd | 1066 | static struct mem_ctl_info *get_mci_for_node_id(u8 node_id) |
eebf11a0 MCC |
1067 | { |
1068 | struct sbridge_dev *sbridge_dev; | |
1069 | ||
1070 | list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) { | |
1071 | if (sbridge_dev->node_id == node_id) | |
1072 | return sbridge_dev->mci; | |
1073 | } | |
1074 | return NULL; | |
1075 | } | |
1076 | ||
1077 | static int get_memory_error_data(struct mem_ctl_info *mci, | |
1078 | u64 addr, | |
1079 | u8 *socket, | |
1080 | long *channel_mask, | |
1081 | u8 *rank, | |
e17a2f42 | 1082 | char **area_type, char *msg) |
eebf11a0 MCC |
1083 | { |
1084 | struct mem_ctl_info *new_mci; | |
1085 | struct sbridge_pvt *pvt = mci->pvt_info; | |
4d715a80 | 1086 | struct pci_dev *pci_ha; |
c41afdca | 1087 | int n_rir, n_sads, n_tads, sad_way, sck_xch; |
eebf11a0 | 1088 | int sad_interl, idx, base_ch; |
50d1bb93 | 1089 | int interleave_mode, shiftup = 0; |
ef1ce51e | 1090 | unsigned sad_interleave[pvt->info.max_interleave]; |
50d1bb93 | 1091 | u32 reg, dram_rule; |
4d715a80 | 1092 | u8 ch_way, sck_way, pkg, sad_ha = 0; |
eebf11a0 MCC |
1093 | u32 tad_offset; |
1094 | u32 rir_way; | |
8c009100 | 1095 | u32 mb, gb; |
bd4b9683 | 1096 | u64 ch_addr, offset, limit = 0, prv = 0; |
eebf11a0 MCC |
1097 | |
1098 | ||
1099 | /* | |
1100 | * Step 0) Check if the address is at special memory ranges | |
1101 | * The check bellow is probably enough to fill all cases where | |
1102 | * the error is not inside a memory, except for the legacy | |
1103 | * range (e. g. VGA addresses). It is unlikely, however, that the | |
1104 | * memory controller would generate an error on that range. | |
1105 | */ | |
5b889e37 | 1106 | if ((addr > (u64) pvt->tolm) && (addr < (1LL << 32))) { |
eebf11a0 | 1107 | sprintf(msg, "Error at TOLM area, on addr 0x%08Lx", addr); |
eebf11a0 MCC |
1108 | return -EINVAL; |
1109 | } | |
1110 | if (addr >= (u64)pvt->tohm) { | |
1111 | sprintf(msg, "Error at MMIOH area, on addr 0x%016Lx", addr); | |
eebf11a0 MCC |
1112 | return -EINVAL; |
1113 | } | |
1114 | ||
1115 | /* | |
1116 | * Step 1) Get socket | |
1117 | */ | |
464f1d82 AR |
1118 | for (n_sads = 0; n_sads < pvt->info.max_sad; n_sads++) { |
1119 | pci_read_config_dword(pvt->pci_sad0, pvt->info.dram_rule[n_sads], | |
eebf11a0 MCC |
1120 | ®); |
1121 | ||
1122 | if (!DRAM_RULE_ENABLE(reg)) | |
1123 | continue; | |
1124 | ||
1125 | limit = SAD_LIMIT(reg); | |
1126 | if (limit <= prv) { | |
1127 | sprintf(msg, "Can't discover the memory socket"); | |
eebf11a0 MCC |
1128 | return -EINVAL; |
1129 | } | |
1130 | if (addr <= limit) | |
1131 | break; | |
1132 | prv = limit; | |
1133 | } | |
464f1d82 | 1134 | if (n_sads == pvt->info.max_sad) { |
eebf11a0 | 1135 | sprintf(msg, "Can't discover the memory socket"); |
eebf11a0 MCC |
1136 | return -EINVAL; |
1137 | } | |
50d1bb93 AR |
1138 | dram_rule = reg; |
1139 | *area_type = get_dram_attr(dram_rule); | |
1140 | interleave_mode = INTERLEAVE_MODE(dram_rule); | |
eebf11a0 | 1141 | |
ef1ce51e | 1142 | pci_read_config_dword(pvt->pci_sad0, pvt->info.interleave_list[n_sads], |
eebf11a0 | 1143 | ®); |
4d715a80 AR |
1144 | |
1145 | if (pvt->info.type == SANDY_BRIDGE) { | |
1146 | sad_interl = sad_pkg(pvt->info.interleave_pkg, reg, 0); | |
1147 | for (sad_way = 0; sad_way < 8; sad_way++) { | |
1148 | u32 pkg = sad_pkg(pvt->info.interleave_pkg, reg, sad_way); | |
1149 | if (sad_way > 0 && sad_interl == pkg) | |
1150 | break; | |
1151 | sad_interleave[sad_way] = pkg; | |
1152 | edac_dbg(0, "SAD interleave #%d: %d\n", | |
1153 | sad_way, sad_interleave[sad_way]); | |
1154 | } | |
1155 | edac_dbg(0, "mc#%d: Error detected on SAD#%d: address 0x%016Lx < 0x%016Lx, Interleave [%d:6]%s\n", | |
1156 | pvt->sbridge_dev->mc, | |
1157 | n_sads, | |
1158 | addr, | |
1159 | limit, | |
1160 | sad_way + 7, | |
1161 | !interleave_mode ? "" : "XOR[18:16]"); | |
1162 | if (interleave_mode) | |
1163 | idx = ((addr >> 6) ^ (addr >> 16)) & 7; | |
1164 | else | |
1165 | idx = (addr >> 6) & 7; | |
1166 | switch (sad_way) { | |
1167 | case 1: | |
1168 | idx = 0; | |
eebf11a0 | 1169 | break; |
4d715a80 AR |
1170 | case 2: |
1171 | idx = idx & 1; | |
1172 | break; | |
1173 | case 4: | |
1174 | idx = idx & 3; | |
1175 | break; | |
1176 | case 8: | |
1177 | break; | |
1178 | default: | |
1179 | sprintf(msg, "Can't discover socket interleave"); | |
1180 | return -EINVAL; | |
1181 | } | |
1182 | *socket = sad_interleave[idx]; | |
1183 | edac_dbg(0, "SAD interleave index: %d (wayness %d) = CPU socket %d\n", | |
1184 | idx, sad_way, *socket); | |
50d1bb93 AR |
1185 | } else if (pvt->info.type == HASWELL) { |
1186 | int bits, a7mode = A7MODE(dram_rule); | |
1187 | ||
1188 | if (a7mode) { | |
1189 | /* A7 mode swaps P9 with P6 */ | |
1190 | bits = GET_BITFIELD(addr, 7, 8) << 1; | |
1191 | bits |= GET_BITFIELD(addr, 9, 9); | |
1192 | } else | |
1193 | bits = GET_BITFIELD(addr, 7, 9); | |
1194 | ||
1195 | if (interleave_mode) { | |
1196 | /* interleave mode will XOR {8,7,6} with {18,17,16} */ | |
1197 | idx = GET_BITFIELD(addr, 16, 18); | |
1198 | idx ^= bits; | |
1199 | } else | |
1200 | idx = bits; | |
1201 | ||
1202 | pkg = sad_pkg(pvt->info.interleave_pkg, reg, idx); | |
1203 | *socket = sad_pkg_socket(pkg); | |
1204 | sad_ha = sad_pkg_ha(pkg); | |
1205 | ||
1206 | if (a7mode) { | |
1207 | /* MCChanShiftUpEnable */ | |
1208 | pci_read_config_dword(pvt->pci_ha0, | |
1209 | HASWELL_HASYSDEFEATURE2, ®); | |
1210 | shiftup = GET_BITFIELD(reg, 22, 22); | |
1211 | } | |
1212 | ||
1213 | edac_dbg(0, "SAD interleave package: %d = CPU socket %d, HA %i, shiftup: %i\n", | |
1214 | idx, *socket, sad_ha, shiftup); | |
4d715a80 AR |
1215 | } else { |
1216 | /* Ivy Bridge's SAD mode doesn't support XOR interleave mode */ | |
eebf11a0 | 1217 | idx = (addr >> 6) & 7; |
4d715a80 AR |
1218 | pkg = sad_pkg(pvt->info.interleave_pkg, reg, idx); |
1219 | *socket = sad_pkg_socket(pkg); | |
1220 | sad_ha = sad_pkg_ha(pkg); | |
1221 | edac_dbg(0, "SAD interleave package: %d = CPU socket %d, HA %d\n", | |
1222 | idx, *socket, sad_ha); | |
eebf11a0 | 1223 | } |
eebf11a0 MCC |
1224 | |
1225 | /* | |
1226 | * Move to the proper node structure, in order to access the | |
1227 | * right PCI registers | |
1228 | */ | |
1229 | new_mci = get_mci_for_node_id(*socket); | |
1230 | if (!new_mci) { | |
1231 | sprintf(msg, "Struct for socket #%u wasn't initialized", | |
1232 | *socket); | |
eebf11a0 MCC |
1233 | return -EINVAL; |
1234 | } | |
1235 | mci = new_mci; | |
1236 | pvt = mci->pvt_info; | |
1237 | ||
1238 | /* | |
1239 | * Step 2) Get memory channel | |
1240 | */ | |
1241 | prv = 0; | |
4d715a80 AR |
1242 | if (pvt->info.type == SANDY_BRIDGE) |
1243 | pci_ha = pvt->pci_ha0; | |
1244 | else { | |
1245 | if (sad_ha) | |
1246 | pci_ha = pvt->pci_ha1; | |
1247 | else | |
1248 | pci_ha = pvt->pci_ha0; | |
1249 | } | |
eebf11a0 | 1250 | for (n_tads = 0; n_tads < MAX_TAD; n_tads++) { |
4d715a80 | 1251 | pci_read_config_dword(pci_ha, tad_dram_rule[n_tads], ®); |
eebf11a0 MCC |
1252 | limit = TAD_LIMIT(reg); |
1253 | if (limit <= prv) { | |
1254 | sprintf(msg, "Can't discover the memory channel"); | |
eebf11a0 MCC |
1255 | return -EINVAL; |
1256 | } | |
1257 | if (addr <= limit) | |
1258 | break; | |
1259 | prv = limit; | |
1260 | } | |
4d715a80 AR |
1261 | if (n_tads == MAX_TAD) { |
1262 | sprintf(msg, "Can't discover the memory channel"); | |
1263 | return -EINVAL; | |
1264 | } | |
1265 | ||
eebf11a0 MCC |
1266 | ch_way = TAD_CH(reg) + 1; |
1267 | sck_way = TAD_SOCK(reg) + 1; | |
eebf11a0 MCC |
1268 | |
1269 | if (ch_way == 3) | |
1270 | idx = addr >> 6; | |
1271 | else | |
50d1bb93 | 1272 | idx = (addr >> (6 + sck_way + shiftup)) & 0x3; |
eebf11a0 MCC |
1273 | idx = idx % ch_way; |
1274 | ||
1275 | /* | |
1276 | * FIXME: Shouldn't we use CHN_IDX_OFFSET() here, when ch_way == 3 ??? | |
1277 | */ | |
1278 | switch (idx) { | |
1279 | case 0: | |
1280 | base_ch = TAD_TGT0(reg); | |
1281 | break; | |
1282 | case 1: | |
1283 | base_ch = TAD_TGT1(reg); | |
1284 | break; | |
1285 | case 2: | |
1286 | base_ch = TAD_TGT2(reg); | |
1287 | break; | |
1288 | case 3: | |
1289 | base_ch = TAD_TGT3(reg); | |
1290 | break; | |
1291 | default: | |
1292 | sprintf(msg, "Can't discover the TAD target"); | |
eebf11a0 MCC |
1293 | return -EINVAL; |
1294 | } | |
1295 | *channel_mask = 1 << base_ch; | |
1296 | ||
4d715a80 AR |
1297 | pci_read_config_dword(pvt->pci_tad[base_ch], |
1298 | tad_ch_nilv_offset[n_tads], | |
1299 | &tad_offset); | |
1300 | ||
eebf11a0 MCC |
1301 | if (pvt->is_mirrored) { |
1302 | *channel_mask |= 1 << ((base_ch + 2) % 4); | |
1303 | switch(ch_way) { | |
1304 | case 2: | |
1305 | case 4: | |
1306 | sck_xch = 1 << sck_way * (ch_way >> 1); | |
1307 | break; | |
1308 | default: | |
1309 | sprintf(msg, "Invalid mirror set. Can't decode addr"); | |
eebf11a0 MCC |
1310 | return -EINVAL; |
1311 | } | |
1312 | } else | |
1313 | sck_xch = (1 << sck_way) * ch_way; | |
1314 | ||
1315 | if (pvt->is_lockstep) | |
1316 | *channel_mask |= 1 << ((base_ch + 1) % 4); | |
1317 | ||
1318 | offset = TAD_OFFSET(tad_offset); | |
1319 | ||
956b9ba1 JP |
1320 | edac_dbg(0, "TAD#%d: address 0x%016Lx < 0x%016Lx, socket interleave %d, channel interleave %d (offset 0x%08Lx), index %d, base ch: %d, ch mask: 0x%02lx\n", |
1321 | n_tads, | |
1322 | addr, | |
1323 | limit, | |
1324 | (u32)TAD_SOCK(reg), | |
1325 | ch_way, | |
1326 | offset, | |
1327 | idx, | |
1328 | base_ch, | |
1329 | *channel_mask); | |
eebf11a0 MCC |
1330 | |
1331 | /* Calculate channel address */ | |
1332 | /* Remove the TAD offset */ | |
1333 | ||
1334 | if (offset > addr) { | |
1335 | sprintf(msg, "Can't calculate ch addr: TAD offset 0x%08Lx is too high for addr 0x%08Lx!", | |
1336 | offset, addr); | |
eebf11a0 MCC |
1337 | return -EINVAL; |
1338 | } | |
1339 | addr -= offset; | |
1340 | /* Store the low bits [0:6] of the addr */ | |
1341 | ch_addr = addr & 0x7f; | |
1342 | /* Remove socket wayness and remove 6 bits */ | |
1343 | addr >>= 6; | |
5b889e37 | 1344 | addr = div_u64(addr, sck_xch); |
eebf11a0 MCC |
1345 | #if 0 |
1346 | /* Divide by channel way */ | |
1347 | addr = addr / ch_way; | |
1348 | #endif | |
1349 | /* Recover the last 6 bits */ | |
1350 | ch_addr |= addr << 6; | |
1351 | ||
1352 | /* | |
1353 | * Step 3) Decode rank | |
1354 | */ | |
1355 | for (n_rir = 0; n_rir < MAX_RIR_RANGES; n_rir++) { | |
1356 | pci_read_config_dword(pvt->pci_tad[base_ch], | |
1357 | rir_way_limit[n_rir], | |
1358 | ®); | |
1359 | ||
1360 | if (!IS_RIR_VALID(reg)) | |
1361 | continue; | |
1362 | ||
b976bcf2 | 1363 | limit = pvt->info.rir_limit(reg); |
8c009100 | 1364 | gb = div_u64_rem(limit >> 20, 1024, &mb); |
956b9ba1 JP |
1365 | edac_dbg(0, "RIR#%d, limit: %u.%03u GB (0x%016Lx), way: %d\n", |
1366 | n_rir, | |
8c009100 | 1367 | gb, (mb*1000)/1024, |
956b9ba1 JP |
1368 | limit, |
1369 | 1 << RIR_WAY(reg)); | |
eebf11a0 MCC |
1370 | if (ch_addr <= limit) |
1371 | break; | |
1372 | } | |
1373 | if (n_rir == MAX_RIR_RANGES) { | |
1374 | sprintf(msg, "Can't discover the memory rank for ch addr 0x%08Lx", | |
1375 | ch_addr); | |
eebf11a0 MCC |
1376 | return -EINVAL; |
1377 | } | |
1378 | rir_way = RIR_WAY(reg); | |
50d1bb93 | 1379 | |
eebf11a0 MCC |
1380 | if (pvt->is_close_pg) |
1381 | idx = (ch_addr >> 6); | |
1382 | else | |
1383 | idx = (ch_addr >> 13); /* FIXME: Datasheet says to shift by 15 */ | |
1384 | idx %= 1 << rir_way; | |
1385 | ||
1386 | pci_read_config_dword(pvt->pci_tad[base_ch], | |
1387 | rir_offset[n_rir][idx], | |
1388 | ®); | |
1389 | *rank = RIR_RNK_TGT(reg); | |
1390 | ||
956b9ba1 JP |
1391 | edac_dbg(0, "RIR#%d: channel address 0x%08Lx < 0x%08Lx, RIR interleave %d, index %d\n", |
1392 | n_rir, | |
1393 | ch_addr, | |
1394 | limit, | |
1395 | rir_way, | |
1396 | idx); | |
eebf11a0 MCC |
1397 | |
1398 | return 0; | |
1399 | } | |
1400 | ||
1401 | /**************************************************************************** | |
1402 | Device initialization routines: put/get, init/exit | |
1403 | ****************************************************************************/ | |
1404 | ||
1405 | /* | |
1406 | * sbridge_put_all_devices 'put' all the devices that we have | |
1407 | * reserved via 'get' | |
1408 | */ | |
1409 | static void sbridge_put_devices(struct sbridge_dev *sbridge_dev) | |
1410 | { | |
1411 | int i; | |
1412 | ||
956b9ba1 | 1413 | edac_dbg(0, "\n"); |
eebf11a0 MCC |
1414 | for (i = 0; i < sbridge_dev->n_devs; i++) { |
1415 | struct pci_dev *pdev = sbridge_dev->pdev[i]; | |
1416 | if (!pdev) | |
1417 | continue; | |
956b9ba1 JP |
1418 | edac_dbg(0, "Removing dev %02x:%02x.%d\n", |
1419 | pdev->bus->number, | |
1420 | PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn)); | |
eebf11a0 MCC |
1421 | pci_dev_put(pdev); |
1422 | } | |
1423 | } | |
1424 | ||
1425 | static void sbridge_put_all_devices(void) | |
1426 | { | |
1427 | struct sbridge_dev *sbridge_dev, *tmp; | |
1428 | ||
1429 | list_for_each_entry_safe(sbridge_dev, tmp, &sbridge_edac_list, list) { | |
1430 | sbridge_put_devices(sbridge_dev); | |
1431 | free_sbridge_dev(sbridge_dev); | |
1432 | } | |
1433 | } | |
1434 | ||
eebf11a0 MCC |
1435 | static int sbridge_get_onedevice(struct pci_dev **prev, |
1436 | u8 *num_mc, | |
1437 | const struct pci_id_table *table, | |
1438 | const unsigned devno) | |
1439 | { | |
1440 | struct sbridge_dev *sbridge_dev; | |
1441 | const struct pci_id_descr *dev_descr = &table->descr[devno]; | |
eebf11a0 MCC |
1442 | struct pci_dev *pdev = NULL; |
1443 | u8 bus = 0; | |
1444 | ||
ec5a0b38 | 1445 | sbridge_printk(KERN_DEBUG, |
dbc954dd | 1446 | "Seeking for: PCI ID %04x:%04x\n", |
eebf11a0 MCC |
1447 | PCI_VENDOR_ID_INTEL, dev_descr->dev_id); |
1448 | ||
1449 | pdev = pci_get_device(PCI_VENDOR_ID_INTEL, | |
1450 | dev_descr->dev_id, *prev); | |
1451 | ||
1452 | if (!pdev) { | |
1453 | if (*prev) { | |
1454 | *prev = pdev; | |
1455 | return 0; | |
1456 | } | |
1457 | ||
1458 | if (dev_descr->optional) | |
1459 | return 0; | |
1460 | ||
dbc954dd | 1461 | /* if the HA wasn't found */ |
eebf11a0 MCC |
1462 | if (devno == 0) |
1463 | return -ENODEV; | |
1464 | ||
1465 | sbridge_printk(KERN_INFO, | |
dbc954dd | 1466 | "Device not found: %04x:%04x\n", |
eebf11a0 MCC |
1467 | PCI_VENDOR_ID_INTEL, dev_descr->dev_id); |
1468 | ||
1469 | /* End of list, leave */ | |
1470 | return -ENODEV; | |
1471 | } | |
1472 | bus = pdev->bus->number; | |
1473 | ||
1474 | sbridge_dev = get_sbridge_dev(bus); | |
1475 | if (!sbridge_dev) { | |
1476 | sbridge_dev = alloc_sbridge_dev(bus, table); | |
1477 | if (!sbridge_dev) { | |
1478 | pci_dev_put(pdev); | |
1479 | return -ENOMEM; | |
1480 | } | |
1481 | (*num_mc)++; | |
1482 | } | |
1483 | ||
1484 | if (sbridge_dev->pdev[devno]) { | |
1485 | sbridge_printk(KERN_ERR, | |
dbc954dd | 1486 | "Duplicated device for %04x:%04x\n", |
eebf11a0 MCC |
1487 | PCI_VENDOR_ID_INTEL, dev_descr->dev_id); |
1488 | pci_dev_put(pdev); | |
1489 | return -ENODEV; | |
1490 | } | |
1491 | ||
1492 | sbridge_dev->pdev[devno] = pdev; | |
1493 | ||
eebf11a0 MCC |
1494 | /* Be sure that the device is enabled */ |
1495 | if (unlikely(pci_enable_device(pdev) < 0)) { | |
1496 | sbridge_printk(KERN_ERR, | |
dbc954dd | 1497 | "Couldn't enable %04x:%04x\n", |
eebf11a0 MCC |
1498 | PCI_VENDOR_ID_INTEL, dev_descr->dev_id); |
1499 | return -ENODEV; | |
1500 | } | |
1501 | ||
dbc954dd | 1502 | edac_dbg(0, "Detected %04x:%04x\n", |
956b9ba1 | 1503 | PCI_VENDOR_ID_INTEL, dev_descr->dev_id); |
eebf11a0 MCC |
1504 | |
1505 | /* | |
1506 | * As stated on drivers/pci/search.c, the reference count for | |
1507 | * @from is always decremented if it is not %NULL. So, as we need | |
1508 | * to get all devices up to null, we need to do a get for the device | |
1509 | */ | |
1510 | pci_dev_get(pdev); | |
1511 | ||
1512 | *prev = pdev; | |
1513 | ||
1514 | return 0; | |
1515 | } | |
1516 | ||
5153a0f9 AR |
1517 | /* |
1518 | * sbridge_get_all_devices - Find and perform 'get' operation on the MCH's | |
dbc954dd | 1519 | * devices we want to reference for this driver. |
5153a0f9 | 1520 | * @num_mc: pointer to the memory controllers count, to be incremented in case |
c41afdca | 1521 | * of success. |
5153a0f9 AR |
1522 | * @table: model specific table |
1523 | * | |
1524 | * returns 0 in case of success or error code | |
1525 | */ | |
1526 | static int sbridge_get_all_devices(u8 *num_mc, | |
1527 | const struct pci_id_table *table) | |
eebf11a0 MCC |
1528 | { |
1529 | int i, rc; | |
1530 | struct pci_dev *pdev = NULL; | |
eebf11a0 MCC |
1531 | |
1532 | while (table && table->descr) { | |
1533 | for (i = 0; i < table->n_devs; i++) { | |
1534 | pdev = NULL; | |
1535 | do { | |
1536 | rc = sbridge_get_onedevice(&pdev, num_mc, | |
1537 | table, i); | |
1538 | if (rc < 0) { | |
1539 | if (i == 0) { | |
1540 | i = table->n_devs; | |
1541 | break; | |
1542 | } | |
1543 | sbridge_put_all_devices(); | |
1544 | return -ENODEV; | |
1545 | } | |
1546 | } while (pdev); | |
1547 | } | |
1548 | table++; | |
1549 | } | |
1550 | ||
1551 | return 0; | |
1552 | } | |
1553 | ||
ea779b5a AR |
1554 | static int sbridge_mci_bind_devs(struct mem_ctl_info *mci, |
1555 | struct sbridge_dev *sbridge_dev) | |
eebf11a0 MCC |
1556 | { |
1557 | struct sbridge_pvt *pvt = mci->pvt_info; | |
1558 | struct pci_dev *pdev; | |
dbc954dd | 1559 | int i; |
eebf11a0 MCC |
1560 | |
1561 | for (i = 0; i < sbridge_dev->n_devs; i++) { | |
1562 | pdev = sbridge_dev->pdev[i]; | |
1563 | if (!pdev) | |
1564 | continue; | |
dbc954dd AR |
1565 | |
1566 | switch (pdev->device) { | |
1567 | case PCI_DEVICE_ID_INTEL_SBRIDGE_SAD0: | |
1568 | pvt->pci_sad0 = pdev; | |
eebf11a0 | 1569 | break; |
dbc954dd AR |
1570 | case PCI_DEVICE_ID_INTEL_SBRIDGE_SAD1: |
1571 | pvt->pci_sad1 = pdev; | |
eebf11a0 | 1572 | break; |
dbc954dd AR |
1573 | case PCI_DEVICE_ID_INTEL_SBRIDGE_BR: |
1574 | pvt->pci_br0 = pdev; | |
eebf11a0 | 1575 | break; |
dbc954dd AR |
1576 | case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0: |
1577 | pvt->pci_ha0 = pdev; | |
eebf11a0 | 1578 | break; |
dbc954dd AR |
1579 | case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA: |
1580 | pvt->pci_ta = pdev; | |
1581 | break; | |
1582 | case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_RAS: | |
1583 | pvt->pci_ras = pdev; | |
1584 | break; | |
1585 | case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0: | |
1586 | case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD1: | |
1587 | case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD2: | |
1588 | case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD3: | |
1589 | { | |
1590 | int id = pdev->device - PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0; | |
1591 | pvt->pci_tad[id] = pdev; | |
1592 | } | |
1593 | break; | |
1594 | case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_DDRIO: | |
1595 | pvt->pci_ddrio = pdev; | |
eebf11a0 MCC |
1596 | break; |
1597 | default: | |
1598 | goto error; | |
1599 | } | |
1600 | ||
dbc954dd AR |
1601 | edac_dbg(0, "Associated PCI %02x:%02x, bus %d with dev = %p\n", |
1602 | pdev->vendor, pdev->device, | |
956b9ba1 | 1603 | sbridge_dev->bus, |
956b9ba1 | 1604 | pdev); |
eebf11a0 MCC |
1605 | } |
1606 | ||
1607 | /* Check if everything were registered */ | |
1608 | if (!pvt->pci_sad0 || !pvt->pci_sad1 || !pvt->pci_ha0 || | |
de4772c6 | 1609 | !pvt-> pci_tad || !pvt->pci_ras || !pvt->pci_ta) |
eebf11a0 MCC |
1610 | goto enodev; |
1611 | ||
1612 | for (i = 0; i < NUM_CHANNELS; i++) { | |
1613 | if (!pvt->pci_tad[i]) | |
1614 | goto enodev; | |
1615 | } | |
1616 | return 0; | |
1617 | ||
1618 | enodev: | |
1619 | sbridge_printk(KERN_ERR, "Some needed devices are missing\n"); | |
1620 | return -ENODEV; | |
1621 | ||
1622 | error: | |
dbc954dd AR |
1623 | sbridge_printk(KERN_ERR, "Unexpected device %02x:%02x\n", |
1624 | PCI_VENDOR_ID_INTEL, pdev->device); | |
eebf11a0 MCC |
1625 | return -EINVAL; |
1626 | } | |
1627 | ||
4d715a80 AR |
1628 | static int ibridge_mci_bind_devs(struct mem_ctl_info *mci, |
1629 | struct sbridge_dev *sbridge_dev) | |
1630 | { | |
1631 | struct sbridge_pvt *pvt = mci->pvt_info; | |
1632 | struct pci_dev *pdev, *tmp; | |
dbc954dd | 1633 | int i; |
4d715a80 AR |
1634 | bool mode_2ha = false; |
1635 | ||
1636 | tmp = pci_get_device(PCI_VENDOR_ID_INTEL, | |
1637 | PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1, NULL); | |
1638 | if (tmp) { | |
1639 | mode_2ha = true; | |
1640 | pci_dev_put(tmp); | |
1641 | } | |
1642 | ||
1643 | for (i = 0; i < sbridge_dev->n_devs; i++) { | |
1644 | pdev = sbridge_dev->pdev[i]; | |
1645 | if (!pdev) | |
1646 | continue; | |
4d715a80 | 1647 | |
dbc954dd AR |
1648 | switch (pdev->device) { |
1649 | case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0: | |
1650 | pvt->pci_ha0 = pdev; | |
1651 | break; | |
1652 | case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA: | |
1653 | pvt->pci_ta = pdev; | |
1654 | case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_RAS: | |
1655 | pvt->pci_ras = pdev; | |
1656 | break; | |
1657 | case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD2: | |
1658 | case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD3: | |
1659 | /* if we have 2 HAs active, channels 2 and 3 | |
1660 | * are in other device */ | |
1661 | if (mode_2ha) | |
4d715a80 | 1662 | break; |
dbc954dd AR |
1663 | /* fall through */ |
1664 | case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0: | |
1665 | case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD1: | |
1666 | { | |
1667 | int id = pdev->device - PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0; | |
1668 | pvt->pci_tad[id] = pdev; | |
1669 | } | |
4d715a80 | 1670 | break; |
dbc954dd AR |
1671 | case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_2HA_DDRIO0: |
1672 | pvt->pci_ddrio = pdev; | |
1673 | break; | |
1674 | case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_1HA_DDRIO0: | |
1675 | if (!mode_2ha) | |
4d715a80 | 1676 | pvt->pci_ddrio = pdev; |
4d715a80 | 1677 | break; |
dbc954dd AR |
1678 | case PCI_DEVICE_ID_INTEL_IBRIDGE_SAD: |
1679 | pvt->pci_sad0 = pdev; | |
1680 | break; | |
1681 | case PCI_DEVICE_ID_INTEL_IBRIDGE_BR0: | |
1682 | pvt->pci_br0 = pdev; | |
1683 | break; | |
1684 | case PCI_DEVICE_ID_INTEL_IBRIDGE_BR1: | |
1685 | pvt->pci_br1 = pdev; | |
1686 | break; | |
1687 | case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1: | |
1688 | pvt->pci_ha1 = pdev; | |
1689 | break; | |
1690 | case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0: | |
1691 | case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD1: | |
1692 | { | |
1693 | int id = pdev->device - PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0 + 2; | |
1694 | ||
4d715a80 AR |
1695 | /* we shouldn't have this device if we have just one |
1696 | * HA present */ | |
1697 | WARN_ON(!mode_2ha); | |
dbc954dd AR |
1698 | pvt->pci_tad[id] = pdev; |
1699 | } | |
1700 | break; | |
4d715a80 AR |
1701 | default: |
1702 | goto error; | |
1703 | } | |
1704 | ||
1705 | edac_dbg(0, "Associated PCI %02x.%02d.%d with dev = %p\n", | |
1706 | sbridge_dev->bus, | |
1707 | PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), | |
1708 | pdev); | |
1709 | } | |
1710 | ||
1711 | /* Check if everything were registered */ | |
1712 | if (!pvt->pci_sad0 || !pvt->pci_ha0 || !pvt->pci_br0 || | |
1713 | !pvt->pci_br1 || !pvt->pci_tad || !pvt->pci_ras || | |
1714 | !pvt->pci_ta) | |
1715 | goto enodev; | |
1716 | ||
1717 | for (i = 0; i < NUM_CHANNELS; i++) { | |
1718 | if (!pvt->pci_tad[i]) | |
1719 | goto enodev; | |
1720 | } | |
1721 | return 0; | |
1722 | ||
1723 | enodev: | |
1724 | sbridge_printk(KERN_ERR, "Some needed devices are missing\n"); | |
1725 | return -ENODEV; | |
1726 | ||
1727 | error: | |
1728 | sbridge_printk(KERN_ERR, | |
dbc954dd AR |
1729 | "Unexpected device %02x:%02x\n", PCI_VENDOR_ID_INTEL, |
1730 | pdev->device); | |
4d715a80 AR |
1731 | return -EINVAL; |
1732 | } | |
1733 | ||
50d1bb93 AR |
1734 | static int haswell_mci_bind_devs(struct mem_ctl_info *mci, |
1735 | struct sbridge_dev *sbridge_dev) | |
1736 | { | |
1737 | struct sbridge_pvt *pvt = mci->pvt_info; | |
1738 | struct pci_dev *pdev, *tmp; | |
1739 | int i; | |
1740 | bool mode_2ha = false; | |
1741 | ||
1742 | tmp = pci_get_device(PCI_VENDOR_ID_INTEL, | |
1743 | PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1, NULL); | |
1744 | if (tmp) { | |
1745 | mode_2ha = true; | |
1746 | pci_dev_put(tmp); | |
1747 | } | |
1748 | ||
1749 | /* there's only one device per system; not tied to any bus */ | |
1750 | if (pvt->info.pci_vtd == NULL) | |
1751 | /* result will be checked later */ | |
1752 | pvt->info.pci_vtd = pci_get_device(PCI_VENDOR_ID_INTEL, | |
1753 | PCI_DEVICE_ID_INTEL_HASWELL_IMC_VTD_MISC, | |
1754 | NULL); | |
1755 | ||
1756 | for (i = 0; i < sbridge_dev->n_devs; i++) { | |
1757 | pdev = sbridge_dev->pdev[i]; | |
1758 | if (!pdev) | |
1759 | continue; | |
1760 | ||
1761 | switch (pdev->device) { | |
1762 | case PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD0: | |
1763 | pvt->pci_sad0 = pdev; | |
1764 | break; | |
1765 | case PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD1: | |
1766 | pvt->pci_sad1 = pdev; | |
1767 | break; | |
1768 | case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0: | |
1769 | pvt->pci_ha0 = pdev; | |
1770 | break; | |
1771 | case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA: | |
1772 | pvt->pci_ta = pdev; | |
1773 | break; | |
1774 | case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_THERMAL: | |
1775 | pvt->pci_ras = pdev; | |
1776 | break; | |
1777 | case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD0: | |
1778 | pvt->pci_tad[0] = pdev; | |
1779 | break; | |
1780 | case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD1: | |
1781 | pvt->pci_tad[1] = pdev; | |
1782 | break; | |
1783 | case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD2: | |
1784 | if (!mode_2ha) | |
1785 | pvt->pci_tad[2] = pdev; | |
1786 | break; | |
1787 | case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD3: | |
1788 | if (!mode_2ha) | |
1789 | pvt->pci_tad[3] = pdev; | |
1790 | break; | |
1791 | case PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO0: | |
1792 | pvt->pci_ddrio = pdev; | |
1793 | break; | |
1794 | case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1: | |
1795 | pvt->pci_ha1 = pdev; | |
1796 | break; | |
1797 | case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TA: | |
1798 | pvt->pci_ha1_ta = pdev; | |
1799 | break; | |
1800 | case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD0: | |
1801 | if (mode_2ha) | |
1802 | pvt->pci_tad[2] = pdev; | |
1803 | break; | |
1804 | case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD1: | |
1805 | if (mode_2ha) | |
1806 | pvt->pci_tad[3] = pdev; | |
1807 | break; | |
1808 | default: | |
1809 | break; | |
1810 | } | |
1811 | ||
1812 | edac_dbg(0, "Associated PCI %02x.%02d.%d with dev = %p\n", | |
1813 | sbridge_dev->bus, | |
1814 | PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), | |
1815 | pdev); | |
1816 | } | |
1817 | ||
1818 | /* Check if everything were registered */ | |
1819 | if (!pvt->pci_sad0 || !pvt->pci_ha0 || !pvt->pci_sad1 || | |
1820 | !pvt->pci_ras || !pvt->pci_ta || !pvt->info.pci_vtd) | |
1821 | goto enodev; | |
1822 | ||
1823 | for (i = 0; i < NUM_CHANNELS; i++) { | |
1824 | if (!pvt->pci_tad[i]) | |
1825 | goto enodev; | |
1826 | } | |
1827 | return 0; | |
1828 | ||
1829 | enodev: | |
1830 | sbridge_printk(KERN_ERR, "Some needed devices are missing\n"); | |
1831 | return -ENODEV; | |
1832 | } | |
1833 | ||
eebf11a0 MCC |
1834 | /**************************************************************************** |
1835 | Error check routines | |
1836 | ****************************************************************************/ | |
1837 | ||
1838 | /* | |
1839 | * While Sandy Bridge has error count registers, SMI BIOS read values from | |
1840 | * and resets the counters. So, they are not reliable for the OS to read | |
1841 | * from them. So, we have no option but to just trust on whatever MCE is | |
1842 | * telling us about the errors. | |
1843 | */ | |
1844 | static void sbridge_mce_output_error(struct mem_ctl_info *mci, | |
1845 | const struct mce *m) | |
1846 | { | |
1847 | struct mem_ctl_info *new_mci; | |
1848 | struct sbridge_pvt *pvt = mci->pvt_info; | |
c36e3e77 | 1849 | enum hw_event_mc_err_type tp_event; |
e17a2f42 | 1850 | char *type, *optype, msg[256]; |
eebf11a0 MCC |
1851 | bool ripv = GET_BITFIELD(m->mcgstatus, 0, 0); |
1852 | bool overflow = GET_BITFIELD(m->status, 62, 62); | |
1853 | bool uncorrected_error = GET_BITFIELD(m->status, 61, 61); | |
4d715a80 | 1854 | bool recoverable; |
eebf11a0 MCC |
1855 | u32 core_err_cnt = GET_BITFIELD(m->status, 38, 52); |
1856 | u32 mscod = GET_BITFIELD(m->status, 16, 31); | |
1857 | u32 errcode = GET_BITFIELD(m->status, 0, 15); | |
1858 | u32 channel = GET_BITFIELD(m->status, 0, 3); | |
1859 | u32 optypenum = GET_BITFIELD(m->status, 4, 6); | |
1860 | long channel_mask, first_channel; | |
1861 | u8 rank, socket; | |
c36e3e77 | 1862 | int rc, dimm; |
e17a2f42 | 1863 | char *area_type = NULL; |
eebf11a0 | 1864 | |
4d715a80 AR |
1865 | if (pvt->info.type == IVY_BRIDGE) |
1866 | recoverable = true; | |
1867 | else | |
1868 | recoverable = GET_BITFIELD(m->status, 56, 56); | |
1869 | ||
c36e3e77 MCC |
1870 | if (uncorrected_error) { |
1871 | if (ripv) { | |
1872 | type = "FATAL"; | |
1873 | tp_event = HW_EVENT_ERR_FATAL; | |
1874 | } else { | |
1875 | type = "NON_FATAL"; | |
1876 | tp_event = HW_EVENT_ERR_UNCORRECTED; | |
1877 | } | |
1878 | } else { | |
1879 | type = "CORRECTED"; | |
1880 | tp_event = HW_EVENT_ERR_CORRECTED; | |
1881 | } | |
eebf11a0 MCC |
1882 | |
1883 | /* | |
15ed103a | 1884 | * According with Table 15-9 of the Intel Architecture spec vol 3A, |
eebf11a0 MCC |
1885 | * memory errors should fit in this mask: |
1886 | * 000f 0000 1mmm cccc (binary) | |
1887 | * where: | |
1888 | * f = Correction Report Filtering Bit. If 1, subsequent errors | |
1889 | * won't be shown | |
1890 | * mmm = error type | |
1891 | * cccc = channel | |
1892 | * If the mask doesn't match, report an error to the parsing logic | |
1893 | */ | |
1894 | if (! ((errcode & 0xef80) == 0x80)) { | |
1895 | optype = "Can't parse: it is not a mem"; | |
1896 | } else { | |
1897 | switch (optypenum) { | |
1898 | case 0: | |
c36e3e77 | 1899 | optype = "generic undef request error"; |
eebf11a0 MCC |
1900 | break; |
1901 | case 1: | |
c36e3e77 | 1902 | optype = "memory read error"; |
eebf11a0 MCC |
1903 | break; |
1904 | case 2: | |
c36e3e77 | 1905 | optype = "memory write error"; |
eebf11a0 MCC |
1906 | break; |
1907 | case 3: | |
c36e3e77 | 1908 | optype = "addr/cmd error"; |
eebf11a0 MCC |
1909 | break; |
1910 | case 4: | |
c36e3e77 | 1911 | optype = "memory scrubbing error"; |
eebf11a0 MCC |
1912 | break; |
1913 | default: | |
1914 | optype = "reserved"; | |
1915 | break; | |
1916 | } | |
1917 | } | |
1918 | ||
be3036d2 AR |
1919 | /* Only decode errors with an valid address (ADDRV) */ |
1920 | if (!GET_BITFIELD(m->status, 58, 58)) | |
1921 | return; | |
1922 | ||
eebf11a0 | 1923 | rc = get_memory_error_data(mci, m->addr, &socket, |
e17a2f42 | 1924 | &channel_mask, &rank, &area_type, msg); |
eebf11a0 | 1925 | if (rc < 0) |
c36e3e77 | 1926 | goto err_parsing; |
eebf11a0 MCC |
1927 | new_mci = get_mci_for_node_id(socket); |
1928 | if (!new_mci) { | |
c36e3e77 MCC |
1929 | strcpy(msg, "Error: socket got corrupted!"); |
1930 | goto err_parsing; | |
eebf11a0 MCC |
1931 | } |
1932 | mci = new_mci; | |
1933 | pvt = mci->pvt_info; | |
1934 | ||
1935 | first_channel = find_first_bit(&channel_mask, NUM_CHANNELS); | |
1936 | ||
1937 | if (rank < 4) | |
1938 | dimm = 0; | |
1939 | else if (rank < 8) | |
1940 | dimm = 1; | |
1941 | else | |
1942 | dimm = 2; | |
1943 | ||
eebf11a0 MCC |
1944 | |
1945 | /* | |
e17a2f42 MCC |
1946 | * FIXME: On some memory configurations (mirror, lockstep), the |
1947 | * Memory Controller can't point the error to a single DIMM. The | |
1948 | * EDAC core should be handling the channel mask, in order to point | |
1949 | * to the group of dimm's where the error may be happening. | |
eebf11a0 | 1950 | */ |
d7c660b7 AR |
1951 | if (!pvt->is_lockstep && !pvt->is_mirrored && !pvt->is_close_pg) |
1952 | channel = first_channel; | |
1953 | ||
c36e3e77 | 1954 | snprintf(msg, sizeof(msg), |
c1053839 | 1955 | "%s%s area:%s err_code:%04x:%04x socket:%d channel_mask:%ld rank:%d", |
e17a2f42 MCC |
1956 | overflow ? " OVERFLOW" : "", |
1957 | (uncorrected_error && recoverable) ? " recoverable" : "", | |
1958 | area_type, | |
1959 | mscod, errcode, | |
1960 | socket, | |
1961 | channel_mask, | |
1962 | rank); | |
eebf11a0 | 1963 | |
956b9ba1 | 1964 | edac_dbg(0, "%s\n", msg); |
eebf11a0 | 1965 | |
c36e3e77 MCC |
1966 | /* FIXME: need support for channel mask */ |
1967 | ||
351fc4a9 SJ |
1968 | if (channel == CHANNEL_UNSPECIFIED) |
1969 | channel = -1; | |
1970 | ||
eebf11a0 | 1971 | /* Call the helper to output message */ |
c1053839 | 1972 | edac_mc_handle_error(tp_event, mci, core_err_cnt, |
c36e3e77 MCC |
1973 | m->addr >> PAGE_SHIFT, m->addr & ~PAGE_MASK, 0, |
1974 | channel, dimm, -1, | |
03f7eae8 | 1975 | optype, msg); |
c36e3e77 MCC |
1976 | return; |
1977 | err_parsing: | |
c1053839 | 1978 | edac_mc_handle_error(tp_event, mci, core_err_cnt, 0, 0, 0, |
c36e3e77 | 1979 | -1, -1, -1, |
03f7eae8 | 1980 | msg, ""); |
eebf11a0 | 1981 | |
eebf11a0 MCC |
1982 | } |
1983 | ||
1984 | /* | |
1985 | * sbridge_check_error Retrieve and process errors reported by the | |
1986 | * hardware. Called by the Core module. | |
1987 | */ | |
1988 | static void sbridge_check_error(struct mem_ctl_info *mci) | |
1989 | { | |
1990 | struct sbridge_pvt *pvt = mci->pvt_info; | |
1991 | int i; | |
1992 | unsigned count = 0; | |
1993 | struct mce *m; | |
1994 | ||
1995 | /* | |
1996 | * MCE first step: Copy all mce errors into a temporary buffer | |
1997 | * We use a double buffering here, to reduce the risk of | |
1998 | * loosing an error. | |
1999 | */ | |
2000 | smp_rmb(); | |
2001 | count = (pvt->mce_out + MCE_LOG_LEN - pvt->mce_in) | |
2002 | % MCE_LOG_LEN; | |
2003 | if (!count) | |
2004 | return; | |
2005 | ||
2006 | m = pvt->mce_outentry; | |
2007 | if (pvt->mce_in + count > MCE_LOG_LEN) { | |
2008 | unsigned l = MCE_LOG_LEN - pvt->mce_in; | |
2009 | ||
2010 | memcpy(m, &pvt->mce_entry[pvt->mce_in], sizeof(*m) * l); | |
2011 | smp_wmb(); | |
2012 | pvt->mce_in = 0; | |
2013 | count -= l; | |
2014 | m += l; | |
2015 | } | |
2016 | memcpy(m, &pvt->mce_entry[pvt->mce_in], sizeof(*m) * count); | |
2017 | smp_wmb(); | |
2018 | pvt->mce_in += count; | |
2019 | ||
2020 | smp_rmb(); | |
2021 | if (pvt->mce_overrun) { | |
2022 | sbridge_printk(KERN_ERR, "Lost %d memory errors\n", | |
2023 | pvt->mce_overrun); | |
2024 | smp_wmb(); | |
2025 | pvt->mce_overrun = 0; | |
2026 | } | |
2027 | ||
2028 | /* | |
2029 | * MCE second step: parse errors and display | |
2030 | */ | |
2031 | for (i = 0; i < count; i++) | |
2032 | sbridge_mce_output_error(mci, &pvt->mce_outentry[i]); | |
2033 | } | |
2034 | ||
2035 | /* | |
2036 | * sbridge_mce_check_error Replicates mcelog routine to get errors | |
2037 | * This routine simply queues mcelog errors, and | |
2038 | * return. The error itself should be handled later | |
2039 | * by sbridge_check_error. | |
2040 | * WARNING: As this routine should be called at NMI time, extra care should | |
2041 | * be taken to avoid deadlocks, and to be as fast as possible. | |
2042 | */ | |
3d78c9af MCC |
2043 | static int sbridge_mce_check_error(struct notifier_block *nb, unsigned long val, |
2044 | void *data) | |
eebf11a0 | 2045 | { |
3d78c9af MCC |
2046 | struct mce *mce = (struct mce *)data; |
2047 | struct mem_ctl_info *mci; | |
2048 | struct sbridge_pvt *pvt; | |
cf40f80c | 2049 | char *type; |
3d78c9af | 2050 | |
fd521039 CG |
2051 | if (get_edac_report_status() == EDAC_REPORTING_DISABLED) |
2052 | return NOTIFY_DONE; | |
2053 | ||
3d78c9af MCC |
2054 | mci = get_mci_for_node_id(mce->socketid); |
2055 | if (!mci) | |
2056 | return NOTIFY_BAD; | |
2057 | pvt = mci->pvt_info; | |
eebf11a0 MCC |
2058 | |
2059 | /* | |
2060 | * Just let mcelog handle it if the error is | |
2061 | * outside the memory controller. A memory error | |
2062 | * is indicated by bit 7 = 1 and bits = 8-11,13-15 = 0. | |
2063 | * bit 12 has an special meaning. | |
2064 | */ | |
2065 | if ((mce->status & 0xefff) >> 7 != 1) | |
3d78c9af | 2066 | return NOTIFY_DONE; |
eebf11a0 | 2067 | |
cf40f80c AR |
2068 | if (mce->mcgstatus & MCG_STATUS_MCIP) |
2069 | type = "Exception"; | |
2070 | else | |
2071 | type = "Event"; | |
2072 | ||
49856dc9 | 2073 | sbridge_mc_printk(mci, KERN_DEBUG, "HANDLING MCE MEMORY ERROR\n"); |
eebf11a0 | 2074 | |
49856dc9 AR |
2075 | sbridge_mc_printk(mci, KERN_DEBUG, "CPU %d: Machine Check %s: %Lx " |
2076 | "Bank %d: %016Lx\n", mce->extcpu, type, | |
2077 | mce->mcgstatus, mce->bank, mce->status); | |
2078 | sbridge_mc_printk(mci, KERN_DEBUG, "TSC %llx ", mce->tsc); | |
2079 | sbridge_mc_printk(mci, KERN_DEBUG, "ADDR %llx ", mce->addr); | |
2080 | sbridge_mc_printk(mci, KERN_DEBUG, "MISC %llx ", mce->misc); | |
eebf11a0 | 2081 | |
49856dc9 AR |
2082 | sbridge_mc_printk(mci, KERN_DEBUG, "PROCESSOR %u:%x TIME %llu SOCKET " |
2083 | "%u APIC %x\n", mce->cpuvendor, mce->cpuid, | |
2084 | mce->time, mce->socketid, mce->apicid); | |
eebf11a0 | 2085 | |
eebf11a0 MCC |
2086 | smp_rmb(); |
2087 | if ((pvt->mce_out + 1) % MCE_LOG_LEN == pvt->mce_in) { | |
2088 | smp_wmb(); | |
2089 | pvt->mce_overrun++; | |
3d78c9af | 2090 | return NOTIFY_DONE; |
eebf11a0 MCC |
2091 | } |
2092 | ||
2093 | /* Copy memory error at the ringbuffer */ | |
2094 | memcpy(&pvt->mce_entry[pvt->mce_out], mce, sizeof(*mce)); | |
2095 | smp_wmb(); | |
2096 | pvt->mce_out = (pvt->mce_out + 1) % MCE_LOG_LEN; | |
2097 | ||
2098 | /* Handle fatal errors immediately */ | |
2099 | if (mce->mcgstatus & 1) | |
2100 | sbridge_check_error(mci); | |
2101 | ||
2102 | /* Advice mcelog that the error were handled */ | |
3d78c9af | 2103 | return NOTIFY_STOP; |
eebf11a0 MCC |
2104 | } |
2105 | ||
3d78c9af MCC |
2106 | static struct notifier_block sbridge_mce_dec = { |
2107 | .notifier_call = sbridge_mce_check_error, | |
2108 | }; | |
2109 | ||
eebf11a0 MCC |
2110 | /**************************************************************************** |
2111 | EDAC register/unregister logic | |
2112 | ****************************************************************************/ | |
2113 | ||
2114 | static void sbridge_unregister_mci(struct sbridge_dev *sbridge_dev) | |
2115 | { | |
2116 | struct mem_ctl_info *mci = sbridge_dev->mci; | |
2117 | struct sbridge_pvt *pvt; | |
2118 | ||
2119 | if (unlikely(!mci || !mci->pvt_info)) { | |
956b9ba1 | 2120 | edac_dbg(0, "MC: dev = %p\n", &sbridge_dev->pdev[0]->dev); |
eebf11a0 MCC |
2121 | |
2122 | sbridge_printk(KERN_ERR, "Couldn't find mci handler\n"); | |
2123 | return; | |
2124 | } | |
2125 | ||
2126 | pvt = mci->pvt_info; | |
2127 | ||
956b9ba1 JP |
2128 | edac_dbg(0, "MC: mci = %p, dev = %p\n", |
2129 | mci, &sbridge_dev->pdev[0]->dev); | |
eebf11a0 | 2130 | |
eebf11a0 | 2131 | /* Remove MC sysfs nodes */ |
fd687502 | 2132 | edac_mc_del_mc(mci->pdev); |
eebf11a0 | 2133 | |
956b9ba1 | 2134 | edac_dbg(1, "%s: free mci struct\n", mci->ctl_name); |
eebf11a0 MCC |
2135 | kfree(mci->ctl_name); |
2136 | edac_mc_free(mci); | |
2137 | sbridge_dev->mci = NULL; | |
2138 | } | |
2139 | ||
4d715a80 | 2140 | static int sbridge_register_mci(struct sbridge_dev *sbridge_dev, enum type type) |
eebf11a0 MCC |
2141 | { |
2142 | struct mem_ctl_info *mci; | |
c36e3e77 | 2143 | struct edac_mc_layer layers[2]; |
eebf11a0 | 2144 | struct sbridge_pvt *pvt; |
4d715a80 | 2145 | struct pci_dev *pdev = sbridge_dev->pdev[0]; |
c36e3e77 | 2146 | int rc; |
eebf11a0 MCC |
2147 | |
2148 | /* Check the number of active and not disabled channels */ | |
dbc954dd | 2149 | rc = check_if_ecc_is_active(sbridge_dev->bus, type); |
eebf11a0 MCC |
2150 | if (unlikely(rc < 0)) |
2151 | return rc; | |
2152 | ||
2153 | /* allocate a new MC control structure */ | |
c36e3e77 MCC |
2154 | layers[0].type = EDAC_MC_LAYER_CHANNEL; |
2155 | layers[0].size = NUM_CHANNELS; | |
2156 | layers[0].is_virt_csrow = false; | |
2157 | layers[1].type = EDAC_MC_LAYER_SLOT; | |
2158 | layers[1].size = MAX_DIMMS; | |
2159 | layers[1].is_virt_csrow = true; | |
ca0907b9 | 2160 | mci = edac_mc_alloc(sbridge_dev->mc, ARRAY_SIZE(layers), layers, |
c36e3e77 MCC |
2161 | sizeof(*pvt)); |
2162 | ||
eebf11a0 MCC |
2163 | if (unlikely(!mci)) |
2164 | return -ENOMEM; | |
2165 | ||
956b9ba1 | 2166 | edac_dbg(0, "MC: mci = %p, dev = %p\n", |
4d715a80 | 2167 | mci, &pdev->dev); |
eebf11a0 MCC |
2168 | |
2169 | pvt = mci->pvt_info; | |
2170 | memset(pvt, 0, sizeof(*pvt)); | |
2171 | ||
2172 | /* Associate sbridge_dev and mci for future usage */ | |
2173 | pvt->sbridge_dev = sbridge_dev; | |
2174 | sbridge_dev->mci = mci; | |
2175 | ||
2176 | mci->mtype_cap = MEM_FLAG_DDR3; | |
2177 | mci->edac_ctl_cap = EDAC_FLAG_NONE; | |
2178 | mci->edac_cap = EDAC_FLAG_NONE; | |
2179 | mci->mod_name = "sbridge_edac.c"; | |
2180 | mci->mod_ver = SBRIDGE_REVISION; | |
4d715a80 | 2181 | mci->dev_name = pci_name(pdev); |
eebf11a0 MCC |
2182 | mci->ctl_page_to_phys = NULL; |
2183 | ||
2184 | /* Set the function pointer to an actual operation function */ | |
2185 | mci->edac_check = sbridge_check_error; | |
2186 | ||
4d715a80 | 2187 | pvt->info.type = type; |
50d1bb93 AR |
2188 | switch (type) { |
2189 | case IVY_BRIDGE: | |
4d715a80 AR |
2190 | pvt->info.rankcfgr = IB_RANK_CFG_A; |
2191 | pvt->info.get_tolm = ibridge_get_tolm; | |
2192 | pvt->info.get_tohm = ibridge_get_tohm; | |
2193 | pvt->info.dram_rule = ibridge_dram_rule; | |
9e375446 | 2194 | pvt->info.get_memory_type = get_memory_type; |
f14d6892 | 2195 | pvt->info.get_node_id = get_node_id; |
b976bcf2 | 2196 | pvt->info.rir_limit = rir_limit; |
4d715a80 AR |
2197 | pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule); |
2198 | pvt->info.interleave_list = ibridge_interleave_list; | |
2199 | pvt->info.max_interleave = ARRAY_SIZE(ibridge_interleave_list); | |
2200 | pvt->info.interleave_pkg = ibridge_interleave_pkg; | |
2201 | mci->ctl_name = kasprintf(GFP_KERNEL, "Ivy Bridge Socket#%d", mci->mc_idx); | |
2202 | ||
2203 | /* Store pci devices at mci for faster access */ | |
2204 | rc = ibridge_mci_bind_devs(mci, sbridge_dev); | |
2205 | if (unlikely(rc < 0)) | |
2206 | goto fail0; | |
50d1bb93 AR |
2207 | break; |
2208 | case SANDY_BRIDGE: | |
4d715a80 AR |
2209 | pvt->info.rankcfgr = SB_RANK_CFG_A; |
2210 | pvt->info.get_tolm = sbridge_get_tolm; | |
2211 | pvt->info.get_tohm = sbridge_get_tohm; | |
2212 | pvt->info.dram_rule = sbridge_dram_rule; | |
9e375446 | 2213 | pvt->info.get_memory_type = get_memory_type; |
f14d6892 | 2214 | pvt->info.get_node_id = get_node_id; |
b976bcf2 | 2215 | pvt->info.rir_limit = rir_limit; |
4d715a80 AR |
2216 | pvt->info.max_sad = ARRAY_SIZE(sbridge_dram_rule); |
2217 | pvt->info.interleave_list = sbridge_interleave_list; | |
2218 | pvt->info.max_interleave = ARRAY_SIZE(sbridge_interleave_list); | |
2219 | pvt->info.interleave_pkg = sbridge_interleave_pkg; | |
2220 | mci->ctl_name = kasprintf(GFP_KERNEL, "Sandy Bridge Socket#%d", mci->mc_idx); | |
2221 | ||
2222 | /* Store pci devices at mci for faster access */ | |
2223 | rc = sbridge_mci_bind_devs(mci, sbridge_dev); | |
2224 | if (unlikely(rc < 0)) | |
2225 | goto fail0; | |
50d1bb93 AR |
2226 | break; |
2227 | case HASWELL: | |
2228 | /* rankcfgr isn't used */ | |
2229 | pvt->info.get_tolm = haswell_get_tolm; | |
2230 | pvt->info.get_tohm = haswell_get_tohm; | |
2231 | pvt->info.dram_rule = ibridge_dram_rule; | |
2232 | pvt->info.get_memory_type = haswell_get_memory_type; | |
2233 | pvt->info.get_node_id = haswell_get_node_id; | |
2234 | pvt->info.rir_limit = haswell_rir_limit; | |
2235 | pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule); | |
2236 | pvt->info.interleave_list = ibridge_interleave_list; | |
2237 | pvt->info.max_interleave = ARRAY_SIZE(ibridge_interleave_list); | |
2238 | pvt->info.interleave_pkg = ibridge_interleave_pkg; | |
2239 | mci->ctl_name = kasprintf(GFP_KERNEL, "Haswell Socket#%d", mci->mc_idx); | |
4d715a80 | 2240 | |
50d1bb93 AR |
2241 | /* Store pci devices at mci for faster access */ |
2242 | rc = haswell_mci_bind_devs(mci, sbridge_dev); | |
2243 | if (unlikely(rc < 0)) | |
2244 | goto fail0; | |
2245 | break; | |
2246 | } | |
eebf11a0 MCC |
2247 | |
2248 | /* Get dimm basic config and the memory layout */ | |
2249 | get_dimm_config(mci); | |
2250 | get_memory_layout(mci); | |
2251 | ||
2252 | /* record ptr to the generic device */ | |
4d715a80 | 2253 | mci->pdev = &pdev->dev; |
eebf11a0 MCC |
2254 | |
2255 | /* add this new MC control structure to EDAC's list of MCs */ | |
2256 | if (unlikely(edac_mc_add_mc(mci))) { | |
956b9ba1 | 2257 | edac_dbg(0, "MC: failed edac_mc_add_mc()\n"); |
eebf11a0 MCC |
2258 | rc = -EINVAL; |
2259 | goto fail0; | |
2260 | } | |
2261 | ||
eebf11a0 | 2262 | return 0; |
eebf11a0 MCC |
2263 | |
2264 | fail0: | |
2265 | kfree(mci->ctl_name); | |
2266 | edac_mc_free(mci); | |
2267 | sbridge_dev->mci = NULL; | |
2268 | return rc; | |
2269 | } | |
2270 | ||
2271 | /* | |
2272 | * sbridge_probe Probe for ONE instance of device to see if it is | |
2273 | * present. | |
2274 | * return: | |
2275 | * 0 for FOUND a device | |
2276 | * < 0 for error code | |
2277 | */ | |
2278 | ||
9b3c6e85 | 2279 | static int sbridge_probe(struct pci_dev *pdev, const struct pci_device_id *id) |
eebf11a0 | 2280 | { |
50d1bb93 | 2281 | int rc = -ENODEV; |
eebf11a0 MCC |
2282 | u8 mc, num_mc = 0; |
2283 | struct sbridge_dev *sbridge_dev; | |
50d1bb93 | 2284 | enum type type = SANDY_BRIDGE; |
eebf11a0 MCC |
2285 | |
2286 | /* get the pci devices we want to reserve for our use */ | |
2287 | mutex_lock(&sbridge_edac_lock); | |
2288 | ||
2289 | /* | |
2290 | * All memory controllers are allocated at the first pass. | |
2291 | */ | |
2292 | if (unlikely(probed >= 1)) { | |
2293 | mutex_unlock(&sbridge_edac_lock); | |
2294 | return -ENODEV; | |
2295 | } | |
2296 | probed++; | |
2297 | ||
50d1bb93 AR |
2298 | switch (pdev->device) { |
2299 | case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA: | |
4d715a80 AR |
2300 | rc = sbridge_get_all_devices(&num_mc, pci_dev_descr_ibridge_table); |
2301 | type = IVY_BRIDGE; | |
50d1bb93 AR |
2302 | break; |
2303 | case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA: | |
4d715a80 AR |
2304 | rc = sbridge_get_all_devices(&num_mc, pci_dev_descr_sbridge_table); |
2305 | type = SANDY_BRIDGE; | |
50d1bb93 AR |
2306 | break; |
2307 | case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0: | |
2308 | rc = sbridge_get_all_devices(&num_mc, pci_dev_descr_haswell_table); | |
2309 | type = HASWELL; | |
2310 | break; | |
4d715a80 | 2311 | } |
eebf11a0 MCC |
2312 | if (unlikely(rc < 0)) |
2313 | goto fail0; | |
2314 | mc = 0; | |
2315 | ||
2316 | list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) { | |
956b9ba1 JP |
2317 | edac_dbg(0, "Registering MC#%d (%d of %d)\n", |
2318 | mc, mc + 1, num_mc); | |
50d1bb93 | 2319 | |
eebf11a0 | 2320 | sbridge_dev->mc = mc++; |
4d715a80 | 2321 | rc = sbridge_register_mci(sbridge_dev, type); |
eebf11a0 MCC |
2322 | if (unlikely(rc < 0)) |
2323 | goto fail1; | |
2324 | } | |
2325 | ||
2326 | sbridge_printk(KERN_INFO, "Driver loaded.\n"); | |
2327 | ||
2328 | mutex_unlock(&sbridge_edac_lock); | |
2329 | return 0; | |
2330 | ||
2331 | fail1: | |
2332 | list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) | |
2333 | sbridge_unregister_mci(sbridge_dev); | |
2334 | ||
2335 | sbridge_put_all_devices(); | |
2336 | fail0: | |
2337 | mutex_unlock(&sbridge_edac_lock); | |
2338 | return rc; | |
2339 | } | |
2340 | ||
2341 | /* | |
2342 | * sbridge_remove destructor for one instance of device | |
2343 | * | |
2344 | */ | |
9b3c6e85 | 2345 | static void sbridge_remove(struct pci_dev *pdev) |
eebf11a0 MCC |
2346 | { |
2347 | struct sbridge_dev *sbridge_dev; | |
2348 | ||
956b9ba1 | 2349 | edac_dbg(0, "\n"); |
eebf11a0 MCC |
2350 | |
2351 | /* | |
2352 | * we have a trouble here: pdev value for removal will be wrong, since | |
2353 | * it will point to the X58 register used to detect that the machine | |
2354 | * is a Nehalem or upper design. However, due to the way several PCI | |
2355 | * devices are grouped together to provide MC functionality, we need | |
2356 | * to use a different method for releasing the devices | |
2357 | */ | |
2358 | ||
2359 | mutex_lock(&sbridge_edac_lock); | |
2360 | ||
2361 | if (unlikely(!probed)) { | |
2362 | mutex_unlock(&sbridge_edac_lock); | |
2363 | return; | |
2364 | } | |
2365 | ||
2366 | list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) | |
2367 | sbridge_unregister_mci(sbridge_dev); | |
2368 | ||
2369 | /* Release PCI resources */ | |
2370 | sbridge_put_all_devices(); | |
2371 | ||
2372 | probed--; | |
2373 | ||
2374 | mutex_unlock(&sbridge_edac_lock); | |
2375 | } | |
2376 | ||
2377 | MODULE_DEVICE_TABLE(pci, sbridge_pci_tbl); | |
2378 | ||
2379 | /* | |
2380 | * sbridge_driver pci_driver structure for this module | |
2381 | * | |
2382 | */ | |
2383 | static struct pci_driver sbridge_driver = { | |
2384 | .name = "sbridge_edac", | |
2385 | .probe = sbridge_probe, | |
9b3c6e85 | 2386 | .remove = sbridge_remove, |
eebf11a0 MCC |
2387 | .id_table = sbridge_pci_tbl, |
2388 | }; | |
2389 | ||
2390 | /* | |
2391 | * sbridge_init Module entry function | |
2392 | * Try to initialize this module for its devices | |
2393 | */ | |
2394 | static int __init sbridge_init(void) | |
2395 | { | |
2396 | int pci_rc; | |
2397 | ||
956b9ba1 | 2398 | edac_dbg(2, "\n"); |
eebf11a0 MCC |
2399 | |
2400 | /* Ensure that the OPSTATE is set correctly for POLL or NMI */ | |
2401 | opstate_init(); | |
2402 | ||
2403 | pci_rc = pci_register_driver(&sbridge_driver); | |
e35fca47 CG |
2404 | if (pci_rc >= 0) { |
2405 | mce_register_decode_chain(&sbridge_mce_dec); | |
fd521039 CG |
2406 | if (get_edac_report_status() == EDAC_REPORTING_DISABLED) |
2407 | sbridge_printk(KERN_WARNING, "Loading driver, error reporting disabled.\n"); | |
eebf11a0 | 2408 | return 0; |
e35fca47 | 2409 | } |
eebf11a0 MCC |
2410 | |
2411 | sbridge_printk(KERN_ERR, "Failed to register device with error %d.\n", | |
2412 | pci_rc); | |
2413 | ||
2414 | return pci_rc; | |
2415 | } | |
2416 | ||
2417 | /* | |
2418 | * sbridge_exit() Module exit function | |
2419 | * Unregister the driver | |
2420 | */ | |
2421 | static void __exit sbridge_exit(void) | |
2422 | { | |
956b9ba1 | 2423 | edac_dbg(2, "\n"); |
eebf11a0 | 2424 | pci_unregister_driver(&sbridge_driver); |
e35fca47 | 2425 | mce_unregister_decode_chain(&sbridge_mce_dec); |
eebf11a0 MCC |
2426 | } |
2427 | ||
2428 | module_init(sbridge_init); | |
2429 | module_exit(sbridge_exit); | |
2430 | ||
2431 | module_param(edac_op_state, int, 0444); | |
2432 | MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI"); | |
2433 | ||
2434 | MODULE_LICENSE("GPL"); | |
37e59f87 | 2435 | MODULE_AUTHOR("Mauro Carvalho Chehab"); |
eebf11a0 | 2436 | MODULE_AUTHOR("Red Hat Inc. (http://www.redhat.com)"); |
4d715a80 | 2437 | MODULE_DESCRIPTION("MC Driver for Intel Sandy Bridge and Ivy Bridge memory controllers - " |
eebf11a0 | 2438 | SBRIDGE_REVISION); |