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EDAC: Fix workqueues poll period resetting
[mirror_ubuntu-bionic-kernel.git] / drivers / edac / sb_edac.c
CommitLineData
eebf11a0
MCC		 1/* Intel Sandy Bridge -EN/-EP/-EX Memory Controller kernel module
2 *
3 * This driver supports the memory controllers found on the Intel
4 * processor family Sandy Bridge.
5 *
6 * This file may be distributed under the terms of the
7 * GNU General Public License version 2 only.
8 *
9 * Copyright (c) 2011 by:
37e59f87 10 * Mauro Carvalho Chehab
eebf11a0
MCC		 11 */
12
13#include <linux/module.h>
14#include <linux/init.h>
15#include <linux/pci.h>
16#include <linux/pci_ids.h>
17#include <linux/slab.h>
18#include <linux/delay.h>
19#include <linux/edac.h>
20#include <linux/mmzone.h>
eebf11a0
MCC		 21#include <linux/smp.h>
22#include <linux/bitmap.h>
5b889e37 23#include <linux/math64.h>
2c1ea4c7
TL		 24#include <linux/mod_devicetable.h>
25#include <asm/cpu_device_id.h>
eebf11a0 26#include <asm/processor.h>
3d78c9af 27#include <asm/mce.h>
eebf11a0
MCC		 28
29#include "edac_core.h"
30
31/* Static vars */
32static LIST_HEAD(sbridge_edac_list);
eebf11a0
MCC		 33
34/*
35 * Alter this version for the module when modifications are made
36 */
7d375bff 37#define SBRIDGE_REVISION " Ver: 1.1.1 "
eebf11a0
MCC		 38#define EDAC_MOD_STR "sbridge_edac"
39
40/*
41 * Debug macros
42 */
43#define sbridge_printk(level, fmt, arg...) \
44 edac_printk(level, "sbridge", fmt, ##arg)
45
46#define sbridge_mc_printk(mci, level, fmt, arg...) \
47 edac_mc_chipset_printk(mci, level, "sbridge", fmt, ##arg)
48
49/*
50 * Get a bit field at register value <v>, from bit <lo> to bit <hi>
51 */
52#define GET_BITFIELD(v, lo, hi) \
10ef6b0d 53 (((v) & GENMASK_ULL(hi, lo)) >> (lo))
eebf11a0 54
eebf11a0 55/* Devices 12 Function 6, Offsets 0x80 to 0xcc */
464f1d82 56static const u32 sbridge_dram_rule[] = {
eebf11a0
MCC		 57 0x80, 0x88, 0x90, 0x98, 0xa0,
58 0xa8, 0xb0, 0xb8, 0xc0, 0xc8,
59};
eebf11a0 60
4d715a80
AR		 61static const u32 ibridge_dram_rule[] = {
62 0x60, 0x68, 0x70, 0x78, 0x80,
63 0x88, 0x90, 0x98, 0xa0, 0xa8,
64 0xb0, 0xb8, 0xc0, 0xc8, 0xd0,
65 0xd8, 0xe0, 0xe8, 0xf0, 0xf8,
66};
eebf11a0 67
d0cdf900
JS		 68static const u32 knl_dram_rule[] = {
69 0x60, 0x68, 0x70, 0x78, 0x80, /* 0-4 */
70 0x88, 0x90, 0x98, 0xa0, 0xa8, /* 5-9 */
71 0xb0, 0xb8, 0xc0, 0xc8, 0xd0, /* 10-14 */
72 0xd8, 0xe0, 0xe8, 0xf0, 0xf8, /* 15-19 */
73 0x100, 0x108, 0x110, 0x118, /* 20-23 */
74};
75
eebf11a0 76#define DRAM_RULE_ENABLE(reg) GET_BITFIELD(reg, 0, 0)
50d1bb93 77#define A7MODE(reg) GET_BITFIELD(reg, 26, 26)
eebf11a0 78
c59f9c06 79static char *show_dram_attr(u32 attr)
eebf11a0 80{
c59f9c06 81 switch (attr) {
eebf11a0
MCC		 82 case 0:
83 return "DRAM";
84 case 1:
85 return "MMCFG";
86 case 2:
87 return "NXM";
88 default:
89 return "unknown";
90 }
91}
92
ef1ce51e 93static const u32 sbridge_interleave_list[] = {
eebf11a0
MCC		 94 0x84, 0x8c, 0x94, 0x9c, 0xa4,
95 0xac, 0xb4, 0xbc, 0xc4, 0xcc,
96};
eebf11a0 97
4d715a80
AR		 98static const u32 ibridge_interleave_list[] = {
99 0x64, 0x6c, 0x74, 0x7c, 0x84,
100 0x8c, 0x94, 0x9c, 0xa4, 0xac,
101 0xb4, 0xbc, 0xc4, 0xcc, 0xd4,
102 0xdc, 0xe4, 0xec, 0xf4, 0xfc,
103};
104
d0cdf900
JS		 105static const u32 knl_interleave_list[] = {
106 0x64, 0x6c, 0x74, 0x7c, 0x84, /* 0-4 */
107 0x8c, 0x94, 0x9c, 0xa4, 0xac, /* 5-9 */
108 0xb4, 0xbc, 0xc4, 0xcc, 0xd4, /* 10-14 */
109 0xdc, 0xe4, 0xec, 0xf4, 0xfc, /* 15-19 */
110 0x104, 0x10c, 0x114, 0x11c, /* 20-23 */
111};
112
cc311991
AR		 113struct interleave_pkg {
114 unsigned char start;
115 unsigned char end;
116};
117
118static const struct interleave_pkg sbridge_interleave_pkg[] = {
119 { 0, 2 },
120 { 3, 5 },
121 { 8, 10 },
122 { 11, 13 },
123 { 16, 18 },
124 { 19, 21 },
125 { 24, 26 },
126 { 27, 29 },
127};
128
4d715a80
AR		 129static const struct interleave_pkg ibridge_interleave_pkg[] = {
130 { 0, 3 },
131 { 4, 7 },
132 { 8, 11 },
133 { 12, 15 },
134 { 16, 19 },
135 { 20, 23 },
136 { 24, 27 },
137 { 28, 31 },
138};
139
cc311991
AR		 140static inline int sad_pkg(const struct interleave_pkg *table, u32 reg,
141 int interleave)
eebf11a0 142{
cc311991
AR		 143 return GET_BITFIELD(reg, table[interleave].start,
144 table[interleave].end);
eebf11a0
MCC		 145}
146
147/* Devices 12 Function 7 */
148
149#define TOLM 0x80
d0cdf900 150#define TOHM 0x84
f7cf2a22 151#define HASWELL_TOLM 0xd0
50d1bb93
AR		 152#define HASWELL_TOHM_0 0xd4
153#define HASWELL_TOHM_1 0xd8
d0cdf900
JS		 154#define KNL_TOLM 0xd0
155#define KNL_TOHM_0 0xd4
156#define KNL_TOHM_1 0xd8
eebf11a0
MCC		 157
158#define GET_TOLM(reg) ((GET_BITFIELD(reg, 0, 3) << 28) | 0x3ffffff)
159#define GET_TOHM(reg) ((GET_BITFIELD(reg, 0, 20) << 25) | 0x3ffffff)
160
161/* Device 13 Function 6 */
162
163#define SAD_TARGET 0xf0
164
165#define SOURCE_ID(reg) GET_BITFIELD(reg, 9, 11)
166
d0cdf900
JS		 167#define SOURCE_ID_KNL(reg) GET_BITFIELD(reg, 12, 14)
168
eebf11a0
MCC		 169#define SAD_CONTROL 0xf4
170
eebf11a0
MCC		 171/* Device 14 function 0 */
172
173static const u32 tad_dram_rule[] = {
174 0x40, 0x44, 0x48, 0x4c,
175 0x50, 0x54, 0x58, 0x5c,
176 0x60, 0x64, 0x68, 0x6c,
177};
178#define MAX_TAD ARRAY_SIZE(tad_dram_rule)
179
180#define TAD_LIMIT(reg) ((GET_BITFIELD(reg, 12, 31) << 26) | 0x3ffffff)
181#define TAD_SOCK(reg) GET_BITFIELD(reg, 10, 11)
182#define TAD_CH(reg) GET_BITFIELD(reg, 8, 9)
183#define TAD_TGT3(reg) GET_BITFIELD(reg, 6, 7)
184#define TAD_TGT2(reg) GET_BITFIELD(reg, 4, 5)
185#define TAD_TGT1(reg) GET_BITFIELD(reg, 2, 3)
186#define TAD_TGT0(reg) GET_BITFIELD(reg, 0, 1)
187
188/* Device 15, function 0 */
189
190#define MCMTR 0x7c
d0cdf900 191#define KNL_MCMTR 0x624
eebf11a0
MCC		 192
193#define IS_ECC_ENABLED(mcmtr) GET_BITFIELD(mcmtr, 2, 2)
194#define IS_LOCKSTEP_ENABLED(mcmtr) GET_BITFIELD(mcmtr, 1, 1)
195#define IS_CLOSE_PG(mcmtr) GET_BITFIELD(mcmtr, 0, 0)
196
197/* Device 15, function 1 */
198
199#define RASENABLES 0xac
200#define IS_MIRROR_ENABLED(reg) GET_BITFIELD(reg, 0, 0)
201
202/* Device 15, functions 2-5 */
203
204static const int mtr_regs[] = {
205 0x80, 0x84, 0x88,
206};
207
d0cdf900
JS		 208static const int knl_mtr_reg = 0xb60;
209
eebf11a0
MCC		 210#define RANK_DISABLE(mtr) GET_BITFIELD(mtr, 16, 19)
211#define IS_DIMM_PRESENT(mtr) GET_BITFIELD(mtr, 14, 14)
212#define RANK_CNT_BITS(mtr) GET_BITFIELD(mtr, 12, 13)
213#define RANK_WIDTH_BITS(mtr) GET_BITFIELD(mtr, 2, 4)
214#define COL_WIDTH_BITS(mtr) GET_BITFIELD(mtr, 0, 1)
215
216static const u32 tad_ch_nilv_offset[] = {
217 0x90, 0x94, 0x98, 0x9c,
218 0xa0, 0xa4, 0xa8, 0xac,
219 0xb0, 0xb4, 0xb8, 0xbc,
220};
221#define CHN_IDX_OFFSET(reg) GET_BITFIELD(reg, 28, 29)
222#define TAD_OFFSET(reg) (GET_BITFIELD(reg, 6, 25) << 26)
223
224static const u32 rir_way_limit[] = {
225 0x108, 0x10c, 0x110, 0x114, 0x118,
226};
227#define MAX_RIR_RANGES ARRAY_SIZE(rir_way_limit)
228
229#define IS_RIR_VALID(reg) GET_BITFIELD(reg, 31, 31)
230#define RIR_WAY(reg) GET_BITFIELD(reg, 28, 29)
eebf11a0
MCC		 231
232#define MAX_RIR_WAY 8
233
234static const u32 rir_offset[MAX_RIR_RANGES][MAX_RIR_WAY] = {
235 { 0x120, 0x124, 0x128, 0x12c, 0x130, 0x134, 0x138, 0x13c },
236 { 0x140, 0x144, 0x148, 0x14c, 0x150, 0x154, 0x158, 0x15c },
237 { 0x160, 0x164, 0x168, 0x16c, 0x170, 0x174, 0x178, 0x17c },
238 { 0x180, 0x184, 0x188, 0x18c, 0x190, 0x194, 0x198, 0x19c },
239 { 0x1a0, 0x1a4, 0x1a8, 0x1ac, 0x1b0, 0x1b4, 0x1b8, 0x1bc },
240};
241
c7103f65
TL		 242#define RIR_RNK_TGT(type, reg) (((type) == BROADWELL) ? \
243 GET_BITFIELD(reg, 20, 23) : GET_BITFIELD(reg, 16, 19))
244
245#define RIR_OFFSET(type, reg) (((type) == HASWELL || (type) == BROADWELL) ? \
246 GET_BITFIELD(reg, 2, 15) : GET_BITFIELD(reg, 2, 14))
eebf11a0
MCC		 247
248/* Device 16, functions 2-7 */
249
250/*
251 * FIXME: Implement the error count reads directly
252 */
253
254static const u32 correrrcnt[] = {
255 0x104, 0x108, 0x10c, 0x110,
256};
257
258#define RANK_ODD_OV(reg) GET_BITFIELD(reg, 31, 31)
259#define RANK_ODD_ERR_CNT(reg) GET_BITFIELD(reg, 16, 30)
260#define RANK_EVEN_OV(reg) GET_BITFIELD(reg, 15, 15)
261#define RANK_EVEN_ERR_CNT(reg) GET_BITFIELD(reg, 0, 14)
262
263static const u32 correrrthrsld[] = {
264 0x11c, 0x120, 0x124, 0x128,
265};
266
267#define RANK_ODD_ERR_THRSLD(reg) GET_BITFIELD(reg, 16, 30)
268#define RANK_EVEN_ERR_THRSLD(reg) GET_BITFIELD(reg, 0, 14)
269
270
271/* Device 17, function 0 */
272
ef1e8d03 273#define SB_RANK_CFG_A 0x0328
eebf11a0 274
4d715a80 275#define IB_RANK_CFG_A 0x0320
eebf11a0 276
eebf11a0
MCC		 277/*
278 * sbridge structs
279 */
280
7d375bff 281#define NUM_CHANNELS 8 /* 2MC per socket, four chan per MC */
351fc4a9 282#define MAX_DIMMS 3 /* Max DIMMS per channel */
d0cdf900
JS		 283#define KNL_MAX_CHAS 38 /* KNL max num. of Cache Home Agents */
284#define KNL_MAX_CHANNELS 6 /* KNL max num. of PCI channels */
285#define KNL_MAX_EDCS 8 /* Embedded DRAM controllers */
351fc4a9 286#define CHANNEL_UNSPECIFIED 0xf /* Intel IA32 SDM 15-14 */
eebf11a0 287
4d715a80
AR		 288enum type {
289 SANDY_BRIDGE,
290 IVY_BRIDGE,
50d1bb93 291 HASWELL,
1f39581a 292 BROADWELL,
d0cdf900 293 KNIGHTS_LANDING,
4d715a80
AR		 294};
295
fb79a509 296struct sbridge_pvt;
eebf11a0 297struct sbridge_info {
4d715a80 298 enum type type;
464f1d82
AR		 299 u32 mcmtr;
300 u32 rankcfgr;
301 u64 (*get_tolm)(struct sbridge_pvt *pvt);
302 u64 (*get_tohm)(struct sbridge_pvt *pvt);
b976bcf2 303 u64 (*rir_limit)(u32 reg);
c59f9c06
JS		 304 u64 (*sad_limit)(u32 reg);
305 u32 (*interleave_mode)(u32 reg);
306 char* (*show_interleave_mode)(u32 reg);
307 u32 (*dram_attr)(u32 reg);
464f1d82 308 const u32 *dram_rule;
ef1ce51e 309 const u32 *interleave_list;
cc311991 310 const struct interleave_pkg *interleave_pkg;
464f1d82 311 u8 max_sad;
ef1ce51e 312 u8 max_interleave;
f14d6892 313 u8 (*get_node_id)(struct sbridge_pvt *pvt);
9e375446 314 enum mem_type (*get_memory_type)(struct sbridge_pvt *pvt);
12f0721c 315 enum dev_type (*get_width)(struct sbridge_pvt *pvt, u32 mtr);
50d1bb93 316 struct pci_dev *pci_vtd;
eebf11a0
MCC		 317};
318
319struct sbridge_channel {
320 u32 ranks;
321 u32 dimms;
322};
323
324struct pci_id_descr {
c41afdca 325 int dev_id;
eebf11a0
MCC		 326 int optional;
327};
328
329struct pci_id_table {
330 const struct pci_id_descr *descr;
331 int n_devs;
332};
333
334struct sbridge_dev {
335 struct list_head list;
336 u8 bus, mc;
337 u8 node_id, source_id;
338 struct pci_dev **pdev;
339 int n_devs;
340 struct mem_ctl_info *mci;
341};
342
d0cdf900
JS		 343struct knl_pvt {
344 struct pci_dev *pci_cha[KNL_MAX_CHAS];
345 struct pci_dev *pci_channel[KNL_MAX_CHANNELS];
346 struct pci_dev *pci_mc0;
347 struct pci_dev *pci_mc1;
348 struct pci_dev *pci_mc0_misc;
349 struct pci_dev *pci_mc1_misc;
350 struct pci_dev *pci_mc_info; /* tolm, tohm */
351};
352
eebf11a0
MCC		 353struct sbridge_pvt {
354 struct pci_dev *pci_ta, *pci_ddrio, *pci_ras;
4d715a80
AR		 355 struct pci_dev *pci_sad0, *pci_sad1;
356 struct pci_dev *pci_ha0, *pci_ha1;
357 struct pci_dev *pci_br0, *pci_br1;
50d1bb93 358 struct pci_dev *pci_ha1_ta;
eebf11a0
MCC		 359 struct pci_dev *pci_tad[NUM_CHANNELS];
360
361 struct sbridge_dev *sbridge_dev;
362
363 struct sbridge_info info;
364 struct sbridge_channel channel[NUM_CHANNELS];
365
eebf11a0
MCC		 366 /* Memory type detection */
367 bool is_mirrored, is_lockstep, is_close_pg;
ea5dfb5f 368 bool is_chan_hash;
eebf11a0 369
eebf11a0
MCC		 370 /* Memory description */
371 u64 tolm, tohm;
d0cdf900 372 struct knl_pvt knl;
eebf11a0
MCC		 373};
374
dbc954dd
AR		 375#define PCI_DESCR(device_id, opt) \
376 .dev_id = (device_id), \
de4772c6 377 .optional = opt
eebf11a0
MCC		 378
379static const struct pci_id_descr pci_dev_descr_sbridge[] = {
380 /* Processor Home Agent */
dbc954dd 381 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0, 0) },
eebf11a0
MCC		 382
383 /* Memory controller */
dbc954dd
AR		 384 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA, 0) },
385 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_RAS, 0) },
386 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0, 0) },
387 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD1, 0) },
388 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD2, 0) },
389 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD3, 0) },
390 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_DDRIO, 1) },
eebf11a0
MCC		 391
392 /* System Address Decoder */
dbc954dd
AR		 393 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_SAD0, 0) },
394 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_SAD1, 0) },
eebf11a0
MCC		 395
396 /* Broadcast Registers */
dbc954dd 397 { PCI_DESCR(PCI_DEVICE_ID_INTEL_SBRIDGE_BR, 0) },
eebf11a0
MCC		 398};
399
400#define PCI_ID_TABLE_ENTRY(A) { .descr=A, .n_devs = ARRAY_SIZE(A) }
401static const struct pci_id_table pci_dev_descr_sbridge_table[] = {
402 PCI_ID_TABLE_ENTRY(pci_dev_descr_sbridge),
403 {0,} /* 0 terminated list. */
404};
405
4d715a80
AR		 406/* This changes depending if 1HA or 2HA:
407 * 1HA:
408 * 0x0eb8 (17.0) is DDRIO0
409 * 2HA:
410 * 0x0ebc (17.4) is DDRIO0
411 */
412#define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_1HA_DDRIO0 0x0eb8
413#define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_2HA_DDRIO0 0x0ebc
414
415/* pci ids */
416#define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0 0x0ea0
417#define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA 0x0ea8
418#define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_RAS 0x0e71
419#define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0 0x0eaa
420#define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD1 0x0eab
421#define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD2 0x0eac
422#define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD3 0x0ead
423#define PCI_DEVICE_ID_INTEL_IBRIDGE_SAD 0x0ec8
424#define PCI_DEVICE_ID_INTEL_IBRIDGE_BR0 0x0ec9
425#define PCI_DEVICE_ID_INTEL_IBRIDGE_BR1 0x0eca
426#define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1 0x0e60
427#define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TA 0x0e68
428#define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_RAS 0x0e79
429#define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0 0x0e6a
430#define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD1 0x0e6b
7d375bff
TL		 431#define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD2 0x0e6c
432#define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD3 0x0e6d
4d715a80
AR		 433
434static const struct pci_id_descr pci_dev_descr_ibridge[] = {
435 /* Processor Home Agent */
dbc954dd 436 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0, 0) },
4d715a80
AR		 437
438 /* Memory controller */
dbc954dd
AR		 439 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA, 0) },
440 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_RAS, 0) },
441 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0, 0) },
442 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD1, 0) },
443 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD2, 0) },
444 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD3, 0) },
4d715a80
AR		 445
446 /* System Address Decoder */
dbc954dd 447 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_SAD, 0) },
4d715a80
AR		 448
449 /* Broadcast Registers */
dbc954dd
AR		 450 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_BR0, 1) },
451 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_BR1, 0) },
4d715a80
AR		 452
453 /* Optional, mode 2HA */
dbc954dd 454 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1, 1) },
4d715a80 455#if 0
dbc954dd
AR		 456 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TA, 1) },
457 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_RAS, 1) },
4d715a80 458#endif
dbc954dd
AR		 459 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0, 1) },
460 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD1, 1) },
7d375bff
TL		 461 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD2, 1) },
462 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD3, 1) },
4d715a80 463
dbc954dd
AR		 464 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_1HA_DDRIO0, 1) },
465 { PCI_DESCR(PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_2HA_DDRIO0, 1) },
4d715a80
AR		 466};
467
468static const struct pci_id_table pci_dev_descr_ibridge_table[] = {
469 PCI_ID_TABLE_ENTRY(pci_dev_descr_ibridge),
470 {0,} /* 0 terminated list. */
471};
472
50d1bb93
AR		 473/* Haswell support */
474/* EN processor:
475 * - 1 IMC
476 * - 3 DDR3 channels, 2 DPC per channel
477 * EP processor:
478 * - 1 or 2 IMC
479 * - 4 DDR4 channels, 3 DPC per channel
480 * EP 4S processor:
481 * - 2 IMC
482 * - 4 DDR4 channels, 3 DPC per channel
483 * EX processor:
484 * - 2 IMC
485 * - each IMC interfaces with a SMI 2 channel
486 * - each SMI channel interfaces with a scalable memory buffer
487 * - each scalable memory buffer supports 4 DDR3/DDR4 channels, 3 DPC
488 */
1f39581a 489#define HASWELL_DDRCRCLKCONTROLS 0xa10 /* Ditto on Broadwell */
50d1bb93
AR		 490#define HASWELL_HASYSDEFEATURE2 0x84
491#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_VTD_MISC 0x2f28
492#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0 0x2fa0
493#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1 0x2f60
494#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA 0x2fa8
495#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_THERMAL 0x2f71
496#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TA 0x2f68
497#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_THERMAL 0x2f79
498#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD0 0x2ffc
499#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD1 0x2ffd
500#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD0 0x2faa
501#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD1 0x2fab
502#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD2 0x2fac
503#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD3 0x2fad
504#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD0 0x2f6a
505#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD1 0x2f6b
506#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD2 0x2f6c
507#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD3 0x2f6d
508#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO0 0x2fbd
7179385a
AR		 509#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO1 0x2fbf
510#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO2 0x2fb9
511#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO3 0x2fbb
50d1bb93
AR		 512static const struct pci_id_descr pci_dev_descr_haswell[] = {
513 /* first item must be the HA */
514 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0, 0) },
515
516 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD0, 0) },
517 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD1, 0) },
518
519 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1, 1) },
520
521 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA, 0) },
522 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_THERMAL, 0) },
523 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD0, 0) },
524 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD1, 0) },
525 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD2, 1) },
526 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD3, 1) },
527
528 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO0, 1) },
7179385a
AR		 529 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO1, 1) },
530 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO2, 1) },
531 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO3, 1) },
50d1bb93
AR		 532
533 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TA, 1) },
534 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_THERMAL, 1) },
535 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD0, 1) },
536 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD1, 1) },
537 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD2, 1) },
538 { PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD3, 1) },
539};
540
541static const struct pci_id_table pci_dev_descr_haswell_table[] = {
542 PCI_ID_TABLE_ENTRY(pci_dev_descr_haswell),
543 {0,} /* 0 terminated list. */
544};
545
d0cdf900
JS		 546/* Knight's Landing Support */
547/*
548 * KNL's memory channels are swizzled between memory controllers.
549 * MC0 is mapped to CH3,5,6 and MC1 is mapped to CH0,1,2
550 */
551#define knl_channel_remap(channel) ((channel + 3) % 6)
552
553/* Memory controller, TAD tables, error injection - 2-8-0, 2-9-0 (2 of these) */
554#define PCI_DEVICE_ID_INTEL_KNL_IMC_MC 0x7840
555/* DRAM channel stuff; bank addrs, dimmmtr, etc.. 2-8-2 - 2-9-4 (6 of these) */
556#define PCI_DEVICE_ID_INTEL_KNL_IMC_CHANNEL 0x7843
557/* kdrwdbu TAD limits/offsets, MCMTR - 2-10-1, 2-11-1 (2 of these) */
558#define PCI_DEVICE_ID_INTEL_KNL_IMC_TA 0x7844
559/* CHA broadcast registers, dram rules - 1-29-0 (1 of these) */
560#define PCI_DEVICE_ID_INTEL_KNL_IMC_SAD0 0x782a
561/* SAD target - 1-29-1 (1 of these) */
562#define PCI_DEVICE_ID_INTEL_KNL_IMC_SAD1 0x782b
563/* Caching / Home Agent */
564#define PCI_DEVICE_ID_INTEL_KNL_IMC_CHA 0x782c
565/* Device with TOLM and TOHM, 0-5-0 (1 of these) */
566#define PCI_DEVICE_ID_INTEL_KNL_IMC_TOLHM 0x7810
567
568/*
569 * KNL differs from SB, IB, and Haswell in that it has multiple
570 * instances of the same device with the same device ID, so we handle that
571 * by creating as many copies in the table as we expect to find.
572 * (Like device ID must be grouped together.)
573 */
574
575static const struct pci_id_descr pci_dev_descr_knl[] = {
576 [0] = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_SAD0, 0) },
577 [1] = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_SAD1, 0) },
578 [2 ... 3] = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_MC, 0)},
579 [4 ... 41] = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_CHA, 0) },
580 [42 ... 47] = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_CHANNEL, 0) },
581 [48] = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_TA, 0) },
582 [49] = { PCI_DESCR(PCI_DEVICE_ID_INTEL_KNL_IMC_TOLHM, 0) },
583};
584
585static const struct pci_id_table pci_dev_descr_knl_table[] = {
586 PCI_ID_TABLE_ENTRY(pci_dev_descr_knl),
587 {0,}
588};
589
1f39581a
TL		 590/*
591 * Broadwell support
592 *
593 * DE processor:
594 * - 1 IMC
595 * - 2 DDR3 channels, 2 DPC per channel
fa2ce64f
TL		 596 * EP processor:
597 * - 1 or 2 IMC
598 * - 4 DDR4 channels, 3 DPC per channel
599 * EP 4S processor:
600 * - 2 IMC
601 * - 4 DDR4 channels, 3 DPC per channel
602 * EX processor:
603 * - 2 IMC
604 * - each IMC interfaces with a SMI 2 channel
605 * - each SMI channel interfaces with a scalable memory buffer
606 * - each scalable memory buffer supports 4 DDR3/DDR4 channels, 3 DPC
1f39581a
TL		 607 */
608#define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_VTD_MISC 0x6f28
609#define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0 0x6fa0
fa2ce64f 610#define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1 0x6f60
1f39581a
TL		 611#define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TA 0x6fa8
612#define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_THERMAL 0x6f71
fa2ce64f
TL		 613#define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TA 0x6f68
614#define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_THERMAL 0x6f79
1f39581a
TL		 615#define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD0 0x6ffc
616#define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD1 0x6ffd
617#define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD0 0x6faa
618#define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD1 0x6fab
619#define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD2 0x6fac
620#define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD3 0x6fad
fa2ce64f
TL		 621#define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD0 0x6f6a
622#define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD1 0x6f6b
623#define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD2 0x6f6c
624#define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD3 0x6f6d
1f39581a
TL		 625#define PCI_DEVICE_ID_INTEL_BROADWELL_IMC_DDRIO0 0x6faf
626
627static const struct pci_id_descr pci_dev_descr_broadwell[] = {
628 /* first item must be the HA */
629 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0, 0) },
630
631 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD0, 0) },
632 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD1, 0) },
633
fa2ce64f
TL		 634 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1, 1) },
635
1f39581a
TL		 636 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TA, 0) },
637 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_THERMAL, 0) },
638 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD0, 0) },
639 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD1, 0) },
fa2ce64f
TL		 640 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD2, 1) },
641 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD3, 1) },
642
1f39581a 643 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_DDRIO0, 1) },
fa2ce64f
TL		 644
645 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TA, 1) },
646 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_THERMAL, 1) },
647 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD0, 1) },
648 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD1, 1) },
649 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD2, 1) },
650 { PCI_DESCR(PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD3, 1) },
1f39581a
TL		 651};
652
653static const struct pci_id_table pci_dev_descr_broadwell_table[] = {
654 PCI_ID_TABLE_ENTRY(pci_dev_descr_broadwell),
655 {0,} /* 0 terminated list. */
656};
657
eebf11a0
MCC		 658
659/****************************************************************************
15ed103a 660 Ancillary status routines
eebf11a0
MCC		 661 ****************************************************************************/
662
50d1bb93 663static inline int numrank(enum type type, u32 mtr)
eebf11a0
MCC		 664{
665 int ranks = (1 << RANK_CNT_BITS(mtr));
50d1bb93
AR		 666 int max = 4;
667
d0cdf900 668 if (type == HASWELL || type == BROADWELL || type == KNIGHTS_LANDING)
50d1bb93 669 max = 8;
eebf11a0 670
50d1bb93
AR		 671 if (ranks > max) {
672 edac_dbg(0, "Invalid number of ranks: %d (max = %i) raw value = %x (%04x)\n",
673 ranks, max, (unsigned int)RANK_CNT_BITS(mtr), mtr);
eebf11a0
MCC		 674 return -EINVAL;
675 }
676
677 return ranks;
678}
679
680static inline int numrow(u32 mtr)
681{
682 int rows = (RANK_WIDTH_BITS(mtr) + 12);
683
684 if (rows < 13 || rows > 18) {
956b9ba1
JP		 685 edac_dbg(0, "Invalid number of rows: %d (should be between 14 and 17) raw value = %x (%04x)\n",
686 rows, (unsigned int)RANK_WIDTH_BITS(mtr), mtr);
eebf11a0
MCC		 687 return -EINVAL;
688 }
689
690 return 1 << rows;
691}
692
693static inline int numcol(u32 mtr)
694{
695 int cols = (COL_WIDTH_BITS(mtr) + 10);
696
697 if (cols > 12) {
956b9ba1
JP		 698 edac_dbg(0, "Invalid number of cols: %d (max = 4) raw value = %x (%04x)\n",
699 cols, (unsigned int)COL_WIDTH_BITS(mtr), mtr);
eebf11a0
MCC		 700 return -EINVAL;
701 }
702
703 return 1 << cols;
704}
705
c1979ba2 706static struct sbridge_dev *get_sbridge_dev(u8 bus, int multi_bus)
eebf11a0
MCC		 707{
708 struct sbridge_dev *sbridge_dev;
709
c1979ba2
JS		 710 /*
711 * If we have devices scattered across several busses that pertain
712 * to the same memory controller, we'll lump them all together.
713 */
714 if (multi_bus) {
715 return list_first_entry_or_null(&sbridge_edac_list,
716 struct sbridge_dev, list);
717 }
718
eebf11a0
MCC		 719 list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) {
720 if (sbridge_dev->bus == bus)
721 return sbridge_dev;
722 }
723
724 return NULL;
725}
726
727static struct sbridge_dev *alloc_sbridge_dev(u8 bus,
728 const struct pci_id_table *table)
729{
730 struct sbridge_dev *sbridge_dev;
731
732 sbridge_dev = kzalloc(sizeof(*sbridge_dev), GFP_KERNEL);
733 if (!sbridge_dev)
734 return NULL;
735
736 sbridge_dev->pdev = kzalloc(sizeof(*sbridge_dev->pdev) * table->n_devs,
737 GFP_KERNEL);
738 if (!sbridge_dev->pdev) {
739 kfree(sbridge_dev);
740 return NULL;
741 }
742
743 sbridge_dev->bus = bus;
744 sbridge_dev->n_devs = table->n_devs;
745 list_add_tail(&sbridge_dev->list, &sbridge_edac_list);
746
747 return sbridge_dev;
748}
749
750static void free_sbridge_dev(struct sbridge_dev *sbridge_dev)
751{
752 list_del(&sbridge_dev->list);
753 kfree(sbridge_dev->pdev);
754 kfree(sbridge_dev);
755}
756
fb79a509
AR		 757static u64 sbridge_get_tolm(struct sbridge_pvt *pvt)
758{
759 u32 reg;
760
761 /* Address range is 32:28 */
762 pci_read_config_dword(pvt->pci_sad1, TOLM, &reg);
763 return GET_TOLM(reg);
764}
765
8fd6a43a
AR		 766static u64 sbridge_get_tohm(struct sbridge_pvt *pvt)
767{
768 u32 reg;
769
770 pci_read_config_dword(pvt->pci_sad1, TOHM, &reg);
771 return GET_TOHM(reg);
772}
773
4d715a80
AR		 774static u64 ibridge_get_tolm(struct sbridge_pvt *pvt)
775{
776 u32 reg;
777
778 pci_read_config_dword(pvt->pci_br1, TOLM, &reg);
779
780 return GET_TOLM(reg);
781}
782
783static u64 ibridge_get_tohm(struct sbridge_pvt *pvt)
784{
785 u32 reg;
786
787 pci_read_config_dword(pvt->pci_br1, TOHM, &reg);
788
789 return GET_TOHM(reg);
790}
791
b976bcf2
AR		 792static u64 rir_limit(u32 reg)
793{
794 return ((u64)GET_BITFIELD(reg, 1, 10) << 29) | 0x1fffffff;
795}
796
c59f9c06
JS		 797static u64 sad_limit(u32 reg)
798{
799 return (GET_BITFIELD(reg, 6, 25) << 26) | 0x3ffffff;
800}
801
802static u32 interleave_mode(u32 reg)
803{
804 return GET_BITFIELD(reg, 1, 1);
805}
806
807char *show_interleave_mode(u32 reg)
808{
809 return interleave_mode(reg) ? "8:6" : "[8:6]XOR[18:16]";
810}
811
812static u32 dram_attr(u32 reg)
813{
814 return GET_BITFIELD(reg, 2, 3);
815}
816
d0cdf900
JS		 817static u64 knl_sad_limit(u32 reg)
818{
819 return (GET_BITFIELD(reg, 7, 26) << 26) | 0x3ffffff;
820}
821
822static u32 knl_interleave_mode(u32 reg)
823{
824 return GET_BITFIELD(reg, 1, 2);
825}
826
827static char *knl_show_interleave_mode(u32 reg)
828{
829 char *s;
830
831 switch (knl_interleave_mode(reg)) {
832 case 0:
833 s = "use address bits [8:6]";
834 break;
835 case 1:
836 s = "use address bits [10:8]";
837 break;
838 case 2:
839 s = "use address bits [14:12]";
840 break;
841 case 3:
842 s = "use address bits [32:30]";
843 break;
844 default:
845 WARN_ON(1);
846 break;
847 }
848
849 return s;
850}
851
852static u32 dram_attr_knl(u32 reg)
853{
854 return GET_BITFIELD(reg, 3, 4);
855}
856
857
9e375446
AR		 858static enum mem_type get_memory_type(struct sbridge_pvt *pvt)
859{
860 u32 reg;
861 enum mem_type mtype;
862
863 if (pvt->pci_ddrio) {
864 pci_read_config_dword(pvt->pci_ddrio, pvt->info.rankcfgr,
865 &reg);
866 if (GET_BITFIELD(reg, 11, 11))
867 /* FIXME: Can also be LRDIMM */
868 mtype = MEM_RDDR3;
869 else
870 mtype = MEM_DDR3;
871 } else
872 mtype = MEM_UNKNOWN;
873
874 return mtype;
875}
876
50d1bb93
AR		 877static enum mem_type haswell_get_memory_type(struct sbridge_pvt *pvt)
878{
879 u32 reg;
880 bool registered = false;
881 enum mem_type mtype = MEM_UNKNOWN;
882
883 if (!pvt->pci_ddrio)
884 goto out;
885
886 pci_read_config_dword(pvt->pci_ddrio,
887 HASWELL_DDRCRCLKCONTROLS, &reg);
888 /* Is_Rdimm */
889 if (GET_BITFIELD(reg, 16, 16))
890 registered = true;
891
892 pci_read_config_dword(pvt->pci_ta, MCMTR, &reg);
893 if (GET_BITFIELD(reg, 14, 14)) {
894 if (registered)
895 mtype = MEM_RDDR4;
896 else
897 mtype = MEM_DDR4;
898 } else {
899 if (registered)
900 mtype = MEM_RDDR3;
901 else
902 mtype = MEM_DDR3;
903 }
904
905out:
906 return mtype;
907}
908
45f4d3ab
HC		 909static enum dev_type knl_get_width(struct sbridge_pvt *pvt, u32 mtr)
910{
911 /* for KNL value is fixed */
912 return DEV_X16;
913}
914
12f0721c
AR		 915static enum dev_type sbridge_get_width(struct sbridge_pvt *pvt, u32 mtr)
916{
917 /* there's no way to figure out */
918 return DEV_UNKNOWN;
919}
920
921static enum dev_type __ibridge_get_width(u32 mtr)
922{
923 enum dev_type type;
924
925 switch (mtr) {
926 case 3:
927 type = DEV_UNKNOWN;
928 break;
929 case 2:
930 type = DEV_X16;
931 break;
932 case 1:
933 type = DEV_X8;
934 break;
935 case 0:
936 type = DEV_X4;
937 break;
938 }
939
940 return type;
941}
942
943static enum dev_type ibridge_get_width(struct sbridge_pvt *pvt, u32 mtr)
944{
945 /*
946 * ddr3_width on the documentation but also valid for DDR4 on
947 * Haswell
948 */
949 return __ibridge_get_width(GET_BITFIELD(mtr, 7, 8));
950}
951
952static enum dev_type broadwell_get_width(struct sbridge_pvt *pvt, u32 mtr)
953{
954 /* ddr3_width on the documentation but also valid for DDR4 */
955 return __ibridge_get_width(GET_BITFIELD(mtr, 8, 9));
956}
957
d0cdf900
JS		 958static enum mem_type knl_get_memory_type(struct sbridge_pvt *pvt)
959{
960 /* DDR4 RDIMMS and LRDIMMS are supported */
961 return MEM_RDDR4;
962}
963
f14d6892
AR		 964static u8 get_node_id(struct sbridge_pvt *pvt)
965{
966 u32 reg;
967 pci_read_config_dword(pvt->pci_br0, SAD_CONTROL, &reg);
968 return GET_BITFIELD(reg, 0, 2);
969}
970
50d1bb93
AR		 971static u8 haswell_get_node_id(struct sbridge_pvt *pvt)
972{
973 u32 reg;
974
975 pci_read_config_dword(pvt->pci_sad1, SAD_CONTROL, &reg);
976 return GET_BITFIELD(reg, 0, 3);
977}
978
d0cdf900
JS		 979static u8 knl_get_node_id(struct sbridge_pvt *pvt)
980{
981 u32 reg;
982
983 pci_read_config_dword(pvt->pci_sad1, SAD_CONTROL, &reg);
984 return GET_BITFIELD(reg, 0, 2);
985}
986
987
50d1bb93
AR		 988static u64 haswell_get_tolm(struct sbridge_pvt *pvt)
989{
990 u32 reg;
991
f7cf2a22
TL		 992 pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOLM, &reg);
993 return (GET_BITFIELD(reg, 26, 31) << 26) | 0x3ffffff;
50d1bb93
AR		 994}
995
996static u64 haswell_get_tohm(struct sbridge_pvt *pvt)
997{
998 u64 rc;
999 u32 reg;
1000
1001 pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOHM_0, &reg);
1002 rc = GET_BITFIELD(reg, 26, 31);
1003 pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOHM_1, &reg);
1004 rc = ((reg << 6) | rc) << 26;
1005
1006 return rc | 0x1ffffff;
1007}
1008
d0cdf900
JS		 1009static u64 knl_get_tolm(struct sbridge_pvt *pvt)
1010{
1011 u32 reg;
1012
1013 pci_read_config_dword(pvt->knl.pci_mc_info, KNL_TOLM, &reg);
1014 return (GET_BITFIELD(reg, 26, 31) << 26) | 0x3ffffff;
1015}
1016
1017static u64 knl_get_tohm(struct sbridge_pvt *pvt)
1018{
1019 u64 rc;
1020 u32 reg_lo, reg_hi;
1021
1022 pci_read_config_dword(pvt->knl.pci_mc_info, KNL_TOHM_0, &reg_lo);
1023 pci_read_config_dword(pvt->knl.pci_mc_info, KNL_TOHM_1, &reg_hi);
1024 rc = ((u64)reg_hi << 32) | reg_lo;
1025 return rc | 0x3ffffff;
1026}
1027
1028
50d1bb93
AR		 1029static u64 haswell_rir_limit(u32 reg)
1030{
1031 return (((u64)GET_BITFIELD(reg, 1, 11) + 1) << 29) - 1;
1032}
1033
4d715a80
AR		 1034static inline u8 sad_pkg_socket(u8 pkg)
1035{
1036 /* on Ivy Bridge, nodeID is SASS, where A is HA and S is node id */
2ff3a308 1037 return ((pkg >> 3) << 2) | (pkg & 0x3);
4d715a80
AR		 1038}
1039
1040static inline u8 sad_pkg_ha(u8 pkg)
1041{
1042 return (pkg >> 2) & 0x1;
1043}
1044
ea5dfb5f
TL		 1045static int haswell_chan_hash(int idx, u64 addr)
1046{
1047 int i;
1048
1049 /*
1050 * XOR even bits from 12:26 to bit0 of idx,
1051 * odd bits from 13:27 to bit1
1052 */
1053 for (i = 12; i < 28; i += 2)
1054 idx ^= (addr >> i) & 3;
1055
1056 return idx;
1057}
1058
eebf11a0
MCC		 1059/****************************************************************************
1060 Memory check routines
1061 ****************************************************************************/
dbc954dd 1062static struct pci_dev *get_pdev_same_bus(u8 bus, u32 id)
eebf11a0 1063{
dbc954dd 1064 struct pci_dev *pdev = NULL;
eebf11a0 1065
dbc954dd
AR		 1066 do {
1067 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, id, pdev);
1068 if (pdev && pdev->bus->number == bus)
1069 break;
1070 } while (pdev);
eebf11a0 1071
dbc954dd 1072 return pdev;
eebf11a0
MCC		 1073}
1074
1075/**
c36e3e77 1076 * check_if_ecc_is_active() - Checks if ECC is active
50d1bb93
AR		 1077 * @bus: Device bus
1078 * @type: Memory controller type
1079 * returns: 0 in case ECC is active, -ENODEV if it can't be determined or
1080 * disabled
eebf11a0 1081 */
dbc954dd 1082static int check_if_ecc_is_active(const u8 bus, enum type type)
eebf11a0
MCC		 1083{
1084 struct pci_dev *pdev = NULL;
dbc954dd 1085 u32 mcmtr, id;
eebf11a0 1086
1f39581a
TL		 1087 switch (type) {
1088 case IVY_BRIDGE:
dbc954dd 1089 id = PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA;
1f39581a
TL		 1090 break;
1091 case HASWELL:
50d1bb93 1092 id = PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA;
1f39581a
TL		 1093 break;
1094 case SANDY_BRIDGE:
dbc954dd 1095 id = PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA;
1f39581a
TL		 1096 break;
1097 case BROADWELL:
1098 id = PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TA;
1099 break;
d0cdf900
JS		 1100 case KNIGHTS_LANDING:
1101 /*
1102 * KNL doesn't group things by bus the same way
1103 * SB/IB/Haswell does.
1104 */
1105 id = PCI_DEVICE_ID_INTEL_KNL_IMC_TA;
1106 break;
1f39581a
TL		 1107 default:
1108 return -ENODEV;
1109 }
dbc954dd 1110
d0cdf900
JS		 1111 if (type != KNIGHTS_LANDING)
1112 pdev = get_pdev_same_bus(bus, id);
1113 else
1114 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, id, 0);
1115
eebf11a0
MCC		 1116 if (!pdev) {
1117 sbridge_printk(KERN_ERR, "Couldn't find PCI device "
dbc954dd
AR		 1118 "%04x:%04x! on bus %02d\n",
1119 PCI_VENDOR_ID_INTEL, id, bus);
eebf11a0
MCC		 1120 return -ENODEV;
1121 }
1122
d0cdf900
JS		 1123 pci_read_config_dword(pdev,
1124 type == KNIGHTS_LANDING ? KNL_MCMTR : MCMTR, &mcmtr);
eebf11a0
MCC		 1125 if (!IS_ECC_ENABLED(mcmtr)) {
1126 sbridge_printk(KERN_ERR, "ECC is disabled. Aborting\n");
1127 return -ENODEV;
1128 }
eebf11a0
MCC		 1129 return 0;
1130}
1131
d0cdf900
JS		 1132/* Low bits of TAD limit, and some metadata. */
1133static const u32 knl_tad_dram_limit_lo[] = {
1134 0x400, 0x500, 0x600, 0x700,
1135 0x800, 0x900, 0xa00, 0xb00,
1136};
1137
1138/* Low bits of TAD offset. */
1139static const u32 knl_tad_dram_offset_lo[] = {
1140 0x404, 0x504, 0x604, 0x704,
1141 0x804, 0x904, 0xa04, 0xb04,
1142};
1143
1144/* High 16 bits of TAD limit and offset. */
1145static const u32 knl_tad_dram_hi[] = {
1146 0x408, 0x508, 0x608, 0x708,
1147 0x808, 0x908, 0xa08, 0xb08,
1148};
1149
1150/* Number of ways a tad entry is interleaved. */
1151static const u32 knl_tad_ways[] = {
1152 8, 6, 4, 3, 2, 1,
1153};
1154
1155/*
1156 * Retrieve the n'th Target Address Decode table entry
1157 * from the memory controller's TAD table.
1158 *
1159 * @pvt: driver private data
1160 * @entry: which entry you want to retrieve
1161 * @mc: which memory controller (0 or 1)
1162 * @offset: output tad range offset
1163 * @limit: output address of first byte above tad range
1164 * @ways: output number of interleave ways
1165 *
1166 * The offset value has curious semantics. It's a sort of running total
1167 * of the sizes of all the memory regions that aren't mapped in this
1168 * tad table.
1169 */
1170static int knl_get_tad(const struct sbridge_pvt *pvt,
1171 const int entry,
1172 const int mc,
1173 u64 *offset,
1174 u64 *limit,
1175 int *ways)
1176{
1177 u32 reg_limit_lo, reg_offset_lo, reg_hi;
1178 struct pci_dev *pci_mc;
1179 int way_id;
1180
1181 switch (mc) {
1182 case 0:
1183 pci_mc = pvt->knl.pci_mc0;
1184 break;
1185 case 1:
1186 pci_mc = pvt->knl.pci_mc1;
1187 break;
1188 default:
1189 WARN_ON(1);
1190 return -EINVAL;
1191 }
1192
1193 pci_read_config_dword(pci_mc,
1194 knl_tad_dram_limit_lo[entry], &reg_limit_lo);
1195 pci_read_config_dword(pci_mc,
1196 knl_tad_dram_offset_lo[entry], &reg_offset_lo);
1197 pci_read_config_dword(pci_mc,
1198 knl_tad_dram_hi[entry], &reg_hi);
1199
1200 /* Is this TAD entry enabled? */
1201 if (!GET_BITFIELD(reg_limit_lo, 0, 0))
1202 return -ENODEV;
1203
1204 way_id = GET_BITFIELD(reg_limit_lo, 3, 5);
1205
1206 if (way_id < ARRAY_SIZE(knl_tad_ways)) {
1207 *ways = knl_tad_ways[way_id];
1208 } else {
1209 *ways = 0;
1210 sbridge_printk(KERN_ERR,
1211 "Unexpected value %d in mc_tad_limit_lo wayness field\n",
1212 way_id);
1213 return -ENODEV;
1214 }
1215
1216 /*
1217 * The least significant 6 bits of base and limit are truncated.
1218 * For limit, we fill the missing bits with 1s.
1219 */
1220 *offset = ((u64) GET_BITFIELD(reg_offset_lo, 6, 31) << 6) |
1221 ((u64) GET_BITFIELD(reg_hi, 0, 15) << 32);
1222 *limit = ((u64) GET_BITFIELD(reg_limit_lo, 6, 31) << 6) | 63 |
1223 ((u64) GET_BITFIELD(reg_hi, 16, 31) << 32);
1224
1225 return 0;
1226}
1227
1228/* Determine which memory controller is responsible for a given channel. */
1229static int knl_channel_mc(int channel)
1230{
1231 WARN_ON(channel < 0 || channel >= 6);
1232
1233 return channel < 3 ? 1 : 0;
1234}
1235
1236/*
1237 * Get the Nth entry from EDC_ROUTE_TABLE register.
1238 * (This is the per-tile mapping of logical interleave targets to
1239 * physical EDC modules.)
1240 *
1241 * entry 0: 0:2
1242 * 1: 3:5
1243 * 2: 6:8
1244 * 3: 9:11
1245 * 4: 12:14
1246 * 5: 15:17
1247 * 6: 18:20
1248 * 7: 21:23
1249 * reserved: 24:31
1250 */
1251static u32 knl_get_edc_route(int entry, u32 reg)
1252{
1253 WARN_ON(entry >= KNL_MAX_EDCS);
1254 return GET_BITFIELD(reg, entry*3, (entry*3)+2);
1255}
1256
1257/*
1258 * Get the Nth entry from MC_ROUTE_TABLE register.
1259 * (This is the per-tile mapping of logical interleave targets to
1260 * physical DRAM channels modules.)
1261 *
1262 * entry 0: mc 0:2 channel 18:19
1263 * 1: mc 3:5 channel 20:21
1264 * 2: mc 6:8 channel 22:23
1265 * 3: mc 9:11 channel 24:25
1266 * 4: mc 12:14 channel 26:27
1267 * 5: mc 15:17 channel 28:29
1268 * reserved: 30:31
1269 *
1270 * Though we have 3 bits to identify the MC, we should only see
1271 * the values 0 or 1.
1272 */
1273
1274static u32 knl_get_mc_route(int entry, u32 reg)
1275{
1276 int mc, chan;
1277
1278 WARN_ON(entry >= KNL_MAX_CHANNELS);
1279
1280 mc = GET_BITFIELD(reg, entry*3, (entry*3)+2);
1281 chan = GET_BITFIELD(reg, (entry*2) + 18, (entry*2) + 18 + 1);
1282
1283 return knl_channel_remap(mc*3 + chan);
1284}
1285
1286/*
1287 * Render the EDC_ROUTE register in human-readable form.
1288 * Output string s should be at least KNL_MAX_EDCS*2 bytes.
1289 */
1290static void knl_show_edc_route(u32 reg, char *s)
1291{
1292 int i;
1293
1294 for (i = 0; i < KNL_MAX_EDCS; i++) {
1295 s[i*2] = knl_get_edc_route(i, reg) + '0';
1296 s[i*2+1] = '-';
1297 }
1298
1299 s[KNL_MAX_EDCS*2 - 1] = '\0';
1300}
1301
1302/*
1303 * Render the MC_ROUTE register in human-readable form.
1304 * Output string s should be at least KNL_MAX_CHANNELS*2 bytes.
1305 */
1306static void knl_show_mc_route(u32 reg, char *s)
1307{
1308 int i;
1309
1310 for (i = 0; i < KNL_MAX_CHANNELS; i++) {
1311 s[i*2] = knl_get_mc_route(i, reg) + '0';
1312 s[i*2+1] = '-';
1313 }
1314
1315 s[KNL_MAX_CHANNELS*2 - 1] = '\0';
1316}
1317
1318#define KNL_EDC_ROUTE 0xb8
1319#define KNL_MC_ROUTE 0xb4
1320
1321/* Is this dram rule backed by regular DRAM in flat mode? */
1322#define KNL_EDRAM(reg) GET_BITFIELD(reg, 29, 29)
1323
1324/* Is this dram rule cached? */
1325#define KNL_CACHEABLE(reg) GET_BITFIELD(reg, 28, 28)
1326
1327/* Is this rule backed by edc ? */
1328#define KNL_EDRAM_ONLY(reg) GET_BITFIELD(reg, 29, 29)
1329
1330/* Is this rule backed by DRAM, cacheable in EDRAM? */
1331#define KNL_CACHEABLE(reg) GET_BITFIELD(reg, 28, 28)
1332
1333/* Is this rule mod3? */
1334#define KNL_MOD3(reg) GET_BITFIELD(reg, 27, 27)
1335
1336/*
1337 * Figure out how big our RAM modules are.
1338 *
1339 * The DIMMMTR register in KNL doesn't tell us the size of the DIMMs, so we
1340 * have to figure this out from the SAD rules, interleave lists, route tables,
1341 * and TAD rules.
1342 *
1343 * SAD rules can have holes in them (e.g. the 3G-4G hole), so we have to
1344 * inspect the TAD rules to figure out how large the SAD regions really are.
1345 *
1346 * When we know the real size of a SAD region and how many ways it's
1347 * interleaved, we know the individual contribution of each channel to
1348 * TAD is size/ways.
1349 *
1350 * Finally, we have to check whether each channel participates in each SAD
1351 * region.
1352 *
1353 * Fortunately, KNL only supports one DIMM per channel, so once we know how
1354 * much memory the channel uses, we know the DIMM is at least that large.
1355 * (The BIOS might possibly choose not to map all available memory, in which
1356 * case we will underreport the size of the DIMM.)
1357 *
1358 * In theory, we could try to determine the EDC sizes as well, but that would
1359 * only work in flat mode, not in cache mode.
1360 *
1361 * @mc_sizes: Output sizes of channels (must have space for KNL_MAX_CHANNELS
1362 * elements)
1363 */
1364static int knl_get_dimm_capacity(struct sbridge_pvt *pvt, u64 *mc_sizes)
1365{
1366 u64 sad_base, sad_size, sad_limit = 0;
1367 u64 tad_base, tad_size, tad_limit, tad_deadspace, tad_livespace;
1368 int sad_rule = 0;
1369 int tad_rule = 0;
1370 int intrlv_ways, tad_ways;
1371 u32 first_pkg, pkg;
1372 int i;
1373 u64 sad_actual_size[2]; /* sad size accounting for holes, per mc */
1374 u32 dram_rule, interleave_reg;
1375 u32 mc_route_reg[KNL_MAX_CHAS];
1376 u32 edc_route_reg[KNL_MAX_CHAS];
1377 int edram_only;
1378 char edc_route_string[KNL_MAX_EDCS*2];
1379 char mc_route_string[KNL_MAX_CHANNELS*2];
1380 int cur_reg_start;
1381 int mc;
1382 int channel;
1383 int way;
1384 int participants[KNL_MAX_CHANNELS];
1385 int participant_count = 0;
1386
1387 for (i = 0; i < KNL_MAX_CHANNELS; i++)
1388 mc_sizes[i] = 0;
1389
1390 /* Read the EDC route table in each CHA. */
1391 cur_reg_start = 0;
1392 for (i = 0; i < KNL_MAX_CHAS; i++) {
1393 pci_read_config_dword(pvt->knl.pci_cha[i],
1394 KNL_EDC_ROUTE, &edc_route_reg[i]);
1395
1396 if (i > 0 && edc_route_reg[i] != edc_route_reg[i-1]) {
1397 knl_show_edc_route(edc_route_reg[i-1],
1398 edc_route_string);
1399 if (cur_reg_start == i-1)
1400 edac_dbg(0, "edc route table for CHA %d: %s\n",
1401 cur_reg_start, edc_route_string);
1402 else
1403 edac_dbg(0, "edc route table for CHA %d-%d: %s\n",
1404 cur_reg_start, i-1, edc_route_string);
1405 cur_reg_start = i;
1406 }
1407 }
1408 knl_show_edc_route(edc_route_reg[i-1], edc_route_string);
1409 if (cur_reg_start == i-1)
1410 edac_dbg(0, "edc route table for CHA %d: %s\n",
1411 cur_reg_start, edc_route_string);
1412 else
1413 edac_dbg(0, "edc route table for CHA %d-%d: %s\n",
1414 cur_reg_start, i-1, edc_route_string);
1415
1416 /* Read the MC route table in each CHA. */
1417 cur_reg_start = 0;
1418 for (i = 0; i < KNL_MAX_CHAS; i++) {
1419 pci_read_config_dword(pvt->knl.pci_cha[i],
1420 KNL_MC_ROUTE, &mc_route_reg[i]);
1421
1422 if (i > 0 && mc_route_reg[i] != mc_route_reg[i-1]) {
1423 knl_show_mc_route(mc_route_reg[i-1], mc_route_string);
1424 if (cur_reg_start == i-1)
1425 edac_dbg(0, "mc route table for CHA %d: %s\n",
1426 cur_reg_start, mc_route_string);
1427 else
1428 edac_dbg(0, "mc route table for CHA %d-%d: %s\n",
1429 cur_reg_start, i-1, mc_route_string);
1430 cur_reg_start = i;
1431 }
1432 }
1433 knl_show_mc_route(mc_route_reg[i-1], mc_route_string);
1434 if (cur_reg_start == i-1)
1435 edac_dbg(0, "mc route table for CHA %d: %s\n",
1436 cur_reg_start, mc_route_string);
1437 else
1438 edac_dbg(0, "mc route table for CHA %d-%d: %s\n",
1439 cur_reg_start, i-1, mc_route_string);
1440
1441 /* Process DRAM rules */
1442 for (sad_rule = 0; sad_rule < pvt->info.max_sad; sad_rule++) {
1443 /* previous limit becomes the new base */
1444 sad_base = sad_limit;
1445
1446 pci_read_config_dword(pvt->pci_sad0,
1447 pvt->info.dram_rule[sad_rule], &dram_rule);
1448
1449 if (!DRAM_RULE_ENABLE(dram_rule))
1450 break;
1451
1452 edram_only = KNL_EDRAM_ONLY(dram_rule);
1453
1454 sad_limit = pvt->info.sad_limit(dram_rule)+1;
1455 sad_size = sad_limit - sad_base;
1456
1457 pci_read_config_dword(pvt->pci_sad0,
1458 pvt->info.interleave_list[sad_rule], &interleave_reg);
1459
1460 /*
1461 * Find out how many ways this dram rule is interleaved.
1462 * We stop when we see the first channel again.
1463 */
1464 first_pkg = sad_pkg(pvt->info.interleave_pkg,
1465 interleave_reg, 0);
1466 for (intrlv_ways = 1; intrlv_ways < 8; intrlv_ways++) {
1467 pkg = sad_pkg(pvt->info.interleave_pkg,
1468 interleave_reg, intrlv_ways);
1469
1470 if ((pkg & 0x8) == 0) {
1471 /*
1472 * 0 bit means memory is non-local,
1473 * which KNL doesn't support
1474 */
1475 edac_dbg(0, "Unexpected interleave target %d\n",
1476 pkg);
1477 return -1;
1478 }
1479
1480 if (pkg == first_pkg)
1481 break;
1482 }
1483 if (KNL_MOD3(dram_rule))
1484 intrlv_ways *= 3;
1485
1486 edac_dbg(3, "dram rule %d (base 0x%llx, limit 0x%llx), %d way interleave%s\n",
1487 sad_rule,
1488 sad_base,
1489 sad_limit,
1490 intrlv_ways,
1491 edram_only ? ", EDRAM" : "");
1492
1493 /*
1494 * Find out how big the SAD region really is by iterating
1495 * over TAD tables (SAD regions may contain holes).
1496 * Each memory controller might have a different TAD table, so
1497 * we have to look at both.
1498 *
1499 * Livespace is the memory that's mapped in this TAD table,
1500 * deadspace is the holes (this could be the MMIO hole, or it
1501 * could be memory that's mapped by the other TAD table but
1502 * not this one).
1503 */
1504 for (mc = 0; mc < 2; mc++) {
1505 sad_actual_size[mc] = 0;
1506 tad_livespace = 0;
1507 for (tad_rule = 0;
1508 tad_rule < ARRAY_SIZE(
1509 knl_tad_dram_limit_lo);
1510 tad_rule++) {
1511 if (knl_get_tad(pvt,
1512 tad_rule,
1513 mc,
1514 &tad_deadspace,
1515 &tad_limit,
1516 &tad_ways))
1517 break;
1518
1519 tad_size = (tad_limit+1) -
1520 (tad_livespace + tad_deadspace);
1521 tad_livespace += tad_size;
1522 tad_base = (tad_limit+1) - tad_size;
1523
1524 if (tad_base < sad_base) {
1525 if (tad_limit > sad_base)
1526 edac_dbg(0, "TAD region overlaps lower SAD boundary -- TAD tables may be configured incorrectly.\n");
1527 } else if (tad_base < sad_limit) {
1528 if (tad_limit+1 > sad_limit) {
1529 edac_dbg(0, "TAD region overlaps upper SAD boundary -- TAD tables may be configured incorrectly.\n");
1530 } else {
1531 /* TAD region is completely inside SAD region */
1532 edac_dbg(3, "TAD region %d 0x%llx - 0x%llx (%lld bytes) table%d\n",
1533 tad_rule, tad_base,
1534 tad_limit, tad_size,
1535 mc);
1536 sad_actual_size[mc] += tad_size;
1537 }
1538 }
1539 tad_base = tad_limit+1;
1540 }
1541 }
1542
1543 for (mc = 0; mc < 2; mc++) {
1544 edac_dbg(3, " total TAD DRAM footprint in table%d : 0x%llx (%lld bytes)\n",
1545 mc, sad_actual_size[mc], sad_actual_size[mc]);
1546 }
1547
1548 /* Ignore EDRAM rule */
1549 if (edram_only)
1550 continue;
1551
1552 /* Figure out which channels participate in interleave. */
1553 for (channel = 0; channel < KNL_MAX_CHANNELS; channel++)
1554 participants[channel] = 0;
1555
1556 /* For each channel, does at least one CHA have
1557 * this channel mapped to the given target?
1558 */
1559 for (channel = 0; channel < KNL_MAX_CHANNELS; channel++) {
1560 for (way = 0; way < intrlv_ways; way++) {
1561 int target;
1562 int cha;
1563
1564 if (KNL_MOD3(dram_rule))
1565 target = way;
1566 else
1567 target = 0x7 & sad_pkg(
1568 pvt->info.interleave_pkg, interleave_reg, way);
1569
1570 for (cha = 0; cha < KNL_MAX_CHAS; cha++) {
1571 if (knl_get_mc_route(target,
1572 mc_route_reg[cha]) == channel
83bdaad4 1573 && !participants[channel]) {
d0cdf900
JS		 1574 participant_count++;
1575 participants[channel] = 1;
1576 break;
1577 }
1578 }
1579 }
1580 }
1581
1582 if (participant_count != intrlv_ways)
1583 edac_dbg(0, "participant_count (%d) != interleave_ways (%d): DIMM size may be incorrect\n",
1584 participant_count, intrlv_ways);
1585
1586 for (channel = 0; channel < KNL_MAX_CHANNELS; channel++) {
1587 mc = knl_channel_mc(channel);
1588 if (participants[channel]) {
1589 edac_dbg(4, "mc channel %d contributes %lld bytes via sad entry %d\n",
1590 channel,
1591 sad_actual_size[mc]/intrlv_ways,
1592 sad_rule);
1593 mc_sizes[channel] +=
1594 sad_actual_size[mc]/intrlv_ways;
1595 }
1596 }
1597 }
1598
1599 return 0;
1600}
1601
084a4fcc 1602static int get_dimm_config(struct mem_ctl_info *mci)
eebf11a0
MCC		 1603{
1604 struct sbridge_pvt *pvt = mci->pvt_info;
c36e3e77 1605 struct dimm_info *dimm;
deb09dda
MCC		 1606 unsigned i, j, banks, ranks, rows, cols, npages;
1607 u64 size;
eebf11a0
MCC		 1608 u32 reg;
1609 enum edac_type mode;
c6e13b52 1610 enum mem_type mtype;
d0cdf900
JS		 1611 int channels = pvt->info.type == KNIGHTS_LANDING ?
1612 KNL_MAX_CHANNELS : NUM_CHANNELS;
1613 u64 knl_mc_sizes[KNL_MAX_CHANNELS];
eebf11a0 1614
ea5dfb5f
TL		 1615 if (pvt->info.type == HASWELL || pvt->info.type == BROADWELL) {
1616 pci_read_config_dword(pvt->pci_ha0, HASWELL_HASYSDEFEATURE2, &reg);
1617 pvt->is_chan_hash = GET_BITFIELD(reg, 21, 21);
1618 }
d0cdf900
JS		 1619 if (pvt->info.type == HASWELL || pvt->info.type == BROADWELL ||
1620 pvt->info.type == KNIGHTS_LANDING)
50d1bb93
AR		 1621 pci_read_config_dword(pvt->pci_sad1, SAD_TARGET, &reg);
1622 else
1623 pci_read_config_dword(pvt->pci_br0, SAD_TARGET, &reg);
1624
d0cdf900
JS		 1625 if (pvt->info.type == KNIGHTS_LANDING)
1626 pvt->sbridge_dev->source_id = SOURCE_ID_KNL(reg);
1627 else
1628 pvt->sbridge_dev->source_id = SOURCE_ID(reg);
eebf11a0 1629
f14d6892 1630 pvt->sbridge_dev->node_id = pvt->info.get_node_id(pvt);
956b9ba1
JP		 1631 edac_dbg(0, "mc#%d: Node ID: %d, source ID: %d\n",
1632 pvt->sbridge_dev->mc,
1633 pvt->sbridge_dev->node_id,
1634 pvt->sbridge_dev->source_id);
eebf11a0 1635
d0cdf900
JS		 1636 /* KNL doesn't support mirroring or lockstep,
1637 * and is always closed page
1638 */
1639 if (pvt->info.type == KNIGHTS_LANDING) {
1640 mode = EDAC_S4ECD4ED;
eebf11a0 1641 pvt->is_mirrored = false;
eebf11a0 1642
d0cdf900
JS		 1643 if (knl_get_dimm_capacity(pvt, knl_mc_sizes) != 0)
1644 return -1;
eebf11a0 1645 } else {
d0cdf900
JS		 1646 pci_read_config_dword(pvt->pci_ras, RASENABLES, &reg);
1647 if (IS_MIRROR_ENABLED(reg)) {
1648 edac_dbg(0, "Memory mirror is enabled\n");
1649 pvt->is_mirrored = true;
1650 } else {
1651 edac_dbg(0, "Memory mirror is disabled\n");
1652 pvt->is_mirrored = false;
1653 }
1654
1655 pci_read_config_dword(pvt->pci_ta, MCMTR, &pvt->info.mcmtr);
1656 if (IS_LOCKSTEP_ENABLED(pvt->info.mcmtr)) {
1657 edac_dbg(0, "Lockstep is enabled\n");
1658 mode = EDAC_S8ECD8ED;
1659 pvt->is_lockstep = true;
1660 } else {
1661 edac_dbg(0, "Lockstep is disabled\n");
1662 mode = EDAC_S4ECD4ED;
1663 pvt->is_lockstep = false;
1664 }
1665 if (IS_CLOSE_PG(pvt->info.mcmtr)) {
1666 edac_dbg(0, "address map is on closed page mode\n");
1667 pvt->is_close_pg = true;
1668 } else {
1669 edac_dbg(0, "address map is on open page mode\n");
1670 pvt->is_close_pg = false;
1671 }
eebf11a0
MCC		 1672 }
1673
9e375446 1674 mtype = pvt->info.get_memory_type(pvt);
50d1bb93 1675 if (mtype == MEM_RDDR3 || mtype == MEM_RDDR4)
9e375446
AR		 1676 edac_dbg(0, "Memory is registered\n");
1677 else if (mtype == MEM_UNKNOWN)
de4772c6 1678 edac_dbg(0, "Cannot determine memory type\n");
9e375446
AR		 1679 else
1680 edac_dbg(0, "Memory is unregistered\n");
eebf11a0 1681
fec53af5 1682 if (mtype == MEM_DDR4 || mtype == MEM_RDDR4)
50d1bb93
AR		 1683 banks = 16;
1684 else
1685 banks = 8;
eebf11a0 1686
d0cdf900 1687 for (i = 0; i < channels; i++) {
eebf11a0
MCC		 1688 u32 mtr;
1689
d0cdf900
JS		 1690 int max_dimms_per_channel;
1691
1692 if (pvt->info.type == KNIGHTS_LANDING) {
1693 max_dimms_per_channel = 1;
1694 if (!pvt->knl.pci_channel[i])
1695 continue;
1696 } else {
1697 max_dimms_per_channel = ARRAY_SIZE(mtr_regs);
1698 if (!pvt->pci_tad[i])
1699 continue;
1700 }
1701
1702 for (j = 0; j < max_dimms_per_channel; j++) {
c36e3e77
MCC		 1703 dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers,
1704 i, j, 0);
d0cdf900
JS		 1705 if (pvt->info.type == KNIGHTS_LANDING) {
1706 pci_read_config_dword(pvt->knl.pci_channel[i],
1707 knl_mtr_reg, &mtr);
1708 } else {
1709 pci_read_config_dword(pvt->pci_tad[i],
1710 mtr_regs[j], &mtr);
1711 }
956b9ba1 1712 edac_dbg(4, "Channel #%d MTR%d = %x\n", i, j, mtr);
eebf11a0
MCC		 1713 if (IS_DIMM_PRESENT(mtr)) {
1714 pvt->channel[i].dimms++;
1715
50d1bb93 1716 ranks = numrank(pvt->info.type, mtr);
d0cdf900
JS		 1717
1718 if (pvt->info.type == KNIGHTS_LANDING) {
1719 /* For DDR4, this is fixed. */
1720 cols = 1 << 10;
1721 rows = knl_mc_sizes[i] /
1722 ((u64) cols * ranks * banks * 8);
1723 } else {
1724 rows = numrow(mtr);
1725 cols = numcol(mtr);
1726 }
eebf11a0 1727
deb09dda 1728 size = ((u64)rows * cols * banks * ranks) >> (20 - 3);
eebf11a0
MCC		 1729 npages = MiB_TO_PAGES(size);
1730
7d375bff
TL		 1731 edac_dbg(0, "mc#%d: ha %d channel %d, dimm %d, %lld Mb (%d pages) bank: %d, rank: %d, row: %#x, col: %#x\n",
1732 pvt->sbridge_dev->mc, i/4, i%4, j,
956b9ba1
JP		 1733 size, npages,
1734 banks, ranks, rows, cols);
eebf11a0 1735
a895bf8b 1736 dimm->nr_pages = npages;
084a4fcc 1737 dimm->grain = 32;
12f0721c 1738 dimm->dtype = pvt->info.get_width(pvt, mtr);
084a4fcc
MCC		 1739 dimm->mtype = mtype;
1740 dimm->edac_mode = mode;
1741 snprintf(dimm->label, sizeof(dimm->label),
7d375bff
TL		 1742 "CPU_SrcID#%u_Ha#%u_Chan#%u_DIMM#%u",
1743 pvt->sbridge_dev->source_id, i/4, i%4, j);
eebf11a0
MCC		 1744 }
1745 }
1746 }
1747
1748 return 0;
1749}
1750
1751static void get_memory_layout(const struct mem_ctl_info *mci)
1752{
1753 struct sbridge_pvt *pvt = mci->pvt_info;
1754 int i, j, k, n_sads, n_tads, sad_interl;
1755 u32 reg;
1756 u64 limit, prv = 0;
1757 u64 tmp_mb;
8c009100 1758 u32 gb, mb;
eebf11a0
MCC		 1759 u32 rir_way;
1760
1761 /*
1762 * Step 1) Get TOLM/TOHM ranges
1763 */
1764
fb79a509 1765 pvt->tolm = pvt->info.get_tolm(pvt);
eebf11a0
MCC		 1766 tmp_mb = (1 + pvt->tolm) >> 20;
1767
8c009100
JS		 1768 gb = div_u64_rem(tmp_mb, 1024, &mb);
1769 edac_dbg(0, "TOLM: %u.%03u GB (0x%016Lx)\n",
1770 gb, (mb*1000)/1024, (u64)pvt->tolm);
eebf11a0
MCC		 1771
1772 /* Address range is already 45:25 */
8fd6a43a 1773 pvt->tohm = pvt->info.get_tohm(pvt);
eebf11a0
MCC		 1774 tmp_mb = (1 + pvt->tohm) >> 20;
1775
8c009100
JS		 1776 gb = div_u64_rem(tmp_mb, 1024, &mb);
1777 edac_dbg(0, "TOHM: %u.%03u GB (0x%016Lx)\n",
1778 gb, (mb*1000)/1024, (u64)pvt->tohm);
eebf11a0
MCC		 1779
1780 /*
1781 * Step 2) Get SAD range and SAD Interleave list
1782 * TAD registers contain the interleave wayness. However, it
1783 * seems simpler to just discover it indirectly, with the
1784 * algorithm bellow.
1785 */
1786 prv = 0;
464f1d82 1787 for (n_sads = 0; n_sads < pvt->info.max_sad; n_sads++) {
eebf11a0 1788 /* SAD_LIMIT Address range is 45:26 */
464f1d82 1789 pci_read_config_dword(pvt->pci_sad0, pvt->info.dram_rule[n_sads],
eebf11a0 1790 &reg);
c59f9c06 1791 limit = pvt->info.sad_limit(reg);
eebf11a0
MCC		 1792
1793 if (!DRAM_RULE_ENABLE(reg))
1794 continue;
1795
1796 if (limit <= prv)
1797 break;
1798
1799 tmp_mb = (limit + 1) >> 20;
8c009100 1800 gb = div_u64_rem(tmp_mb, 1024, &mb);
956b9ba1
JP		 1801 edac_dbg(0, "SAD#%d %s up to %u.%03u GB (0x%016Lx) Interleave: %s reg=0x%08x\n",
1802 n_sads,
c59f9c06 1803 show_dram_attr(pvt->info.dram_attr(reg)),
8c009100 1804 gb, (mb*1000)/1024,
956b9ba1 1805 ((u64)tmp_mb) << 20L,
c59f9c06 1806 pvt->info.show_interleave_mode(reg),
956b9ba1 1807 reg);
eebf11a0
MCC		 1808 prv = limit;
1809
ef1ce51e 1810 pci_read_config_dword(pvt->pci_sad0, pvt->info.interleave_list[n_sads],
eebf11a0 1811 &reg);
cc311991 1812 sad_interl = sad_pkg(pvt->info.interleave_pkg, reg, 0);
eebf11a0 1813 for (j = 0; j < 8; j++) {
cc311991
AR		 1814 u32 pkg = sad_pkg(pvt->info.interleave_pkg, reg, j);
1815 if (j > 0 && sad_interl == pkg)
eebf11a0
MCC		 1816 break;
1817
956b9ba1 1818 edac_dbg(0, "SAD#%d, interleave #%d: %d\n",
cc311991 1819 n_sads, j, pkg);
eebf11a0
MCC		 1820 }
1821 }
1822
d0cdf900
JS		 1823 if (pvt->info.type == KNIGHTS_LANDING)
1824 return;
1825
eebf11a0
MCC		 1826 /*
1827 * Step 3) Get TAD range
1828 */
1829 prv = 0;
1830 for (n_tads = 0; n_tads < MAX_TAD; n_tads++) {
1831 pci_read_config_dword(pvt->pci_ha0, tad_dram_rule[n_tads],
1832 &reg);
1833 limit = TAD_LIMIT(reg);
1834 if (limit <= prv)
1835 break;
1836 tmp_mb = (limit + 1) >> 20;
1837
8c009100 1838 gb = div_u64_rem(tmp_mb, 1024, &mb);
956b9ba1 1839 edac_dbg(0, "TAD#%d: up to %u.%03u GB (0x%016Lx), socket interleave %d, memory interleave %d, TGT: %d, %d, %d, %d, reg=0x%08x\n",
8c009100 1840 n_tads, gb, (mb*1000)/1024,
956b9ba1 1841 ((u64)tmp_mb) << 20L,
eb1af3b7
TL		 1842 (u32)(1 << TAD_SOCK(reg)),
1843 (u32)TAD_CH(reg) + 1,
956b9ba1
JP		 1844 (u32)TAD_TGT0(reg),
1845 (u32)TAD_TGT1(reg),
1846 (u32)TAD_TGT2(reg),
1847 (u32)TAD_TGT3(reg),
1848 reg);
7fae0db4 1849 prv = limit;
eebf11a0
MCC		 1850 }
1851
1852 /*
1853 * Step 4) Get TAD offsets, per each channel
1854 */
1855 for (i = 0; i < NUM_CHANNELS; i++) {
1856 if (!pvt->channel[i].dimms)
1857 continue;
1858 for (j = 0; j < n_tads; j++) {
1859 pci_read_config_dword(pvt->pci_tad[i],
1860 tad_ch_nilv_offset[j],
1861 &reg);
1862 tmp_mb = TAD_OFFSET(reg) >> 20;
8c009100 1863 gb = div_u64_rem(tmp_mb, 1024, &mb);
956b9ba1
JP		 1864 edac_dbg(0, "TAD CH#%d, offset #%d: %u.%03u GB (0x%016Lx), reg=0x%08x\n",
1865 i, j,
8c009100 1866 gb, (mb*1000)/1024,
956b9ba1
JP		 1867 ((u64)tmp_mb) << 20L,
1868 reg);
eebf11a0
MCC		 1869 }
1870 }
1871
1872 /*
1873 * Step 6) Get RIR Wayness/Limit, per each channel
1874 */
1875 for (i = 0; i < NUM_CHANNELS; i++) {
1876 if (!pvt->channel[i].dimms)
1877 continue;
1878 for (j = 0; j < MAX_RIR_RANGES; j++) {
1879 pci_read_config_dword(pvt->pci_tad[i],
1880 rir_way_limit[j],
1881 &reg);
1882
1883 if (!IS_RIR_VALID(reg))
1884 continue;
1885
b976bcf2 1886 tmp_mb = pvt->info.rir_limit(reg) >> 20;
eebf11a0 1887 rir_way = 1 << RIR_WAY(reg);
8c009100 1888 gb = div_u64_rem(tmp_mb, 1024, &mb);
956b9ba1
JP		 1889 edac_dbg(0, "CH#%d RIR#%d, limit: %u.%03u GB (0x%016Lx), way: %d, reg=0x%08x\n",
1890 i, j,
8c009100 1891 gb, (mb*1000)/1024,
956b9ba1
JP		 1892 ((u64)tmp_mb) << 20L,
1893 rir_way,
1894 reg);
eebf11a0
MCC		 1895
1896 for (k = 0; k < rir_way; k++) {
1897 pci_read_config_dword(pvt->pci_tad[i],
1898 rir_offset[j][k],
1899 &reg);
c7103f65 1900 tmp_mb = RIR_OFFSET(pvt->info.type, reg) << 6;
eebf11a0 1901
8c009100 1902 gb = div_u64_rem(tmp_mb, 1024, &mb);
956b9ba1
JP		 1903 edac_dbg(0, "CH#%d RIR#%d INTL#%d, offset %u.%03u GB (0x%016Lx), tgt: %d, reg=0x%08x\n",
1904 i, j, k,
8c009100 1905 gb, (mb*1000)/1024,
956b9ba1 1906 ((u64)tmp_mb) << 20L,
c7103f65 1907 (u32)RIR_RNK_TGT(pvt->info.type, reg),
956b9ba1 1908 reg);
eebf11a0
MCC		 1909 }
1910 }
1911 }
1912}
1913
8112c0cd 1914static struct mem_ctl_info *get_mci_for_node_id(u8 node_id)
eebf11a0
MCC		 1915{
1916 struct sbridge_dev *sbridge_dev;
1917
1918 list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) {
1919 if (sbridge_dev->node_id == node_id)
1920 return sbridge_dev->mci;
1921 }
1922 return NULL;
1923}
1924
1925static int get_memory_error_data(struct mem_ctl_info *mci,
1926 u64 addr,
7d375bff 1927 u8 *socket, u8 *ha,
eebf11a0
MCC		 1928 long *channel_mask,
1929 u8 *rank,
e17a2f42 1930 char **area_type, char *msg)
eebf11a0
MCC		 1931{
1932 struct mem_ctl_info *new_mci;
1933 struct sbridge_pvt *pvt = mci->pvt_info;
4d715a80 1934 struct pci_dev *pci_ha;
c41afdca 1935 int n_rir, n_sads, n_tads, sad_way, sck_xch;
eebf11a0 1936 int sad_interl, idx, base_ch;
50d1bb93 1937 int interleave_mode, shiftup = 0;
ef1ce51e 1938 unsigned sad_interleave[pvt->info.max_interleave];
50d1bb93 1939 u32 reg, dram_rule;
7d375bff 1940 u8 ch_way, sck_way, pkg, sad_ha = 0, ch_add = 0;
eebf11a0
MCC		 1941 u32 tad_offset;
1942 u32 rir_way;
8c009100 1943 u32 mb, gb;
bd4b9683 1944 u64 ch_addr, offset, limit = 0, prv = 0;
eebf11a0
MCC		 1945
1946
1947 /*
1948 * Step 0) Check if the address is at special memory ranges
1949 * The check bellow is probably enough to fill all cases where
1950 * the error is not inside a memory, except for the legacy
1951 * range (e. g. VGA addresses). It is unlikely, however, that the
1952 * memory controller would generate an error on that range.
1953 */
5b889e37 1954 if ((addr > (u64) pvt->tolm) && (addr < (1LL << 32))) {
eebf11a0 1955 sprintf(msg, "Error at TOLM area, on addr 0x%08Lx", addr);
eebf11a0
MCC		 1956 return -EINVAL;
1957 }
1958 if (addr >= (u64)pvt->tohm) {
1959 sprintf(msg, "Error at MMIOH area, on addr 0x%016Lx", addr);
eebf11a0
MCC		 1960 return -EINVAL;
1961 }
1962
1963 /*
1964 * Step 1) Get socket
1965 */
464f1d82
AR		 1966 for (n_sads = 0; n_sads < pvt->info.max_sad; n_sads++) {
1967 pci_read_config_dword(pvt->pci_sad0, pvt->info.dram_rule[n_sads],
eebf11a0
MCC		 1968 &reg);
1969
1970 if (!DRAM_RULE_ENABLE(reg))
1971 continue;
1972
c59f9c06 1973 limit = pvt->info.sad_limit(reg);
eebf11a0
MCC		 1974 if (limit <= prv) {
1975 sprintf(msg, "Can't discover the memory socket");
eebf11a0
MCC		 1976 return -EINVAL;
1977 }
1978 if (addr <= limit)
1979 break;
1980 prv = limit;
1981 }
464f1d82 1982 if (n_sads == pvt->info.max_sad) {
eebf11a0 1983 sprintf(msg, "Can't discover the memory socket");
eebf11a0
MCC		 1984 return -EINVAL;
1985 }
50d1bb93 1986 dram_rule = reg;
c59f9c06
JS		 1987 *area_type = show_dram_attr(pvt->info.dram_attr(dram_rule));
1988 interleave_mode = pvt->info.interleave_mode(dram_rule);
eebf11a0 1989
ef1ce51e 1990 pci_read_config_dword(pvt->pci_sad0, pvt->info.interleave_list[n_sads],
eebf11a0 1991 &reg);
4d715a80
AR		 1992
1993 if (pvt->info.type == SANDY_BRIDGE) {
1994 sad_interl = sad_pkg(pvt->info.interleave_pkg, reg, 0);
1995 for (sad_way = 0; sad_way < 8; sad_way++) {
1996 u32 pkg = sad_pkg(pvt->info.interleave_pkg, reg, sad_way);
1997 if (sad_way > 0 && sad_interl == pkg)
1998 break;
1999 sad_interleave[sad_way] = pkg;
2000 edac_dbg(0, "SAD interleave #%d: %d\n",
2001 sad_way, sad_interleave[sad_way]);
2002 }
2003 edac_dbg(0, "mc#%d: Error detected on SAD#%d: address 0x%016Lx < 0x%016Lx, Interleave [%d:6]%s\n",
2004 pvt->sbridge_dev->mc,
2005 n_sads,
2006 addr,
2007 limit,
2008 sad_way + 7,
2009 !interleave_mode ? "" : "XOR[18:16]");
2010 if (interleave_mode)
2011 idx = ((addr >> 6) ^ (addr >> 16)) & 7;
2012 else
2013 idx = (addr >> 6) & 7;
2014 switch (sad_way) {
2015 case 1:
2016 idx = 0;
eebf11a0 2017 break;
4d715a80
AR		 2018 case 2:
2019 idx = idx & 1;
2020 break;
2021 case 4:
2022 idx = idx & 3;
2023 break;
2024 case 8:
2025 break;
2026 default:
2027 sprintf(msg, "Can't discover socket interleave");
2028 return -EINVAL;
2029 }
2030 *socket = sad_interleave[idx];
2031 edac_dbg(0, "SAD interleave index: %d (wayness %d) = CPU socket %d\n",
2032 idx, sad_way, *socket);
1f39581a 2033 } else if (pvt->info.type == HASWELL || pvt->info.type == BROADWELL) {
50d1bb93
AR		 2034 int bits, a7mode = A7MODE(dram_rule);
2035
2036 if (a7mode) {
2037 /* A7 mode swaps P9 with P6 */
2038 bits = GET_BITFIELD(addr, 7, 8) << 1;
2039 bits |= GET_BITFIELD(addr, 9, 9);
2040 } else
bb89e714 2041 bits = GET_BITFIELD(addr, 6, 8);
50d1bb93 2042
bb89e714 2043 if (interleave_mode == 0) {
50d1bb93
AR		 2044 /* interleave mode will XOR {8,7,6} with {18,17,16} */
2045 idx = GET_BITFIELD(addr, 16, 18);
2046 idx ^= bits;
2047 } else
2048 idx = bits;
2049
2050 pkg = sad_pkg(pvt->info.interleave_pkg, reg, idx);
2051 *socket = sad_pkg_socket(pkg);
2052 sad_ha = sad_pkg_ha(pkg);
7d375bff
TL		 2053 if (sad_ha)
2054 ch_add = 4;
50d1bb93
AR		 2055
2056 if (a7mode) {
2057 /* MCChanShiftUpEnable */
2058 pci_read_config_dword(pvt->pci_ha0,
2059 HASWELL_HASYSDEFEATURE2, &reg);
2060 shiftup = GET_BITFIELD(reg, 22, 22);
2061 }
2062
2063 edac_dbg(0, "SAD interleave package: %d = CPU socket %d, HA %i, shiftup: %i\n",
2064 idx, *socket, sad_ha, shiftup);
4d715a80
AR		 2065 } else {
2066 /* Ivy Bridge's SAD mode doesn't support XOR interleave mode */
eebf11a0 2067 idx = (addr >> 6) & 7;
4d715a80
AR		 2068 pkg = sad_pkg(pvt->info.interleave_pkg, reg, idx);
2069 *socket = sad_pkg_socket(pkg);
2070 sad_ha = sad_pkg_ha(pkg);
7d375bff
TL		 2071 if (sad_ha)
2072 ch_add = 4;
4d715a80
AR		 2073 edac_dbg(0, "SAD interleave package: %d = CPU socket %d, HA %d\n",
2074 idx, *socket, sad_ha);
eebf11a0 2075 }
eebf11a0 2076
7d375bff
TL		 2077 *ha = sad_ha;
2078
eebf11a0
MCC		 2079 /*
2080 * Move to the proper node structure, in order to access the
2081 * right PCI registers
2082 */
2083 new_mci = get_mci_for_node_id(*socket);
2084 if (!new_mci) {
2085 sprintf(msg, "Struct for socket #%u wasn't initialized",
2086 *socket);
eebf11a0
MCC		 2087 return -EINVAL;
2088 }
2089 mci = new_mci;
2090 pvt = mci->pvt_info;
2091
2092 /*
2093 * Step 2) Get memory channel
2094 */
2095 prv = 0;
4d715a80
AR		 2096 if (pvt->info.type == SANDY_BRIDGE)
2097 pci_ha = pvt->pci_ha0;
2098 else {
2099 if (sad_ha)
2100 pci_ha = pvt->pci_ha1;
2101 else
2102 pci_ha = pvt->pci_ha0;
2103 }
eebf11a0 2104 for (n_tads = 0; n_tads < MAX_TAD; n_tads++) {
4d715a80 2105 pci_read_config_dword(pci_ha, tad_dram_rule[n_tads], &reg);
eebf11a0
MCC		 2106 limit = TAD_LIMIT(reg);
2107 if (limit <= prv) {
2108 sprintf(msg, "Can't discover the memory channel");
eebf11a0
MCC		 2109 return -EINVAL;
2110 }
2111 if (addr <= limit)
2112 break;
2113 prv = limit;
2114 }
4d715a80
AR		 2115 if (n_tads == MAX_TAD) {
2116 sprintf(msg, "Can't discover the memory channel");
2117 return -EINVAL;
2118 }
2119
eebf11a0 2120 ch_way = TAD_CH(reg) + 1;
ff15e95c 2121 sck_way = TAD_SOCK(reg);
eebf11a0
MCC		 2122
2123 if (ch_way == 3)
2124 idx = addr >> 6;
ea5dfb5f 2125 else {
50d1bb93 2126 idx = (addr >> (6 + sck_way + shiftup)) & 0x3;
ea5dfb5f
TL		 2127 if (pvt->is_chan_hash)
2128 idx = haswell_chan_hash(idx, addr);
2129 }
eebf11a0
MCC		 2130 idx = idx % ch_way;
2131
2132 /*
2133 * FIXME: Shouldn't we use CHN_IDX_OFFSET() here, when ch_way == 3 ???
2134 */
2135 switch (idx) {
2136 case 0:
2137 base_ch = TAD_TGT0(reg);
2138 break;
2139 case 1:
2140 base_ch = TAD_TGT1(reg);
2141 break;
2142 case 2:
2143 base_ch = TAD_TGT2(reg);
2144 break;
2145 case 3:
2146 base_ch = TAD_TGT3(reg);
2147 break;
2148 default:
2149 sprintf(msg, "Can't discover the TAD target");
eebf11a0
MCC		 2150 return -EINVAL;
2151 }
2152 *channel_mask = 1 << base_ch;
2153
7d375bff 2154 pci_read_config_dword(pvt->pci_tad[ch_add + base_ch],
4d715a80
AR		 2155 tad_ch_nilv_offset[n_tads],
2156 &tad_offset);
2157
eebf11a0
MCC		 2158 if (pvt->is_mirrored) {
2159 *channel_mask |= 1 << ((base_ch + 2) % 4);
2160 switch(ch_way) {
2161 case 2:
2162 case 4:
ff15e95c 2163 sck_xch = (1 << sck_way) * (ch_way >> 1);
eebf11a0
MCC		 2164 break;
2165 default:
2166 sprintf(msg, "Invalid mirror set. Can't decode addr");
eebf11a0
MCC		 2167 return -EINVAL;
2168 }
2169 } else
2170 sck_xch = (1 << sck_way) * ch_way;
2171
2172 if (pvt->is_lockstep)
2173 *channel_mask |= 1 << ((base_ch + 1) % 4);
2174
2175 offset = TAD_OFFSET(tad_offset);
2176
956b9ba1
JP		 2177 edac_dbg(0, "TAD#%d: address 0x%016Lx < 0x%016Lx, socket interleave %d, channel interleave %d (offset 0x%08Lx), index %d, base ch: %d, ch mask: 0x%02lx\n",
2178 n_tads,
2179 addr,
2180 limit,
eb1af3b7 2181 sck_way,
956b9ba1
JP		 2182 ch_way,
2183 offset,
2184 idx,
2185 base_ch,
2186 *channel_mask);
eebf11a0
MCC		 2187
2188 /* Calculate channel address */
2189 /* Remove the TAD offset */
2190
2191 if (offset > addr) {
2192 sprintf(msg, "Can't calculate ch addr: TAD offset 0x%08Lx is too high for addr 0x%08Lx!",
2193 offset, addr);
eebf11a0
MCC		 2194 return -EINVAL;
2195 }
eb1af3b7
TL		 2196
2197 ch_addr = addr - offset;
2198 ch_addr >>= (6 + shiftup);
ff15e95c 2199 ch_addr /= sck_xch;
eb1af3b7
TL		 2200 ch_addr <<= (6 + shiftup);
2201 ch_addr |= addr & ((1 << (6 + shiftup)) - 1);
eebf11a0
MCC		 2202
2203 /*
2204 * Step 3) Decode rank
2205 */
2206 for (n_rir = 0; n_rir < MAX_RIR_RANGES; n_rir++) {
7d375bff 2207 pci_read_config_dword(pvt->pci_tad[ch_add + base_ch],
eebf11a0
MCC		 2208 rir_way_limit[n_rir],
2209 &reg);
2210
2211 if (!IS_RIR_VALID(reg))
2212 continue;
2213
b976bcf2 2214 limit = pvt->info.rir_limit(reg);
8c009100 2215 gb = div_u64_rem(limit >> 20, 1024, &mb);
956b9ba1
JP		 2216 edac_dbg(0, "RIR#%d, limit: %u.%03u GB (0x%016Lx), way: %d\n",
2217 n_rir,
8c009100 2218 gb, (mb*1000)/1024,
956b9ba1
JP		 2219 limit,
2220 1 << RIR_WAY(reg));
eebf11a0
MCC		 2221 if (ch_addr <= limit)
2222 break;
2223 }
2224 if (n_rir == MAX_RIR_RANGES) {
2225 sprintf(msg, "Can't discover the memory rank for ch addr 0x%08Lx",
2226 ch_addr);
eebf11a0
MCC		 2227 return -EINVAL;
2228 }
2229 rir_way = RIR_WAY(reg);
50d1bb93 2230
eebf11a0
MCC		 2231 if (pvt->is_close_pg)
2232 idx = (ch_addr >> 6);
2233 else
2234 idx = (ch_addr >> 13); /* FIXME: Datasheet says to shift by 15 */
2235 idx %= 1 << rir_way;
2236
7d375bff 2237 pci_read_config_dword(pvt->pci_tad[ch_add + base_ch],
eebf11a0
MCC		 2238 rir_offset[n_rir][idx],
2239 &reg);
c7103f65 2240 *rank = RIR_RNK_TGT(pvt->info.type, reg);
eebf11a0 2241
956b9ba1
JP		 2242 edac_dbg(0, "RIR#%d: channel address 0x%08Lx < 0x%08Lx, RIR interleave %d, index %d\n",
2243 n_rir,
2244 ch_addr,
2245 limit,
2246 rir_way,
2247 idx);
eebf11a0
MCC		 2248
2249 return 0;
2250}
2251
2252/****************************************************************************
2253 Device initialization routines: put/get, init/exit
2254 ****************************************************************************/
2255
2256/*
2257 * sbridge_put_all_devices 'put' all the devices that we have
2258 * reserved via 'get'
2259 */
2260static void sbridge_put_devices(struct sbridge_dev *sbridge_dev)
2261{
2262 int i;
2263
956b9ba1 2264 edac_dbg(0, "\n");
eebf11a0
MCC		 2265 for (i = 0; i < sbridge_dev->n_devs; i++) {
2266 struct pci_dev *pdev = sbridge_dev->pdev[i];
2267 if (!pdev)
2268 continue;
956b9ba1
JP		 2269 edac_dbg(0, "Removing dev %02x:%02x.%d\n",
2270 pdev->bus->number,
2271 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
eebf11a0
MCC		 2272 pci_dev_put(pdev);
2273 }
2274}
2275
2276static void sbridge_put_all_devices(void)
2277{
2278 struct sbridge_dev *sbridge_dev, *tmp;
2279
2280 list_for_each_entry_safe(sbridge_dev, tmp, &sbridge_edac_list, list) {
2281 sbridge_put_devices(sbridge_dev);
2282 free_sbridge_dev(sbridge_dev);
2283 }
2284}
2285
eebf11a0
MCC		 2286static int sbridge_get_onedevice(struct pci_dev **prev,
2287 u8 *num_mc,
2288 const struct pci_id_table *table,
c1979ba2
JS		 2289 const unsigned devno,
2290 const int multi_bus)
eebf11a0
MCC		 2291{
2292 struct sbridge_dev *sbridge_dev;
2293 const struct pci_id_descr *dev_descr = &table->descr[devno];
eebf11a0
MCC		 2294 struct pci_dev *pdev = NULL;
2295 u8 bus = 0;
2296
ec5a0b38 2297 sbridge_printk(KERN_DEBUG,
dbc954dd 2298 "Seeking for: PCI ID %04x:%04x\n",
eebf11a0
MCC		 2299 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
2300
2301 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
2302 dev_descr->dev_id, *prev);
2303
2304 if (!pdev) {
2305 if (*prev) {
2306 *prev = pdev;
2307 return 0;
2308 }
2309
2310 if (dev_descr->optional)
2311 return 0;
2312
dbc954dd 2313 /* if the HA wasn't found */
eebf11a0
MCC		 2314 if (devno == 0)
2315 return -ENODEV;
2316
2317 sbridge_printk(KERN_INFO,
dbc954dd 2318 "Device not found: %04x:%04x\n",
eebf11a0
MCC		 2319 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
2320
2321 /* End of list, leave */
2322 return -ENODEV;
2323 }
2324 bus = pdev->bus->number;
2325
c1979ba2 2326 sbridge_dev = get_sbridge_dev(bus, multi_bus);
eebf11a0
MCC		 2327 if (!sbridge_dev) {
2328 sbridge_dev = alloc_sbridge_dev(bus, table);
2329 if (!sbridge_dev) {
2330 pci_dev_put(pdev);
2331 return -ENOMEM;
2332 }
2333 (*num_mc)++;
2334 }
2335
2336 if (sbridge_dev->pdev[devno]) {
2337 sbridge_printk(KERN_ERR,
dbc954dd 2338 "Duplicated device for %04x:%04x\n",
eebf11a0
MCC		 2339 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
2340 pci_dev_put(pdev);
2341 return -ENODEV;
2342 }
2343
2344 sbridge_dev->pdev[devno] = pdev;
2345
eebf11a0
MCC		 2346 /* Be sure that the device is enabled */
2347 if (unlikely(pci_enable_device(pdev) < 0)) {
2348 sbridge_printk(KERN_ERR,
dbc954dd 2349 "Couldn't enable %04x:%04x\n",
eebf11a0
MCC		 2350 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
2351 return -ENODEV;
2352 }
2353
dbc954dd 2354 edac_dbg(0, "Detected %04x:%04x\n",
956b9ba1 2355 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
eebf11a0
MCC		 2356
2357 /*
2358 * As stated on drivers/pci/search.c, the reference count for
2359 * @from is always decremented if it is not %NULL. So, as we need
2360 * to get all devices up to null, we need to do a get for the device
2361 */
2362 pci_dev_get(pdev);
2363
2364 *prev = pdev;
2365
2366 return 0;
2367}
2368
5153a0f9
AR		 2369/*
2370 * sbridge_get_all_devices - Find and perform 'get' operation on the MCH's
dbc954dd 2371 * devices we want to reference for this driver.
5153a0f9 2372 * @num_mc: pointer to the memory controllers count, to be incremented in case
c41afdca 2373 * of success.
5153a0f9 2374 * @table: model specific table
c1979ba2
JS		 2375 * @allow_dups: allow for multiple devices to exist with the same device id
2376 * (as implemented, this isn't expected to work correctly in the
2377 * multi-socket case).
2378 * @multi_bus: don't assume devices on different buses belong to different
2379 * memory controllers.
5153a0f9
AR		 2380 *
2381 * returns 0 in case of success or error code
2382 */
c1979ba2
JS		 2383static int sbridge_get_all_devices_full(u8 *num_mc,
2384 const struct pci_id_table *table,
2385 int allow_dups,
2386 int multi_bus)
eebf11a0
MCC		 2387{
2388 int i, rc;
2389 struct pci_dev *pdev = NULL;
eebf11a0
MCC		 2390
2391 while (table && table->descr) {
2392 for (i = 0; i < table->n_devs; i++) {
c1979ba2
JS		 2393 if (!allow_dups || i == 0 ||
2394 table->descr[i].dev_id !=
2395 table->descr[i-1].dev_id) {
2396 pdev = NULL;
2397 }
eebf11a0
MCC		 2398 do {
2399 rc = sbridge_get_onedevice(&pdev, num_mc,
c1979ba2 2400 table, i, multi_bus);
eebf11a0
MCC		 2401 if (rc < 0) {
2402 if (i == 0) {
2403 i = table->n_devs;
2404 break;
2405 }
2406 sbridge_put_all_devices();
2407 return -ENODEV;
2408 }
c1979ba2 2409 } while (pdev && !allow_dups);
eebf11a0
MCC		 2410 }
2411 table++;
2412 }
2413
2414 return 0;
2415}
2416
c1979ba2
JS		 2417#define sbridge_get_all_devices(num_mc, table) \
2418 sbridge_get_all_devices_full(num_mc, table, 0, 0)
d0cdf900
JS		 2419#define sbridge_get_all_devices_knl(num_mc, table) \
2420 sbridge_get_all_devices_full(num_mc, table, 1, 1)
c1979ba2 2421
ea779b5a
AR		 2422static int sbridge_mci_bind_devs(struct mem_ctl_info *mci,
2423 struct sbridge_dev *sbridge_dev)
eebf11a0
MCC		 2424{
2425 struct sbridge_pvt *pvt = mci->pvt_info;
2426 struct pci_dev *pdev;
2900ea60 2427 u8 saw_chan_mask = 0;
dbc954dd 2428 int i;
eebf11a0
MCC		 2429
2430 for (i = 0; i < sbridge_dev->n_devs; i++) {
2431 pdev = sbridge_dev->pdev[i];
2432 if (!pdev)
2433 continue;
dbc954dd
AR		 2434
2435 switch (pdev->device) {
2436 case PCI_DEVICE_ID_INTEL_SBRIDGE_SAD0:
2437 pvt->pci_sad0 = pdev;
eebf11a0 2438 break;
dbc954dd
AR		 2439 case PCI_DEVICE_ID_INTEL_SBRIDGE_SAD1:
2440 pvt->pci_sad1 = pdev;
eebf11a0 2441 break;
dbc954dd
AR		 2442 case PCI_DEVICE_ID_INTEL_SBRIDGE_BR:
2443 pvt->pci_br0 = pdev;
eebf11a0 2444 break;
dbc954dd
AR		 2445 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0:
2446 pvt->pci_ha0 = pdev;
eebf11a0 2447 break;
dbc954dd
AR		 2448 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA:
2449 pvt->pci_ta = pdev;
2450 break;
2451 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_RAS:
2452 pvt->pci_ras = pdev;
2453 break;
2454 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0:
2455 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD1:
2456 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD2:
2457 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD3:
2458 {
2459 int id = pdev->device - PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0;
2460 pvt->pci_tad[id] = pdev;
2900ea60 2461 saw_chan_mask |= 1 << id;
dbc954dd
AR		 2462 }
2463 break;
2464 case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_DDRIO:
2465 pvt->pci_ddrio = pdev;
eebf11a0
MCC		 2466 break;
2467 default:
2468 goto error;
2469 }
2470
dbc954dd
AR		 2471 edac_dbg(0, "Associated PCI %02x:%02x, bus %d with dev = %p\n",
2472 pdev->vendor, pdev->device,
956b9ba1 2473 sbridge_dev->bus,
956b9ba1 2474 pdev);
eebf11a0
MCC		 2475 }
2476
2477 /* Check if everything were registered */
2478 if (!pvt->pci_sad0 || !pvt->pci_sad1 || !pvt->pci_ha0 ||
de4772c6 2479 !pvt-> pci_tad || !pvt->pci_ras || !pvt->pci_ta)
eebf11a0
MCC		 2480 goto enodev;
2481
2900ea60
SJ		 2482 if (saw_chan_mask != 0x0f)
2483 goto enodev;
eebf11a0
MCC		 2484 return 0;
2485
2486enodev:
2487 sbridge_printk(KERN_ERR, "Some needed devices are missing\n");
2488 return -ENODEV;
2489
2490error:
dbc954dd
AR		 2491 sbridge_printk(KERN_ERR, "Unexpected device %02x:%02x\n",
2492 PCI_VENDOR_ID_INTEL, pdev->device);
eebf11a0
MCC		 2493 return -EINVAL;
2494}
2495
4d715a80
AR		 2496static int ibridge_mci_bind_devs(struct mem_ctl_info *mci,
2497 struct sbridge_dev *sbridge_dev)
2498{
2499 struct sbridge_pvt *pvt = mci->pvt_info;
7d375bff
TL		 2500 struct pci_dev *pdev;
2501 u8 saw_chan_mask = 0;
dbc954dd 2502 int i;
4d715a80
AR		 2503
2504 for (i = 0; i < sbridge_dev->n_devs; i++) {
2505 pdev = sbridge_dev->pdev[i];
2506 if (!pdev)
2507 continue;
4d715a80 2508
dbc954dd
AR		 2509 switch (pdev->device) {
2510 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0:
2511 pvt->pci_ha0 = pdev;
2512 break;
2513 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA:
2514 pvt->pci_ta = pdev;
2515 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_RAS:
2516 pvt->pci_ras = pdev;
2517 break;
dbc954dd
AR		 2518 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0:
2519 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD1:
7d375bff
TL		 2520 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD2:
2521 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD3:
dbc954dd
AR		 2522 {
2523 int id = pdev->device - PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0;
2524 pvt->pci_tad[id] = pdev;
7d375bff 2525 saw_chan_mask |= 1 << id;
dbc954dd 2526 }
4d715a80 2527 break;
dbc954dd
AR		 2528 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_2HA_DDRIO0:
2529 pvt->pci_ddrio = pdev;
2530 break;
2531 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_1HA_DDRIO0:
7d375bff 2532 pvt->pci_ddrio = pdev;
4d715a80 2533 break;
dbc954dd
AR		 2534 case PCI_DEVICE_ID_INTEL_IBRIDGE_SAD:
2535 pvt->pci_sad0 = pdev;
2536 break;
2537 case PCI_DEVICE_ID_INTEL_IBRIDGE_BR0:
2538 pvt->pci_br0 = pdev;
2539 break;
2540 case PCI_DEVICE_ID_INTEL_IBRIDGE_BR1:
2541 pvt->pci_br1 = pdev;
2542 break;
2543 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1:
2544 pvt->pci_ha1 = pdev;
2545 break;
2546 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0:
2547 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD1:
7d375bff
TL		 2548 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD2:
2549 case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD3:
dbc954dd 2550 {
7d375bff 2551 int id = pdev->device - PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0 + 4;
dbc954dd 2552 pvt->pci_tad[id] = pdev;
7d375bff 2553 saw_chan_mask |= 1 << id;
dbc954dd
AR		 2554 }
2555 break;
4d715a80
AR		 2556 default:
2557 goto error;
2558 }
2559
2560 edac_dbg(0, "Associated PCI %02x.%02d.%d with dev = %p\n",
2561 sbridge_dev->bus,
2562 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
2563 pdev);
2564 }
2565
2566 /* Check if everything were registered */
2567 if (!pvt->pci_sad0 || !pvt->pci_ha0 || !pvt->pci_br0 ||
2568 !pvt->pci_br1 || !pvt->pci_tad || !pvt->pci_ras ||
2569 !pvt->pci_ta)
2570 goto enodev;
2571
7d375bff
TL		 2572 if (saw_chan_mask != 0x0f && /* -EN */
2573 saw_chan_mask != 0x33 && /* -EP */
2574 saw_chan_mask != 0xff) /* -EX */
2575 goto enodev;
4d715a80
AR		 2576 return 0;
2577
2578enodev:
2579 sbridge_printk(KERN_ERR, "Some needed devices are missing\n");
2580 return -ENODEV;
2581
2582error:
2583 sbridge_printk(KERN_ERR,
dbc954dd
AR		 2584 "Unexpected device %02x:%02x\n", PCI_VENDOR_ID_INTEL,
2585 pdev->device);
4d715a80
AR		 2586 return -EINVAL;
2587}
2588
50d1bb93
AR		 2589static int haswell_mci_bind_devs(struct mem_ctl_info *mci,
2590 struct sbridge_dev *sbridge_dev)
2591{
2592 struct sbridge_pvt *pvt = mci->pvt_info;
7d375bff
TL		 2593 struct pci_dev *pdev;
2594 u8 saw_chan_mask = 0;
50d1bb93 2595 int i;
50d1bb93
AR		 2596
2597 /* there's only one device per system; not tied to any bus */
2598 if (pvt->info.pci_vtd == NULL)
2599 /* result will be checked later */
2600 pvt->info.pci_vtd = pci_get_device(PCI_VENDOR_ID_INTEL,
2601 PCI_DEVICE_ID_INTEL_HASWELL_IMC_VTD_MISC,
2602 NULL);
2603
2604 for (i = 0; i < sbridge_dev->n_devs; i++) {
2605 pdev = sbridge_dev->pdev[i];
2606 if (!pdev)
2607 continue;
2608
2609 switch (pdev->device) {
2610 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD0:
2611 pvt->pci_sad0 = pdev;
2612 break;
2613 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD1:
2614 pvt->pci_sad1 = pdev;
2615 break;
2616 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0:
2617 pvt->pci_ha0 = pdev;
2618 break;
2619 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA:
2620 pvt->pci_ta = pdev;
2621 break;
2622 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_THERMAL:
2623 pvt->pci_ras = pdev;
2624 break;
2625 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD0:
50d1bb93 2626 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD1:
50d1bb93 2627 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD2:
50d1bb93 2628 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD3:
7d375bff
TL		 2629 {
2630 int id = pdev->device - PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD0;
2631
2632 pvt->pci_tad[id] = pdev;
2633 saw_chan_mask |= 1 << id;
2634 }
2635 break;
2636 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD0:
2637 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD1:
2638 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD2:
2639 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD3:
2640 {
2641 int id = pdev->device - PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD0 + 4;
2642
2643 pvt->pci_tad[id] = pdev;
2644 saw_chan_mask |= 1 << id;
2645 }
50d1bb93
AR		 2646 break;
2647 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO0:
7179385a
AR		 2648 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO1:
2649 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO2:
2650 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO3:
2651 if (!pvt->pci_ddrio)
2652 pvt->pci_ddrio = pdev;
50d1bb93
AR		 2653 break;
2654 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1:
2655 pvt->pci_ha1 = pdev;
2656 break;
2657 case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TA:
2658 pvt->pci_ha1_ta = pdev;
2659 break;
50d1bb93
AR		 2660 default:
2661 break;
2662 }
2663
2664 edac_dbg(0, "Associated PCI %02x.%02d.%d with dev = %p\n",
2665 sbridge_dev->bus,
2666 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
2667 pdev);
2668 }
2669
2670 /* Check if everything were registered */
2671 if (!pvt->pci_sad0 || !pvt->pci_ha0 || !pvt->pci_sad1 ||
2672 !pvt->pci_ras || !pvt->pci_ta || !pvt->info.pci_vtd)
2673 goto enodev;
2674
7d375bff
TL		 2675 if (saw_chan_mask != 0x0f && /* -EN */
2676 saw_chan_mask != 0x33 && /* -EP */
2677 saw_chan_mask != 0xff) /* -EX */
2678 goto enodev;
50d1bb93
AR		 2679 return 0;
2680
2681enodev:
2682 sbridge_printk(KERN_ERR, "Some needed devices are missing\n");
2683 return -ENODEV;
2684}
2685
1f39581a
TL		 2686static int broadwell_mci_bind_devs(struct mem_ctl_info *mci,
2687 struct sbridge_dev *sbridge_dev)
2688{
2689 struct sbridge_pvt *pvt = mci->pvt_info;
2690 struct pci_dev *pdev;
fa2ce64f 2691 u8 saw_chan_mask = 0;
1f39581a
TL		 2692 int i;
2693
2694 /* there's only one device per system; not tied to any bus */
2695 if (pvt->info.pci_vtd == NULL)
2696 /* result will be checked later */
2697 pvt->info.pci_vtd = pci_get_device(PCI_VENDOR_ID_INTEL,
2698 PCI_DEVICE_ID_INTEL_BROADWELL_IMC_VTD_MISC,
2699 NULL);
2700
2701 for (i = 0; i < sbridge_dev->n_devs; i++) {
2702 pdev = sbridge_dev->pdev[i];
2703 if (!pdev)
2704 continue;
2705
2706 switch (pdev->device) {
2707 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD0:
2708 pvt->pci_sad0 = pdev;
2709 break;
2710 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_CBO_SAD1:
2711 pvt->pci_sad1 = pdev;
2712 break;
2713 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0:
2714 pvt->pci_ha0 = pdev;
2715 break;
2716 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TA:
2717 pvt->pci_ta = pdev;
2718 break;
2719 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_THERMAL:
2720 pvt->pci_ras = pdev;
2721 break;
2722 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD0:
1f39581a 2723 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD1:
1f39581a 2724 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD2:
1f39581a 2725 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD3:
fa2ce64f
TL		 2726 {
2727 int id = pdev->device - PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA0_TAD0;
2728 pvt->pci_tad[id] = pdev;
2729 saw_chan_mask |= 1 << id;
2730 }
2731 break;
2732 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD0:
2733 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD1:
2734 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD2:
2735 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD3:
2736 {
2737 int id = pdev->device - PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TAD0 + 4;
2738 pvt->pci_tad[id] = pdev;
2739 saw_chan_mask |= 1 << id;
2740 }
1f39581a
TL		 2741 break;
2742 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_DDRIO0:
2743 pvt->pci_ddrio = pdev;
2744 break;
fa2ce64f
TL		 2745 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1:
2746 pvt->pci_ha1 = pdev;
2747 break;
2748 case PCI_DEVICE_ID_INTEL_BROADWELL_IMC_HA1_TA:
2749 pvt->pci_ha1_ta = pdev;
2750 break;
1f39581a
TL		 2751 default:
2752 break;
2753 }
2754
2755 edac_dbg(0, "Associated PCI %02x.%02d.%d with dev = %p\n",
2756 sbridge_dev->bus,
2757 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
2758 pdev);
2759 }
2760
2761 /* Check if everything were registered */
2762 if (!pvt->pci_sad0 || !pvt->pci_ha0 || !pvt->pci_sad1 ||
2763 !pvt->pci_ras || !pvt->pci_ta || !pvt->info.pci_vtd)
2764 goto enodev;
2765
fa2ce64f
TL		 2766 if (saw_chan_mask != 0x0f && /* -EN */
2767 saw_chan_mask != 0x33 && /* -EP */
2768 saw_chan_mask != 0xff) /* -EX */
2769 goto enodev;
1f39581a
TL		 2770 return 0;
2771
2772enodev:
2773 sbridge_printk(KERN_ERR, "Some needed devices are missing\n");
2774 return -ENODEV;
2775}
2776
d0cdf900
JS		 2777static int knl_mci_bind_devs(struct mem_ctl_info *mci,
2778 struct sbridge_dev *sbridge_dev)
2779{
2780 struct sbridge_pvt *pvt = mci->pvt_info;
2781 struct pci_dev *pdev;
2782 int dev, func;
2783
2784 int i;
2785 int devidx;
2786
2787 for (i = 0; i < sbridge_dev->n_devs; i++) {
2788 pdev = sbridge_dev->pdev[i];
2789 if (!pdev)
2790 continue;
2791
2792 /* Extract PCI device and function. */
2793 dev = (pdev->devfn >> 3) & 0x1f;
2794 func = pdev->devfn & 0x7;
2795
2796 switch (pdev->device) {
2797 case PCI_DEVICE_ID_INTEL_KNL_IMC_MC:
2798 if (dev == 8)
2799 pvt->knl.pci_mc0 = pdev;
2800 else if (dev == 9)
2801 pvt->knl.pci_mc1 = pdev;
2802 else {
2803 sbridge_printk(KERN_ERR,
2804 "Memory controller in unexpected place! (dev %d, fn %d)\n",
2805 dev, func);
2806 continue;
2807 }
2808 break;
2809
2810 case PCI_DEVICE_ID_INTEL_KNL_IMC_SAD0:
2811 pvt->pci_sad0 = pdev;
2812 break;
2813
2814 case PCI_DEVICE_ID_INTEL_KNL_IMC_SAD1:
2815 pvt->pci_sad1 = pdev;
2816 break;
2817
2818 case PCI_DEVICE_ID_INTEL_KNL_IMC_CHA:
2819 /* There are one of these per tile, and range from
2820 * 1.14.0 to 1.18.5.
2821 */
2822 devidx = ((dev-14)*8)+func;
2823
2824 if (devidx < 0 || devidx >= KNL_MAX_CHAS) {
2825 sbridge_printk(KERN_ERR,
2826 "Caching and Home Agent in unexpected place! (dev %d, fn %d)\n",
2827 dev, func);
2828 continue;
2829 }
2830
2831 WARN_ON(pvt->knl.pci_cha[devidx] != NULL);
2832
2833 pvt->knl.pci_cha[devidx] = pdev;
2834 break;
2835
2836 case PCI_DEVICE_ID_INTEL_KNL_IMC_CHANNEL:
2837 devidx = -1;
2838
2839 /*
2840 * MC0 channels 0-2 are device 9 function 2-4,
2841 * MC1 channels 3-5 are device 8 function 2-4.
2842 */
2843
2844 if (dev == 9)
2845 devidx = func-2;
2846 else if (dev == 8)
2847 devidx = 3 + (func-2);
2848
2849 if (devidx < 0 || devidx >= KNL_MAX_CHANNELS) {
2850 sbridge_printk(KERN_ERR,
2851 "DRAM Channel Registers in unexpected place! (dev %d, fn %d)\n",
2852 dev, func);
2853 continue;
2854 }
2855
2856 WARN_ON(pvt->knl.pci_channel[devidx] != NULL);
2857 pvt->knl.pci_channel[devidx] = pdev;
2858 break;
2859
2860 case PCI_DEVICE_ID_INTEL_KNL_IMC_TOLHM:
2861 pvt->knl.pci_mc_info = pdev;
2862 break;
2863
2864 case PCI_DEVICE_ID_INTEL_KNL_IMC_TA:
2865 pvt->pci_ta = pdev;
2866 break;
2867
2868 default:
2869 sbridge_printk(KERN_ERR, "Unexpected device %d\n",
2870 pdev->device);
2871 break;
2872 }
2873 }
2874
2875 if (!pvt->knl.pci_mc0 || !pvt->knl.pci_mc1 ||
2876 !pvt->pci_sad0 || !pvt->pci_sad1 ||
2877 !pvt->pci_ta) {
2878 goto enodev;
2879 }
2880
2881 for (i = 0; i < KNL_MAX_CHANNELS; i++) {
2882 if (!pvt->knl.pci_channel[i]) {
2883 sbridge_printk(KERN_ERR, "Missing channel %d\n", i);
2884 goto enodev;
2885 }
2886 }
2887
2888 for (i = 0; i < KNL_MAX_CHAS; i++) {
2889 if (!pvt->knl.pci_cha[i]) {
2890 sbridge_printk(KERN_ERR, "Missing CHA %d\n", i);
2891 goto enodev;
2892 }
2893 }
2894
2895 return 0;
2896
2897enodev:
2898 sbridge_printk(KERN_ERR, "Some needed devices are missing\n");
2899 return -ENODEV;
2900}
2901
eebf11a0
MCC		 2902/****************************************************************************
2903 Error check routines
2904 ****************************************************************************/
2905
2906/*
2907 * While Sandy Bridge has error count registers, SMI BIOS read values from
2908 * and resets the counters. So, they are not reliable for the OS to read
2909 * from them. So, we have no option but to just trust on whatever MCE is
2910 * telling us about the errors.
2911 */
2912static void sbridge_mce_output_error(struct mem_ctl_info *mci,
2913 const struct mce *m)
2914{
2915 struct mem_ctl_info *new_mci;
2916 struct sbridge_pvt *pvt = mci->pvt_info;
c36e3e77 2917 enum hw_event_mc_err_type tp_event;
e17a2f42 2918 char *type, *optype, msg[256];
eebf11a0
MCC		 2919 bool ripv = GET_BITFIELD(m->mcgstatus, 0, 0);
2920 bool overflow = GET_BITFIELD(m->status, 62, 62);
2921 bool uncorrected_error = GET_BITFIELD(m->status, 61, 61);
4d715a80 2922 bool recoverable;
eebf11a0
MCC		 2923 u32 core_err_cnt = GET_BITFIELD(m->status, 38, 52);
2924 u32 mscod = GET_BITFIELD(m->status, 16, 31);
2925 u32 errcode = GET_BITFIELD(m->status, 0, 15);
2926 u32 channel = GET_BITFIELD(m->status, 0, 3);
2927 u32 optypenum = GET_BITFIELD(m->status, 4, 6);
2928 long channel_mask, first_channel;
7d375bff 2929 u8 rank, socket, ha;
c36e3e77 2930 int rc, dimm;
e17a2f42 2931 char *area_type = NULL;
eebf11a0 2932
fa2ce64f 2933 if (pvt->info.type != SANDY_BRIDGE)
4d715a80
AR		 2934 recoverable = true;
2935 else
2936 recoverable = GET_BITFIELD(m->status, 56, 56);
2937
c36e3e77
MCC		 2938 if (uncorrected_error) {
2939 if (ripv) {
2940 type = "FATAL";
2941 tp_event = HW_EVENT_ERR_FATAL;
2942 } else {
2943 type = "NON_FATAL";
2944 tp_event = HW_EVENT_ERR_UNCORRECTED;
2945 }
2946 } else {
2947 type = "CORRECTED";
2948 tp_event = HW_EVENT_ERR_CORRECTED;
2949 }
eebf11a0
MCC		 2950
2951 /*
15ed103a 2952 * According with Table 15-9 of the Intel Architecture spec vol 3A,
eebf11a0
MCC		 2953 * memory errors should fit in this mask:
2954 * 000f 0000 1mmm cccc (binary)
2955 * where:
2956 * f = Correction Report Filtering Bit. If 1, subsequent errors
2957 * won't be shown
2958 * mmm = error type
2959 * cccc = channel
2960 * If the mask doesn't match, report an error to the parsing logic
2961 */
2962 if (! ((errcode & 0xef80) == 0x80)) {
2963 optype = "Can't parse: it is not a mem";
2964 } else {
2965 switch (optypenum) {
2966 case 0:
c36e3e77 2967 optype = "generic undef request error";
eebf11a0
MCC		 2968 break;
2969 case 1:
c36e3e77 2970 optype = "memory read error";
eebf11a0
MCC		 2971 break;
2972 case 2:
c36e3e77 2973 optype = "memory write error";
eebf11a0
MCC		 2974 break;
2975 case 3:
c36e3e77 2976 optype = "addr/cmd error";
eebf11a0
MCC		 2977 break;
2978 case 4:
c36e3e77 2979 optype = "memory scrubbing error";
eebf11a0
MCC		 2980 break;
2981 default:
2982 optype = "reserved";
2983 break;
2984 }
2985 }
2986
be3036d2
AR		 2987 /* Only decode errors with an valid address (ADDRV) */
2988 if (!GET_BITFIELD(m->status, 58, 58))
2989 return;
2990
d0cdf900
JS		 2991 if (pvt->info.type == KNIGHTS_LANDING) {
2992 if (channel == 14) {
2993 edac_dbg(0, "%s%s err_code:%04x:%04x EDRAM bank %d\n",
2994 overflow ? " OVERFLOW" : "",
2995 (uncorrected_error && recoverable)
2996 ? " recoverable" : "",
2997 mscod, errcode,
2998 m->bank);
2999 } else {
3000 char A = *("A");
3001
3002 channel = knl_channel_remap(channel);
3003 channel_mask = 1 << channel;
3004 snprintf(msg, sizeof(msg),
3005 "%s%s err_code:%04x:%04x channel:%d (DIMM_%c)",
3006 overflow ? " OVERFLOW" : "",
3007 (uncorrected_error && recoverable)
3008 ? " recoverable" : " ",
3009 mscod, errcode, channel, A + channel);
3010 edac_mc_handle_error(tp_event, mci, core_err_cnt,
3011 m->addr >> PAGE_SHIFT, m->addr & ~PAGE_MASK, 0,
3012 channel, 0, -1,
3013 optype, msg);
3014 }
3015 return;
3016 } else {
3017 rc = get_memory_error_data(mci, m->addr, &socket, &ha,
3018 &channel_mask, &rank, &area_type, msg);
3019 }
3020
eebf11a0 3021 if (rc < 0)
c36e3e77 3022 goto err_parsing;
eebf11a0
MCC		 3023 new_mci = get_mci_for_node_id(socket);
3024 if (!new_mci) {
c36e3e77
MCC		 3025 strcpy(msg, "Error: socket got corrupted!");
3026 goto err_parsing;
eebf11a0
MCC		 3027 }
3028 mci = new_mci;
3029 pvt = mci->pvt_info;
3030
3031 first_channel = find_first_bit(&channel_mask, NUM_CHANNELS);
3032
3033 if (rank < 4)
3034 dimm = 0;
3035 else if (rank < 8)
3036 dimm = 1;
3037 else
3038 dimm = 2;
3039
eebf11a0
MCC		 3040
3041 /*
e17a2f42
MCC		 3042 * FIXME: On some memory configurations (mirror, lockstep), the
3043 * Memory Controller can't point the error to a single DIMM. The
3044 * EDAC core should be handling the channel mask, in order to point
3045 * to the group of dimm's where the error may be happening.
eebf11a0 3046 */
d7c660b7
AR		 3047 if (!pvt->is_lockstep && !pvt->is_mirrored && !pvt->is_close_pg)
3048 channel = first_channel;
3049
c36e3e77 3050 snprintf(msg, sizeof(msg),
7d375bff 3051 "%s%s area:%s err_code:%04x:%04x socket:%d ha:%d channel_mask:%ld rank:%d",
e17a2f42
MCC		 3052 overflow ? " OVERFLOW" : "",
3053 (uncorrected_error && recoverable) ? " recoverable" : "",
3054 area_type,
3055 mscod, errcode,
7d375bff 3056 socket, ha,
e17a2f42
MCC		 3057 channel_mask,
3058 rank);
eebf11a0 3059
956b9ba1 3060 edac_dbg(0, "%s\n", msg);
eebf11a0 3061
c36e3e77
MCC		 3062 /* FIXME: need support for channel mask */
3063
351fc4a9
SJ		 3064 if (channel == CHANNEL_UNSPECIFIED)
3065 channel = -1;
3066
eebf11a0 3067 /* Call the helper to output message */
c1053839 3068 edac_mc_handle_error(tp_event, mci, core_err_cnt,
c36e3e77 3069 m->addr >> PAGE_SHIFT, m->addr & ~PAGE_MASK, 0,
7d375bff 3070 4*ha+channel, dimm, -1,
03f7eae8 3071 optype, msg);
c36e3e77
MCC		 3072 return;
3073err_parsing:
c1053839 3074 edac_mc_handle_error(tp_event, mci, core_err_cnt, 0, 0, 0,
c36e3e77 3075 -1, -1, -1,
03f7eae8 3076 msg, "");
eebf11a0 3077
eebf11a0
MCC		 3078}
3079
3080/*
ad08c4e9
TL		 3081 * Check that logging is enabled and that this is the right type
3082 * of error for us to handle.
eebf11a0 3083 */
3d78c9af
MCC		 3084static int sbridge_mce_check_error(struct notifier_block *nb, unsigned long val,
3085 void *data)
eebf11a0 3086{
3d78c9af
MCC		 3087 struct mce *mce = (struct mce *)data;
3088 struct mem_ctl_info *mci;
3089 struct sbridge_pvt *pvt;
cf40f80c 3090 char *type;
3d78c9af 3091
fd521039
CG		 3092 if (get_edac_report_status() == EDAC_REPORTING_DISABLED)
3093 return NOTIFY_DONE;
3094
3d78c9af
MCC		 3095 mci = get_mci_for_node_id(mce->socketid);
3096 if (!mci)
c4fc1956 3097 return NOTIFY_DONE;
3d78c9af 3098 pvt = mci->pvt_info;
eebf11a0
MCC		 3099
3100 /*
3101 * Just let mcelog handle it if the error is
3102 * outside the memory controller. A memory error
3103 * is indicated by bit 7 = 1 and bits = 8-11,13-15 = 0.
3104 * bit 12 has an special meaning.
3105 */
3106 if ((mce->status & 0xefff) >> 7 != 1)
3d78c9af 3107 return NOTIFY_DONE;
eebf11a0 3108
cf40f80c
AR		 3109 if (mce->mcgstatus & MCG_STATUS_MCIP)
3110 type = "Exception";
3111 else
3112 type = "Event";
3113
49856dc9 3114 sbridge_mc_printk(mci, KERN_DEBUG, "HANDLING MCE MEMORY ERROR\n");
eebf11a0 3115
49856dc9
AR		 3116 sbridge_mc_printk(mci, KERN_DEBUG, "CPU %d: Machine Check %s: %Lx "
3117 "Bank %d: %016Lx\n", mce->extcpu, type,
3118 mce->mcgstatus, mce->bank, mce->status);
3119 sbridge_mc_printk(mci, KERN_DEBUG, "TSC %llx ", mce->tsc);
3120 sbridge_mc_printk(mci, KERN_DEBUG, "ADDR %llx ", mce->addr);
3121 sbridge_mc_printk(mci, KERN_DEBUG, "MISC %llx ", mce->misc);
eebf11a0 3122
49856dc9
AR		 3123 sbridge_mc_printk(mci, KERN_DEBUG, "PROCESSOR %u:%x TIME %llu SOCKET "
3124 "%u APIC %x\n", mce->cpuvendor, mce->cpuid,
3125 mce->time, mce->socketid, mce->apicid);
eebf11a0 3126
ad08c4e9 3127 sbridge_mce_output_error(mci, mce);
eebf11a0
MCC		 3128
3129 /* Advice mcelog that the error were handled */
3d78c9af 3130 return NOTIFY_STOP;
eebf11a0
MCC		 3131}
3132
3d78c9af
MCC		 3133static struct notifier_block sbridge_mce_dec = {
3134 .notifier_call = sbridge_mce_check_error,
3135};
3136
eebf11a0
MCC		 3137/****************************************************************************
3138 EDAC register/unregister logic
3139 ****************************************************************************/
3140
3141static void sbridge_unregister_mci(struct sbridge_dev *sbridge_dev)
3142{
3143 struct mem_ctl_info *mci = sbridge_dev->mci;
3144 struct sbridge_pvt *pvt;
3145
3146 if (unlikely(!mci || !mci->pvt_info)) {
956b9ba1 3147 edac_dbg(0, "MC: dev = %p\n", &sbridge_dev->pdev[0]->dev);
eebf11a0
MCC		 3148
3149 sbridge_printk(KERN_ERR, "Couldn't find mci handler\n");
3150 return;
3151 }
3152
3153 pvt = mci->pvt_info;
3154
956b9ba1
JP		 3155 edac_dbg(0, "MC: mci = %p, dev = %p\n",
3156 mci, &sbridge_dev->pdev[0]->dev);
eebf11a0 3157
eebf11a0 3158 /* Remove MC sysfs nodes */
fd687502 3159 edac_mc_del_mc(mci->pdev);
eebf11a0 3160
956b9ba1 3161 edac_dbg(1, "%s: free mci struct\n", mci->ctl_name);
eebf11a0
MCC		 3162 kfree(mci->ctl_name);
3163 edac_mc_free(mci);
3164 sbridge_dev->mci = NULL;
3165}
3166
4d715a80 3167static int sbridge_register_mci(struct sbridge_dev *sbridge_dev, enum type type)
eebf11a0
MCC		 3168{
3169 struct mem_ctl_info *mci;
c36e3e77 3170 struct edac_mc_layer layers[2];
eebf11a0 3171 struct sbridge_pvt *pvt;
4d715a80 3172 struct pci_dev *pdev = sbridge_dev->pdev[0];
c36e3e77 3173 int rc;
eebf11a0
MCC		 3174
3175 /* Check the number of active and not disabled channels */
dbc954dd 3176 rc = check_if_ecc_is_active(sbridge_dev->bus, type);
eebf11a0
MCC		 3177 if (unlikely(rc < 0))
3178 return rc;
3179
3180 /* allocate a new MC control structure */
c36e3e77 3181 layers[0].type = EDAC_MC_LAYER_CHANNEL;
d0cdf900
JS		 3182 layers[0].size = type == KNIGHTS_LANDING ?
3183 KNL_MAX_CHANNELS : NUM_CHANNELS;
c36e3e77
MCC		 3184 layers[0].is_virt_csrow = false;
3185 layers[1].type = EDAC_MC_LAYER_SLOT;
d0cdf900 3186 layers[1].size = type == KNIGHTS_LANDING ? 1 : MAX_DIMMS;
c36e3e77 3187 layers[1].is_virt_csrow = true;
ca0907b9 3188 mci = edac_mc_alloc(sbridge_dev->mc, ARRAY_SIZE(layers), layers,
c36e3e77
MCC		 3189 sizeof(*pvt));
3190
eebf11a0
MCC		 3191 if (unlikely(!mci))
3192 return -ENOMEM;
3193
956b9ba1 3194 edac_dbg(0, "MC: mci = %p, dev = %p\n",
4d715a80 3195 mci, &pdev->dev);
eebf11a0
MCC		 3196
3197 pvt = mci->pvt_info;
3198 memset(pvt, 0, sizeof(*pvt));
3199
3200 /* Associate sbridge_dev and mci for future usage */
3201 pvt->sbridge_dev = sbridge_dev;
3202 sbridge_dev->mci = mci;
3203
d0cdf900
JS		 3204 mci->mtype_cap = type == KNIGHTS_LANDING ?
3205 MEM_FLAG_DDR4 : MEM_FLAG_DDR3;
eebf11a0
MCC		 3206 mci->edac_ctl_cap = EDAC_FLAG_NONE;
3207 mci->edac_cap = EDAC_FLAG_NONE;
3208 mci->mod_name = "sbridge_edac.c";
3209 mci->mod_ver = SBRIDGE_REVISION;
4d715a80 3210 mci->dev_name = pci_name(pdev);
eebf11a0
MCC		 3211 mci->ctl_page_to_phys = NULL;
3212
4d715a80 3213 pvt->info.type = type;
50d1bb93
AR		 3214 switch (type) {
3215 case IVY_BRIDGE:
4d715a80
AR		 3216 pvt->info.rankcfgr = IB_RANK_CFG_A;
3217 pvt->info.get_tolm = ibridge_get_tolm;
3218 pvt->info.get_tohm = ibridge_get_tohm;
3219 pvt->info.dram_rule = ibridge_dram_rule;
9e375446 3220 pvt->info.get_memory_type = get_memory_type;
f14d6892 3221 pvt->info.get_node_id = get_node_id;
b976bcf2 3222 pvt->info.rir_limit = rir_limit;
c59f9c06
JS		 3223 pvt->info.sad_limit = sad_limit;
3224 pvt->info.interleave_mode = interleave_mode;
3225 pvt->info.show_interleave_mode = show_interleave_mode;
3226 pvt->info.dram_attr = dram_attr;
4d715a80
AR		 3227 pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule);
3228 pvt->info.interleave_list = ibridge_interleave_list;
3229 pvt->info.max_interleave = ARRAY_SIZE(ibridge_interleave_list);
3230 pvt->info.interleave_pkg = ibridge_interleave_pkg;
12f0721c 3231 pvt->info.get_width = ibridge_get_width;
4d715a80
AR		 3232 mci->ctl_name = kasprintf(GFP_KERNEL, "Ivy Bridge Socket#%d", mci->mc_idx);
3233
3234 /* Store pci devices at mci for faster access */
3235 rc = ibridge_mci_bind_devs(mci, sbridge_dev);
3236 if (unlikely(rc < 0))
3237 goto fail0;
50d1bb93
AR		 3238 break;
3239 case SANDY_BRIDGE:
4d715a80
AR		 3240 pvt->info.rankcfgr = SB_RANK_CFG_A;
3241 pvt->info.get_tolm = sbridge_get_tolm;
3242 pvt->info.get_tohm = sbridge_get_tohm;
3243 pvt->info.dram_rule = sbridge_dram_rule;
9e375446 3244 pvt->info.get_memory_type = get_memory_type;
f14d6892 3245 pvt->info.get_node_id = get_node_id;
b976bcf2 3246 pvt->info.rir_limit = rir_limit;
c59f9c06
JS		 3247 pvt->info.sad_limit = sad_limit;
3248 pvt->info.interleave_mode = interleave_mode;
3249 pvt->info.show_interleave_mode = show_interleave_mode;
3250 pvt->info.dram_attr = dram_attr;
4d715a80
AR		 3251 pvt->info.max_sad = ARRAY_SIZE(sbridge_dram_rule);
3252 pvt->info.interleave_list = sbridge_interleave_list;
3253 pvt->info.max_interleave = ARRAY_SIZE(sbridge_interleave_list);
3254 pvt->info.interleave_pkg = sbridge_interleave_pkg;
12f0721c 3255 pvt->info.get_width = sbridge_get_width;
4d715a80
AR		 3256 mci->ctl_name = kasprintf(GFP_KERNEL, "Sandy Bridge Socket#%d", mci->mc_idx);
3257
3258 /* Store pci devices at mci for faster access */
3259 rc = sbridge_mci_bind_devs(mci, sbridge_dev);
3260 if (unlikely(rc < 0))
3261 goto fail0;
50d1bb93
AR		 3262 break;
3263 case HASWELL:
3264 /* rankcfgr isn't used */
3265 pvt->info.get_tolm = haswell_get_tolm;
3266 pvt->info.get_tohm = haswell_get_tohm;
3267 pvt->info.dram_rule = ibridge_dram_rule;
3268 pvt->info.get_memory_type = haswell_get_memory_type;
3269 pvt->info.get_node_id = haswell_get_node_id;
3270 pvt->info.rir_limit = haswell_rir_limit;
c59f9c06
JS		 3271 pvt->info.sad_limit = sad_limit;
3272 pvt->info.interleave_mode = interleave_mode;
3273 pvt->info.show_interleave_mode = show_interleave_mode;
3274 pvt->info.dram_attr = dram_attr;
50d1bb93
AR		 3275 pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule);
3276 pvt->info.interleave_list = ibridge_interleave_list;
3277 pvt->info.max_interleave = ARRAY_SIZE(ibridge_interleave_list);
3278 pvt->info.interleave_pkg = ibridge_interleave_pkg;
12f0721c 3279 pvt->info.get_width = ibridge_get_width;
50d1bb93 3280 mci->ctl_name = kasprintf(GFP_KERNEL, "Haswell Socket#%d", mci->mc_idx);
4d715a80 3281
50d1bb93
AR		 3282 /* Store pci devices at mci for faster access */
3283 rc = haswell_mci_bind_devs(mci, sbridge_dev);
3284 if (unlikely(rc < 0))
3285 goto fail0;
3286 break;
1f39581a
TL		 3287 case BROADWELL:
3288 /* rankcfgr isn't used */
3289 pvt->info.get_tolm = haswell_get_tolm;
3290 pvt->info.get_tohm = haswell_get_tohm;
3291 pvt->info.dram_rule = ibridge_dram_rule;
3292 pvt->info.get_memory_type = haswell_get_memory_type;
3293 pvt->info.get_node_id = haswell_get_node_id;
3294 pvt->info.rir_limit = haswell_rir_limit;
c59f9c06
JS		 3295 pvt->info.sad_limit = sad_limit;
3296 pvt->info.interleave_mode = interleave_mode;
3297 pvt->info.show_interleave_mode = show_interleave_mode;
3298 pvt->info.dram_attr = dram_attr;
1f39581a
TL		 3299 pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule);
3300 pvt->info.interleave_list = ibridge_interleave_list;
3301 pvt->info.max_interleave = ARRAY_SIZE(ibridge_interleave_list);
3302 pvt->info.interleave_pkg = ibridge_interleave_pkg;
12f0721c 3303 pvt->info.get_width = broadwell_get_width;
1f39581a
TL		 3304 mci->ctl_name = kasprintf(GFP_KERNEL, "Broadwell Socket#%d", mci->mc_idx);
3305
3306 /* Store pci devices at mci for faster access */
3307 rc = broadwell_mci_bind_devs(mci, sbridge_dev);
3308 if (unlikely(rc < 0))
3309 goto fail0;
3310 break;
d0cdf900
JS		 3311 case KNIGHTS_LANDING:
3312 /* pvt->info.rankcfgr == ??? */
3313 pvt->info.get_tolm = knl_get_tolm;
3314 pvt->info.get_tohm = knl_get_tohm;
3315 pvt->info.dram_rule = knl_dram_rule;
3316 pvt->info.get_memory_type = knl_get_memory_type;
3317 pvt->info.get_node_id = knl_get_node_id;
3318 pvt->info.rir_limit = NULL;
3319 pvt->info.sad_limit = knl_sad_limit;
3320 pvt->info.interleave_mode = knl_interleave_mode;
3321 pvt->info.show_interleave_mode = knl_show_interleave_mode;
3322 pvt->info.dram_attr = dram_attr_knl;
3323 pvt->info.max_sad = ARRAY_SIZE(knl_dram_rule);
3324 pvt->info.interleave_list = knl_interleave_list;
3325 pvt->info.max_interleave = ARRAY_SIZE(knl_interleave_list);
3326 pvt->info.interleave_pkg = ibridge_interleave_pkg;
45f4d3ab 3327 pvt->info.get_width = knl_get_width;
d0cdf900
JS		 3328 mci->ctl_name = kasprintf(GFP_KERNEL,
3329 "Knights Landing Socket#%d", mci->mc_idx);
3330
3331 rc = knl_mci_bind_devs(mci, sbridge_dev);
3332 if (unlikely(rc < 0))
3333 goto fail0;
3334 break;
50d1bb93 3335 }
eebf11a0
MCC		 3336
3337 /* Get dimm basic config and the memory layout */
3338 get_dimm_config(mci);
3339 get_memory_layout(mci);
3340
3341 /* record ptr to the generic device */
4d715a80 3342 mci->pdev = &pdev->dev;
eebf11a0
MCC		 3343
3344 /* add this new MC control structure to EDAC's list of MCs */
3345 if (unlikely(edac_mc_add_mc(mci))) {
956b9ba1 3346 edac_dbg(0, "MC: failed edac_mc_add_mc()\n");
eebf11a0
MCC		 3347 rc = -EINVAL;
3348 goto fail0;
3349 }
3350
eebf11a0 3351 return 0;
eebf11a0
MCC		 3352
3353fail0:
3354 kfree(mci->ctl_name);
3355 edac_mc_free(mci);
3356 sbridge_dev->mci = NULL;
3357 return rc;
3358}
3359
2c1ea4c7
TL		 3360#define ICPU(model, table) \
3361 { X86_VENDOR_INTEL, 6, model, 0, (unsigned long)&table }
3362
3363/* Order here must match "enum type" */
3364static const struct x86_cpu_id sbridge_cpuids[] = {
3365 ICPU(0x2d, pci_dev_descr_sbridge_table), /* SANDY_BRIDGE */
3366 ICPU(0x3e, pci_dev_descr_ibridge_table), /* IVY_BRIDGE */
3367 ICPU(0x3f, pci_dev_descr_haswell_table), /* HASWELL */
3368 ICPU(0x4f, pci_dev_descr_broadwell_table), /* BROADWELL */
3369 ICPU(0x57, pci_dev_descr_knl_table), /* KNIGHTS_LANDING */
3370 { }
3371};
3372MODULE_DEVICE_TABLE(x86cpu, sbridge_cpuids);
3373
eebf11a0 3374/*
2c1ea4c7 3375 * sbridge_probe Get all devices and register memory controllers
eebf11a0
MCC		 3376 * present.
3377 * return:
3378 * 0 for FOUND a device
3379 * < 0 for error code
3380 */
3381
2c1ea4c7 3382static int sbridge_probe(const struct x86_cpu_id *id)
eebf11a0 3383{
50d1bb93 3384 int rc = -ENODEV;
eebf11a0
MCC		 3385 u8 mc, num_mc = 0;
3386 struct sbridge_dev *sbridge_dev;
2c1ea4c7 3387 struct pci_id_table *ptable = (struct pci_id_table *)id->driver_data;
eebf11a0
MCC		 3388
3389 /* get the pci devices we want to reserve for our use */
2c1ea4c7 3390 rc = sbridge_get_all_devices(&num_mc, ptable);
eebf11a0 3391
11249e73 3392 if (unlikely(rc < 0)) {
2c1ea4c7 3393 edac_dbg(0, "couldn't get all devices\n");
eebf11a0 3394 goto fail0;
11249e73
BP		 3395 }
3396
eebf11a0
MCC		 3397 mc = 0;
3398
3399 list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) {
956b9ba1
JP		 3400 edac_dbg(0, "Registering MC#%d (%d of %d)\n",
3401 mc, mc + 1, num_mc);
50d1bb93 3402
eebf11a0 3403 sbridge_dev->mc = mc++;
2c1ea4c7 3404 rc = sbridge_register_mci(sbridge_dev, id - sbridge_cpuids);
eebf11a0
MCC		 3405 if (unlikely(rc < 0))
3406 goto fail1;
3407 }
3408
11249e73 3409 sbridge_printk(KERN_INFO, "%s\n", SBRIDGE_REVISION);
eebf11a0 3410
eebf11a0
MCC		 3411 return 0;
3412
3413fail1:
3414 list_for_each_entry(sbridge_dev, &sbridge_edac_list, list)
3415 sbridge_unregister_mci(sbridge_dev);
3416
3417 sbridge_put_all_devices();
3418fail0:
eebf11a0
MCC		 3419 return rc;
3420}
3421
3422/*
2c1ea4c7 3423 * sbridge_remove cleanup
eebf11a0
MCC		 3424 *
3425 */
2c1ea4c7 3426static void sbridge_remove(void)
eebf11a0
MCC		 3427{
3428 struct sbridge_dev *sbridge_dev;
3429
956b9ba1 3430 edac_dbg(0, "\n");
eebf11a0 3431
eebf11a0
MCC		 3432 list_for_each_entry(sbridge_dev, &sbridge_edac_list, list)
3433 sbridge_unregister_mci(sbridge_dev);
3434
3435 /* Release PCI resources */
3436 sbridge_put_all_devices();
eebf11a0
MCC		 3437}
3438
eebf11a0
MCC		 3439/*
3440 * sbridge_init Module entry function
3441 * Try to initialize this module for its devices
3442 */
3443static int __init sbridge_init(void)
3444{
2c1ea4c7
TL		 3445 const struct x86_cpu_id *id;
3446 int rc;
eebf11a0 3447
956b9ba1 3448 edac_dbg(2, "\n");
eebf11a0 3449
2c1ea4c7
TL		 3450 id = x86_match_cpu(sbridge_cpuids);
3451 if (!id)
3452 return -ENODEV;
3453
eebf11a0
MCC		 3454 /* Ensure that the OPSTATE is set correctly for POLL or NMI */
3455 opstate_init();
3456
2c1ea4c7
TL		 3457 rc = sbridge_probe(id);
3458
3459 if (rc >= 0) {
e35fca47 3460 mce_register_decode_chain(&sbridge_mce_dec);
fd521039
CG		 3461 if (get_edac_report_status() == EDAC_REPORTING_DISABLED)
3462 sbridge_printk(KERN_WARNING, "Loading driver, error reporting disabled.\n");
eebf11a0 3463 return 0;
e35fca47 3464 }
eebf11a0
MCC		 3465
3466 sbridge_printk(KERN_ERR, "Failed to register device with error %d.\n",
2c1ea4c7 3467 rc);
eebf11a0 3468
2c1ea4c7 3469 return rc;
eebf11a0
MCC		 3470}
3471
3472/*
3473 * sbridge_exit() Module exit function
3474 * Unregister the driver
3475 */
3476static void __exit sbridge_exit(void)
3477{
956b9ba1 3478 edac_dbg(2, "\n");
2c1ea4c7 3479 sbridge_remove();
e35fca47 3480 mce_unregister_decode_chain(&sbridge_mce_dec);
eebf11a0
MCC		 3481}
3482
3483module_init(sbridge_init);
3484module_exit(sbridge_exit);
3485
3486module_param(edac_op_state, int, 0444);
3487MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
3488
3489MODULE_LICENSE("GPL");
37e59f87 3490MODULE_AUTHOR("Mauro Carvalho Chehab");
eebf11a0 3491MODULE_AUTHOR("Red Hat Inc. (http://www.redhat.com)");
4d715a80 3492MODULE_DESCRIPTION("MC Driver for Intel Sandy Bridge and Ivy Bridge memory controllers - "
eebf11a0 3493 SBRIDGE_REVISION);
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