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4ec656bd TL |
1 | /* |
2 | * EDAC driver for Intel(R) Xeon(R) Skylake processors | |
3 | * Copyright (c) 2016, Intel Corporation. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms and conditions of the GNU General Public License, | |
7 | * version 2, as published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | */ | |
14 | ||
15 | #include <linux/module.h> | |
16 | #include <linux/init.h> | |
17 | #include <linux/pci.h> | |
18 | #include <linux/pci_ids.h> | |
19 | #include <linux/slab.h> | |
20 | #include <linux/delay.h> | |
21 | #include <linux/edac.h> | |
22 | #include <linux/mmzone.h> | |
23 | #include <linux/smp.h> | |
24 | #include <linux/bitmap.h> | |
25 | #include <linux/math64.h> | |
26 | #include <linux/mod_devicetable.h> | |
27 | #include <asm/cpu_device_id.h> | |
20f4d692 | 28 | #include <asm/intel-family.h> |
4ec656bd TL |
29 | #include <asm/processor.h> |
30 | #include <asm/mce.h> | |
31 | ||
78d88e8a | 32 | #include "edac_module.h" |
4ec656bd TL |
33 | |
34 | #define SKX_REVISION " Ver: 1.0 " | |
35 | ||
36 | /* | |
37 | * Debug macros | |
38 | */ | |
39 | #define skx_printk(level, fmt, arg...) \ | |
40 | edac_printk(level, "skx", fmt, ##arg) | |
41 | ||
42 | #define skx_mc_printk(mci, level, fmt, arg...) \ | |
43 | edac_mc_chipset_printk(mci, level, "skx", fmt, ##arg) | |
44 | ||
45 | /* | |
46 | * Get a bit field at register value <v>, from bit <lo> to bit <hi> | |
47 | */ | |
48 | #define GET_BITFIELD(v, lo, hi) \ | |
49 | (((v) & GENMASK_ULL((hi), (lo))) >> (lo)) | |
50 | ||
51 | static LIST_HEAD(skx_edac_list); | |
52 | ||
53 | static u64 skx_tolm, skx_tohm; | |
54 | ||
55 | #define NUM_IMC 2 /* memory controllers per socket */ | |
56 | #define NUM_CHANNELS 3 /* channels per memory controller */ | |
57 | #define NUM_DIMMS 2 /* Max DIMMS per channel */ | |
58 | ||
59 | #define MASK26 0x3FFFFFF /* Mask for 2^26 */ | |
60 | #define MASK29 0x1FFFFFFF /* Mask for 2^29 */ | |
61 | ||
62 | /* | |
63 | * Each cpu socket contains some pci devices that provide global | |
64 | * information, and also some that are local to each of the two | |
65 | * memory controllers on the die. | |
66 | */ | |
67 | struct skx_dev { | |
68 | struct list_head list; | |
69 | u8 bus[4]; | |
70 | struct pci_dev *sad_all; | |
71 | struct pci_dev *util_all; | |
72 | u32 mcroute; | |
73 | struct skx_imc { | |
74 | struct mem_ctl_info *mci; | |
75 | u8 mc; /* system wide mc# */ | |
76 | u8 lmc; /* socket relative mc# */ | |
77 | u8 src_id, node_id; | |
78 | struct skx_channel { | |
79 | struct pci_dev *cdev; | |
80 | struct skx_dimm { | |
81 | u8 close_pg; | |
82 | u8 bank_xor_enable; | |
83 | u8 fine_grain_bank; | |
84 | u8 rowbits; | |
85 | u8 colbits; | |
86 | } dimms[NUM_DIMMS]; | |
87 | } chan[NUM_CHANNELS]; | |
88 | } imc[NUM_IMC]; | |
89 | }; | |
90 | static int skx_num_sockets; | |
91 | ||
92 | struct skx_pvt { | |
93 | struct skx_imc *imc; | |
94 | }; | |
95 | ||
96 | struct decoded_addr { | |
97 | struct skx_dev *dev; | |
98 | u64 addr; | |
99 | int socket; | |
100 | int imc; | |
101 | int channel; | |
102 | u64 chan_addr; | |
103 | int sktways; | |
104 | int chanways; | |
105 | int dimm; | |
106 | int rank; | |
107 | int channel_rank; | |
108 | u64 rank_address; | |
109 | int row; | |
110 | int column; | |
111 | int bank_address; | |
112 | int bank_group; | |
113 | }; | |
114 | ||
115 | static struct skx_dev *get_skx_dev(u8 bus, u8 idx) | |
116 | { | |
117 | struct skx_dev *d; | |
118 | ||
119 | list_for_each_entry(d, &skx_edac_list, list) { | |
120 | if (d->bus[idx] == bus) | |
121 | return d; | |
122 | } | |
123 | ||
124 | return NULL; | |
125 | } | |
126 | ||
127 | enum munittype { | |
128 | CHAN0, CHAN1, CHAN2, SAD_ALL, UTIL_ALL, SAD | |
129 | }; | |
130 | ||
131 | struct munit { | |
132 | u16 did; | |
133 | u16 devfn[NUM_IMC]; | |
134 | u8 busidx; | |
135 | u8 per_socket; | |
136 | enum munittype mtype; | |
137 | }; | |
138 | ||
139 | /* | |
140 | * List of PCI device ids that we need together with some device | |
141 | * number and function numbers to tell which memory controller the | |
142 | * device belongs to. | |
143 | */ | |
144 | static const struct munit skx_all_munits[] = { | |
145 | { 0x2054, { }, 1, 1, SAD_ALL }, | |
146 | { 0x2055, { }, 1, 1, UTIL_ALL }, | |
147 | { 0x2040, { PCI_DEVFN(10, 0), PCI_DEVFN(12, 0) }, 2, 2, CHAN0 }, | |
148 | { 0x2044, { PCI_DEVFN(10, 4), PCI_DEVFN(12, 4) }, 2, 2, CHAN1 }, | |
149 | { 0x2048, { PCI_DEVFN(11, 0), PCI_DEVFN(13, 0) }, 2, 2, CHAN2 }, | |
150 | { 0x208e, { }, 1, 0, SAD }, | |
151 | { } | |
152 | }; | |
153 | ||
154 | /* | |
155 | * We use the per-socket device 0x2016 to count how many sockets are present, | |
156 | * and to detemine which PCI buses are associated with each socket. Allocate | |
157 | * and build the full list of all the skx_dev structures that we need here. | |
158 | */ | |
159 | static int get_all_bus_mappings(void) | |
160 | { | |
161 | struct pci_dev *pdev, *prev; | |
162 | struct skx_dev *d; | |
163 | u32 reg; | |
164 | int ndev = 0; | |
165 | ||
166 | prev = NULL; | |
167 | for (;;) { | |
168 | pdev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x2016, prev); | |
169 | if (!pdev) | |
170 | break; | |
171 | ndev++; | |
172 | d = kzalloc(sizeof(*d), GFP_KERNEL); | |
173 | if (!d) { | |
174 | pci_dev_put(pdev); | |
175 | return -ENOMEM; | |
176 | } | |
177 | pci_read_config_dword(pdev, 0xCC, ®); | |
178 | d->bus[0] = GET_BITFIELD(reg, 0, 7); | |
179 | d->bus[1] = GET_BITFIELD(reg, 8, 15); | |
180 | d->bus[2] = GET_BITFIELD(reg, 16, 23); | |
181 | d->bus[3] = GET_BITFIELD(reg, 24, 31); | |
182 | edac_dbg(2, "busses: %x, %x, %x, %x\n", | |
183 | d->bus[0], d->bus[1], d->bus[2], d->bus[3]); | |
184 | list_add_tail(&d->list, &skx_edac_list); | |
185 | skx_num_sockets++; | |
186 | prev = pdev; | |
187 | } | |
188 | ||
189 | return ndev; | |
190 | } | |
191 | ||
192 | static int get_all_munits(const struct munit *m) | |
193 | { | |
194 | struct pci_dev *pdev, *prev; | |
195 | struct skx_dev *d; | |
196 | u32 reg; | |
197 | int i = 0, ndev = 0; | |
198 | ||
199 | prev = NULL; | |
200 | for (;;) { | |
201 | pdev = pci_get_device(PCI_VENDOR_ID_INTEL, m->did, prev); | |
202 | if (!pdev) | |
203 | break; | |
204 | ndev++; | |
205 | if (m->per_socket == NUM_IMC) { | |
206 | for (i = 0; i < NUM_IMC; i++) | |
207 | if (m->devfn[i] == pdev->devfn) | |
208 | break; | |
209 | if (i == NUM_IMC) | |
210 | goto fail; | |
211 | } | |
212 | d = get_skx_dev(pdev->bus->number, m->busidx); | |
213 | if (!d) | |
214 | goto fail; | |
215 | ||
216 | /* Be sure that the device is enabled */ | |
217 | if (unlikely(pci_enable_device(pdev) < 0)) { | |
218 | skx_printk(KERN_ERR, | |
219 | "Couldn't enable %04x:%04x\n", PCI_VENDOR_ID_INTEL, m->did); | |
220 | goto fail; | |
221 | } | |
222 | ||
223 | switch (m->mtype) { | |
224 | case CHAN0: case CHAN1: case CHAN2: | |
225 | pci_dev_get(pdev); | |
226 | d->imc[i].chan[m->mtype].cdev = pdev; | |
227 | break; | |
228 | case SAD_ALL: | |
229 | pci_dev_get(pdev); | |
230 | d->sad_all = pdev; | |
231 | break; | |
232 | case UTIL_ALL: | |
233 | pci_dev_get(pdev); | |
234 | d->util_all = pdev; | |
235 | break; | |
236 | case SAD: | |
237 | /* | |
238 | * one of these devices per core, including cores | |
239 | * that don't exist on this SKU. Ignore any that | |
240 | * read a route table of zero, make sure all the | |
241 | * non-zero values match. | |
242 | */ | |
243 | pci_read_config_dword(pdev, 0xB4, ®); | |
244 | if (reg != 0) { | |
245 | if (d->mcroute == 0) | |
246 | d->mcroute = reg; | |
247 | else if (d->mcroute != reg) { | |
248 | skx_printk(KERN_ERR, | |
249 | "mcroute mismatch\n"); | |
250 | goto fail; | |
251 | } | |
252 | } | |
253 | ndev--; | |
254 | break; | |
255 | } | |
256 | ||
257 | prev = pdev; | |
258 | } | |
259 | ||
260 | return ndev; | |
261 | fail: | |
262 | pci_dev_put(pdev); | |
263 | return -ENODEV; | |
264 | } | |
265 | ||
240ea921 | 266 | static const struct x86_cpu_id skx_cpuids[] = { |
20f4d692 | 267 | { X86_VENDOR_INTEL, 6, INTEL_FAM6_SKYLAKE_X, 0, 0 }, |
4ec656bd TL |
268 | { } |
269 | }; | |
270 | MODULE_DEVICE_TABLE(x86cpu, skx_cpuids); | |
271 | ||
272 | static u8 get_src_id(struct skx_dev *d) | |
273 | { | |
274 | u32 reg; | |
275 | ||
276 | pci_read_config_dword(d->util_all, 0xF0, ®); | |
277 | ||
278 | return GET_BITFIELD(reg, 12, 14); | |
279 | } | |
280 | ||
281 | static u8 skx_get_node_id(struct skx_dev *d) | |
282 | { | |
283 | u32 reg; | |
284 | ||
285 | pci_read_config_dword(d->util_all, 0xF4, ®); | |
286 | ||
287 | return GET_BITFIELD(reg, 0, 2); | |
288 | } | |
289 | ||
290 | static int get_dimm_attr(u32 reg, int lobit, int hibit, int add, int minval, | |
291 | int maxval, char *name) | |
292 | { | |
293 | u32 val = GET_BITFIELD(reg, lobit, hibit); | |
294 | ||
295 | if (val < minval || val > maxval) { | |
296 | edac_dbg(2, "bad %s = %d (raw=%x)\n", name, val, reg); | |
297 | return -EINVAL; | |
298 | } | |
299 | return val + add; | |
300 | } | |
301 | ||
302 | #define IS_DIMM_PRESENT(mtr) GET_BITFIELD((mtr), 15, 15) | |
303 | ||
304 | #define numrank(reg) get_dimm_attr((reg), 12, 13, 0, 1, 2, "ranks") | |
305 | #define numrow(reg) get_dimm_attr((reg), 2, 4, 12, 1, 6, "rows") | |
306 | #define numcol(reg) get_dimm_attr((reg), 0, 1, 10, 0, 2, "cols") | |
307 | ||
308 | static int get_width(u32 mtr) | |
309 | { | |
310 | switch (GET_BITFIELD(mtr, 8, 9)) { | |
311 | case 0: | |
312 | return DEV_X4; | |
313 | case 1: | |
314 | return DEV_X8; | |
315 | case 2: | |
316 | return DEV_X16; | |
317 | } | |
318 | return DEV_UNKNOWN; | |
319 | } | |
320 | ||
321 | static int skx_get_hi_lo(void) | |
322 | { | |
323 | struct pci_dev *pdev; | |
324 | u32 reg; | |
325 | ||
326 | pdev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x2034, NULL); | |
327 | if (!pdev) { | |
328 | edac_dbg(0, "Can't get tolm/tohm\n"); | |
329 | return -ENODEV; | |
330 | } | |
331 | ||
332 | pci_read_config_dword(pdev, 0xD0, ®); | |
333 | skx_tolm = reg; | |
334 | pci_read_config_dword(pdev, 0xD4, ®); | |
335 | skx_tohm = reg; | |
336 | pci_read_config_dword(pdev, 0xD8, ®); | |
337 | skx_tohm |= (u64)reg << 32; | |
338 | ||
339 | pci_dev_put(pdev); | |
340 | edac_dbg(2, "tolm=%llx tohm=%llx\n", skx_tolm, skx_tohm); | |
341 | ||
342 | return 0; | |
343 | } | |
344 | ||
345 | static int get_dimm_info(u32 mtr, u32 amap, struct dimm_info *dimm, | |
346 | struct skx_imc *imc, int chan, int dimmno) | |
347 | { | |
348 | int banks = 16, ranks, rows, cols, npages; | |
349 | u64 size; | |
350 | ||
351 | if (!IS_DIMM_PRESENT(mtr)) | |
352 | return 0; | |
353 | ranks = numrank(mtr); | |
354 | rows = numrow(mtr); | |
355 | cols = numcol(mtr); | |
356 | ||
357 | /* | |
358 | * Compute size in 8-byte (2^3) words, then shift to MiB (2^20) | |
359 | */ | |
360 | size = ((1ull << (rows + cols + ranks)) * banks) >> (20 - 3); | |
361 | npages = MiB_TO_PAGES(size); | |
362 | ||
363 | edac_dbg(0, "mc#%d: channel %d, dimm %d, %lld Mb (%d pages) bank: %d, rank: %d, row: %#x, col: %#x\n", | |
364 | imc->mc, chan, dimmno, size, npages, | |
365 | banks, ranks, rows, cols); | |
366 | ||
367 | imc->chan[chan].dimms[dimmno].close_pg = GET_BITFIELD(mtr, 0, 0); | |
368 | imc->chan[chan].dimms[dimmno].bank_xor_enable = GET_BITFIELD(mtr, 9, 9); | |
369 | imc->chan[chan].dimms[dimmno].fine_grain_bank = GET_BITFIELD(amap, 0, 0); | |
370 | imc->chan[chan].dimms[dimmno].rowbits = rows; | |
371 | imc->chan[chan].dimms[dimmno].colbits = cols; | |
372 | ||
373 | dimm->nr_pages = npages; | |
374 | dimm->grain = 32; | |
375 | dimm->dtype = get_width(mtr); | |
376 | dimm->mtype = MEM_DDR4; | |
377 | dimm->edac_mode = EDAC_SECDED; /* likely better than this */ | |
378 | snprintf(dimm->label, sizeof(dimm->label), "CPU_SrcID#%u_MC#%u_Chan#%u_DIMM#%u", | |
379 | imc->src_id, imc->lmc, chan, dimmno); | |
380 | ||
381 | return 1; | |
382 | } | |
383 | ||
384 | #define SKX_GET_MTMTR(dev, reg) \ | |
385 | pci_read_config_dword((dev), 0x87c, ®) | |
386 | ||
387 | static bool skx_check_ecc(struct pci_dev *pdev) | |
388 | { | |
389 | u32 mtmtr; | |
390 | ||
391 | SKX_GET_MTMTR(pdev, mtmtr); | |
392 | ||
393 | return !!GET_BITFIELD(mtmtr, 2, 2); | |
394 | } | |
395 | ||
396 | static int skx_get_dimm_config(struct mem_ctl_info *mci) | |
397 | { | |
398 | struct skx_pvt *pvt = mci->pvt_info; | |
399 | struct skx_imc *imc = pvt->imc; | |
400 | struct dimm_info *dimm; | |
401 | int i, j; | |
402 | u32 mtr, amap; | |
403 | int ndimms; | |
404 | ||
405 | for (i = 0; i < NUM_CHANNELS; i++) { | |
406 | ndimms = 0; | |
407 | pci_read_config_dword(imc->chan[i].cdev, 0x8C, &amap); | |
408 | for (j = 0; j < NUM_DIMMS; j++) { | |
409 | dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, | |
410 | mci->n_layers, i, j, 0); | |
411 | pci_read_config_dword(imc->chan[i].cdev, | |
412 | 0x80 + 4*j, &mtr); | |
413 | ndimms += get_dimm_info(mtr, amap, dimm, imc, i, j); | |
414 | } | |
415 | if (ndimms && !skx_check_ecc(imc->chan[0].cdev)) { | |
416 | skx_printk(KERN_ERR, "ECC is disabled on imc %d\n", imc->mc); | |
417 | return -ENODEV; | |
418 | } | |
419 | } | |
420 | ||
421 | return 0; | |
422 | } | |
423 | ||
424 | static void skx_unregister_mci(struct skx_imc *imc) | |
425 | { | |
426 | struct mem_ctl_info *mci = imc->mci; | |
427 | ||
428 | if (!mci) | |
429 | return; | |
430 | ||
431 | edac_dbg(0, "MC%d: mci = %p\n", imc->mc, mci); | |
432 | ||
433 | /* Remove MC sysfs nodes */ | |
434 | edac_mc_del_mc(mci->pdev); | |
435 | ||
436 | edac_dbg(1, "%s: free mci struct\n", mci->ctl_name); | |
437 | kfree(mci->ctl_name); | |
438 | edac_mc_free(mci); | |
439 | } | |
440 | ||
441 | static int skx_register_mci(struct skx_imc *imc) | |
442 | { | |
443 | struct mem_ctl_info *mci; | |
444 | struct edac_mc_layer layers[2]; | |
445 | struct pci_dev *pdev = imc->chan[0].cdev; | |
446 | struct skx_pvt *pvt; | |
447 | int rc; | |
448 | ||
449 | /* allocate a new MC control structure */ | |
450 | layers[0].type = EDAC_MC_LAYER_CHANNEL; | |
451 | layers[0].size = NUM_CHANNELS; | |
452 | layers[0].is_virt_csrow = false; | |
453 | layers[1].type = EDAC_MC_LAYER_SLOT; | |
454 | layers[1].size = NUM_DIMMS; | |
455 | layers[1].is_virt_csrow = true; | |
456 | mci = edac_mc_alloc(imc->mc, ARRAY_SIZE(layers), layers, | |
457 | sizeof(struct skx_pvt)); | |
458 | ||
459 | if (unlikely(!mci)) | |
460 | return -ENOMEM; | |
461 | ||
462 | edac_dbg(0, "MC#%d: mci = %p\n", imc->mc, mci); | |
463 | ||
464 | /* Associate skx_dev and mci for future usage */ | |
465 | imc->mci = mci; | |
466 | pvt = mci->pvt_info; | |
467 | pvt->imc = imc; | |
468 | ||
469 | mci->ctl_name = kasprintf(GFP_KERNEL, "Skylake Socket#%d IMC#%d", | |
470 | imc->node_id, imc->lmc); | |
471 | mci->mtype_cap = MEM_FLAG_DDR4; | |
472 | mci->edac_ctl_cap = EDAC_FLAG_NONE; | |
473 | mci->edac_cap = EDAC_FLAG_NONE; | |
474 | mci->mod_name = "skx_edac.c"; | |
475 | mci->dev_name = pci_name(imc->chan[0].cdev); | |
476 | mci->mod_ver = SKX_REVISION; | |
477 | mci->ctl_page_to_phys = NULL; | |
478 | ||
479 | rc = skx_get_dimm_config(mci); | |
480 | if (rc < 0) | |
481 | goto fail; | |
482 | ||
483 | /* record ptr to the generic device */ | |
484 | mci->pdev = &pdev->dev; | |
485 | ||
486 | /* add this new MC control structure to EDAC's list of MCs */ | |
487 | if (unlikely(edac_mc_add_mc(mci))) { | |
488 | edac_dbg(0, "MC: failed edac_mc_add_mc()\n"); | |
489 | rc = -EINVAL; | |
490 | goto fail; | |
491 | } | |
492 | ||
493 | return 0; | |
494 | ||
495 | fail: | |
496 | kfree(mci->ctl_name); | |
497 | edac_mc_free(mci); | |
498 | imc->mci = NULL; | |
499 | return rc; | |
500 | } | |
501 | ||
502 | #define SKX_MAX_SAD 24 | |
503 | ||
504 | #define SKX_GET_SAD(d, i, reg) \ | |
505 | pci_read_config_dword((d)->sad_all, 0x60 + 8 * (i), ®) | |
506 | #define SKX_GET_ILV(d, i, reg) \ | |
507 | pci_read_config_dword((d)->sad_all, 0x64 + 8 * (i), ®) | |
508 | ||
509 | #define SKX_SAD_MOD3MODE(sad) GET_BITFIELD((sad), 30, 31) | |
510 | #define SKX_SAD_MOD3(sad) GET_BITFIELD((sad), 27, 27) | |
511 | #define SKX_SAD_LIMIT(sad) (((u64)GET_BITFIELD((sad), 7, 26) << 26) | MASK26) | |
512 | #define SKX_SAD_MOD3ASMOD2(sad) GET_BITFIELD((sad), 5, 6) | |
513 | #define SKX_SAD_ATTR(sad) GET_BITFIELD((sad), 3, 4) | |
514 | #define SKX_SAD_INTERLEAVE(sad) GET_BITFIELD((sad), 1, 2) | |
515 | #define SKX_SAD_ENABLE(sad) GET_BITFIELD((sad), 0, 0) | |
516 | ||
517 | #define SKX_ILV_REMOTE(tgt) (((tgt) & 8) == 0) | |
518 | #define SKX_ILV_TARGET(tgt) ((tgt) & 7) | |
519 | ||
520 | static bool skx_sad_decode(struct decoded_addr *res) | |
521 | { | |
522 | struct skx_dev *d = list_first_entry(&skx_edac_list, typeof(*d), list); | |
523 | u64 addr = res->addr; | |
524 | int i, idx, tgt, lchan, shift; | |
525 | u32 sad, ilv; | |
526 | u64 limit, prev_limit; | |
527 | int remote = 0; | |
528 | ||
529 | /* Simple sanity check for I/O space or out of range */ | |
530 | if (addr >= skx_tohm || (addr >= skx_tolm && addr < BIT_ULL(32))) { | |
531 | edac_dbg(0, "Address %llx out of range\n", addr); | |
532 | return false; | |
533 | } | |
534 | ||
535 | restart: | |
536 | prev_limit = 0; | |
537 | for (i = 0; i < SKX_MAX_SAD; i++) { | |
538 | SKX_GET_SAD(d, i, sad); | |
539 | limit = SKX_SAD_LIMIT(sad); | |
540 | if (SKX_SAD_ENABLE(sad)) { | |
541 | if (addr >= prev_limit && addr <= limit) | |
542 | goto sad_found; | |
543 | } | |
544 | prev_limit = limit + 1; | |
545 | } | |
546 | edac_dbg(0, "No SAD entry for %llx\n", addr); | |
547 | return false; | |
548 | ||
549 | sad_found: | |
550 | SKX_GET_ILV(d, i, ilv); | |
551 | ||
552 | switch (SKX_SAD_INTERLEAVE(sad)) { | |
553 | case 0: | |
554 | idx = GET_BITFIELD(addr, 6, 8); | |
555 | break; | |
556 | case 1: | |
557 | idx = GET_BITFIELD(addr, 8, 10); | |
558 | break; | |
559 | case 2: | |
560 | idx = GET_BITFIELD(addr, 12, 14); | |
561 | break; | |
562 | case 3: | |
563 | idx = GET_BITFIELD(addr, 30, 32); | |
564 | break; | |
565 | } | |
566 | ||
567 | tgt = GET_BITFIELD(ilv, 4 * idx, 4 * idx + 3); | |
568 | ||
569 | /* If point to another node, find it and start over */ | |
570 | if (SKX_ILV_REMOTE(tgt)) { | |
571 | if (remote) { | |
572 | edac_dbg(0, "Double remote!\n"); | |
573 | return false; | |
574 | } | |
575 | remote = 1; | |
576 | list_for_each_entry(d, &skx_edac_list, list) { | |
577 | if (d->imc[0].src_id == SKX_ILV_TARGET(tgt)) | |
578 | goto restart; | |
579 | } | |
580 | edac_dbg(0, "Can't find node %d\n", SKX_ILV_TARGET(tgt)); | |
581 | return false; | |
582 | } | |
583 | ||
584 | if (SKX_SAD_MOD3(sad) == 0) | |
585 | lchan = SKX_ILV_TARGET(tgt); | |
586 | else { | |
587 | switch (SKX_SAD_MOD3MODE(sad)) { | |
588 | case 0: | |
589 | shift = 6; | |
590 | break; | |
591 | case 1: | |
592 | shift = 8; | |
593 | break; | |
594 | case 2: | |
595 | shift = 12; | |
596 | break; | |
597 | default: | |
598 | edac_dbg(0, "illegal mod3mode\n"); | |
599 | return false; | |
600 | } | |
601 | switch (SKX_SAD_MOD3ASMOD2(sad)) { | |
602 | case 0: | |
603 | lchan = (addr >> shift) % 3; | |
604 | break; | |
605 | case 1: | |
606 | lchan = (addr >> shift) % 2; | |
607 | break; | |
608 | case 2: | |
609 | lchan = (addr >> shift) % 2; | |
610 | lchan = (lchan << 1) | ~lchan; | |
611 | break; | |
612 | case 3: | |
613 | lchan = ((addr >> shift) % 2) << 1; | |
614 | break; | |
615 | } | |
616 | lchan = (lchan << 1) | (SKX_ILV_TARGET(tgt) & 1); | |
617 | } | |
618 | ||
619 | res->dev = d; | |
620 | res->socket = d->imc[0].src_id; | |
621 | res->imc = GET_BITFIELD(d->mcroute, lchan * 3, lchan * 3 + 2); | |
622 | res->channel = GET_BITFIELD(d->mcroute, lchan * 2 + 18, lchan * 2 + 19); | |
623 | ||
624 | edac_dbg(2, "%llx: socket=%d imc=%d channel=%d\n", | |
625 | res->addr, res->socket, res->imc, res->channel); | |
626 | return true; | |
627 | } | |
628 | ||
629 | #define SKX_MAX_TAD 8 | |
630 | ||
631 | #define SKX_GET_TADBASE(d, mc, i, reg) \ | |
632 | pci_read_config_dword((d)->imc[mc].chan[0].cdev, 0x850 + 4 * (i), ®) | |
633 | #define SKX_GET_TADWAYNESS(d, mc, i, reg) \ | |
634 | pci_read_config_dword((d)->imc[mc].chan[0].cdev, 0x880 + 4 * (i), ®) | |
635 | #define SKX_GET_TADCHNILVOFFSET(d, mc, ch, i, reg) \ | |
636 | pci_read_config_dword((d)->imc[mc].chan[ch].cdev, 0x90 + 4 * (i), ®) | |
637 | ||
638 | #define SKX_TAD_BASE(b) ((u64)GET_BITFIELD((b), 12, 31) << 26) | |
639 | #define SKX_TAD_SKT_GRAN(b) GET_BITFIELD((b), 4, 5) | |
640 | #define SKX_TAD_CHN_GRAN(b) GET_BITFIELD((b), 6, 7) | |
641 | #define SKX_TAD_LIMIT(b) (((u64)GET_BITFIELD((b), 12, 31) << 26) | MASK26) | |
642 | #define SKX_TAD_OFFSET(b) ((u64)GET_BITFIELD((b), 4, 23) << 26) | |
643 | #define SKX_TAD_SKTWAYS(b) (1 << GET_BITFIELD((b), 10, 11)) | |
644 | #define SKX_TAD_CHNWAYS(b) (GET_BITFIELD((b), 8, 9) + 1) | |
645 | ||
646 | /* which bit used for both socket and channel interleave */ | |
647 | static int skx_granularity[] = { 6, 8, 12, 30 }; | |
648 | ||
649 | static u64 skx_do_interleave(u64 addr, int shift, int ways, u64 lowbits) | |
650 | { | |
651 | addr >>= shift; | |
652 | addr /= ways; | |
653 | addr <<= shift; | |
654 | ||
655 | return addr | (lowbits & ((1ull << shift) - 1)); | |
656 | } | |
657 | ||
658 | static bool skx_tad_decode(struct decoded_addr *res) | |
659 | { | |
660 | int i; | |
661 | u32 base, wayness, chnilvoffset; | |
662 | int skt_interleave_bit, chn_interleave_bit; | |
663 | u64 channel_addr; | |
664 | ||
665 | for (i = 0; i < SKX_MAX_TAD; i++) { | |
666 | SKX_GET_TADBASE(res->dev, res->imc, i, base); | |
667 | SKX_GET_TADWAYNESS(res->dev, res->imc, i, wayness); | |
668 | if (SKX_TAD_BASE(base) <= res->addr && res->addr <= SKX_TAD_LIMIT(wayness)) | |
669 | goto tad_found; | |
670 | } | |
671 | edac_dbg(0, "No TAD entry for %llx\n", res->addr); | |
672 | return false; | |
673 | ||
674 | tad_found: | |
675 | res->sktways = SKX_TAD_SKTWAYS(wayness); | |
676 | res->chanways = SKX_TAD_CHNWAYS(wayness); | |
677 | skt_interleave_bit = skx_granularity[SKX_TAD_SKT_GRAN(base)]; | |
678 | chn_interleave_bit = skx_granularity[SKX_TAD_CHN_GRAN(base)]; | |
679 | ||
680 | SKX_GET_TADCHNILVOFFSET(res->dev, res->imc, res->channel, i, chnilvoffset); | |
681 | channel_addr = res->addr - SKX_TAD_OFFSET(chnilvoffset); | |
682 | ||
683 | if (res->chanways == 3 && skt_interleave_bit > chn_interleave_bit) { | |
684 | /* Must handle channel first, then socket */ | |
685 | channel_addr = skx_do_interleave(channel_addr, chn_interleave_bit, | |
686 | res->chanways, channel_addr); | |
687 | channel_addr = skx_do_interleave(channel_addr, skt_interleave_bit, | |
688 | res->sktways, channel_addr); | |
689 | } else { | |
690 | /* Handle socket then channel. Preserve low bits from original address */ | |
691 | channel_addr = skx_do_interleave(channel_addr, skt_interleave_bit, | |
692 | res->sktways, res->addr); | |
693 | channel_addr = skx_do_interleave(channel_addr, chn_interleave_bit, | |
694 | res->chanways, res->addr); | |
695 | } | |
696 | ||
697 | res->chan_addr = channel_addr; | |
698 | ||
699 | edac_dbg(2, "%llx: chan_addr=%llx sktways=%d chanways=%d\n", | |
700 | res->addr, res->chan_addr, res->sktways, res->chanways); | |
701 | return true; | |
702 | } | |
703 | ||
704 | #define SKX_MAX_RIR 4 | |
705 | ||
706 | #define SKX_GET_RIRWAYNESS(d, mc, ch, i, reg) \ | |
707 | pci_read_config_dword((d)->imc[mc].chan[ch].cdev, \ | |
708 | 0x108 + 4 * (i), ®) | |
709 | #define SKX_GET_RIRILV(d, mc, ch, idx, i, reg) \ | |
710 | pci_read_config_dword((d)->imc[mc].chan[ch].cdev, \ | |
711 | 0x120 + 16 * idx + 4 * (i), ®) | |
712 | ||
713 | #define SKX_RIR_VALID(b) GET_BITFIELD((b), 31, 31) | |
714 | #define SKX_RIR_LIMIT(b) (((u64)GET_BITFIELD((b), 1, 11) << 29) | MASK29) | |
715 | #define SKX_RIR_WAYS(b) (1 << GET_BITFIELD((b), 28, 29)) | |
716 | #define SKX_RIR_CHAN_RANK(b) GET_BITFIELD((b), 16, 19) | |
717 | #define SKX_RIR_OFFSET(b) ((u64)(GET_BITFIELD((b), 2, 15) << 26)) | |
718 | ||
719 | static bool skx_rir_decode(struct decoded_addr *res) | |
720 | { | |
721 | int i, idx, chan_rank; | |
722 | int shift; | |
723 | u32 rirway, rirlv; | |
724 | u64 rank_addr, prev_limit = 0, limit; | |
725 | ||
726 | if (res->dev->imc[res->imc].chan[res->channel].dimms[0].close_pg) | |
727 | shift = 6; | |
728 | else | |
729 | shift = 13; | |
730 | ||
731 | for (i = 0; i < SKX_MAX_RIR; i++) { | |
732 | SKX_GET_RIRWAYNESS(res->dev, res->imc, res->channel, i, rirway); | |
733 | limit = SKX_RIR_LIMIT(rirway); | |
734 | if (SKX_RIR_VALID(rirway)) { | |
735 | if (prev_limit <= res->chan_addr && | |
736 | res->chan_addr <= limit) | |
737 | goto rir_found; | |
738 | } | |
739 | prev_limit = limit; | |
740 | } | |
741 | edac_dbg(0, "No RIR entry for %llx\n", res->addr); | |
742 | return false; | |
743 | ||
744 | rir_found: | |
745 | rank_addr = res->chan_addr >> shift; | |
746 | rank_addr /= SKX_RIR_WAYS(rirway); | |
747 | rank_addr <<= shift; | |
748 | rank_addr |= res->chan_addr & GENMASK_ULL(shift - 1, 0); | |
749 | ||
750 | res->rank_address = rank_addr; | |
751 | idx = (res->chan_addr >> shift) % SKX_RIR_WAYS(rirway); | |
752 | ||
753 | SKX_GET_RIRILV(res->dev, res->imc, res->channel, idx, i, rirlv); | |
754 | res->rank_address = rank_addr - SKX_RIR_OFFSET(rirlv); | |
755 | chan_rank = SKX_RIR_CHAN_RANK(rirlv); | |
756 | res->channel_rank = chan_rank; | |
757 | res->dimm = chan_rank / 4; | |
758 | res->rank = chan_rank % 4; | |
759 | ||
760 | edac_dbg(2, "%llx: dimm=%d rank=%d chan_rank=%d rank_addr=%llx\n", | |
761 | res->addr, res->dimm, res->rank, | |
762 | res->channel_rank, res->rank_address); | |
763 | return true; | |
764 | } | |
765 | ||
766 | static u8 skx_close_row[] = { | |
767 | 15, 16, 17, 18, 20, 21, 22, 28, 10, 11, 12, 13, 29, 30, 31, 32, 33 | |
768 | }; | |
769 | static u8 skx_close_column[] = { | |
770 | 3, 4, 5, 14, 19, 23, 24, 25, 26, 27 | |
771 | }; | |
772 | static u8 skx_open_row[] = { | |
773 | 14, 15, 16, 20, 28, 21, 22, 23, 24, 25, 26, 27, 29, 30, 31, 32, 33 | |
774 | }; | |
775 | static u8 skx_open_column[] = { | |
776 | 3, 4, 5, 6, 7, 8, 9, 10, 11, 12 | |
777 | }; | |
778 | static u8 skx_open_fine_column[] = { | |
779 | 3, 4, 5, 7, 8, 9, 10, 11, 12, 13 | |
780 | }; | |
781 | ||
782 | static int skx_bits(u64 addr, int nbits, u8 *bits) | |
783 | { | |
784 | int i, res = 0; | |
785 | ||
786 | for (i = 0; i < nbits; i++) | |
787 | res |= ((addr >> bits[i]) & 1) << i; | |
788 | return res; | |
789 | } | |
790 | ||
791 | static int skx_bank_bits(u64 addr, int b0, int b1, int do_xor, int x0, int x1) | |
792 | { | |
793 | int ret = GET_BITFIELD(addr, b0, b0) | (GET_BITFIELD(addr, b1, b1) << 1); | |
794 | ||
795 | if (do_xor) | |
796 | ret ^= GET_BITFIELD(addr, x0, x0) | (GET_BITFIELD(addr, x1, x1) << 1); | |
797 | ||
798 | return ret; | |
799 | } | |
800 | ||
801 | static bool skx_mad_decode(struct decoded_addr *r) | |
802 | { | |
803 | struct skx_dimm *dimm = &r->dev->imc[r->imc].chan[r->channel].dimms[r->dimm]; | |
804 | int bg0 = dimm->fine_grain_bank ? 6 : 13; | |
805 | ||
806 | if (dimm->close_pg) { | |
807 | r->row = skx_bits(r->rank_address, dimm->rowbits, skx_close_row); | |
808 | r->column = skx_bits(r->rank_address, dimm->colbits, skx_close_column); | |
809 | r->column |= 0x400; /* C10 is autoprecharge, always set */ | |
810 | r->bank_address = skx_bank_bits(r->rank_address, 8, 9, dimm->bank_xor_enable, 22, 28); | |
811 | r->bank_group = skx_bank_bits(r->rank_address, 6, 7, dimm->bank_xor_enable, 20, 21); | |
812 | } else { | |
813 | r->row = skx_bits(r->rank_address, dimm->rowbits, skx_open_row); | |
814 | if (dimm->fine_grain_bank) | |
815 | r->column = skx_bits(r->rank_address, dimm->colbits, skx_open_fine_column); | |
816 | else | |
817 | r->column = skx_bits(r->rank_address, dimm->colbits, skx_open_column); | |
818 | r->bank_address = skx_bank_bits(r->rank_address, 18, 19, dimm->bank_xor_enable, 22, 23); | |
819 | r->bank_group = skx_bank_bits(r->rank_address, bg0, 17, dimm->bank_xor_enable, 20, 21); | |
820 | } | |
821 | r->row &= (1u << dimm->rowbits) - 1; | |
822 | ||
823 | edac_dbg(2, "%llx: row=%x col=%x bank_addr=%d bank_group=%d\n", | |
824 | r->addr, r->row, r->column, r->bank_address, | |
825 | r->bank_group); | |
826 | return true; | |
827 | } | |
828 | ||
829 | static bool skx_decode(struct decoded_addr *res) | |
830 | { | |
831 | ||
832 | return skx_sad_decode(res) && skx_tad_decode(res) && | |
833 | skx_rir_decode(res) && skx_mad_decode(res); | |
834 | } | |
835 | ||
836 | #ifdef CONFIG_EDAC_DEBUG | |
837 | /* | |
838 | * Debug feature. Make /sys/kernel/debug/skx_edac_test/addr. | |
839 | * Write an address to this file to exercise the address decode | |
840 | * logic in this driver. | |
841 | */ | |
842 | static struct dentry *skx_test; | |
843 | static u64 skx_fake_addr; | |
844 | ||
845 | static int debugfs_u64_set(void *data, u64 val) | |
846 | { | |
847 | struct decoded_addr res; | |
848 | ||
849 | res.addr = val; | |
850 | skx_decode(&res); | |
851 | ||
852 | return 0; | |
853 | } | |
854 | ||
855 | DEFINE_SIMPLE_ATTRIBUTE(fops_u64_wo, NULL, debugfs_u64_set, "%llu\n"); | |
856 | ||
857 | static struct dentry *mydebugfs_create(const char *name, umode_t mode, | |
858 | struct dentry *parent, u64 *value) | |
859 | { | |
860 | return debugfs_create_file(name, mode, parent, value, &fops_u64_wo); | |
861 | } | |
862 | ||
863 | static void setup_skx_debug(void) | |
864 | { | |
865 | skx_test = debugfs_create_dir("skx_edac_test", NULL); | |
866 | mydebugfs_create("addr", S_IWUSR, skx_test, &skx_fake_addr); | |
867 | } | |
868 | ||
869 | static void teardown_skx_debug(void) | |
870 | { | |
871 | debugfs_remove_recursive(skx_test); | |
872 | } | |
873 | #else | |
874 | static void setup_skx_debug(void) | |
875 | { | |
876 | } | |
877 | ||
878 | static void teardown_skx_debug(void) | |
879 | { | |
880 | } | |
881 | #endif /*CONFIG_EDAC_DEBUG*/ | |
882 | ||
883 | static void skx_mce_output_error(struct mem_ctl_info *mci, | |
884 | const struct mce *m, | |
885 | struct decoded_addr *res) | |
886 | { | |
887 | enum hw_event_mc_err_type tp_event; | |
888 | char *type, *optype, msg[256]; | |
889 | bool ripv = GET_BITFIELD(m->mcgstatus, 0, 0); | |
890 | bool overflow = GET_BITFIELD(m->status, 62, 62); | |
891 | bool uncorrected_error = GET_BITFIELD(m->status, 61, 61); | |
892 | bool recoverable; | |
893 | u32 core_err_cnt = GET_BITFIELD(m->status, 38, 52); | |
894 | u32 mscod = GET_BITFIELD(m->status, 16, 31); | |
895 | u32 errcode = GET_BITFIELD(m->status, 0, 15); | |
896 | u32 optypenum = GET_BITFIELD(m->status, 4, 6); | |
897 | ||
898 | recoverable = GET_BITFIELD(m->status, 56, 56); | |
899 | ||
900 | if (uncorrected_error) { | |
901 | if (ripv) { | |
902 | type = "FATAL"; | |
903 | tp_event = HW_EVENT_ERR_FATAL; | |
904 | } else { | |
905 | type = "NON_FATAL"; | |
906 | tp_event = HW_EVENT_ERR_UNCORRECTED; | |
907 | } | |
908 | } else { | |
909 | type = "CORRECTED"; | |
910 | tp_event = HW_EVENT_ERR_CORRECTED; | |
911 | } | |
912 | ||
913 | /* | |
914 | * According with Table 15-9 of the Intel Architecture spec vol 3A, | |
915 | * memory errors should fit in this mask: | |
916 | * 000f 0000 1mmm cccc (binary) | |
917 | * where: | |
918 | * f = Correction Report Filtering Bit. If 1, subsequent errors | |
919 | * won't be shown | |
920 | * mmm = error type | |
921 | * cccc = channel | |
922 | * If the mask doesn't match, report an error to the parsing logic | |
923 | */ | |
924 | if (!((errcode & 0xef80) == 0x80)) { | |
925 | optype = "Can't parse: it is not a mem"; | |
926 | } else { | |
927 | switch (optypenum) { | |
928 | case 0: | |
929 | optype = "generic undef request error"; | |
930 | break; | |
931 | case 1: | |
932 | optype = "memory read error"; | |
933 | break; | |
934 | case 2: | |
935 | optype = "memory write error"; | |
936 | break; | |
937 | case 3: | |
938 | optype = "addr/cmd error"; | |
939 | break; | |
940 | case 4: | |
941 | optype = "memory scrubbing error"; | |
942 | break; | |
943 | default: | |
944 | optype = "reserved"; | |
945 | break; | |
946 | } | |
947 | } | |
948 | ||
949 | snprintf(msg, sizeof(msg), | |
950 | "%s%s err_code:%04x:%04x socket:%d imc:%d rank:%d bg:%d ba:%d row:%x col:%x", | |
951 | overflow ? " OVERFLOW" : "", | |
952 | (uncorrected_error && recoverable) ? " recoverable" : "", | |
953 | mscod, errcode, | |
954 | res->socket, res->imc, res->rank, | |
955 | res->bank_group, res->bank_address, res->row, res->column); | |
956 | ||
957 | edac_dbg(0, "%s\n", msg); | |
958 | ||
959 | /* Call the helper to output message */ | |
960 | edac_mc_handle_error(tp_event, mci, core_err_cnt, | |
961 | m->addr >> PAGE_SHIFT, m->addr & ~PAGE_MASK, 0, | |
962 | res->channel, res->dimm, -1, | |
963 | optype, msg); | |
964 | } | |
965 | ||
966 | static int skx_mce_check_error(struct notifier_block *nb, unsigned long val, | |
967 | void *data) | |
968 | { | |
969 | struct mce *mce = (struct mce *)data; | |
970 | struct decoded_addr res; | |
971 | struct mem_ctl_info *mci; | |
972 | char *type; | |
973 | ||
bffc7dec | 974 | if (edac_get_report_status() == EDAC_REPORTING_DISABLED) |
4ec656bd TL |
975 | return NOTIFY_DONE; |
976 | ||
977 | /* ignore unless this is memory related with an address */ | |
978 | if ((mce->status & 0xefff) >> 7 != 1 || !(mce->status & MCI_STATUS_ADDRV)) | |
979 | return NOTIFY_DONE; | |
980 | ||
981 | res.addr = mce->addr; | |
982 | if (!skx_decode(&res)) | |
983 | return NOTIFY_DONE; | |
984 | mci = res.dev->imc[res.imc].mci; | |
985 | ||
986 | if (mce->mcgstatus & MCG_STATUS_MCIP) | |
987 | type = "Exception"; | |
988 | else | |
989 | type = "Event"; | |
990 | ||
991 | skx_mc_printk(mci, KERN_DEBUG, "HANDLING MCE MEMORY ERROR\n"); | |
992 | ||
993 | skx_mc_printk(mci, KERN_DEBUG, "CPU %d: Machine Check %s: %Lx " | |
994 | "Bank %d: %016Lx\n", mce->extcpu, type, | |
995 | mce->mcgstatus, mce->bank, mce->status); | |
996 | skx_mc_printk(mci, KERN_DEBUG, "TSC %llx ", mce->tsc); | |
997 | skx_mc_printk(mci, KERN_DEBUG, "ADDR %llx ", mce->addr); | |
998 | skx_mc_printk(mci, KERN_DEBUG, "MISC %llx ", mce->misc); | |
999 | ||
1000 | skx_mc_printk(mci, KERN_DEBUG, "PROCESSOR %u:%x TIME %llu SOCKET " | |
1001 | "%u APIC %x\n", mce->cpuvendor, mce->cpuid, | |
1002 | mce->time, mce->socketid, mce->apicid); | |
1003 | ||
1004 | skx_mce_output_error(mci, mce, &res); | |
1005 | ||
1006 | return NOTIFY_DONE; | |
1007 | } | |
1008 | ||
1009 | static struct notifier_block skx_mce_dec = { | |
9026cc82 BP |
1010 | .notifier_call = skx_mce_check_error, |
1011 | .priority = MCE_PRIO_EDAC, | |
4ec656bd TL |
1012 | }; |
1013 | ||
1014 | static void skx_remove(void) | |
1015 | { | |
1016 | int i, j; | |
1017 | struct skx_dev *d, *tmp; | |
1018 | ||
1019 | edac_dbg(0, "\n"); | |
1020 | ||
1021 | list_for_each_entry_safe(d, tmp, &skx_edac_list, list) { | |
1022 | list_del(&d->list); | |
1023 | for (i = 0; i < NUM_IMC; i++) { | |
1024 | skx_unregister_mci(&d->imc[i]); | |
1025 | for (j = 0; j < NUM_CHANNELS; j++) | |
1026 | pci_dev_put(d->imc[i].chan[j].cdev); | |
1027 | } | |
1028 | pci_dev_put(d->util_all); | |
1029 | pci_dev_put(d->sad_all); | |
1030 | ||
1031 | kfree(d); | |
1032 | } | |
1033 | } | |
1034 | ||
1035 | /* | |
1036 | * skx_init: | |
1037 | * make sure we are running on the correct cpu model | |
1038 | * search for all the devices we need | |
1039 | * check which DIMMs are present. | |
1040 | */ | |
240ea921 | 1041 | static int __init skx_init(void) |
4ec656bd TL |
1042 | { |
1043 | const struct x86_cpu_id *id; | |
1044 | const struct munit *m; | |
1045 | int rc = 0, i; | |
1046 | u8 mc = 0, src_id, node_id; | |
1047 | struct skx_dev *d; | |
1048 | ||
1049 | edac_dbg(2, "\n"); | |
1050 | ||
1051 | id = x86_match_cpu(skx_cpuids); | |
1052 | if (!id) | |
1053 | return -ENODEV; | |
1054 | ||
1055 | rc = skx_get_hi_lo(); | |
1056 | if (rc) | |
1057 | return rc; | |
1058 | ||
1059 | rc = get_all_bus_mappings(); | |
1060 | if (rc < 0) | |
1061 | goto fail; | |
1062 | if (rc == 0) { | |
1063 | edac_dbg(2, "No memory controllers found\n"); | |
1064 | return -ENODEV; | |
1065 | } | |
1066 | ||
1067 | for (m = skx_all_munits; m->did; m++) { | |
1068 | rc = get_all_munits(m); | |
1069 | if (rc < 0) | |
1070 | goto fail; | |
1071 | if (rc != m->per_socket * skx_num_sockets) { | |
1072 | edac_dbg(2, "Expected %d, got %d of %x\n", | |
1073 | m->per_socket * skx_num_sockets, rc, m->did); | |
1074 | rc = -ENODEV; | |
1075 | goto fail; | |
1076 | } | |
1077 | } | |
1078 | ||
1079 | list_for_each_entry(d, &skx_edac_list, list) { | |
1080 | src_id = get_src_id(d); | |
1081 | node_id = skx_get_node_id(d); | |
1082 | edac_dbg(2, "src_id=%d node_id=%d\n", src_id, node_id); | |
1083 | for (i = 0; i < NUM_IMC; i++) { | |
1084 | d->imc[i].mc = mc++; | |
1085 | d->imc[i].lmc = i; | |
1086 | d->imc[i].src_id = src_id; | |
1087 | d->imc[i].node_id = node_id; | |
1088 | rc = skx_register_mci(&d->imc[i]); | |
1089 | if (rc < 0) | |
1090 | goto fail; | |
1091 | } | |
1092 | } | |
1093 | ||
1094 | /* Ensure that the OPSTATE is set correctly for POLL or NMI */ | |
1095 | opstate_init(); | |
1096 | ||
1097 | setup_skx_debug(); | |
1098 | ||
1099 | mce_register_decode_chain(&skx_mce_dec); | |
1100 | ||
1101 | return 0; | |
1102 | fail: | |
1103 | skx_remove(); | |
1104 | return rc; | |
1105 | } | |
1106 | ||
1107 | static void __exit skx_exit(void) | |
1108 | { | |
1109 | edac_dbg(2, "\n"); | |
1110 | mce_unregister_decode_chain(&skx_mce_dec); | |
1111 | skx_remove(); | |
1112 | teardown_skx_debug(); | |
1113 | } | |
1114 | ||
1115 | module_init(skx_init); | |
1116 | module_exit(skx_exit); | |
1117 | ||
1118 | module_param(edac_op_state, int, 0444); | |
1119 | MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI"); | |
1120 | ||
1121 | MODULE_LICENSE("GPL v2"); | |
1122 | MODULE_AUTHOR("Tony Luck"); | |
1123 | MODULE_DESCRIPTION("MC Driver for Intel Skylake server processors"); |