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ae9b56e3 PCK |
1 | /* |
2 | * Synopsys DDR ECC Driver | |
3 | * This driver is based on ppc4xx_edac.c drivers | |
4 | * | |
5 | * Copyright (C) 2012 - 2014 Xilinx, Inc. | |
6 | * | |
7 | * This program is free software: you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation, either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * This file is subject to the terms and conditions of the GNU General Public | |
18 | * License. See the file "COPYING" in the main directory of this archive | |
19 | * for more details | |
20 | */ | |
21 | ||
22 | #include <linux/edac.h> | |
23 | #include <linux/module.h> | |
24 | #include <linux/platform_device.h> | |
3d02a897 MN |
25 | #include <linux/of.h> |
26 | #include <linux/of_device.h> | |
ae9b56e3 | 27 | |
78d88e8a | 28 | #include "edac_module.h" |
ae9b56e3 PCK |
29 | |
30 | /* Number of cs_rows needed per memory controller */ | |
1b51adc6 | 31 | #define SYNPS_EDAC_NR_CSROWS 1 |
ae9b56e3 PCK |
32 | |
33 | /* Number of channels per memory controller */ | |
1b51adc6 | 34 | #define SYNPS_EDAC_NR_CHANS 1 |
ae9b56e3 PCK |
35 | |
36 | /* Granularity of reported error in bytes */ | |
1b51adc6 | 37 | #define SYNPS_EDAC_ERR_GRAIN 1 |
ae9b56e3 | 38 | |
1b51adc6 | 39 | #define SYNPS_EDAC_MSG_SIZE 256 |
ae9b56e3 | 40 | |
1b51adc6 MN |
41 | #define SYNPS_EDAC_MOD_STRING "synps_edac" |
42 | #define SYNPS_EDAC_MOD_VER "1" | |
ae9b56e3 PCK |
43 | |
44 | /* Synopsys DDR memory controller registers that are relevant to ECC */ | |
1b51adc6 MN |
45 | #define CTRL_OFST 0x0 |
46 | #define T_ZQ_OFST 0xA4 | |
ae9b56e3 PCK |
47 | |
48 | /* ECC control register */ | |
1b51adc6 | 49 | #define ECC_CTRL_OFST 0xC4 |
ae9b56e3 | 50 | /* ECC log register */ |
1b51adc6 | 51 | #define CE_LOG_OFST 0xC8 |
ae9b56e3 | 52 | /* ECC address register */ |
1b51adc6 | 53 | #define CE_ADDR_OFST 0xCC |
ae9b56e3 | 54 | /* ECC data[31:0] register */ |
1b51adc6 | 55 | #define CE_DATA_31_0_OFST 0xD0 |
ae9b56e3 PCK |
56 | |
57 | /* Uncorrectable error info registers */ | |
1b51adc6 MN |
58 | #define UE_LOG_OFST 0xDC |
59 | #define UE_ADDR_OFST 0xE0 | |
60 | #define UE_DATA_31_0_OFST 0xE4 | |
ae9b56e3 | 61 | |
1b51adc6 MN |
62 | #define STAT_OFST 0xF0 |
63 | #define SCRUB_OFST 0xF4 | |
ae9b56e3 PCK |
64 | |
65 | /* Control register bit field definitions */ | |
1b51adc6 MN |
66 | #define CTRL_BW_MASK 0xC |
67 | #define CTRL_BW_SHIFT 2 | |
ae9b56e3 | 68 | |
1b51adc6 MN |
69 | #define DDRCTL_WDTH_16 1 |
70 | #define DDRCTL_WDTH_32 0 | |
ae9b56e3 PCK |
71 | |
72 | /* ZQ register bit field definitions */ | |
1b51adc6 | 73 | #define T_ZQ_DDRMODE_MASK 0x2 |
ae9b56e3 PCK |
74 | |
75 | /* ECC control register bit field definitions */ | |
1b51adc6 MN |
76 | #define ECC_CTRL_CLR_CE_ERR 0x2 |
77 | #define ECC_CTRL_CLR_UE_ERR 0x1 | |
ae9b56e3 PCK |
78 | |
79 | /* ECC correctable/uncorrectable error log register definitions */ | |
1b51adc6 MN |
80 | #define LOG_VALID 0x1 |
81 | #define CE_LOG_BITPOS_MASK 0xFE | |
82 | #define CE_LOG_BITPOS_SHIFT 1 | |
ae9b56e3 PCK |
83 | |
84 | /* ECC correctable/uncorrectable error address register definitions */ | |
1b51adc6 MN |
85 | #define ADDR_COL_MASK 0xFFF |
86 | #define ADDR_ROW_MASK 0xFFFF000 | |
87 | #define ADDR_ROW_SHIFT 12 | |
88 | #define ADDR_BANK_MASK 0x70000000 | |
89 | #define ADDR_BANK_SHIFT 28 | |
ae9b56e3 PCK |
90 | |
91 | /* ECC statistic register definitions */ | |
1b51adc6 MN |
92 | #define STAT_UECNT_MASK 0xFF |
93 | #define STAT_CECNT_MASK 0xFF00 | |
94 | #define STAT_CECNT_SHIFT 8 | |
ae9b56e3 PCK |
95 | |
96 | /* ECC scrub register definitions */ | |
1b51adc6 MN |
97 | #define SCRUB_MODE_MASK 0x7 |
98 | #define SCRUB_MODE_SECDED 0x4 | |
ae9b56e3 PCK |
99 | |
100 | /** | |
225af74d MN |
101 | * struct ecc_error_info - ECC error log information. |
102 | * @row: Row number. | |
103 | * @col: Column number. | |
104 | * @bank: Bank number. | |
105 | * @bitpos: Bit position. | |
106 | * @data: Data causing the error. | |
ae9b56e3 PCK |
107 | */ |
108 | struct ecc_error_info { | |
109 | u32 row; | |
110 | u32 col; | |
111 | u32 bank; | |
112 | u32 bitpos; | |
113 | u32 data; | |
114 | }; | |
115 | ||
116 | /** | |
225af74d MN |
117 | * struct synps_ecc_status - ECC status information to report. |
118 | * @ce_cnt: Correctable error count. | |
119 | * @ue_cnt: Uncorrectable error count. | |
120 | * @ceinfo: Correctable error log information. | |
121 | * @ueinfo: Uncorrectable error log information. | |
ae9b56e3 PCK |
122 | */ |
123 | struct synps_ecc_status { | |
124 | u32 ce_cnt; | |
125 | u32 ue_cnt; | |
126 | struct ecc_error_info ceinfo; | |
127 | struct ecc_error_info ueinfo; | |
128 | }; | |
129 | ||
130 | /** | |
225af74d MN |
131 | * struct synps_edac_priv - DDR memory controller private instance data. |
132 | * @baseaddr: Base address of the DDR controller. | |
133 | * @message: Buffer for framing the event specific info. | |
134 | * @stat: ECC status information. | |
3d02a897 | 135 | * @p_data: Platform data. |
225af74d MN |
136 | * @ce_cnt: Correctable Error count. |
137 | * @ue_cnt: Uncorrectable Error count. | |
ae9b56e3 PCK |
138 | */ |
139 | struct synps_edac_priv { | |
140 | void __iomem *baseaddr; | |
141 | char message[SYNPS_EDAC_MSG_SIZE]; | |
142 | struct synps_ecc_status stat; | |
3d02a897 | 143 | const struct synps_platform_data *p_data; |
ae9b56e3 PCK |
144 | u32 ce_cnt; |
145 | u32 ue_cnt; | |
146 | }; | |
147 | ||
148 | /** | |
3d02a897 MN |
149 | * struct synps_platform_data - synps platform data structure. |
150 | * @get_error_info: Get EDAC error info. | |
151 | * @get_mtype: Get mtype. | |
152 | * @get_dtype: Get dtype. | |
153 | * @get_ecc_state: Get ECC state. | |
154 | * @quirks: To differentiate IPs. | |
155 | */ | |
156 | struct synps_platform_data { | |
157 | int (*get_error_info)(struct synps_edac_priv *priv); | |
158 | enum mem_type (*get_mtype)(const void __iomem *base); | |
159 | enum dev_type (*get_dtype)(const void __iomem *base); | |
160 | bool (*get_ecc_state)(void __iomem *base); | |
161 | int quirks; | |
162 | }; | |
163 | ||
164 | /** | |
165 | * zynq_get_error_info - Get the current ECC error info. | |
166 | * @priv: DDR memory controller private instance data. | |
ae9b56e3 | 167 | * |
3d02a897 | 168 | * Return: one if there is no error, otherwise zero. |
ae9b56e3 | 169 | */ |
3d02a897 | 170 | static int zynq_get_error_info(struct synps_edac_priv *priv) |
ae9b56e3 | 171 | { |
3d02a897 | 172 | struct synps_ecc_status *p; |
ae9b56e3 | 173 | u32 regval, clearval = 0; |
3d02a897 MN |
174 | void __iomem *base; |
175 | ||
176 | base = priv->baseaddr; | |
177 | p = &priv->stat; | |
ae9b56e3 PCK |
178 | |
179 | regval = readl(base + STAT_OFST); | |
180 | if (!regval) | |
181 | return 1; | |
182 | ||
183 | p->ce_cnt = (regval & STAT_CECNT_MASK) >> STAT_CECNT_SHIFT; | |
184 | p->ue_cnt = regval & STAT_UECNT_MASK; | |
185 | ||
186 | regval = readl(base + CE_LOG_OFST); | |
187 | if (!(p->ce_cnt && (regval & LOG_VALID))) | |
188 | goto ue_err; | |
189 | ||
190 | p->ceinfo.bitpos = (regval & CE_LOG_BITPOS_MASK) >> CE_LOG_BITPOS_SHIFT; | |
191 | regval = readl(base + CE_ADDR_OFST); | |
192 | p->ceinfo.row = (regval & ADDR_ROW_MASK) >> ADDR_ROW_SHIFT; | |
193 | p->ceinfo.col = regval & ADDR_COL_MASK; | |
194 | p->ceinfo.bank = (regval & ADDR_BANK_MASK) >> ADDR_BANK_SHIFT; | |
195 | p->ceinfo.data = readl(base + CE_DATA_31_0_OFST); | |
1b51adc6 | 196 | edac_dbg(3, "CE bit position: %d data: %d\n", p->ceinfo.bitpos, |
ae9b56e3 PCK |
197 | p->ceinfo.data); |
198 | clearval = ECC_CTRL_CLR_CE_ERR; | |
199 | ||
200 | ue_err: | |
201 | regval = readl(base + UE_LOG_OFST); | |
202 | if (!(p->ue_cnt && (regval & LOG_VALID))) | |
203 | goto out; | |
204 | ||
205 | regval = readl(base + UE_ADDR_OFST); | |
206 | p->ueinfo.row = (regval & ADDR_ROW_MASK) >> ADDR_ROW_SHIFT; | |
207 | p->ueinfo.col = regval & ADDR_COL_MASK; | |
208 | p->ueinfo.bank = (regval & ADDR_BANK_MASK) >> ADDR_BANK_SHIFT; | |
209 | p->ueinfo.data = readl(base + UE_DATA_31_0_OFST); | |
210 | clearval |= ECC_CTRL_CLR_UE_ERR; | |
211 | ||
212 | out: | |
213 | writel(clearval, base + ECC_CTRL_OFST); | |
214 | writel(0x0, base + ECC_CTRL_OFST); | |
215 | ||
216 | return 0; | |
217 | } | |
218 | ||
219 | /** | |
225af74d MN |
220 | * handle_error - Handle Correctable and Uncorrectable errors. |
221 | * @mci: EDAC memory controller instance. | |
222 | * @p: Synopsys ECC status structure. | |
ae9b56e3 | 223 | * |
225af74d | 224 | * Handles ECC correctable and uncorrectable errors. |
ae9b56e3 | 225 | */ |
bb894bc4 | 226 | static void handle_error(struct mem_ctl_info *mci, struct synps_ecc_status *p) |
ae9b56e3 PCK |
227 | { |
228 | struct synps_edac_priv *priv = mci->pvt_info; | |
229 | struct ecc_error_info *pinf; | |
230 | ||
231 | if (p->ce_cnt) { | |
232 | pinf = &p->ceinfo; | |
233 | snprintf(priv->message, SYNPS_EDAC_MSG_SIZE, | |
234 | "DDR ECC error type :%s Row %d Bank %d Col %d ", | |
235 | "CE", pinf->row, pinf->bank, pinf->col); | |
236 | edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, | |
237 | p->ce_cnt, 0, 0, 0, 0, 0, -1, | |
238 | priv->message, ""); | |
239 | } | |
240 | ||
241 | if (p->ue_cnt) { | |
242 | pinf = &p->ueinfo; | |
243 | snprintf(priv->message, SYNPS_EDAC_MSG_SIZE, | |
244 | "DDR ECC error type :%s Row %d Bank %d Col %d ", | |
245 | "UE", pinf->row, pinf->bank, pinf->col); | |
246 | edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, | |
247 | p->ue_cnt, 0, 0, 0, 0, 0, -1, | |
248 | priv->message, ""); | |
249 | } | |
250 | ||
251 | memset(p, 0, sizeof(*p)); | |
252 | } | |
253 | ||
254 | /** | |
225af74d MN |
255 | * check_errors - Check controller for ECC errors. |
256 | * @mci: EDAC memory controller instance. | |
ae9b56e3 | 257 | * |
225af74d | 258 | * Check and post ECC errors. Called by the polling thread. |
ae9b56e3 | 259 | */ |
bb894bc4 | 260 | static void check_errors(struct mem_ctl_info *mci) |
ae9b56e3 PCK |
261 | { |
262 | struct synps_edac_priv *priv = mci->pvt_info; | |
3d02a897 | 263 | const struct synps_platform_data *p_data = priv->p_data; |
ae9b56e3 PCK |
264 | int status; |
265 | ||
3d02a897 | 266 | status = p_data->get_error_info(priv); |
ae9b56e3 PCK |
267 | if (status) |
268 | return; | |
269 | ||
270 | priv->ce_cnt += priv->stat.ce_cnt; | |
271 | priv->ue_cnt += priv->stat.ue_cnt; | |
bb894bc4 | 272 | handle_error(mci, &priv->stat); |
ae9b56e3 | 273 | |
1b51adc6 | 274 | edac_dbg(3, "Total error count CE %d UE %d\n", |
ae9b56e3 PCK |
275 | priv->ce_cnt, priv->ue_cnt); |
276 | } | |
277 | ||
278 | /** | |
3d02a897 | 279 | * zynq_get_dtype - Return the controller memory width. |
225af74d | 280 | * @base: DDR memory controller base address. |
ae9b56e3 PCK |
281 | * |
282 | * Get the EDAC device type width appropriate for the current controller | |
283 | * configuration. | |
284 | * | |
285 | * Return: a device type width enumeration. | |
286 | */ | |
3d02a897 | 287 | static enum dev_type zynq_get_dtype(const void __iomem *base) |
ae9b56e3 PCK |
288 | { |
289 | enum dev_type dt; | |
290 | u32 width; | |
291 | ||
292 | width = readl(base + CTRL_OFST); | |
293 | width = (width & CTRL_BW_MASK) >> CTRL_BW_SHIFT; | |
294 | ||
295 | switch (width) { | |
296 | case DDRCTL_WDTH_16: | |
297 | dt = DEV_X2; | |
298 | break; | |
299 | case DDRCTL_WDTH_32: | |
300 | dt = DEV_X4; | |
301 | break; | |
302 | default: | |
303 | dt = DEV_UNKNOWN; | |
304 | } | |
305 | ||
306 | return dt; | |
307 | } | |
308 | ||
309 | /** | |
3d02a897 | 310 | * zynq_get_ecc_state - Return the controller ECC enable/disable status. |
225af74d | 311 | * @base: DDR memory controller base address. |
ae9b56e3 | 312 | * |
225af74d | 313 | * Get the ECC enable/disable status of the controller. |
ae9b56e3 | 314 | * |
225af74d | 315 | * Return: true if enabled, otherwise false. |
ae9b56e3 | 316 | */ |
3d02a897 | 317 | static bool zynq_get_ecc_state(void __iomem *base) |
ae9b56e3 | 318 | { |
1b51adc6 | 319 | bool state = false; |
ae9b56e3 PCK |
320 | enum dev_type dt; |
321 | u32 ecctype; | |
ae9b56e3 | 322 | |
3d02a897 | 323 | dt = zynq_get_dtype(base); |
ae9b56e3 PCK |
324 | if (dt == DEV_UNKNOWN) |
325 | return state; | |
326 | ||
327 | ecctype = readl(base + SCRUB_OFST) & SCRUB_MODE_MASK; | |
328 | if ((ecctype == SCRUB_MODE_SECDED) && (dt == DEV_X2)) | |
329 | state = true; | |
330 | ||
331 | return state; | |
332 | } | |
333 | ||
334 | /** | |
225af74d | 335 | * get_memsize - Read the size of the attached memory device. |
ae9b56e3 | 336 | * |
225af74d | 337 | * Return: the memory size in bytes. |
ae9b56e3 | 338 | */ |
bb894bc4 | 339 | static u32 get_memsize(void) |
ae9b56e3 PCK |
340 | { |
341 | struct sysinfo inf; | |
342 | ||
343 | si_meminfo(&inf); | |
344 | ||
345 | return inf.totalram * inf.mem_unit; | |
346 | } | |
347 | ||
348 | /** | |
3d02a897 | 349 | * zynq_get_mtype - Return the controller memory type. |
225af74d | 350 | * @base: Synopsys ECC status structure. |
ae9b56e3 PCK |
351 | * |
352 | * Get the EDAC memory type appropriate for the current controller | |
353 | * configuration. | |
354 | * | |
355 | * Return: a memory type enumeration. | |
356 | */ | |
3d02a897 | 357 | static enum mem_type zynq_get_mtype(const void __iomem *base) |
ae9b56e3 PCK |
358 | { |
359 | enum mem_type mt; | |
360 | u32 memtype; | |
361 | ||
362 | memtype = readl(base + T_ZQ_OFST); | |
363 | ||
364 | if (memtype & T_ZQ_DDRMODE_MASK) | |
365 | mt = MEM_DDR3; | |
366 | else | |
367 | mt = MEM_DDR2; | |
368 | ||
369 | return mt; | |
370 | } | |
371 | ||
372 | /** | |
225af74d MN |
373 | * init_csrows - Initialize the csrow data. |
374 | * @mci: EDAC memory controller instance. | |
ae9b56e3 | 375 | * |
225af74d MN |
376 | * Initialize the chip select rows associated with the EDAC memory |
377 | * controller instance. | |
ae9b56e3 | 378 | */ |
fa9f6b9e | 379 | static void init_csrows(struct mem_ctl_info *mci) |
ae9b56e3 | 380 | { |
1b51adc6 | 381 | struct synps_edac_priv *priv = mci->pvt_info; |
3d02a897 | 382 | const struct synps_platform_data *p_data; |
ae9b56e3 PCK |
383 | struct csrow_info *csi; |
384 | struct dimm_info *dimm; | |
1b51adc6 MN |
385 | u32 size, row; |
386 | int j; | |
ae9b56e3 | 387 | |
3d02a897 MN |
388 | p_data = priv->p_data; |
389 | ||
ae9b56e3 PCK |
390 | for (row = 0; row < mci->nr_csrows; row++) { |
391 | csi = mci->csrows[row]; | |
bb894bc4 | 392 | size = get_memsize(); |
ae9b56e3 PCK |
393 | |
394 | for (j = 0; j < csi->nr_channels; j++) { | |
1b51adc6 MN |
395 | dimm = csi->channels[j]->dimm; |
396 | dimm->edac_mode = EDAC_FLAG_SECDED; | |
3d02a897 | 397 | dimm->mtype = p_data->get_mtype(priv->baseaddr); |
1b51adc6 MN |
398 | dimm->nr_pages = (size >> PAGE_SHIFT) / csi->nr_channels; |
399 | dimm->grain = SYNPS_EDAC_ERR_GRAIN; | |
3d02a897 | 400 | dimm->dtype = p_data->get_dtype(priv->baseaddr); |
ae9b56e3 PCK |
401 | } |
402 | } | |
ae9b56e3 PCK |
403 | } |
404 | ||
405 | /** | |
225af74d MN |
406 | * mc_init - Initialize one driver instance. |
407 | * @mci: EDAC memory controller instance. | |
408 | * @pdev: platform device. | |
ae9b56e3 | 409 | * |
225af74d | 410 | * Perform initialization of the EDAC memory controller instance and |
ae9b56e3 PCK |
411 | * related driver-private data associated with the memory controller the |
412 | * instance is bound to. | |
ae9b56e3 | 413 | */ |
fa9f6b9e | 414 | static void mc_init(struct mem_ctl_info *mci, struct platform_device *pdev) |
ae9b56e3 | 415 | { |
ae9b56e3 PCK |
416 | struct synps_edac_priv *priv; |
417 | ||
418 | mci->pdev = &pdev->dev; | |
419 | priv = mci->pvt_info; | |
420 | platform_set_drvdata(pdev, mci); | |
421 | ||
422 | /* Initialize controller capabilities and configuration */ | |
423 | mci->mtype_cap = MEM_FLAG_DDR3 | MEM_FLAG_DDR2; | |
424 | mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED; | |
425 | mci->scrub_cap = SCRUB_HW_SRC; | |
426 | mci->scrub_mode = SCRUB_NONE; | |
427 | ||
428 | mci->edac_cap = EDAC_FLAG_SECDED; | |
429 | mci->ctl_name = "synps_ddr_controller"; | |
430 | mci->dev_name = SYNPS_EDAC_MOD_STRING; | |
431 | mci->mod_name = SYNPS_EDAC_MOD_VER; | |
ae9b56e3 PCK |
432 | |
433 | edac_op_state = EDAC_OPSTATE_POLL; | |
bb894bc4 | 434 | mci->edac_check = check_errors; |
ae9b56e3 PCK |
435 | mci->ctl_page_to_phys = NULL; |
436 | ||
fa9f6b9e | 437 | init_csrows(mci); |
ae9b56e3 PCK |
438 | } |
439 | ||
3d02a897 MN |
440 | static const struct synps_platform_data zynq_edac_def = { |
441 | .get_error_info = zynq_get_error_info, | |
442 | .get_mtype = zynq_get_mtype, | |
443 | .get_dtype = zynq_get_dtype, | |
444 | .get_ecc_state = zynq_get_ecc_state, | |
445 | .quirks = 0, | |
446 | }; | |
447 | ||
448 | static const struct of_device_id synps_edac_match[] = { | |
449 | { .compatible = "xlnx,zynq-ddrc-a05", .data = (void *)&zynq_edac_def }, | |
450 | { /* end of table */ } | |
451 | }; | |
452 | ||
453 | MODULE_DEVICE_TABLE(of, synps_edac_match); | |
454 | ||
ae9b56e3 | 455 | /** |
225af74d MN |
456 | * mc_probe - Check controller and bind driver. |
457 | * @pdev: platform device. | |
ae9b56e3 | 458 | * |
225af74d | 459 | * Probe a specific controller instance for binding with the driver. |
ae9b56e3 PCK |
460 | * |
461 | * Return: 0 if the controller instance was successfully bound to the | |
462 | * driver; otherwise, < 0 on error. | |
463 | */ | |
bb894bc4 | 464 | static int mc_probe(struct platform_device *pdev) |
ae9b56e3 | 465 | { |
3d02a897 | 466 | const struct synps_platform_data *p_data; |
ae9b56e3 PCK |
467 | struct edac_mc_layer layers[2]; |
468 | struct synps_edac_priv *priv; | |
1b51adc6 | 469 | struct mem_ctl_info *mci; |
ae9b56e3 | 470 | void __iomem *baseaddr; |
1b51adc6 MN |
471 | struct resource *res; |
472 | int rc; | |
ae9b56e3 PCK |
473 | |
474 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
475 | baseaddr = devm_ioremap_resource(&pdev->dev, res); | |
476 | if (IS_ERR(baseaddr)) | |
477 | return PTR_ERR(baseaddr); | |
478 | ||
3d02a897 MN |
479 | p_data = of_device_get_match_data(&pdev->dev); |
480 | if (!p_data->get_ecc_state(baseaddr)) { | |
ae9b56e3 PCK |
481 | edac_printk(KERN_INFO, EDAC_MC, "ECC not enabled\n"); |
482 | return -ENXIO; | |
483 | } | |
484 | ||
485 | layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; | |
486 | layers[0].size = SYNPS_EDAC_NR_CSROWS; | |
487 | layers[0].is_virt_csrow = true; | |
488 | layers[1].type = EDAC_MC_LAYER_CHANNEL; | |
489 | layers[1].size = SYNPS_EDAC_NR_CHANS; | |
490 | layers[1].is_virt_csrow = false; | |
491 | ||
492 | mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, | |
493 | sizeof(struct synps_edac_priv)); | |
494 | if (!mci) { | |
495 | edac_printk(KERN_ERR, EDAC_MC, | |
496 | "Failed memory allocation for mc instance\n"); | |
497 | return -ENOMEM; | |
498 | } | |
499 | ||
500 | priv = mci->pvt_info; | |
501 | priv->baseaddr = baseaddr; | |
3d02a897 MN |
502 | priv->p_data = p_data; |
503 | ||
fa9f6b9e | 504 | mc_init(mci, pdev); |
ae9b56e3 PCK |
505 | |
506 | rc = edac_mc_add_mc(mci); | |
507 | if (rc) { | |
508 | edac_printk(KERN_ERR, EDAC_MC, | |
509 | "Failed to register with EDAC core\n"); | |
510 | goto free_edac_mc; | |
511 | } | |
512 | ||
513 | /* | |
514 | * Start capturing the correctable and uncorrectable errors. A write of | |
515 | * 0 starts the counters. | |
516 | */ | |
517 | writel(0x0, baseaddr + ECC_CTRL_OFST); | |
518 | return rc; | |
519 | ||
520 | free_edac_mc: | |
521 | edac_mc_free(mci); | |
522 | ||
523 | return rc; | |
524 | } | |
525 | ||
526 | /** | |
225af74d MN |
527 | * mc_remove - Unbind driver from controller. |
528 | * @pdev: Platform device. | |
ae9b56e3 PCK |
529 | * |
530 | * Return: Unconditionally 0 | |
531 | */ | |
bb894bc4 | 532 | static int mc_remove(struct platform_device *pdev) |
ae9b56e3 PCK |
533 | { |
534 | struct mem_ctl_info *mci = platform_get_drvdata(pdev); | |
535 | ||
536 | edac_mc_del_mc(&pdev->dev); | |
537 | edac_mc_free(mci); | |
538 | ||
539 | return 0; | |
540 | } | |
541 | ||
ae9b56e3 PCK |
542 | static struct platform_driver synps_edac_mc_driver = { |
543 | .driver = { | |
544 | .name = "synopsys-edac", | |
545 | .of_match_table = synps_edac_match, | |
546 | }, | |
bb894bc4 MN |
547 | .probe = mc_probe, |
548 | .remove = mc_remove, | |
ae9b56e3 PCK |
549 | }; |
550 | ||
551 | module_platform_driver(synps_edac_mc_driver); | |
552 | ||
553 | MODULE_AUTHOR("Xilinx Inc"); | |
554 | MODULE_DESCRIPTION("Synopsys DDR ECC driver"); | |
555 | MODULE_LICENSE("GPL v2"); |