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ae9b56e3 PCK |
1 | /* |
2 | * Synopsys DDR ECC Driver | |
3 | * This driver is based on ppc4xx_edac.c drivers | |
4 | * | |
5 | * Copyright (C) 2012 - 2014 Xilinx, Inc. | |
6 | * | |
7 | * This program is free software: you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation, either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * This file is subject to the terms and conditions of the GNU General Public | |
18 | * License. See the file "COPYING" in the main directory of this archive | |
19 | * for more details | |
20 | */ | |
21 | ||
22 | #include <linux/edac.h> | |
23 | #include <linux/module.h> | |
24 | #include <linux/platform_device.h> | |
25 | ||
78d88e8a | 26 | #include "edac_module.h" |
ae9b56e3 PCK |
27 | |
28 | /* Number of cs_rows needed per memory controller */ | |
1b51adc6 | 29 | #define SYNPS_EDAC_NR_CSROWS 1 |
ae9b56e3 PCK |
30 | |
31 | /* Number of channels per memory controller */ | |
1b51adc6 | 32 | #define SYNPS_EDAC_NR_CHANS 1 |
ae9b56e3 PCK |
33 | |
34 | /* Granularity of reported error in bytes */ | |
1b51adc6 | 35 | #define SYNPS_EDAC_ERR_GRAIN 1 |
ae9b56e3 | 36 | |
1b51adc6 | 37 | #define SYNPS_EDAC_MSG_SIZE 256 |
ae9b56e3 | 38 | |
1b51adc6 MN |
39 | #define SYNPS_EDAC_MOD_STRING "synps_edac" |
40 | #define SYNPS_EDAC_MOD_VER "1" | |
ae9b56e3 PCK |
41 | |
42 | /* Synopsys DDR memory controller registers that are relevant to ECC */ | |
1b51adc6 MN |
43 | #define CTRL_OFST 0x0 |
44 | #define T_ZQ_OFST 0xA4 | |
ae9b56e3 PCK |
45 | |
46 | /* ECC control register */ | |
1b51adc6 | 47 | #define ECC_CTRL_OFST 0xC4 |
ae9b56e3 | 48 | /* ECC log register */ |
1b51adc6 | 49 | #define CE_LOG_OFST 0xC8 |
ae9b56e3 | 50 | /* ECC address register */ |
1b51adc6 | 51 | #define CE_ADDR_OFST 0xCC |
ae9b56e3 | 52 | /* ECC data[31:0] register */ |
1b51adc6 | 53 | #define CE_DATA_31_0_OFST 0xD0 |
ae9b56e3 PCK |
54 | |
55 | /* Uncorrectable error info registers */ | |
1b51adc6 MN |
56 | #define UE_LOG_OFST 0xDC |
57 | #define UE_ADDR_OFST 0xE0 | |
58 | #define UE_DATA_31_0_OFST 0xE4 | |
ae9b56e3 | 59 | |
1b51adc6 MN |
60 | #define STAT_OFST 0xF0 |
61 | #define SCRUB_OFST 0xF4 | |
ae9b56e3 PCK |
62 | |
63 | /* Control register bit field definitions */ | |
1b51adc6 MN |
64 | #define CTRL_BW_MASK 0xC |
65 | #define CTRL_BW_SHIFT 2 | |
ae9b56e3 | 66 | |
1b51adc6 MN |
67 | #define DDRCTL_WDTH_16 1 |
68 | #define DDRCTL_WDTH_32 0 | |
ae9b56e3 PCK |
69 | |
70 | /* ZQ register bit field definitions */ | |
1b51adc6 | 71 | #define T_ZQ_DDRMODE_MASK 0x2 |
ae9b56e3 PCK |
72 | |
73 | /* ECC control register bit field definitions */ | |
1b51adc6 MN |
74 | #define ECC_CTRL_CLR_CE_ERR 0x2 |
75 | #define ECC_CTRL_CLR_UE_ERR 0x1 | |
ae9b56e3 PCK |
76 | |
77 | /* ECC correctable/uncorrectable error log register definitions */ | |
1b51adc6 MN |
78 | #define LOG_VALID 0x1 |
79 | #define CE_LOG_BITPOS_MASK 0xFE | |
80 | #define CE_LOG_BITPOS_SHIFT 1 | |
ae9b56e3 PCK |
81 | |
82 | /* ECC correctable/uncorrectable error address register definitions */ | |
1b51adc6 MN |
83 | #define ADDR_COL_MASK 0xFFF |
84 | #define ADDR_ROW_MASK 0xFFFF000 | |
85 | #define ADDR_ROW_SHIFT 12 | |
86 | #define ADDR_BANK_MASK 0x70000000 | |
87 | #define ADDR_BANK_SHIFT 28 | |
ae9b56e3 PCK |
88 | |
89 | /* ECC statistic register definitions */ | |
1b51adc6 MN |
90 | #define STAT_UECNT_MASK 0xFF |
91 | #define STAT_CECNT_MASK 0xFF00 | |
92 | #define STAT_CECNT_SHIFT 8 | |
ae9b56e3 PCK |
93 | |
94 | /* ECC scrub register definitions */ | |
1b51adc6 MN |
95 | #define SCRUB_MODE_MASK 0x7 |
96 | #define SCRUB_MODE_SECDED 0x4 | |
ae9b56e3 PCK |
97 | |
98 | /** | |
225af74d MN |
99 | * struct ecc_error_info - ECC error log information. |
100 | * @row: Row number. | |
101 | * @col: Column number. | |
102 | * @bank: Bank number. | |
103 | * @bitpos: Bit position. | |
104 | * @data: Data causing the error. | |
ae9b56e3 PCK |
105 | */ |
106 | struct ecc_error_info { | |
107 | u32 row; | |
108 | u32 col; | |
109 | u32 bank; | |
110 | u32 bitpos; | |
111 | u32 data; | |
112 | }; | |
113 | ||
114 | /** | |
225af74d MN |
115 | * struct synps_ecc_status - ECC status information to report. |
116 | * @ce_cnt: Correctable error count. | |
117 | * @ue_cnt: Uncorrectable error count. | |
118 | * @ceinfo: Correctable error log information. | |
119 | * @ueinfo: Uncorrectable error log information. | |
ae9b56e3 PCK |
120 | */ |
121 | struct synps_ecc_status { | |
122 | u32 ce_cnt; | |
123 | u32 ue_cnt; | |
124 | struct ecc_error_info ceinfo; | |
125 | struct ecc_error_info ueinfo; | |
126 | }; | |
127 | ||
128 | /** | |
225af74d MN |
129 | * struct synps_edac_priv - DDR memory controller private instance data. |
130 | * @baseaddr: Base address of the DDR controller. | |
131 | * @message: Buffer for framing the event specific info. | |
132 | * @stat: ECC status information. | |
133 | * @ce_cnt: Correctable Error count. | |
134 | * @ue_cnt: Uncorrectable Error count. | |
ae9b56e3 PCK |
135 | */ |
136 | struct synps_edac_priv { | |
137 | void __iomem *baseaddr; | |
138 | char message[SYNPS_EDAC_MSG_SIZE]; | |
139 | struct synps_ecc_status stat; | |
140 | u32 ce_cnt; | |
141 | u32 ue_cnt; | |
142 | }; | |
143 | ||
144 | /** | |
225af74d MN |
145 | * get_error_info - Get the current ECC error info. |
146 | * @base: Base address of the DDR memory controller. | |
147 | * @p: Synopsys ECC status structure. | |
ae9b56e3 | 148 | * |
225af74d | 149 | * Return: one if there is no error otherwise zero. |
ae9b56e3 | 150 | */ |
bb894bc4 | 151 | static int get_error_info(void __iomem *base, struct synps_ecc_status *p) |
ae9b56e3 PCK |
152 | { |
153 | u32 regval, clearval = 0; | |
154 | ||
155 | regval = readl(base + STAT_OFST); | |
156 | if (!regval) | |
157 | return 1; | |
158 | ||
159 | p->ce_cnt = (regval & STAT_CECNT_MASK) >> STAT_CECNT_SHIFT; | |
160 | p->ue_cnt = regval & STAT_UECNT_MASK; | |
161 | ||
162 | regval = readl(base + CE_LOG_OFST); | |
163 | if (!(p->ce_cnt && (regval & LOG_VALID))) | |
164 | goto ue_err; | |
165 | ||
166 | p->ceinfo.bitpos = (regval & CE_LOG_BITPOS_MASK) >> CE_LOG_BITPOS_SHIFT; | |
167 | regval = readl(base + CE_ADDR_OFST); | |
168 | p->ceinfo.row = (regval & ADDR_ROW_MASK) >> ADDR_ROW_SHIFT; | |
169 | p->ceinfo.col = regval & ADDR_COL_MASK; | |
170 | p->ceinfo.bank = (regval & ADDR_BANK_MASK) >> ADDR_BANK_SHIFT; | |
171 | p->ceinfo.data = readl(base + CE_DATA_31_0_OFST); | |
1b51adc6 | 172 | edac_dbg(3, "CE bit position: %d data: %d\n", p->ceinfo.bitpos, |
ae9b56e3 PCK |
173 | p->ceinfo.data); |
174 | clearval = ECC_CTRL_CLR_CE_ERR; | |
175 | ||
176 | ue_err: | |
177 | regval = readl(base + UE_LOG_OFST); | |
178 | if (!(p->ue_cnt && (regval & LOG_VALID))) | |
179 | goto out; | |
180 | ||
181 | regval = readl(base + UE_ADDR_OFST); | |
182 | p->ueinfo.row = (regval & ADDR_ROW_MASK) >> ADDR_ROW_SHIFT; | |
183 | p->ueinfo.col = regval & ADDR_COL_MASK; | |
184 | p->ueinfo.bank = (regval & ADDR_BANK_MASK) >> ADDR_BANK_SHIFT; | |
185 | p->ueinfo.data = readl(base + UE_DATA_31_0_OFST); | |
186 | clearval |= ECC_CTRL_CLR_UE_ERR; | |
187 | ||
188 | out: | |
189 | writel(clearval, base + ECC_CTRL_OFST); | |
190 | writel(0x0, base + ECC_CTRL_OFST); | |
191 | ||
192 | return 0; | |
193 | } | |
194 | ||
195 | /** | |
225af74d MN |
196 | * handle_error - Handle Correctable and Uncorrectable errors. |
197 | * @mci: EDAC memory controller instance. | |
198 | * @p: Synopsys ECC status structure. | |
ae9b56e3 | 199 | * |
225af74d | 200 | * Handles ECC correctable and uncorrectable errors. |
ae9b56e3 | 201 | */ |
bb894bc4 | 202 | static void handle_error(struct mem_ctl_info *mci, struct synps_ecc_status *p) |
ae9b56e3 PCK |
203 | { |
204 | struct synps_edac_priv *priv = mci->pvt_info; | |
205 | struct ecc_error_info *pinf; | |
206 | ||
207 | if (p->ce_cnt) { | |
208 | pinf = &p->ceinfo; | |
209 | snprintf(priv->message, SYNPS_EDAC_MSG_SIZE, | |
210 | "DDR ECC error type :%s Row %d Bank %d Col %d ", | |
211 | "CE", pinf->row, pinf->bank, pinf->col); | |
212 | edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, | |
213 | p->ce_cnt, 0, 0, 0, 0, 0, -1, | |
214 | priv->message, ""); | |
215 | } | |
216 | ||
217 | if (p->ue_cnt) { | |
218 | pinf = &p->ueinfo; | |
219 | snprintf(priv->message, SYNPS_EDAC_MSG_SIZE, | |
220 | "DDR ECC error type :%s Row %d Bank %d Col %d ", | |
221 | "UE", pinf->row, pinf->bank, pinf->col); | |
222 | edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, | |
223 | p->ue_cnt, 0, 0, 0, 0, 0, -1, | |
224 | priv->message, ""); | |
225 | } | |
226 | ||
227 | memset(p, 0, sizeof(*p)); | |
228 | } | |
229 | ||
230 | /** | |
225af74d MN |
231 | * check_errors - Check controller for ECC errors. |
232 | * @mci: EDAC memory controller instance. | |
ae9b56e3 | 233 | * |
225af74d | 234 | * Check and post ECC errors. Called by the polling thread. |
ae9b56e3 | 235 | */ |
bb894bc4 | 236 | static void check_errors(struct mem_ctl_info *mci) |
ae9b56e3 PCK |
237 | { |
238 | struct synps_edac_priv *priv = mci->pvt_info; | |
239 | int status; | |
240 | ||
bb894bc4 | 241 | status = get_error_info(priv->baseaddr, &priv->stat); |
ae9b56e3 PCK |
242 | if (status) |
243 | return; | |
244 | ||
245 | priv->ce_cnt += priv->stat.ce_cnt; | |
246 | priv->ue_cnt += priv->stat.ue_cnt; | |
bb894bc4 | 247 | handle_error(mci, &priv->stat); |
ae9b56e3 | 248 | |
1b51adc6 | 249 | edac_dbg(3, "Total error count CE %d UE %d\n", |
ae9b56e3 PCK |
250 | priv->ce_cnt, priv->ue_cnt); |
251 | } | |
252 | ||
253 | /** | |
225af74d MN |
254 | * get_dtype - Return the controller memory width. |
255 | * @base: DDR memory controller base address. | |
ae9b56e3 PCK |
256 | * |
257 | * Get the EDAC device type width appropriate for the current controller | |
258 | * configuration. | |
259 | * | |
260 | * Return: a device type width enumeration. | |
261 | */ | |
bb894bc4 | 262 | static enum dev_type get_dtype(const void __iomem *base) |
ae9b56e3 PCK |
263 | { |
264 | enum dev_type dt; | |
265 | u32 width; | |
266 | ||
267 | width = readl(base + CTRL_OFST); | |
268 | width = (width & CTRL_BW_MASK) >> CTRL_BW_SHIFT; | |
269 | ||
270 | switch (width) { | |
271 | case DDRCTL_WDTH_16: | |
272 | dt = DEV_X2; | |
273 | break; | |
274 | case DDRCTL_WDTH_32: | |
275 | dt = DEV_X4; | |
276 | break; | |
277 | default: | |
278 | dt = DEV_UNKNOWN; | |
279 | } | |
280 | ||
281 | return dt; | |
282 | } | |
283 | ||
284 | /** | |
225af74d MN |
285 | * get_ecc_state - Return the controller ECC enable/disable status. |
286 | * @base: DDR memory controller base address. | |
ae9b56e3 | 287 | * |
225af74d | 288 | * Get the ECC enable/disable status of the controller. |
ae9b56e3 | 289 | * |
225af74d | 290 | * Return: true if enabled, otherwise false. |
ae9b56e3 | 291 | */ |
bb894bc4 | 292 | static bool get_ecc_state(void __iomem *base) |
ae9b56e3 | 293 | { |
1b51adc6 | 294 | bool state = false; |
ae9b56e3 PCK |
295 | enum dev_type dt; |
296 | u32 ecctype; | |
ae9b56e3 | 297 | |
bb894bc4 | 298 | dt = get_dtype(base); |
ae9b56e3 PCK |
299 | if (dt == DEV_UNKNOWN) |
300 | return state; | |
301 | ||
302 | ecctype = readl(base + SCRUB_OFST) & SCRUB_MODE_MASK; | |
303 | if ((ecctype == SCRUB_MODE_SECDED) && (dt == DEV_X2)) | |
304 | state = true; | |
305 | ||
306 | return state; | |
307 | } | |
308 | ||
309 | /** | |
225af74d | 310 | * get_memsize - Read the size of the attached memory device. |
ae9b56e3 | 311 | * |
225af74d | 312 | * Return: the memory size in bytes. |
ae9b56e3 | 313 | */ |
bb894bc4 | 314 | static u32 get_memsize(void) |
ae9b56e3 PCK |
315 | { |
316 | struct sysinfo inf; | |
317 | ||
318 | si_meminfo(&inf); | |
319 | ||
320 | return inf.totalram * inf.mem_unit; | |
321 | } | |
322 | ||
323 | /** | |
225af74d MN |
324 | * get_mtype - Return the controller memory type. |
325 | * @base: Synopsys ECC status structure. | |
ae9b56e3 PCK |
326 | * |
327 | * Get the EDAC memory type appropriate for the current controller | |
328 | * configuration. | |
329 | * | |
330 | * Return: a memory type enumeration. | |
331 | */ | |
bb894bc4 | 332 | static enum mem_type get_mtype(const void __iomem *base) |
ae9b56e3 PCK |
333 | { |
334 | enum mem_type mt; | |
335 | u32 memtype; | |
336 | ||
337 | memtype = readl(base + T_ZQ_OFST); | |
338 | ||
339 | if (memtype & T_ZQ_DDRMODE_MASK) | |
340 | mt = MEM_DDR3; | |
341 | else | |
342 | mt = MEM_DDR2; | |
343 | ||
344 | return mt; | |
345 | } | |
346 | ||
347 | /** | |
225af74d MN |
348 | * init_csrows - Initialize the csrow data. |
349 | * @mci: EDAC memory controller instance. | |
ae9b56e3 | 350 | * |
225af74d MN |
351 | * Initialize the chip select rows associated with the EDAC memory |
352 | * controller instance. | |
ae9b56e3 | 353 | */ |
fa9f6b9e | 354 | static void init_csrows(struct mem_ctl_info *mci) |
ae9b56e3 | 355 | { |
1b51adc6 | 356 | struct synps_edac_priv *priv = mci->pvt_info; |
ae9b56e3 PCK |
357 | struct csrow_info *csi; |
358 | struct dimm_info *dimm; | |
1b51adc6 MN |
359 | u32 size, row; |
360 | int j; | |
ae9b56e3 PCK |
361 | |
362 | for (row = 0; row < mci->nr_csrows; row++) { | |
363 | csi = mci->csrows[row]; | |
bb894bc4 | 364 | size = get_memsize(); |
ae9b56e3 PCK |
365 | |
366 | for (j = 0; j < csi->nr_channels; j++) { | |
1b51adc6 MN |
367 | dimm = csi->channels[j]->dimm; |
368 | dimm->edac_mode = EDAC_FLAG_SECDED; | |
bb894bc4 | 369 | dimm->mtype = get_mtype(priv->baseaddr); |
1b51adc6 MN |
370 | dimm->nr_pages = (size >> PAGE_SHIFT) / csi->nr_channels; |
371 | dimm->grain = SYNPS_EDAC_ERR_GRAIN; | |
bb894bc4 | 372 | dimm->dtype = get_dtype(priv->baseaddr); |
ae9b56e3 PCK |
373 | } |
374 | } | |
ae9b56e3 PCK |
375 | } |
376 | ||
377 | /** | |
225af74d MN |
378 | * mc_init - Initialize one driver instance. |
379 | * @mci: EDAC memory controller instance. | |
380 | * @pdev: platform device. | |
ae9b56e3 | 381 | * |
225af74d | 382 | * Perform initialization of the EDAC memory controller instance and |
ae9b56e3 PCK |
383 | * related driver-private data associated with the memory controller the |
384 | * instance is bound to. | |
ae9b56e3 | 385 | */ |
fa9f6b9e | 386 | static void mc_init(struct mem_ctl_info *mci, struct platform_device *pdev) |
ae9b56e3 | 387 | { |
ae9b56e3 PCK |
388 | struct synps_edac_priv *priv; |
389 | ||
390 | mci->pdev = &pdev->dev; | |
391 | priv = mci->pvt_info; | |
392 | platform_set_drvdata(pdev, mci); | |
393 | ||
394 | /* Initialize controller capabilities and configuration */ | |
395 | mci->mtype_cap = MEM_FLAG_DDR3 | MEM_FLAG_DDR2; | |
396 | mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED; | |
397 | mci->scrub_cap = SCRUB_HW_SRC; | |
398 | mci->scrub_mode = SCRUB_NONE; | |
399 | ||
400 | mci->edac_cap = EDAC_FLAG_SECDED; | |
401 | mci->ctl_name = "synps_ddr_controller"; | |
402 | mci->dev_name = SYNPS_EDAC_MOD_STRING; | |
403 | mci->mod_name = SYNPS_EDAC_MOD_VER; | |
ae9b56e3 PCK |
404 | |
405 | edac_op_state = EDAC_OPSTATE_POLL; | |
bb894bc4 | 406 | mci->edac_check = check_errors; |
ae9b56e3 PCK |
407 | mci->ctl_page_to_phys = NULL; |
408 | ||
fa9f6b9e | 409 | init_csrows(mci); |
ae9b56e3 PCK |
410 | } |
411 | ||
412 | /** | |
225af74d MN |
413 | * mc_probe - Check controller and bind driver. |
414 | * @pdev: platform device. | |
ae9b56e3 | 415 | * |
225af74d | 416 | * Probe a specific controller instance for binding with the driver. |
ae9b56e3 PCK |
417 | * |
418 | * Return: 0 if the controller instance was successfully bound to the | |
419 | * driver; otherwise, < 0 on error. | |
420 | */ | |
bb894bc4 | 421 | static int mc_probe(struct platform_device *pdev) |
ae9b56e3 | 422 | { |
ae9b56e3 PCK |
423 | struct edac_mc_layer layers[2]; |
424 | struct synps_edac_priv *priv; | |
1b51adc6 | 425 | struct mem_ctl_info *mci; |
ae9b56e3 | 426 | void __iomem *baseaddr; |
1b51adc6 MN |
427 | struct resource *res; |
428 | int rc; | |
ae9b56e3 PCK |
429 | |
430 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
431 | baseaddr = devm_ioremap_resource(&pdev->dev, res); | |
432 | if (IS_ERR(baseaddr)) | |
433 | return PTR_ERR(baseaddr); | |
434 | ||
bb894bc4 | 435 | if (!get_ecc_state(baseaddr)) { |
ae9b56e3 PCK |
436 | edac_printk(KERN_INFO, EDAC_MC, "ECC not enabled\n"); |
437 | return -ENXIO; | |
438 | } | |
439 | ||
440 | layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; | |
441 | layers[0].size = SYNPS_EDAC_NR_CSROWS; | |
442 | layers[0].is_virt_csrow = true; | |
443 | layers[1].type = EDAC_MC_LAYER_CHANNEL; | |
444 | layers[1].size = SYNPS_EDAC_NR_CHANS; | |
445 | layers[1].is_virt_csrow = false; | |
446 | ||
447 | mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, | |
448 | sizeof(struct synps_edac_priv)); | |
449 | if (!mci) { | |
450 | edac_printk(KERN_ERR, EDAC_MC, | |
451 | "Failed memory allocation for mc instance\n"); | |
452 | return -ENOMEM; | |
453 | } | |
454 | ||
455 | priv = mci->pvt_info; | |
456 | priv->baseaddr = baseaddr; | |
fa9f6b9e | 457 | mc_init(mci, pdev); |
ae9b56e3 PCK |
458 | |
459 | rc = edac_mc_add_mc(mci); | |
460 | if (rc) { | |
461 | edac_printk(KERN_ERR, EDAC_MC, | |
462 | "Failed to register with EDAC core\n"); | |
463 | goto free_edac_mc; | |
464 | } | |
465 | ||
466 | /* | |
467 | * Start capturing the correctable and uncorrectable errors. A write of | |
468 | * 0 starts the counters. | |
469 | */ | |
470 | writel(0x0, baseaddr + ECC_CTRL_OFST); | |
471 | return rc; | |
472 | ||
473 | free_edac_mc: | |
474 | edac_mc_free(mci); | |
475 | ||
476 | return rc; | |
477 | } | |
478 | ||
479 | /** | |
225af74d MN |
480 | * mc_remove - Unbind driver from controller. |
481 | * @pdev: Platform device. | |
ae9b56e3 PCK |
482 | * |
483 | * Return: Unconditionally 0 | |
484 | */ | |
bb894bc4 | 485 | static int mc_remove(struct platform_device *pdev) |
ae9b56e3 PCK |
486 | { |
487 | struct mem_ctl_info *mci = platform_get_drvdata(pdev); | |
488 | ||
489 | edac_mc_del_mc(&pdev->dev); | |
490 | edac_mc_free(mci); | |
491 | ||
492 | return 0; | |
493 | } | |
494 | ||
1afaa055 | 495 | static const struct of_device_id synps_edac_match[] = { |
ae9b56e3 PCK |
496 | { .compatible = "xlnx,zynq-ddrc-a05", }, |
497 | { /* end of table */ } | |
498 | }; | |
499 | ||
500 | MODULE_DEVICE_TABLE(of, synps_edac_match); | |
501 | ||
502 | static struct platform_driver synps_edac_mc_driver = { | |
503 | .driver = { | |
504 | .name = "synopsys-edac", | |
505 | .of_match_table = synps_edac_match, | |
506 | }, | |
bb894bc4 MN |
507 | .probe = mc_probe, |
508 | .remove = mc_remove, | |
ae9b56e3 PCK |
509 | }; |
510 | ||
511 | module_platform_driver(synps_edac_mc_driver); | |
512 | ||
513 | MODULE_AUTHOR("Xilinx Inc"); | |
514 | MODULE_DESCRIPTION("Synopsys DDR ECC driver"); | |
515 | MODULE_LICENSE("GPL v2"); |