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EDAC: Get rid of mci->mod_ver
[mirror_ubuntu-bionic-kernel.git] / drivers / edac / thunderx_edac.c
CommitLineData
41003396
ST		 1/*
2 * Cavium ThunderX memory controller kernel module
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright Cavium, Inc. (C) 2015-2017. All rights reserved.
9 *
10 */
11
12#include <linux/module.h>
13#include <linux/pci.h>
14#include <linux/edac.h>
15#include <linux/interrupt.h>
16#include <linux/string.h>
17#include <linux/stop_machine.h>
18#include <linux/delay.h>
19#include <linux/sizes.h>
20#include <linux/atomic.h>
21#include <linux/bitfield.h>
22#include <linux/circ_buf.h>
23
24#include <asm/page.h>
25
26#include "edac_module.h"
27
28#define phys_to_pfn(phys) (PFN_DOWN(phys))
29
30#define THUNDERX_NODE GENMASK(45, 44)
31
32enum {
33 ERR_CORRECTED = 1,
34 ERR_UNCORRECTED = 2,
35 ERR_UNKNOWN = 3,
36};
37
38#define MAX_SYNDROME_REGS 4
39
40struct error_syndrome {
41 u64 reg[MAX_SYNDROME_REGS];
42};
43
44struct error_descr {
45 int type;
46 u64 mask;
47 char *descr;
48};
49
50static void decode_register(char *str, size_t size,
51 const struct error_descr *descr,
52 const uint64_t reg)
53{
54 int ret = 0;
55
56 while (descr->type && descr->mask && descr->descr) {
57 if (reg & descr->mask) {
58 ret = snprintf(str, size, "\n\t%s, %s",
59 descr->type == ERR_CORRECTED ?
60 "Corrected" : "Uncorrected",
61 descr->descr);
62 str += ret;
63 size -= ret;
64 }
65 descr++;
66 }
67}
68
69static unsigned long get_bits(unsigned long data, int pos, int width)
70{
71 return (data >> pos) & ((1 << width) - 1);
72}
73
74#define L2C_CTL 0x87E080800000
75#define L2C_CTL_DISIDXALIAS BIT(0)
76
77#define PCI_DEVICE_ID_THUNDER_LMC 0xa022
78
79#define LMC_FADR 0x20
80#define LMC_FADR_FDIMM(x) ((x >> 37) & 0x1)
81#define LMC_FADR_FBUNK(x) ((x >> 36) & 0x1)
82#define LMC_FADR_FBANK(x) ((x >> 32) & 0xf)
83#define LMC_FADR_FROW(x) ((x >> 14) & 0xffff)
84#define LMC_FADR_FCOL(x) ((x >> 0) & 0x1fff)
85
86#define LMC_NXM_FADR 0x28
87#define LMC_ECC_SYND 0x38
88
89#define LMC_ECC_PARITY_TEST 0x108
90
91#define LMC_INT_W1S 0x150
92
93#define LMC_INT_ENA_W1C 0x158
94#define LMC_INT_ENA_W1S 0x160
95
96#define LMC_CONFIG 0x188
97
98#define LMC_CONFIG_BG2 BIT(62)
99#define LMC_CONFIG_RANK_ENA BIT(42)
100#define LMC_CONFIG_PBANK_LSB(x) (((x) >> 5) & 0xF)
101#define LMC_CONFIG_ROW_LSB(x) (((x) >> 2) & 0x7)
102
103#define LMC_CONTROL 0x190
104#define LMC_CONTROL_XOR_BANK BIT(16)
105
106#define LMC_INT 0x1F0
107
108#define LMC_INT_DDR_ERR BIT(11)
109#define LMC_INT_DED_ERR (0xFUL << 5)
110#define LMC_INT_SEC_ERR (0xFUL << 1)
111#define LMC_INT_NXM_WR_MASK BIT(0)
112
113#define LMC_DDR_PLL_CTL 0x258
114#define LMC_DDR_PLL_CTL_DDR4 BIT(29)
115
116#define LMC_FADR_SCRAMBLED 0x330
117
118#define LMC_INT_UE (LMC_INT_DDR_ERR | LMC_INT_DED_ERR | \
119 LMC_INT_NXM_WR_MASK)
120
121#define LMC_INT_CE (LMC_INT_SEC_ERR)
122
123static const struct error_descr lmc_errors[] = {
124 {
125 .type = ERR_CORRECTED,
126 .mask = LMC_INT_SEC_ERR,
127 .descr = "Single-bit ECC error",
128 },
129 {
130 .type = ERR_UNCORRECTED,
131 .mask = LMC_INT_DDR_ERR,
132 .descr = "DDR chip error",
133 },
134 {
135 .type = ERR_UNCORRECTED,
136 .mask = LMC_INT_DED_ERR,
137 .descr = "Double-bit ECC error",
138 },
139 {
140 .type = ERR_UNCORRECTED,
141 .mask = LMC_INT_NXM_WR_MASK,
142 .descr = "Non-existent memory write",
143 },
144 {0, 0, NULL},
145};
146
147#define LMC_INT_EN_DDR_ERROR_ALERT_ENA BIT(5)
148#define LMC_INT_EN_DLCRAM_DED_ERR BIT(4)
149#define LMC_INT_EN_DLCRAM_SEC_ERR BIT(3)
150#define LMC_INT_INTR_DED_ENA BIT(2)
151#define LMC_INT_INTR_SEC_ENA BIT(1)
152#define LMC_INT_INTR_NXM_WR_ENA BIT(0)
153
154#define LMC_INT_ENA_ALL GENMASK(5, 0)
155
156#define LMC_DDR_PLL_CTL 0x258
157#define LMC_DDR_PLL_CTL_DDR4 BIT(29)
158
159#define LMC_CONTROL 0x190
160#define LMC_CONTROL_RDIMM BIT(0)
161
162#define LMC_SCRAM_FADR 0x330
163
164#define LMC_CHAR_MASK0 0x228
165#define LMC_CHAR_MASK2 0x238
166
167#define RING_ENTRIES 8
168
169struct debugfs_entry {
170 const char *name;
171 umode_t mode;
172 const struct file_operations fops;
173};
174
175struct lmc_err_ctx {
176 u64 reg_int;
177 u64 reg_fadr;
178 u64 reg_nxm_fadr;
179 u64 reg_scram_fadr;
180 u64 reg_ecc_synd;
181};
182
183struct thunderx_lmc {
184 void __iomem *regs;
185 struct pci_dev *pdev;
186 struct msix_entry msix_ent;
187
188 atomic_t ecc_int;
189
190 u64 mask0;
191 u64 mask2;
192 u64 parity_test;
193 u64 node;
194
195 int xbits;
196 int bank_width;
197 int pbank_lsb;
198 int dimm_lsb;
199 int rank_lsb;
200 int bank_lsb;
201 int row_lsb;
202 int col_hi_lsb;
203
204 int xor_bank;
205 int l2c_alias;
206
207 struct page *mem;
208
209 struct lmc_err_ctx err_ctx[RING_ENTRIES];
210 unsigned long ring_head;
211 unsigned long ring_tail;
212};
213
214#define ring_pos(pos, size) ((pos) & (size - 1))
215
216#define DEBUGFS_STRUCT(_name, _mode, _write, _read) \
217static struct debugfs_entry debugfs_##_name = { \
218 .name = __stringify(_name), \
219 .mode = VERIFY_OCTAL_PERMISSIONS(_mode), \
220 .fops = { \
221 .open = simple_open, \
222 .write = _write, \
223 .read = _read, \
224 .llseek = generic_file_llseek, \
225 }, \
226}
227
228#define DEBUGFS_FIELD_ATTR(_type, _field) \
229static ssize_t thunderx_##_type##_##_field##_read(struct file *file, \
230 char __user *data, \
231 size_t count, loff_t *ppos) \
232{ \
233 struct thunderx_##_type *pdata = file->private_data; \
234 char buf[20]; \
235 \
236 snprintf(buf, count, "0x%016llx", pdata->_field); \
237 return simple_read_from_buffer(data, count, ppos, \
238 buf, sizeof(buf)); \
239} \
240 \
241static ssize_t thunderx_##_type##_##_field##_write(struct file *file, \
242 const char __user *data, \
243 size_t count, loff_t *ppos) \
244{ \
245 struct thunderx_##_type *pdata = file->private_data; \
246 int res; \
247 \
248 res = kstrtoull_from_user(data, count, 0, &pdata->_field); \
249 \
250 return res ? res : count; \
251} \
252 \
253DEBUGFS_STRUCT(_field, 0600, \
254 thunderx_##_type##_##_field##_write, \
255 thunderx_##_type##_##_field##_read) \
256
257#define DEBUGFS_REG_ATTR(_type, _name, _reg) \
258static ssize_t thunderx_##_type##_##_name##_read(struct file *file, \
259 char __user *data, \
260 size_t count, loff_t *ppos) \
261{ \
262 struct thunderx_##_type *pdata = file->private_data; \
263 char buf[20]; \
264 \
265 sprintf(buf, "0x%016llx", readq(pdata->regs + _reg)); \
266 return simple_read_from_buffer(data, count, ppos, \
267 buf, sizeof(buf)); \
268} \
269 \
270static ssize_t thunderx_##_type##_##_name##_write(struct file *file, \
271 const char __user *data, \
272 size_t count, loff_t *ppos) \
273{ \
274 struct thunderx_##_type *pdata = file->private_data; \
275 u64 val; \
276 int res; \
277 \
278 res = kstrtoull_from_user(data, count, 0, &val); \
279 \
280 if (!res) { \
281 writeq(val, pdata->regs + _reg); \
282 res = count; \
283 } \
284 \
285 return res; \
286} \
287 \
288DEBUGFS_STRUCT(_name, 0600, \
289 thunderx_##_type##_##_name##_write, \
290 thunderx_##_type##_##_name##_read)
291
292#define LMC_DEBUGFS_ENT(_field) DEBUGFS_FIELD_ATTR(lmc, _field)
293
294/*
295 * To get an ECC error injected, the following steps are needed:
296 * - Setup the ECC injection by writing the appropriate parameters:
297 * echo <bit mask value> > /sys/kernel/debug/<device number>/ecc_mask0
298 * echo <bit mask value> > /sys/kernel/debug/<device number>/ecc_mask2
299 * echo 0x802 > /sys/kernel/debug/<device number>/ecc_parity_test
300 * - Do the actual injection:
301 * echo 1 > /sys/kernel/debug/<device number>/inject_ecc
302 */
303static ssize_t thunderx_lmc_inject_int_write(struct file *file,
304 const char __user *data,
305 size_t count, loff_t *ppos)
306{
307 struct thunderx_lmc *lmc = file->private_data;
308 u64 val;
309 int res;
310
311 res = kstrtoull_from_user(data, count, 0, &val);
312
313 if (!res) {
314 /* Trigger the interrupt */
315 writeq(val, lmc->regs + LMC_INT_W1S);
316 res = count;
317 }
318
319 return res;
320}
321
322static ssize_t thunderx_lmc_int_read(struct file *file,
323 char __user *data,
324 size_t count, loff_t *ppos)
325{
326 struct thunderx_lmc *lmc = file->private_data;
327 char buf[20];
328 u64 lmc_int = readq(lmc->regs + LMC_INT);
329
330 snprintf(buf, sizeof(buf), "0x%016llx", lmc_int);
331 return simple_read_from_buffer(data, count, ppos, buf, sizeof(buf));
332}
333
334#define TEST_PATTERN 0xa5
335
336static int inject_ecc_fn(void *arg)
337{
338 struct thunderx_lmc *lmc = arg;
339 uintptr_t addr, phys;
340 unsigned int cline_size = cache_line_size();
341 const unsigned int lines = PAGE_SIZE / cline_size;
342 unsigned int i, cl_idx;
343
344 addr = (uintptr_t)page_address(lmc->mem);
345 phys = (uintptr_t)page_to_phys(lmc->mem);
346
347 cl_idx = (phys & 0x7f) >> 4;
348 lmc->parity_test &= ~(7ULL << 8);
349 lmc->parity_test |= (cl_idx << 8);
350
351 writeq(lmc->mask0, lmc->regs + LMC_CHAR_MASK0);
352 writeq(lmc->mask2, lmc->regs + LMC_CHAR_MASK2);
353 writeq(lmc->parity_test, lmc->regs + LMC_ECC_PARITY_TEST);
354
355 readq(lmc->regs + LMC_CHAR_MASK0);
356 readq(lmc->regs + LMC_CHAR_MASK2);
357 readq(lmc->regs + LMC_ECC_PARITY_TEST);
358
359 for (i = 0; i < lines; i++) {
360 memset((void *)addr, TEST_PATTERN, cline_size);
361 barrier();
362
363 /*
364 * Flush L1 cachelines to the PoC (L2).
365 * This will cause cacheline eviction to the L2.
366 */
367 asm volatile("dc civac, %0\n"
368 "dsb sy\n"
369 : : "r"(addr + i * cline_size));
370 }
371
372 for (i = 0; i < lines; i++) {
373 /*
374 * Flush L2 cachelines to the DRAM.
375 * This will cause cacheline eviction to the DRAM
376 * and ECC corruption according to the masks set.
377 */
378 __asm__ volatile("sys #0,c11,C1,#2, %0\n"
379 : : "r"(phys + i * cline_size));
380 }
381
382 for (i = 0; i < lines; i++) {
383 /*
384 * Invalidate L2 cachelines.
385 * The subsequent load will cause cacheline fetch
386 * from the DRAM and an error interrupt
387 */
388 __asm__ volatile("sys #0,c11,C1,#1, %0"
389 : : "r"(phys + i * cline_size));
390 }
391
392 for (i = 0; i < lines; i++) {
393 /*
394 * Invalidate L1 cachelines.
395 * The subsequent load will cause cacheline fetch
396 * from the L2 and/or DRAM
397 */
398 asm volatile("dc ivac, %0\n"
399 "dsb sy\n"
400 : : "r"(addr + i * cline_size));
401 }
402
403 return 0;
404}
405
406static ssize_t thunderx_lmc_inject_ecc_write(struct file *file,
407 const char __user *data,
408 size_t count, loff_t *ppos)
409{
410 struct thunderx_lmc *lmc = file->private_data;
411
412 unsigned int cline_size = cache_line_size();
413
414 u8 tmp[cline_size];
415 void __iomem *addr;
416 unsigned int offs, timeout = 100000;
417
418 atomic_set(&lmc->ecc_int, 0);
419
420 lmc->mem = alloc_pages_node(lmc->node, GFP_KERNEL, 0);
421
422 if (!lmc->mem)
423 return -ENOMEM;
424
425 addr = page_address(lmc->mem);
426
427 while (!atomic_read(&lmc->ecc_int) && timeout--) {
428 stop_machine(inject_ecc_fn, lmc, NULL);
429
430 for (offs = 0; offs < PAGE_SIZE; offs += sizeof(tmp)) {
431 /*
432 * Do a load from the previously rigged location
433 * This should generate an error interrupt.
434 */
435 memcpy(tmp, addr + offs, cline_size);
436 asm volatile("dsb ld\n");
437 }
438 }
439
440 __free_pages(lmc->mem, 0);
441
442 return count;
443}
444
445LMC_DEBUGFS_ENT(mask0);
446LMC_DEBUGFS_ENT(mask2);
447LMC_DEBUGFS_ENT(parity_test);
448
449DEBUGFS_STRUCT(inject_int, 0200, thunderx_lmc_inject_int_write, NULL);
450DEBUGFS_STRUCT(inject_ecc, 0200, thunderx_lmc_inject_ecc_write, NULL);
451DEBUGFS_STRUCT(int_w1c, 0400, NULL, thunderx_lmc_int_read);
452
453struct debugfs_entry *lmc_dfs_ents[] = {
454 &debugfs_mask0,
455 &debugfs_mask2,
456 &debugfs_parity_test,
457 &debugfs_inject_ecc,
458 &debugfs_inject_int,
459 &debugfs_int_w1c,
460};
461
462static int thunderx_create_debugfs_nodes(struct dentry *parent,
463 struct debugfs_entry *attrs[],
464 void *data,
465 size_t num)
466{
467 int i;
468 struct dentry *ent;
469
470 if (!IS_ENABLED(CONFIG_EDAC_DEBUG))
471 return 0;
472
473 if (!parent)
474 return -ENOENT;
475
476 for (i = 0; i < num; i++) {
477 ent = edac_debugfs_create_file(attrs[i]->name, attrs[i]->mode,
478 parent, data, &attrs[i]->fops);
479
480 if (!ent)
481 break;
482 }
483
484 return i;
485}
486
487static phys_addr_t thunderx_faddr_to_phys(u64 faddr, struct thunderx_lmc *lmc)
488{
489 phys_addr_t addr = 0;
490 int bank, xbits;
491
492 addr |= lmc->node << 40;
493 addr |= LMC_FADR_FDIMM(faddr) << lmc->dimm_lsb;
494 addr |= LMC_FADR_FBUNK(faddr) << lmc->rank_lsb;
495 addr |= LMC_FADR_FROW(faddr) << lmc->row_lsb;
496 addr |= (LMC_FADR_FCOL(faddr) >> 4) << lmc->col_hi_lsb;
497
498 bank = LMC_FADR_FBANK(faddr) << lmc->bank_lsb;
499
500 if (lmc->xor_bank)
501 bank ^= get_bits(addr, 12 + lmc->xbits, lmc->bank_width);
502
503 addr |= bank << lmc->bank_lsb;
504
505 xbits = PCI_FUNC(lmc->pdev->devfn);
506
507 if (lmc->l2c_alias)
508 xbits ^= get_bits(addr, 20, lmc->xbits) ^
509 get_bits(addr, 12, lmc->xbits);
510
511 addr |= xbits << 7;
512
513 return addr;
514}
515
516static unsigned int thunderx_get_num_lmcs(unsigned int node)
517{
518 unsigned int number = 0;
519 struct pci_dev *pdev = NULL;
520
521 do {
522 pdev = pci_get_device(PCI_VENDOR_ID_CAVIUM,
523 PCI_DEVICE_ID_THUNDER_LMC,
524 pdev);
525 if (pdev) {
526#ifdef CONFIG_NUMA
527 if (pdev->dev.numa_node == node)
528 number++;
529#else
530 number++;
531#endif
532 }
533 } while (pdev);
534
535 return number;
536}
537
538#define LMC_MESSAGE_SIZE 120
539#define LMC_OTHER_SIZE (50 * ARRAY_SIZE(lmc_errors))
540
541static irqreturn_t thunderx_lmc_err_isr(int irq, void *dev_id)
542{
543 struct mem_ctl_info *mci = dev_id;
544 struct thunderx_lmc *lmc = mci->pvt_info;
545
546 unsigned long head = ring_pos(lmc->ring_head, ARRAY_SIZE(lmc->err_ctx));
547 struct lmc_err_ctx *ctx = &lmc->err_ctx[head];
548
549 writeq(0, lmc->regs + LMC_CHAR_MASK0);
550 writeq(0, lmc->regs + LMC_CHAR_MASK2);
551 writeq(0x2, lmc->regs + LMC_ECC_PARITY_TEST);
552
553 ctx->reg_int = readq(lmc->regs + LMC_INT);
554 ctx->reg_fadr = readq(lmc->regs + LMC_FADR);
555 ctx->reg_nxm_fadr = readq(lmc->regs + LMC_NXM_FADR);
556 ctx->reg_scram_fadr = readq(lmc->regs + LMC_SCRAM_FADR);
557 ctx->reg_ecc_synd = readq(lmc->regs + LMC_ECC_SYND);
558
559 lmc->ring_head++;
560
561 atomic_set(&lmc->ecc_int, 1);
562
563 /* Clear the interrupt */
564 writeq(ctx->reg_int, lmc->regs + LMC_INT);
565
566 return IRQ_WAKE_THREAD;
567}
568
569static irqreturn_t thunderx_lmc_threaded_isr(int irq, void *dev_id)
570{
571 struct mem_ctl_info *mci = dev_id;
572 struct thunderx_lmc *lmc = mci->pvt_info;
573 phys_addr_t phys_addr;
574
575 unsigned long tail;
576 struct lmc_err_ctx *ctx;
577
578 irqreturn_t ret = IRQ_NONE;
579
580 char *msg;
581 char *other;
582
583 msg = kmalloc(LMC_MESSAGE_SIZE, GFP_KERNEL);
584 other = kmalloc(LMC_OTHER_SIZE, GFP_KERNEL);
585
586 if (!msg || !other)
587 goto err_free;
588
589 while (CIRC_CNT(lmc->ring_head, lmc->ring_tail,
590 ARRAY_SIZE(lmc->err_ctx))) {
591 tail = ring_pos(lmc->ring_tail, ARRAY_SIZE(lmc->err_ctx));
592
593 ctx = &lmc->err_ctx[tail];
594
595 dev_dbg(&lmc->pdev->dev, "LMC_INT: %016llx\n",
596 ctx->reg_int);
597 dev_dbg(&lmc->pdev->dev, "LMC_FADR: %016llx\n",
598 ctx->reg_fadr);
599 dev_dbg(&lmc->pdev->dev, "LMC_NXM_FADR: %016llx\n",
600 ctx->reg_nxm_fadr);
601 dev_dbg(&lmc->pdev->dev, "LMC_SCRAM_FADR: %016llx\n",
602 ctx->reg_scram_fadr);
603 dev_dbg(&lmc->pdev->dev, "LMC_ECC_SYND: %016llx\n",
604 ctx->reg_ecc_synd);
605
606 snprintf(msg, LMC_MESSAGE_SIZE,
607 "DIMM %lld rank %lld bank %lld row %lld col %lld",
608 LMC_FADR_FDIMM(ctx->reg_scram_fadr),
609 LMC_FADR_FBUNK(ctx->reg_scram_fadr),
610 LMC_FADR_FBANK(ctx->reg_scram_fadr),
611 LMC_FADR_FROW(ctx->reg_scram_fadr),
612 LMC_FADR_FCOL(ctx->reg_scram_fadr));
613
614 decode_register(other, LMC_OTHER_SIZE, lmc_errors,
615 ctx->reg_int);
616
617 phys_addr = thunderx_faddr_to_phys(ctx->reg_fadr, lmc);
618
619 if (ctx->reg_int & LMC_INT_UE)
620 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
621 phys_to_pfn(phys_addr),
622 offset_in_page(phys_addr),
623 0, -1, -1, -1, msg, other);
624 else if (ctx->reg_int & LMC_INT_CE)
625 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
626 phys_to_pfn(phys_addr),
627 offset_in_page(phys_addr),
628 0, -1, -1, -1, msg, other);
629
630 lmc->ring_tail++;
631 }
632
633 ret = IRQ_HANDLED;
634
635err_free:
636 kfree(msg);
637 kfree(other);
638
639 return ret;
640}
641
642#ifdef CONFIG_PM
643static int thunderx_lmc_suspend(struct pci_dev *pdev, pm_message_t state)
644{
645 pci_save_state(pdev);
646 pci_disable_device(pdev);
647
648 pci_set_power_state(pdev, pci_choose_state(pdev, state));
649
650 return 0;
651}
652
653static int thunderx_lmc_resume(struct pci_dev *pdev)
654{
655 pci_set_power_state(pdev, PCI_D0);
656 pci_enable_wake(pdev, PCI_D0, 0);
657 pci_restore_state(pdev);
658
659 return 0;
660}
661#endif
662
663static const struct pci_device_id thunderx_lmc_pci_tbl[] = {
664 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVICE_ID_THUNDER_LMC) },
665 { 0, },
666};
667
668static inline int pci_dev_to_mc_idx(struct pci_dev *pdev)
669{
670 int node = dev_to_node(&pdev->dev);
671 int ret = PCI_FUNC(pdev->devfn);
672
3d2d8c0f 673 ret += max(node, 0) << 3;
41003396
ST		 674
675 return ret;
676}
677
678static int thunderx_lmc_probe(struct pci_dev *pdev,
679 const struct pci_device_id *id)
680{
681 struct thunderx_lmc *lmc;
682 struct edac_mc_layer layer;
683 struct mem_ctl_info *mci;
684 u64 lmc_control, lmc_ddr_pll_ctl, lmc_config;
685 int ret;
686 u64 lmc_int;
687 void *l2c_ioaddr;
688
689 layer.type = EDAC_MC_LAYER_SLOT;
690 layer.size = 2;
691 layer.is_virt_csrow = false;
692
693 ret = pcim_enable_device(pdev);
694 if (ret) {
695 dev_err(&pdev->dev, "Cannot enable PCI device: %d\n", ret);
696 return ret;
697 }
698
699 ret = pcim_iomap_regions(pdev, BIT(0), "thunderx_lmc");
700 if (ret) {
701 dev_err(&pdev->dev, "Cannot map PCI resources: %d\n", ret);
702 return ret;
703 }
704
705 mci = edac_mc_alloc(pci_dev_to_mc_idx(pdev), 1, &layer,
706 sizeof(struct thunderx_lmc));
707 if (!mci)
708 return -ENOMEM;
709
710 mci->pdev = &pdev->dev;
711 lmc = mci->pvt_info;
712
713 pci_set_drvdata(pdev, mci);
714
715 lmc->regs = pcim_iomap_table(pdev)[0];
716
717 lmc_control = readq(lmc->regs + LMC_CONTROL);
718 lmc_ddr_pll_ctl = readq(lmc->regs + LMC_DDR_PLL_CTL);
719 lmc_config = readq(lmc->regs + LMC_CONFIG);
720
721 if (lmc_control & LMC_CONTROL_RDIMM) {
722 mci->mtype_cap = FIELD_GET(LMC_DDR_PLL_CTL_DDR4,
723 lmc_ddr_pll_ctl) ?
724 MEM_RDDR4 : MEM_RDDR3;
725 } else {
726 mci->mtype_cap = FIELD_GET(LMC_DDR_PLL_CTL_DDR4,
727 lmc_ddr_pll_ctl) ?
728 MEM_DDR4 : MEM_DDR3;
729 }
730
731 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
732 mci->edac_cap = EDAC_FLAG_SECDED;
733
734 mci->mod_name = "thunderx-lmc";
41003396
ST		 735 mci->ctl_name = "thunderx-lmc";
736 mci->dev_name = dev_name(&pdev->dev);
737 mci->scrub_mode = SCRUB_NONE;
738
739 lmc->pdev = pdev;
740 lmc->msix_ent.entry = 0;
741
742 lmc->ring_head = 0;
743 lmc->ring_tail = 0;
744
745 ret = pci_enable_msix_exact(pdev, &lmc->msix_ent, 1);
746 if (ret) {
747 dev_err(&pdev->dev, "Cannot enable interrupt: %d\n", ret);
748 goto err_free;
749 }
750
751 ret = devm_request_threaded_irq(&pdev->dev, lmc->msix_ent.vector,
752 thunderx_lmc_err_isr,
753 thunderx_lmc_threaded_isr, 0,
754 "[EDAC] ThunderX LMC", mci);
755 if (ret) {
756 dev_err(&pdev->dev, "Cannot set ISR: %d\n", ret);
757 goto err_free;
758 }
759
760 lmc->node = FIELD_GET(THUNDERX_NODE, pci_resource_start(pdev, 0));
761
762 lmc->xbits = thunderx_get_num_lmcs(lmc->node) >> 1;
763 lmc->bank_width = (FIELD_GET(LMC_DDR_PLL_CTL_DDR4, lmc_ddr_pll_ctl) &&
764 FIELD_GET(LMC_CONFIG_BG2, lmc_config)) ? 4 : 3;
765
766 lmc->pbank_lsb = (lmc_config >> 5) & 0xf;
767 lmc->dimm_lsb = 28 + lmc->pbank_lsb + lmc->xbits;
768 lmc->rank_lsb = lmc->dimm_lsb;
769 lmc->rank_lsb -= FIELD_GET(LMC_CONFIG_RANK_ENA, lmc_config) ? 1 : 0;
770 lmc->bank_lsb = 7 + lmc->xbits;
771 lmc->row_lsb = 14 + LMC_CONFIG_ROW_LSB(lmc_config) + lmc->xbits;
772
773 lmc->col_hi_lsb = lmc->bank_lsb + lmc->bank_width;
774
775 lmc->xor_bank = lmc_control & LMC_CONTROL_XOR_BANK;
776
777 l2c_ioaddr = ioremap(L2C_CTL | FIELD_PREP(THUNDERX_NODE, lmc->node),
778 PAGE_SIZE);
779
780 if (!l2c_ioaddr) {
781 dev_err(&pdev->dev, "Cannot map L2C_CTL\n");
782 goto err_free;
783 }
784
785 lmc->l2c_alias = !(readq(l2c_ioaddr) & L2C_CTL_DISIDXALIAS);
786
787 iounmap(l2c_ioaddr);
788
789 ret = edac_mc_add_mc(mci);
790 if (ret) {
791 dev_err(&pdev->dev, "Cannot add the MC: %d\n", ret);
792 goto err_free;
793 }
794
795 lmc_int = readq(lmc->regs + LMC_INT);
796 writeq(lmc_int, lmc->regs + LMC_INT);
797
798 writeq(LMC_INT_ENA_ALL, lmc->regs + LMC_INT_ENA_W1S);
799
800 if (IS_ENABLED(CONFIG_EDAC_DEBUG)) {
801 ret = thunderx_create_debugfs_nodes(mci->debugfs,
802 lmc_dfs_ents,
803 lmc,
804 ARRAY_SIZE(lmc_dfs_ents));
805
806 if (ret != ARRAY_SIZE(lmc_dfs_ents)) {
807 dev_warn(&pdev->dev, "Error creating debugfs entries: %d%s\n",
808 ret, ret >= 0 ? " created" : "");
809 }
810 }
811
812 return 0;
813
814err_free:
815 pci_set_drvdata(pdev, NULL);
816 edac_mc_free(mci);
817
818 return ret;
819}
820
821static void thunderx_lmc_remove(struct pci_dev *pdev)
822{
823 struct mem_ctl_info *mci = pci_get_drvdata(pdev);
824 struct thunderx_lmc *lmc = mci->pvt_info;
825
826 writeq(LMC_INT_ENA_ALL, lmc->regs + LMC_INT_ENA_W1C);
827
828 edac_mc_del_mc(&pdev->dev);
829 edac_mc_free(mci);
830}
831
832MODULE_DEVICE_TABLE(pci, thunderx_lmc_pci_tbl);
833
834static struct pci_driver thunderx_lmc_driver = {
835 .name = "thunderx_lmc_edac",
836 .probe = thunderx_lmc_probe,
837 .remove = thunderx_lmc_remove,
838#ifdef CONFIG_PM
839 .suspend = thunderx_lmc_suspend,
840 .resume = thunderx_lmc_resume,
841#endif
842 .id_table = thunderx_lmc_pci_tbl,
843};
844
845/*---------------------- OCX driver ---------------------------------*/
846
847#define PCI_DEVICE_ID_THUNDER_OCX 0xa013
848
849#define OCX_LINK_INTS 3
850#define OCX_INTS (OCX_LINK_INTS + 1)
851#define OCX_RX_LANES 24
852#define OCX_RX_LANE_STATS 15
853
854#define OCX_COM_INT 0x100
855#define OCX_COM_INT_W1S 0x108
856#define OCX_COM_INT_ENA_W1S 0x110
857#define OCX_COM_INT_ENA_W1C 0x118
858
859#define OCX_COM_IO_BADID BIT(54)
860#define OCX_COM_MEM_BADID BIT(53)
861#define OCX_COM_COPR_BADID BIT(52)
862#define OCX_COM_WIN_REQ_BADID BIT(51)
863#define OCX_COM_WIN_REQ_TOUT BIT(50)
864#define OCX_COM_RX_LANE GENMASK(23, 0)
865
41003396
ST		 866#define OCX_COM_INT_CE (OCX_COM_IO_BADID | \
867 OCX_COM_MEM_BADID | \
868 OCX_COM_COPR_BADID | \
869 OCX_COM_WIN_REQ_BADID | \
870 OCX_COM_WIN_REQ_TOUT)
871
872static const struct error_descr ocx_com_errors[] = {
873 {
874 .type = ERR_CORRECTED,
875 .mask = OCX_COM_IO_BADID,
876 .descr = "Invalid IO transaction node ID",
877 },
878 {
879 .type = ERR_CORRECTED,
880 .mask = OCX_COM_MEM_BADID,
881 .descr = "Invalid memory transaction node ID",
882 },
883 {
884 .type = ERR_CORRECTED,
885 .mask = OCX_COM_COPR_BADID,
886 .descr = "Invalid coprocessor transaction node ID",
887 },
888 {
889 .type = ERR_CORRECTED,
890 .mask = OCX_COM_WIN_REQ_BADID,
891 .descr = "Invalid SLI transaction node ID",
892 },
893 {
894 .type = ERR_CORRECTED,
895 .mask = OCX_COM_WIN_REQ_TOUT,
896 .descr = "Window/core request timeout",
897 },
898 {0, 0, NULL},
899};
900
901#define OCX_COM_LINKX_INT(x) (0x120 + (x) * 8)
902#define OCX_COM_LINKX_INT_W1S(x) (0x140 + (x) * 8)
903#define OCX_COM_LINKX_INT_ENA_W1S(x) (0x160 + (x) * 8)
904#define OCX_COM_LINKX_INT_ENA_W1C(x) (0x180 + (x) * 8)
905
906#define OCX_COM_LINK_BAD_WORD BIT(13)
907#define OCX_COM_LINK_ALIGN_FAIL BIT(12)
908#define OCX_COM_LINK_ALIGN_DONE BIT(11)
909#define OCX_COM_LINK_UP BIT(10)
910#define OCX_COM_LINK_STOP BIT(9)
911#define OCX_COM_LINK_BLK_ERR BIT(8)
912#define OCX_COM_LINK_REINIT BIT(7)
913#define OCX_COM_LINK_LNK_DATA BIT(6)
914#define OCX_COM_LINK_RXFIFO_DBE BIT(5)
915#define OCX_COM_LINK_RXFIFO_SBE BIT(4)
916#define OCX_COM_LINK_TXFIFO_DBE BIT(3)
917#define OCX_COM_LINK_TXFIFO_SBE BIT(2)
918#define OCX_COM_LINK_REPLAY_DBE BIT(1)
919#define OCX_COM_LINK_REPLAY_SBE BIT(0)
920
921static const struct error_descr ocx_com_link_errors[] = {
922 {
923 .type = ERR_CORRECTED,
924 .mask = OCX_COM_LINK_REPLAY_SBE,
925 .descr = "Replay buffer single-bit error",
926 },
927 {
928 .type = ERR_CORRECTED,
929 .mask = OCX_COM_LINK_TXFIFO_SBE,
930 .descr = "TX FIFO single-bit error",
931 },
932 {
933 .type = ERR_CORRECTED,
934 .mask = OCX_COM_LINK_RXFIFO_SBE,
935 .descr = "RX FIFO single-bit error",
936 },
937 {
938 .type = ERR_CORRECTED,
939 .mask = OCX_COM_LINK_BLK_ERR,
940 .descr = "Block code error",
941 },
942 {
943 .type = ERR_CORRECTED,
944 .mask = OCX_COM_LINK_ALIGN_FAIL,
945 .descr = "Link alignment failure",
946 },
947 {
948 .type = ERR_CORRECTED,
949 .mask = OCX_COM_LINK_BAD_WORD,
950 .descr = "Bad code word",
951 },
952 {
953 .type = ERR_UNCORRECTED,
954 .mask = OCX_COM_LINK_REPLAY_DBE,
955 .descr = "Replay buffer double-bit error",
956 },
957 {
958 .type = ERR_UNCORRECTED,
959 .mask = OCX_COM_LINK_TXFIFO_DBE,
960 .descr = "TX FIFO double-bit error",
961 },
962 {
963 .type = ERR_UNCORRECTED,
964 .mask = OCX_COM_LINK_RXFIFO_DBE,
965 .descr = "RX FIFO double-bit error",
966 },
967 {
968 .type = ERR_UNCORRECTED,
969 .mask = OCX_COM_LINK_STOP,
970 .descr = "Link stopped",
971 },
972 {0, 0, NULL},
973};
974
975#define OCX_COM_LINK_INT_UE (OCX_COM_LINK_REPLAY_DBE | \
976 OCX_COM_LINK_TXFIFO_DBE | \
977 OCX_COM_LINK_RXFIFO_DBE | \
978 OCX_COM_LINK_STOP)
979
980#define OCX_COM_LINK_INT_CE (OCX_COM_LINK_REPLAY_SBE | \
981 OCX_COM_LINK_TXFIFO_SBE | \
982 OCX_COM_LINK_RXFIFO_SBE | \
983 OCX_COM_LINK_BLK_ERR | \
984 OCX_COM_LINK_ALIGN_FAIL | \
985 OCX_COM_LINK_BAD_WORD)
986
987#define OCX_LNE_INT(x) (0x8018 + (x) * 0x100)
988#define OCX_LNE_INT_EN(x) (0x8020 + (x) * 0x100)
989#define OCX_LNE_BAD_CNT(x) (0x8028 + (x) * 0x100)
990#define OCX_LNE_CFG(x) (0x8000 + (x) * 0x100)
991#define OCX_LNE_STAT(x, y) (0x8040 + (x) * 0x100 + (y) * 8)
992
993#define OCX_LNE_CFG_RX_BDRY_LOCK_DIS BIT(8)
994#define OCX_LNE_CFG_RX_STAT_WRAP_DIS BIT(2)
995#define OCX_LNE_CFG_RX_STAT_RDCLR BIT(1)
996#define OCX_LNE_CFG_RX_STAT_ENA BIT(0)
997
998
999#define OCX_LANE_BAD_64B67B BIT(8)
1000#define OCX_LANE_DSKEW_FIFO_OVFL BIT(5)
1001#define OCX_LANE_SCRM_SYNC_LOSS BIT(4)
1002#define OCX_LANE_UKWN_CNTL_WORD BIT(3)
1003#define OCX_LANE_CRC32_ERR BIT(2)
1004#define OCX_LANE_BDRY_SYNC_LOSS BIT(1)
1005#define OCX_LANE_SERDES_LOCK_LOSS BIT(0)
1006
1007#define OCX_COM_LANE_INT_UE (0)
1008#define OCX_COM_LANE_INT_CE (OCX_LANE_SERDES_LOCK_LOSS | \
1009 OCX_LANE_BDRY_SYNC_LOSS | \
1010 OCX_LANE_CRC32_ERR | \
1011 OCX_LANE_UKWN_CNTL_WORD | \
1012 OCX_LANE_SCRM_SYNC_LOSS | \
1013 OCX_LANE_DSKEW_FIFO_OVFL | \
1014 OCX_LANE_BAD_64B67B)
1015
1016static const struct error_descr ocx_lane_errors[] = {
1017 {
1018 .type = ERR_CORRECTED,
1019 .mask = OCX_LANE_SERDES_LOCK_LOSS,
1020 .descr = "RX SerDes lock lost",
1021 },
1022 {
1023 .type = ERR_CORRECTED,
1024 .mask = OCX_LANE_BDRY_SYNC_LOSS,
1025 .descr = "RX word boundary lost",
1026 },
1027 {
1028 .type = ERR_CORRECTED,
1029 .mask = OCX_LANE_CRC32_ERR,
1030 .descr = "CRC32 error",
1031 },
1032 {
1033 .type = ERR_CORRECTED,
1034 .mask = OCX_LANE_UKWN_CNTL_WORD,
1035 .descr = "Unknown control word",
1036 },
1037 {
1038 .type = ERR_CORRECTED,
1039 .mask = OCX_LANE_SCRM_SYNC_LOSS,
1040 .descr = "Scrambler synchronization lost",
1041 },
1042 {
1043 .type = ERR_CORRECTED,
1044 .mask = OCX_LANE_DSKEW_FIFO_OVFL,
1045 .descr = "RX deskew FIFO overflow",
1046 },
1047 {
1048 .type = ERR_CORRECTED,
1049 .mask = OCX_LANE_BAD_64B67B,
1050 .descr = "Bad 64B/67B codeword",
1051 },
1052 {0, 0, NULL},
1053};
1054
1055#define OCX_LNE_INT_ENA_ALL (GENMASK(9, 8) | GENMASK(6, 0))
1056#define OCX_COM_INT_ENA_ALL (GENMASK(54, 50) | GENMASK(23, 0))
1057#define OCX_COM_LINKX_INT_ENA_ALL (GENMASK(13, 12) | \
1058 GENMASK(9, 7) | GENMASK(5, 0))
1059
1060#define OCX_TLKX_ECC_CTL(x) (0x10018 + (x) * 0x2000)
1061#define OCX_RLKX_ECC_CTL(x) (0x18018 + (x) * 0x2000)
1062
1063struct ocx_com_err_ctx {
1064 u64 reg_com_int;
1065 u64 reg_lane_int[OCX_RX_LANES];
1066 u64 reg_lane_stat11[OCX_RX_LANES];
1067};
1068
1069struct ocx_link_err_ctx {
1070 u64 reg_com_link_int;
1071 int link;
1072};
1073
1074struct thunderx_ocx {
1075 void __iomem *regs;
1076 int com_link;
1077 struct pci_dev *pdev;
1078 struct edac_device_ctl_info *edac_dev;
1079
1080 struct dentry *debugfs;
1081 struct msix_entry msix_ent[OCX_INTS];
1082
1083 struct ocx_com_err_ctx com_err_ctx[RING_ENTRIES];
1084 struct ocx_link_err_ctx link_err_ctx[RING_ENTRIES];
1085
1086 unsigned long com_ring_head;
1087 unsigned long com_ring_tail;
1088
1089 unsigned long link_ring_head;
1090 unsigned long link_ring_tail;
1091};
1092
1093#define OCX_MESSAGE_SIZE SZ_1K
1094#define OCX_OTHER_SIZE (50 * ARRAY_SIZE(ocx_com_link_errors))
1095
1096/* This handler is threaded */
1097static irqreturn_t thunderx_ocx_com_isr(int irq, void *irq_id)
1098{
1099 struct msix_entry *msix = irq_id;
1100 struct thunderx_ocx *ocx = container_of(msix, struct thunderx_ocx,
1101 msix_ent[msix->entry]);
1102
1103 int lane;
1104 unsigned long head = ring_pos(ocx->com_ring_head,
1105 ARRAY_SIZE(ocx->com_err_ctx));
1106 struct ocx_com_err_ctx *ctx = &ocx->com_err_ctx[head];
1107
1108 ctx->reg_com_int = readq(ocx->regs + OCX_COM_INT);
1109
1110 for (lane = 0; lane < OCX_RX_LANES; lane++) {
1111 ctx->reg_lane_int[lane] =
1112 readq(ocx->regs + OCX_LNE_INT(lane));
1113 ctx->reg_lane_stat11[lane] =
1114 readq(ocx->regs + OCX_LNE_STAT(lane, 11));
1115
1116 writeq(ctx->reg_lane_int[lane], ocx->regs + OCX_LNE_INT(lane));
1117 }
1118
1119 writeq(ctx->reg_com_int, ocx->regs + OCX_COM_INT);
1120
1121 ocx->com_ring_head++;
1122
1123 return IRQ_WAKE_THREAD;
1124}
1125
1126static irqreturn_t thunderx_ocx_com_threaded_isr(int irq, void *irq_id)
1127{
1128 struct msix_entry *msix = irq_id;
1129 struct thunderx_ocx *ocx = container_of(msix, struct thunderx_ocx,
1130 msix_ent[msix->entry]);
1131
1132 irqreturn_t ret = IRQ_NONE;
1133
1134 unsigned long tail;
1135 struct ocx_com_err_ctx *ctx;
1136 int lane;
1137 char *msg;
1138 char *other;
1139
1140 msg = kmalloc(OCX_MESSAGE_SIZE, GFP_KERNEL);
1141 other = kmalloc(OCX_OTHER_SIZE, GFP_KERNEL);
1142
1143 if (!msg || !other)
1144 goto err_free;
1145
1146 while (CIRC_CNT(ocx->com_ring_head, ocx->com_ring_tail,
1147 ARRAY_SIZE(ocx->com_err_ctx))) {
1148 tail = ring_pos(ocx->com_ring_tail,
1149 ARRAY_SIZE(ocx->com_err_ctx));
1150 ctx = &ocx->com_err_ctx[tail];
1151
1152 snprintf(msg, OCX_MESSAGE_SIZE, "%s: OCX_COM_INT: %016llx",
1153 ocx->edac_dev->ctl_name, ctx->reg_com_int);
1154
1155 decode_register(other, OCX_OTHER_SIZE,
1156 ocx_com_errors, ctx->reg_com_int);
1157
1158 strncat(msg, other, OCX_MESSAGE_SIZE);
1159
1160 for (lane = 0; lane < OCX_RX_LANES; lane++)
1161 if (ctx->reg_com_int & BIT(lane)) {
1162 snprintf(other, OCX_OTHER_SIZE,
1163 "\n\tOCX_LNE_INT[%02d]: %016llx OCX_LNE_STAT11[%02d]: %016llx",
1164 lane, ctx->reg_lane_int[lane],
1165 lane, ctx->reg_lane_stat11[lane]);
1166
1167 strncat(msg, other, OCX_MESSAGE_SIZE);
1168
1169 decode_register(other, OCX_OTHER_SIZE,
1170 ocx_lane_errors,
1171 ctx->reg_lane_int[lane]);
1172 strncat(msg, other, OCX_MESSAGE_SIZE);
1173 }
1174
5195c206 1175 if (ctx->reg_com_int & OCX_COM_INT_CE)
41003396
ST		 1176 edac_device_handle_ce(ocx->edac_dev, 0, 0, msg);
1177
1178 ocx->com_ring_tail++;
1179 }
1180
1181 ret = IRQ_HANDLED;
1182
1183err_free:
1184 kfree(other);
1185 kfree(msg);
1186
1187 return ret;
1188}
1189
1190static irqreturn_t thunderx_ocx_lnk_isr(int irq, void *irq_id)
1191{
1192 struct msix_entry *msix = irq_id;
1193 struct thunderx_ocx *ocx = container_of(msix, struct thunderx_ocx,
1194 msix_ent[msix->entry]);
1195 unsigned long head = ring_pos(ocx->link_ring_head,
1196 ARRAY_SIZE(ocx->link_err_ctx));
1197 struct ocx_link_err_ctx *ctx = &ocx->link_err_ctx[head];
1198
1199 ctx->link = msix->entry;
1200 ctx->reg_com_link_int = readq(ocx->regs + OCX_COM_LINKX_INT(ctx->link));
1201
1202 writeq(ctx->reg_com_link_int, ocx->regs + OCX_COM_LINKX_INT(ctx->link));
1203
1204 ocx->link_ring_head++;
1205
1206 return IRQ_WAKE_THREAD;
1207}
1208
1209static irqreturn_t thunderx_ocx_lnk_threaded_isr(int irq, void *irq_id)
1210{
1211 struct msix_entry *msix = irq_id;
1212 struct thunderx_ocx *ocx = container_of(msix, struct thunderx_ocx,
1213 msix_ent[msix->entry]);
1214 irqreturn_t ret = IRQ_NONE;
1215 unsigned long tail;
1216 struct ocx_link_err_ctx *ctx;
1217
1218 char *msg;
1219 char *other;
1220
1221 msg = kmalloc(OCX_MESSAGE_SIZE, GFP_KERNEL);
1222 other = kmalloc(OCX_OTHER_SIZE, GFP_KERNEL);
1223
1224 if (!msg || !other)
1225 goto err_free;
1226
1227 while (CIRC_CNT(ocx->link_ring_head, ocx->link_ring_tail,
1228 ARRAY_SIZE(ocx->link_err_ctx))) {
1229 tail = ring_pos(ocx->link_ring_head,
1230 ARRAY_SIZE(ocx->link_err_ctx));
1231
1232 ctx = &ocx->link_err_ctx[tail];
1233
1234 snprintf(msg, OCX_MESSAGE_SIZE,
1235 "%s: OCX_COM_LINK_INT[%d]: %016llx",
1236 ocx->edac_dev->ctl_name,
1237 ctx->link, ctx->reg_com_link_int);
1238
1239 decode_register(other, OCX_OTHER_SIZE,
1240 ocx_com_link_errors, ctx->reg_com_link_int);
1241
1242 strncat(msg, other, OCX_MESSAGE_SIZE);
1243
1244 if (ctx->reg_com_link_int & OCX_COM_LINK_INT_UE)
1245 edac_device_handle_ue(ocx->edac_dev, 0, 0, msg);
1246 else if (ctx->reg_com_link_int & OCX_COM_LINK_INT_CE)
1247 edac_device_handle_ce(ocx->edac_dev, 0, 0, msg);
1248
1249 ocx->link_ring_tail++;
1250 }
1251
1252 ret = IRQ_HANDLED;
1253err_free:
1254 kfree(other);
1255 kfree(msg);
1256
1257 return ret;
1258}
1259
1260#define OCX_DEBUGFS_ATTR(_name, _reg) DEBUGFS_REG_ATTR(ocx, _name, _reg)
1261
1262OCX_DEBUGFS_ATTR(tlk0_ecc_ctl, OCX_TLKX_ECC_CTL(0));
1263OCX_DEBUGFS_ATTR(tlk1_ecc_ctl, OCX_TLKX_ECC_CTL(1));
1264OCX_DEBUGFS_ATTR(tlk2_ecc_ctl, OCX_TLKX_ECC_CTL(2));
1265
1266OCX_DEBUGFS_ATTR(rlk0_ecc_ctl, OCX_RLKX_ECC_CTL(0));
1267OCX_DEBUGFS_ATTR(rlk1_ecc_ctl, OCX_RLKX_ECC_CTL(1));
1268OCX_DEBUGFS_ATTR(rlk2_ecc_ctl, OCX_RLKX_ECC_CTL(2));
1269
1270OCX_DEBUGFS_ATTR(com_link0_int, OCX_COM_LINKX_INT_W1S(0));
1271OCX_DEBUGFS_ATTR(com_link1_int, OCX_COM_LINKX_INT_W1S(1));
1272OCX_DEBUGFS_ATTR(com_link2_int, OCX_COM_LINKX_INT_W1S(2));
1273
1274OCX_DEBUGFS_ATTR(lne00_badcnt, OCX_LNE_BAD_CNT(0));
1275OCX_DEBUGFS_ATTR(lne01_badcnt, OCX_LNE_BAD_CNT(1));
1276OCX_DEBUGFS_ATTR(lne02_badcnt, OCX_LNE_BAD_CNT(2));
1277OCX_DEBUGFS_ATTR(lne03_badcnt, OCX_LNE_BAD_CNT(3));
1278OCX_DEBUGFS_ATTR(lne04_badcnt, OCX_LNE_BAD_CNT(4));
1279OCX_DEBUGFS_ATTR(lne05_badcnt, OCX_LNE_BAD_CNT(5));
1280OCX_DEBUGFS_ATTR(lne06_badcnt, OCX_LNE_BAD_CNT(6));
1281OCX_DEBUGFS_ATTR(lne07_badcnt, OCX_LNE_BAD_CNT(7));
1282
1283OCX_DEBUGFS_ATTR(lne08_badcnt, OCX_LNE_BAD_CNT(8));
1284OCX_DEBUGFS_ATTR(lne09_badcnt, OCX_LNE_BAD_CNT(9));
1285OCX_DEBUGFS_ATTR(lne10_badcnt, OCX_LNE_BAD_CNT(10));
1286OCX_DEBUGFS_ATTR(lne11_badcnt, OCX_LNE_BAD_CNT(11));
1287OCX_DEBUGFS_ATTR(lne12_badcnt, OCX_LNE_BAD_CNT(12));
1288OCX_DEBUGFS_ATTR(lne13_badcnt, OCX_LNE_BAD_CNT(13));
1289OCX_DEBUGFS_ATTR(lne14_badcnt, OCX_LNE_BAD_CNT(14));
1290OCX_DEBUGFS_ATTR(lne15_badcnt, OCX_LNE_BAD_CNT(15));
1291
1292OCX_DEBUGFS_ATTR(lne16_badcnt, OCX_LNE_BAD_CNT(16));
1293OCX_DEBUGFS_ATTR(lne17_badcnt, OCX_LNE_BAD_CNT(17));
1294OCX_DEBUGFS_ATTR(lne18_badcnt, OCX_LNE_BAD_CNT(18));
1295OCX_DEBUGFS_ATTR(lne19_badcnt, OCX_LNE_BAD_CNT(19));
1296OCX_DEBUGFS_ATTR(lne20_badcnt, OCX_LNE_BAD_CNT(20));
1297OCX_DEBUGFS_ATTR(lne21_badcnt, OCX_LNE_BAD_CNT(21));
1298OCX_DEBUGFS_ATTR(lne22_badcnt, OCX_LNE_BAD_CNT(22));
1299OCX_DEBUGFS_ATTR(lne23_badcnt, OCX_LNE_BAD_CNT(23));
1300
1301OCX_DEBUGFS_ATTR(com_int, OCX_COM_INT_W1S);
1302
1303struct debugfs_entry *ocx_dfs_ents[] = {
1304 &debugfs_tlk0_ecc_ctl,
1305 &debugfs_tlk1_ecc_ctl,
1306 &debugfs_tlk2_ecc_ctl,
1307
1308 &debugfs_rlk0_ecc_ctl,
1309 &debugfs_rlk1_ecc_ctl,
1310 &debugfs_rlk2_ecc_ctl,
1311
1312 &debugfs_com_link0_int,
1313 &debugfs_com_link1_int,
1314 &debugfs_com_link2_int,
1315
1316 &debugfs_lne00_badcnt,
1317 &debugfs_lne01_badcnt,
1318 &debugfs_lne02_badcnt,
1319 &debugfs_lne03_badcnt,
1320 &debugfs_lne04_badcnt,
1321 &debugfs_lne05_badcnt,
1322 &debugfs_lne06_badcnt,
1323 &debugfs_lne07_badcnt,
1324 &debugfs_lne08_badcnt,
1325 &debugfs_lne09_badcnt,
1326 &debugfs_lne10_badcnt,
1327 &debugfs_lne11_badcnt,
1328 &debugfs_lne12_badcnt,
1329 &debugfs_lne13_badcnt,
1330 &debugfs_lne14_badcnt,
1331 &debugfs_lne15_badcnt,
1332 &debugfs_lne16_badcnt,
1333 &debugfs_lne17_badcnt,
1334 &debugfs_lne18_badcnt,
1335 &debugfs_lne19_badcnt,
1336 &debugfs_lne20_badcnt,
1337 &debugfs_lne21_badcnt,
1338 &debugfs_lne22_badcnt,
1339 &debugfs_lne23_badcnt,
1340
1341 &debugfs_com_int,
1342};
1343
1344static const struct pci_device_id thunderx_ocx_pci_tbl[] = {
1345 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVICE_ID_THUNDER_OCX) },
1346 { 0, },
1347};
1348
1349static void thunderx_ocx_clearstats(struct thunderx_ocx *ocx)
1350{
1351 int lane, stat, cfg;
1352
1353 for (lane = 0; lane < OCX_RX_LANES; lane++) {
1354 cfg = readq(ocx->regs + OCX_LNE_CFG(lane));
1355 cfg |= OCX_LNE_CFG_RX_STAT_RDCLR;
1356 cfg &= ~OCX_LNE_CFG_RX_STAT_ENA;
1357 writeq(cfg, ocx->regs + OCX_LNE_CFG(lane));
1358
1359 for (stat = 0; stat < OCX_RX_LANE_STATS; stat++)
1360 readq(ocx->regs + OCX_LNE_STAT(lane, stat));
1361 }
1362}
1363
1364static int thunderx_ocx_probe(struct pci_dev *pdev,
1365 const struct pci_device_id *id)
1366{
1367 struct thunderx_ocx *ocx;
1368 struct edac_device_ctl_info *edac_dev;
1369 char name[32];
1370 int idx;
1371 int i;
1372 int ret;
1373 u64 reg;
1374
1375 ret = pcim_enable_device(pdev);
1376 if (ret) {
1377 dev_err(&pdev->dev, "Cannot enable PCI device: %d\n", ret);
1378 return ret;
1379 }
1380
1381 ret = pcim_iomap_regions(pdev, BIT(0), "thunderx_ocx");
1382 if (ret) {
1383 dev_err(&pdev->dev, "Cannot map PCI resources: %d\n", ret);
1384 return ret;
1385 }
1386
1387 idx = edac_device_alloc_index();
1388 snprintf(name, sizeof(name), "OCX%d", idx);
1389 edac_dev = edac_device_alloc_ctl_info(sizeof(struct thunderx_ocx),
1390 name, 1, "CCPI", 1,
1391 0, NULL, 0, idx);
1392 if (!edac_dev) {
1393 dev_err(&pdev->dev, "Cannot allocate EDAC device: %d\n", ret);
1394 return -ENOMEM;
1395 }
1396 ocx = edac_dev->pvt_info;
1397 ocx->edac_dev = edac_dev;
1398 ocx->com_ring_head = 0;
1399 ocx->com_ring_tail = 0;
1400 ocx->link_ring_head = 0;
1401 ocx->link_ring_tail = 0;
1402
1403 ocx->regs = pcim_iomap_table(pdev)[0];
1404 if (!ocx->regs) {
1405 dev_err(&pdev->dev, "Cannot map PCI resources: %d\n", ret);
1406 ret = -ENODEV;
1407 goto err_free;
1408 }
1409
1410 ocx->pdev = pdev;
1411
1412 for (i = 0; i < OCX_INTS; i++) {
1413 ocx->msix_ent[i].entry = i;
1414 ocx->msix_ent[i].vector = 0;
1415 }
1416
1417 ret = pci_enable_msix_exact(pdev, ocx->msix_ent, OCX_INTS);
1418 if (ret) {
1419 dev_err(&pdev->dev, "Cannot enable interrupt: %d\n", ret);
1420 goto err_free;
1421 }
1422
1423 for (i = 0; i < OCX_INTS; i++) {
1424 ret = devm_request_threaded_irq(&pdev->dev,
1425 ocx->msix_ent[i].vector,
1426 (i == 3) ?
1427 thunderx_ocx_com_isr :
1428 thunderx_ocx_lnk_isr,
1429 (i == 3) ?
1430 thunderx_ocx_com_threaded_isr :
1431 thunderx_ocx_lnk_threaded_isr,
1432 0, "[EDAC] ThunderX OCX",
1433 &ocx->msix_ent[i]);
1434 if (ret)
1435 goto err_free;
1436 }
1437
1438 edac_dev->dev = &pdev->dev;
1439 edac_dev->dev_name = dev_name(&pdev->dev);
1440 edac_dev->mod_name = "thunderx-ocx";
1441 edac_dev->ctl_name = "thunderx-ocx";
1442
1443 ret = edac_device_add_device(edac_dev);
1444 if (ret) {
1445 dev_err(&pdev->dev, "Cannot add EDAC device: %d\n", ret);
1446 goto err_free;
1447 }
1448
1449 if (IS_ENABLED(CONFIG_EDAC_DEBUG)) {
1450 ocx->debugfs = edac_debugfs_create_dir(pdev->dev.kobj.name);
1451
1452 ret = thunderx_create_debugfs_nodes(ocx->debugfs,
1453 ocx_dfs_ents,
1454 ocx,
1455 ARRAY_SIZE(ocx_dfs_ents));
1456 if (ret != ARRAY_SIZE(ocx_dfs_ents)) {
1457 dev_warn(&pdev->dev, "Error creating debugfs entries: %d%s\n",
1458 ret, ret >= 0 ? " created" : "");
1459 }
1460 }
1461
1462 pci_set_drvdata(pdev, edac_dev);
1463
1464 thunderx_ocx_clearstats(ocx);
1465
1466 for (i = 0; i < OCX_RX_LANES; i++) {
1467 writeq(OCX_LNE_INT_ENA_ALL,
1468 ocx->regs + OCX_LNE_INT_EN(i));
1469
1470 reg = readq(ocx->regs + OCX_LNE_INT(i));
1471 writeq(reg, ocx->regs + OCX_LNE_INT(i));
1472
1473 }
1474
1475 for (i = 0; i < OCX_LINK_INTS; i++) {
1476 reg = readq(ocx->regs + OCX_COM_LINKX_INT(i));
1477 writeq(reg, ocx->regs + OCX_COM_LINKX_INT(i));
1478
1479 writeq(OCX_COM_LINKX_INT_ENA_ALL,
1480 ocx->regs + OCX_COM_LINKX_INT_ENA_W1S(i));
1481 }
1482
1483 reg = readq(ocx->regs + OCX_COM_INT);
1484 writeq(reg, ocx->regs + OCX_COM_INT);
1485
1486 writeq(OCX_COM_INT_ENA_ALL, ocx->regs + OCX_COM_INT_ENA_W1S);
1487
1488 return 0;
1489err_free:
1490 edac_device_free_ctl_info(edac_dev);
1491
1492 return ret;
1493}
1494
1495static void thunderx_ocx_remove(struct pci_dev *pdev)
1496{
1497 struct edac_device_ctl_info *edac_dev = pci_get_drvdata(pdev);
1498 struct thunderx_ocx *ocx = edac_dev->pvt_info;
1499 int i;
1500
1501 writeq(OCX_COM_INT_ENA_ALL, ocx->regs + OCX_COM_INT_ENA_W1C);
1502
1503 for (i = 0; i < OCX_INTS; i++) {
1504 writeq(OCX_COM_LINKX_INT_ENA_ALL,
1505 ocx->regs + OCX_COM_LINKX_INT_ENA_W1C(i));
1506 }
1507
1508 edac_debugfs_remove_recursive(ocx->debugfs);
1509
1510 edac_device_del_device(&pdev->dev);
1511 edac_device_free_ctl_info(edac_dev);
1512}
1513
1514MODULE_DEVICE_TABLE(pci, thunderx_ocx_pci_tbl);
1515
1516static struct pci_driver thunderx_ocx_driver = {
1517 .name = "thunderx_ocx_edac",
1518 .probe = thunderx_ocx_probe,
1519 .remove = thunderx_ocx_remove,
1520 .id_table = thunderx_ocx_pci_tbl,
1521};
1522
1523/*---------------------- L2C driver ---------------------------------*/
1524
1525#define PCI_DEVICE_ID_THUNDER_L2C_TAD 0xa02e
1526#define PCI_DEVICE_ID_THUNDER_L2C_CBC 0xa02f
1527#define PCI_DEVICE_ID_THUNDER_L2C_MCI 0xa030
1528
1529#define L2C_TAD_INT_W1C 0x40000
1530#define L2C_TAD_INT_W1S 0x40008
1531
1532#define L2C_TAD_INT_ENA_W1C 0x40020
1533#define L2C_TAD_INT_ENA_W1S 0x40028
1534
1535
1536#define L2C_TAD_INT_L2DDBE BIT(1)
1537#define L2C_TAD_INT_SBFSBE BIT(2)
1538#define L2C_TAD_INT_SBFDBE BIT(3)
1539#define L2C_TAD_INT_FBFSBE BIT(4)
1540#define L2C_TAD_INT_FBFDBE BIT(5)
1541#define L2C_TAD_INT_TAGDBE BIT(9)
1542#define L2C_TAD_INT_RDDISLMC BIT(15)
1543#define L2C_TAD_INT_WRDISLMC BIT(16)
1544#define L2C_TAD_INT_LFBTO BIT(17)
1545#define L2C_TAD_INT_GSYNCTO BIT(18)
1546#define L2C_TAD_INT_RTGSBE BIT(32)
1547#define L2C_TAD_INT_RTGDBE BIT(33)
1548#define L2C_TAD_INT_RDDISOCI BIT(34)
1549#define L2C_TAD_INT_WRDISOCI BIT(35)
1550
1551#define L2C_TAD_INT_ECC (L2C_TAD_INT_L2DDBE | \
1552 L2C_TAD_INT_SBFSBE | L2C_TAD_INT_SBFDBE | \
1553 L2C_TAD_INT_FBFSBE | L2C_TAD_INT_FBFDBE)
1554
1555#define L2C_TAD_INT_CE (L2C_TAD_INT_SBFSBE | \
1556 L2C_TAD_INT_FBFSBE)
1557
1558#define L2C_TAD_INT_UE (L2C_TAD_INT_L2DDBE | \
1559 L2C_TAD_INT_SBFDBE | \
1560 L2C_TAD_INT_FBFDBE | \
1561 L2C_TAD_INT_TAGDBE | \
1562 L2C_TAD_INT_RTGDBE | \
1563 L2C_TAD_INT_WRDISOCI | \
1564 L2C_TAD_INT_RDDISOCI | \
1565 L2C_TAD_INT_WRDISLMC | \
1566 L2C_TAD_INT_RDDISLMC | \
1567 L2C_TAD_INT_LFBTO | \
1568 L2C_TAD_INT_GSYNCTO)
1569
1570static const struct error_descr l2_tad_errors[] = {
1571 {
1572 .type = ERR_CORRECTED,
1573 .mask = L2C_TAD_INT_SBFSBE,
1574 .descr = "SBF single-bit error",
1575 },
1576 {
1577 .type = ERR_CORRECTED,
1578 .mask = L2C_TAD_INT_FBFSBE,
1579 .descr = "FBF single-bit error",
1580 },
1581 {
1582 .type = ERR_UNCORRECTED,
1583 .mask = L2C_TAD_INT_L2DDBE,
1584 .descr = "L2D double-bit error",
1585 },
1586 {
1587 .type = ERR_UNCORRECTED,
1588 .mask = L2C_TAD_INT_SBFDBE,
1589 .descr = "SBF double-bit error",
1590 },
1591 {
1592 .type = ERR_UNCORRECTED,
1593 .mask = L2C_TAD_INT_FBFDBE,
1594 .descr = "FBF double-bit error",
1595 },
1596 {
1597 .type = ERR_UNCORRECTED,
1598 .mask = L2C_TAD_INT_TAGDBE,
1599 .descr = "TAG double-bit error",
1600 },
1601 {
1602 .type = ERR_UNCORRECTED,
1603 .mask = L2C_TAD_INT_RTGDBE,
1604 .descr = "RTG double-bit error",
1605 },
1606 {
1607 .type = ERR_UNCORRECTED,
1608 .mask = L2C_TAD_INT_WRDISOCI,
1609 .descr = "Write to a disabled CCPI",
1610 },
1611 {
1612 .type = ERR_UNCORRECTED,
1613 .mask = L2C_TAD_INT_RDDISOCI,
1614 .descr = "Read from a disabled CCPI",
1615 },
1616 {
1617 .type = ERR_UNCORRECTED,
1618 .mask = L2C_TAD_INT_WRDISLMC,
1619 .descr = "Write to a disabled LMC",
1620 },
1621 {
1622 .type = ERR_UNCORRECTED,
1623 .mask = L2C_TAD_INT_RDDISLMC,
1624 .descr = "Read from a disabled LMC",
1625 },
1626 {
1627 .type = ERR_UNCORRECTED,
1628 .mask = L2C_TAD_INT_LFBTO,
1629 .descr = "LFB entry timeout",
1630 },
1631 {
1632 .type = ERR_UNCORRECTED,
1633 .mask = L2C_TAD_INT_GSYNCTO,
1634 .descr = "Global sync CCPI timeout",
1635 },
1636 {0, 0, NULL},
1637};
1638
1639#define L2C_TAD_INT_TAG (L2C_TAD_INT_TAGDBE)
1640
1641#define L2C_TAD_INT_RTG (L2C_TAD_INT_RTGDBE)
1642
41003396
ST		 1643#define L2C_TAD_INT_DISLMC (L2C_TAD_INT_WRDISLMC | L2C_TAD_INT_RDDISLMC)
1644
1645#define L2C_TAD_INT_DISOCI (L2C_TAD_INT_WRDISOCI | L2C_TAD_INT_RDDISOCI)
1646
1647#define L2C_TAD_INT_ENA_ALL (L2C_TAD_INT_ECC | L2C_TAD_INT_TAG | \
5195c206 1648 L2C_TAD_INT_RTG | \
41003396
ST		 1649 L2C_TAD_INT_DISLMC | L2C_TAD_INT_DISOCI | \
1650 L2C_TAD_INT_LFBTO)
1651
1652#define L2C_TAD_TIMETWO 0x50000
1653#define L2C_TAD_TIMEOUT 0x50100
1654#define L2C_TAD_ERR 0x60000
1655#define L2C_TAD_TQD_ERR 0x60100
1656#define L2C_TAD_TTG_ERR 0x60200
1657
1658
1659#define L2C_CBC_INT_W1C 0x60000
1660
1661#define L2C_CBC_INT_RSDSBE BIT(0)
1662#define L2C_CBC_INT_RSDDBE BIT(1)
1663
1664#define L2C_CBC_INT_RSD (L2C_CBC_INT_RSDSBE | L2C_CBC_INT_RSDDBE)
1665
1666#define L2C_CBC_INT_MIBSBE BIT(4)
1667#define L2C_CBC_INT_MIBDBE BIT(5)
1668
1669#define L2C_CBC_INT_MIB (L2C_CBC_INT_MIBSBE | L2C_CBC_INT_MIBDBE)
1670
1671#define L2C_CBC_INT_IORDDISOCI BIT(6)
1672#define L2C_CBC_INT_IOWRDISOCI BIT(7)
1673
1674#define L2C_CBC_INT_IODISOCI (L2C_CBC_INT_IORDDISOCI | \
1675 L2C_CBC_INT_IOWRDISOCI)
1676
1677#define L2C_CBC_INT_CE (L2C_CBC_INT_RSDSBE | L2C_CBC_INT_MIBSBE)
1678#define L2C_CBC_INT_UE (L2C_CBC_INT_RSDDBE | L2C_CBC_INT_MIBDBE)
1679
1680
1681static const struct error_descr l2_cbc_errors[] = {
1682 {
1683 .type = ERR_CORRECTED,
1684 .mask = L2C_CBC_INT_RSDSBE,
1685 .descr = "RSD single-bit error",
1686 },
1687 {
1688 .type = ERR_CORRECTED,
1689 .mask = L2C_CBC_INT_MIBSBE,
1690 .descr = "MIB single-bit error",
1691 },
1692 {
1693 .type = ERR_UNCORRECTED,
1694 .mask = L2C_CBC_INT_RSDDBE,
1695 .descr = "RSD double-bit error",
1696 },
1697 {
1698 .type = ERR_UNCORRECTED,
1699 .mask = L2C_CBC_INT_MIBDBE,
1700 .descr = "MIB double-bit error",
1701 },
1702 {
1703 .type = ERR_UNCORRECTED,
1704 .mask = L2C_CBC_INT_IORDDISOCI,
1705 .descr = "Read from a disabled CCPI",
1706 },
1707 {
1708 .type = ERR_UNCORRECTED,
1709 .mask = L2C_CBC_INT_IOWRDISOCI,
1710 .descr = "Write to a disabled CCPI",
1711 },
1712 {0, 0, NULL},
1713};
1714
1715#define L2C_CBC_INT_W1S 0x60008
1716#define L2C_CBC_INT_ENA_W1C 0x60020
1717
1718#define L2C_CBC_INT_ENA_ALL (L2C_CBC_INT_RSD | L2C_CBC_INT_MIB | \
1719 L2C_CBC_INT_IODISOCI)
1720
1721#define L2C_CBC_INT_ENA_W1S 0x60028
1722
1723#define L2C_CBC_IODISOCIERR 0x80008
1724#define L2C_CBC_IOCERR 0x80010
1725#define L2C_CBC_RSDERR 0x80018
1726#define L2C_CBC_MIBERR 0x80020
1727
1728
1729#define L2C_MCI_INT_W1C 0x0
1730
1731#define L2C_MCI_INT_VBFSBE BIT(0)
1732#define L2C_MCI_INT_VBFDBE BIT(1)
1733
1734static const struct error_descr l2_mci_errors[] = {
1735 {
1736 .type = ERR_CORRECTED,
1737 .mask = L2C_MCI_INT_VBFSBE,
1738 .descr = "VBF single-bit error",
1739 },
1740 {
1741 .type = ERR_UNCORRECTED,
1742 .mask = L2C_MCI_INT_VBFDBE,
1743 .descr = "VBF double-bit error",
1744 },
1745 {0, 0, NULL},
1746};
1747
1748#define L2C_MCI_INT_W1S 0x8
1749#define L2C_MCI_INT_ENA_W1C 0x20
1750
1751#define L2C_MCI_INT_ENA_ALL (L2C_MCI_INT_VBFSBE | L2C_MCI_INT_VBFDBE)
1752
1753#define L2C_MCI_INT_ENA_W1S 0x28
1754
1755#define L2C_MCI_ERR 0x10000
1756
1757#define L2C_MESSAGE_SIZE SZ_1K
1758#define L2C_OTHER_SIZE (50 * ARRAY_SIZE(l2_tad_errors))
1759
1760struct l2c_err_ctx {
1761 char *reg_ext_name;
1762 u64 reg_int;
1763 u64 reg_ext;
1764};
1765
1766struct thunderx_l2c {
1767 void __iomem *regs;
1768 struct pci_dev *pdev;
1769 struct edac_device_ctl_info *edac_dev;
1770
1771 struct dentry *debugfs;
1772
1773 int index;
1774
1775 struct msix_entry msix_ent;
1776
1777 struct l2c_err_ctx err_ctx[RING_ENTRIES];
1778 unsigned long ring_head;
1779 unsigned long ring_tail;
1780};
1781
1782static irqreturn_t thunderx_l2c_tad_isr(int irq, void *irq_id)
1783{
1784 struct msix_entry *msix = irq_id;
1785 struct thunderx_l2c *tad = container_of(msix, struct thunderx_l2c,
1786 msix_ent);
1787
1788 unsigned long head = ring_pos(tad->ring_head, ARRAY_SIZE(tad->err_ctx));
1789 struct l2c_err_ctx *ctx = &tad->err_ctx[head];
1790
1791 ctx->reg_int = readq(tad->regs + L2C_TAD_INT_W1C);
1792
1793 if (ctx->reg_int & L2C_TAD_INT_ECC) {
1794 ctx->reg_ext_name = "TQD_ERR";
1795 ctx->reg_ext = readq(tad->regs + L2C_TAD_TQD_ERR);
1796 } else if (ctx->reg_int & L2C_TAD_INT_TAG) {
1797 ctx->reg_ext_name = "TTG_ERR";
1798 ctx->reg_ext = readq(tad->regs + L2C_TAD_TTG_ERR);
41003396
ST		 1799 } else if (ctx->reg_int & L2C_TAD_INT_LFBTO) {
1800 ctx->reg_ext_name = "TIMEOUT";
1801 ctx->reg_ext = readq(tad->regs + L2C_TAD_TIMEOUT);
1802 } else if (ctx->reg_int & L2C_TAD_INT_DISOCI) {
1803 ctx->reg_ext_name = "ERR";
1804 ctx->reg_ext = readq(tad->regs + L2C_TAD_ERR);
1805 }
1806
1807 writeq(ctx->reg_int, tad->regs + L2C_TAD_INT_W1C);
1808
1809 tad->ring_head++;
1810
1811 return IRQ_WAKE_THREAD;
1812}
1813
1814static irqreturn_t thunderx_l2c_cbc_isr(int irq, void *irq_id)
1815{
1816 struct msix_entry *msix = irq_id;
1817 struct thunderx_l2c *cbc = container_of(msix, struct thunderx_l2c,
1818 msix_ent);
1819
1820 unsigned long head = ring_pos(cbc->ring_head, ARRAY_SIZE(cbc->err_ctx));
1821 struct l2c_err_ctx *ctx = &cbc->err_ctx[head];
1822
1823 ctx->reg_int = readq(cbc->regs + L2C_CBC_INT_W1C);
1824
1825 if (ctx->reg_int & L2C_CBC_INT_RSD) {
1826 ctx->reg_ext_name = "RSDERR";
1827 ctx->reg_ext = readq(cbc->regs + L2C_CBC_RSDERR);
1828 } else if (ctx->reg_int & L2C_CBC_INT_MIB) {
1829 ctx->reg_ext_name = "MIBERR";
1830 ctx->reg_ext = readq(cbc->regs + L2C_CBC_MIBERR);
1831 } else if (ctx->reg_int & L2C_CBC_INT_IODISOCI) {
1832 ctx->reg_ext_name = "IODISOCIERR";
1833 ctx->reg_ext = readq(cbc->regs + L2C_CBC_IODISOCIERR);
1834 }
1835
1836 writeq(ctx->reg_int, cbc->regs + L2C_CBC_INT_W1C);
1837
1838 cbc->ring_head++;
1839
1840 return IRQ_WAKE_THREAD;
1841}
1842
1843static irqreturn_t thunderx_l2c_mci_isr(int irq, void *irq_id)
1844{
1845 struct msix_entry *msix = irq_id;
1846 struct thunderx_l2c *mci = container_of(msix, struct thunderx_l2c,
1847 msix_ent);
1848
1849 unsigned long head = ring_pos(mci->ring_head, ARRAY_SIZE(mci->err_ctx));
1850 struct l2c_err_ctx *ctx = &mci->err_ctx[head];
1851
1852 ctx->reg_int = readq(mci->regs + L2C_MCI_INT_W1C);
1853 ctx->reg_ext = readq(mci->regs + L2C_MCI_ERR);
1854
1855 writeq(ctx->reg_int, mci->regs + L2C_MCI_INT_W1C);
1856
1857 ctx->reg_ext_name = "ERR";
1858
1859 mci->ring_head++;
1860
1861 return IRQ_WAKE_THREAD;
1862}
1863
1864static irqreturn_t thunderx_l2c_threaded_isr(int irq, void *irq_id)
1865{
1866 struct msix_entry *msix = irq_id;
1867 struct thunderx_l2c *l2c = container_of(msix, struct thunderx_l2c,
1868 msix_ent);
1869
1870 unsigned long tail = ring_pos(l2c->ring_tail, ARRAY_SIZE(l2c->err_ctx));
1871 struct l2c_err_ctx *ctx = &l2c->err_ctx[tail];
1872 irqreturn_t ret = IRQ_NONE;
1873
1874 u64 mask_ue, mask_ce;
1875 const struct error_descr *l2_errors;
1876 char *reg_int_name;
1877
1878 char *msg;
1879 char *other;
1880
1881 msg = kmalloc(OCX_MESSAGE_SIZE, GFP_KERNEL);
1882 other = kmalloc(OCX_OTHER_SIZE, GFP_KERNEL);
1883
1884 if (!msg || !other)
1885 goto err_free;
1886
1887 switch (l2c->pdev->device) {
1888 case PCI_DEVICE_ID_THUNDER_L2C_TAD:
1889 reg_int_name = "L2C_TAD_INT";
1890 mask_ue = L2C_TAD_INT_UE;
1891 mask_ce = L2C_TAD_INT_CE;
1892 l2_errors = l2_tad_errors;
1893 break;
1894 case PCI_DEVICE_ID_THUNDER_L2C_CBC:
1895 reg_int_name = "L2C_CBC_INT";
1896 mask_ue = L2C_CBC_INT_UE;
1897 mask_ce = L2C_CBC_INT_CE;
1898 l2_errors = l2_cbc_errors;
1899 break;
1900 case PCI_DEVICE_ID_THUNDER_L2C_MCI:
1901 reg_int_name = "L2C_MCI_INT";
1902 mask_ue = L2C_MCI_INT_VBFDBE;
1903 mask_ce = L2C_MCI_INT_VBFSBE;
1904 l2_errors = l2_mci_errors;
1905 break;
1906 default:
1907 dev_err(&l2c->pdev->dev, "Unsupported device: %04x\n",
1908 l2c->pdev->device);
1909 return IRQ_NONE;
1910 }
1911
1912 while (CIRC_CNT(l2c->ring_head, l2c->ring_tail,
1913 ARRAY_SIZE(l2c->err_ctx))) {
1914 snprintf(msg, L2C_MESSAGE_SIZE,
1915 "%s: %s: %016llx, %s: %016llx",
1916 l2c->edac_dev->ctl_name, reg_int_name, ctx->reg_int,
1917 ctx->reg_ext_name, ctx->reg_ext);
1918
1919 decode_register(other, L2C_OTHER_SIZE, l2_errors, ctx->reg_int);
1920
1921 strncat(msg, other, L2C_MESSAGE_SIZE);
1922
1923 if (ctx->reg_int & mask_ue)
1924 edac_device_handle_ue(l2c->edac_dev, 0, 0, msg);
1925 else if (ctx->reg_int & mask_ce)
1926 edac_device_handle_ce(l2c->edac_dev, 0, 0, msg);
1927
1928 l2c->ring_tail++;
1929 }
1930
1931 return IRQ_HANDLED;
1932
1933err_free:
1934 kfree(other);
1935 kfree(msg);
1936
1937 return ret;
1938}
1939
1940#define L2C_DEBUGFS_ATTR(_name, _reg) DEBUGFS_REG_ATTR(l2c, _name, _reg)
1941
1942L2C_DEBUGFS_ATTR(tad_int, L2C_TAD_INT_W1S);
1943
1944struct debugfs_entry *l2c_tad_dfs_ents[] = {
1945 &debugfs_tad_int,
1946};
1947
1948L2C_DEBUGFS_ATTR(cbc_int, L2C_CBC_INT_W1S);
1949
1950struct debugfs_entry *l2c_cbc_dfs_ents[] = {
1951 &debugfs_cbc_int,
1952};
1953
1954L2C_DEBUGFS_ATTR(mci_int, L2C_MCI_INT_W1S);
1955
1956struct debugfs_entry *l2c_mci_dfs_ents[] = {
1957 &debugfs_mci_int,
1958};
1959
1960static const struct pci_device_id thunderx_l2c_pci_tbl[] = {
1961 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVICE_ID_THUNDER_L2C_TAD), },
1962 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVICE_ID_THUNDER_L2C_CBC), },
1963 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVICE_ID_THUNDER_L2C_MCI), },
1964 { 0, },
1965};
1966
1967static int thunderx_l2c_probe(struct pci_dev *pdev,
1968 const struct pci_device_id *id)
1969{
1970 struct thunderx_l2c *l2c;
1971 struct edac_device_ctl_info *edac_dev;
1972 struct debugfs_entry **l2c_devattr;
1973 size_t dfs_entries;
1974 irqreturn_t (*thunderx_l2c_isr)(int, void *) = NULL;
1975 char name[32];
1976 const char *fmt;
1977 u64 reg_en_offs, reg_en_mask;
1978 int idx;
1979 int ret;
1980
1981 ret = pcim_enable_device(pdev);
1982 if (ret) {
1983 dev_err(&pdev->dev, "Cannot enable PCI device: %d\n", ret);
1984 return ret;
1985 }
1986
1987 ret = pcim_iomap_regions(pdev, BIT(0), "thunderx_l2c");
1988 if (ret) {
1989 dev_err(&pdev->dev, "Cannot map PCI resources: %d\n", ret);
1990 return ret;
1991 }
1992
1993 switch (pdev->device) {
1994 case PCI_DEVICE_ID_THUNDER_L2C_TAD:
1995 thunderx_l2c_isr = thunderx_l2c_tad_isr;
1996 l2c_devattr = l2c_tad_dfs_ents;
1997 dfs_entries = ARRAY_SIZE(l2c_tad_dfs_ents);
1998 fmt = "L2C-TAD%d";
1999 reg_en_offs = L2C_TAD_INT_ENA_W1S;
2000 reg_en_mask = L2C_TAD_INT_ENA_ALL;
2001 break;
2002 case PCI_DEVICE_ID_THUNDER_L2C_CBC:
2003 thunderx_l2c_isr = thunderx_l2c_cbc_isr;
2004 l2c_devattr = l2c_cbc_dfs_ents;
2005 dfs_entries = ARRAY_SIZE(l2c_cbc_dfs_ents);
2006 fmt = "L2C-CBC%d";
2007 reg_en_offs = L2C_CBC_INT_ENA_W1S;
2008 reg_en_mask = L2C_CBC_INT_ENA_ALL;
2009 break;
2010 case PCI_DEVICE_ID_THUNDER_L2C_MCI:
2011 thunderx_l2c_isr = thunderx_l2c_mci_isr;
2012 l2c_devattr = l2c_mci_dfs_ents;
2013 dfs_entries = ARRAY_SIZE(l2c_mci_dfs_ents);
2014 fmt = "L2C-MCI%d";
2015 reg_en_offs = L2C_MCI_INT_ENA_W1S;
2016 reg_en_mask = L2C_MCI_INT_ENA_ALL;
2017 break;
2018 default:
2019 //Should never ever get here
2020 dev_err(&pdev->dev, "Unsupported PCI device: %04x\n",
2021 pdev->device);
2022 return -EINVAL;
2023 }
2024
2025 idx = edac_device_alloc_index();
2026 snprintf(name, sizeof(name), fmt, idx);
2027
2028 edac_dev = edac_device_alloc_ctl_info(sizeof(struct thunderx_l2c),
2029 name, 1, "L2C", 1, 0,
2030 NULL, 0, idx);
2031 if (!edac_dev) {
2032 dev_err(&pdev->dev, "Cannot allocate EDAC device\n");
2033 return -ENOMEM;
2034 }
2035
2036 l2c = edac_dev->pvt_info;
2037 l2c->edac_dev = edac_dev;
2038
2039 l2c->regs = pcim_iomap_table(pdev)[0];
2040 if (!l2c->regs) {
2041 dev_err(&pdev->dev, "Cannot map PCI resources\n");
2042 ret = -ENODEV;
2043 goto err_free;
2044 }
2045
2046 l2c->pdev = pdev;
2047
2048 l2c->ring_head = 0;
2049 l2c->ring_tail = 0;
2050
2051 l2c->msix_ent.entry = 0;
2052 l2c->msix_ent.vector = 0;
2053
2054 ret = pci_enable_msix_exact(pdev, &l2c->msix_ent, 1);
2055 if (ret) {
2056 dev_err(&pdev->dev, "Cannot enable interrupt: %d\n", ret);
2057 goto err_free;
2058 }
2059
2060 ret = devm_request_threaded_irq(&pdev->dev, l2c->msix_ent.vector,
2061 thunderx_l2c_isr,
2062 thunderx_l2c_threaded_isr,
2063 0, "[EDAC] ThunderX L2C",
2064 &l2c->msix_ent);
2065 if (ret)
2066 goto err_free;
2067
2068 edac_dev->dev = &pdev->dev;
2069 edac_dev->dev_name = dev_name(&pdev->dev);
2070 edac_dev->mod_name = "thunderx-l2c";
2071 edac_dev->ctl_name = "thunderx-l2c";
2072
2073 ret = edac_device_add_device(edac_dev);
2074 if (ret) {
2075 dev_err(&pdev->dev, "Cannot add EDAC device: %d\n", ret);
2076 goto err_free;
2077 }
2078
2079 if (IS_ENABLED(CONFIG_EDAC_DEBUG)) {
2080 l2c->debugfs = edac_debugfs_create_dir(pdev->dev.kobj.name);
2081
cf978258 2082 ret = thunderx_create_debugfs_nodes(l2c->debugfs, l2c_devattr,
41003396
ST		 2083 l2c, dfs_entries);
2084
2085 if (ret != dfs_entries) {
2086 dev_warn(&pdev->dev, "Error creating debugfs entries: %d%s\n",
2087 ret, ret >= 0 ? " created" : "");
2088 }
2089 }
2090
2091 pci_set_drvdata(pdev, edac_dev);
2092
2093 writeq(reg_en_mask, l2c->regs + reg_en_offs);
2094
2095 return 0;
2096
2097err_free:
2098 edac_device_free_ctl_info(edac_dev);
2099
2100 return ret;
2101}
2102
2103static void thunderx_l2c_remove(struct pci_dev *pdev)
2104{
2105 struct edac_device_ctl_info *edac_dev = pci_get_drvdata(pdev);
2106 struct thunderx_l2c *l2c = edac_dev->pvt_info;
2107
2108 switch (pdev->device) {
2109 case PCI_DEVICE_ID_THUNDER_L2C_TAD:
2110 writeq(L2C_TAD_INT_ENA_ALL, l2c->regs + L2C_TAD_INT_ENA_W1C);
2111 break;
2112 case PCI_DEVICE_ID_THUNDER_L2C_CBC:
2113 writeq(L2C_CBC_INT_ENA_ALL, l2c->regs + L2C_CBC_INT_ENA_W1C);
2114 break;
2115 case PCI_DEVICE_ID_THUNDER_L2C_MCI:
621c4fe3 2116 writeq(L2C_MCI_INT_ENA_ALL, l2c->regs + L2C_MCI_INT_ENA_W1C);
41003396
ST		 2117 break;
2118 }
2119
2120 edac_debugfs_remove_recursive(l2c->debugfs);
2121
2122 edac_device_del_device(&pdev->dev);
2123 edac_device_free_ctl_info(edac_dev);
2124}
2125
2126MODULE_DEVICE_TABLE(pci, thunderx_l2c_pci_tbl);
2127
2128static struct pci_driver thunderx_l2c_driver = {
2129 .name = "thunderx_l2c_edac",
2130 .probe = thunderx_l2c_probe,
2131 .remove = thunderx_l2c_remove,
2132 .id_table = thunderx_l2c_pci_tbl,
2133};
2134
2135static int __init thunderx_edac_init(void)
2136{
2137 int rc = 0;
2138
2139 rc = pci_register_driver(&thunderx_lmc_driver);
2140 if (rc)
2141 return rc;
2142
2143 rc = pci_register_driver(&thunderx_ocx_driver);
2144 if (rc)
2145 goto err_lmc;
2146
2147 rc = pci_register_driver(&thunderx_l2c_driver);
2148 if (rc)
2149 goto err_ocx;
2150
2151 return rc;
2152err_ocx:
2153 pci_unregister_driver(&thunderx_ocx_driver);
2154err_lmc:
2155 pci_unregister_driver(&thunderx_lmc_driver);
2156
2157 return rc;
2158}
2159
2160static void __exit thunderx_edac_exit(void)
2161{
2162 pci_unregister_driver(&thunderx_l2c_driver);
2163 pci_unregister_driver(&thunderx_ocx_driver);
2164 pci_unregister_driver(&thunderx_lmc_driver);
2165
2166}
2167
2168module_init(thunderx_edac_init);
2169module_exit(thunderx_edac_exit);
2170
2171MODULE_LICENSE("GPL v2");
2172MODULE_AUTHOR("Cavium, Inc.");
2173MODULE_DESCRIPTION("EDAC Driver for Cavium ThunderX");
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