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CommitLineData
c781c06d 1/*
b1bda4cd
JFSR
2 * Isochronous I/O functionality:
3 * - Isochronous DMA context management
4 * - Isochronous bus resource management (channels, bandwidth), client side
3038e353 5 *
3038e353
KH
6 * Copyright (C) 2006 Kristian Hoegsberg <krh@bitplanet.net>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
21 */
22
3038e353 23#include <linux/dma-mapping.h>
b1bda4cd 24#include <linux/errno.h>
77c9a5da 25#include <linux/firewire.h>
b1bda4cd
JFSR
26#include <linux/firewire-constants.h>
27#include <linux/kernel.h>
3038e353 28#include <linux/mm.h>
5a0e3ad6 29#include <linux/slab.h>
b1bda4cd
JFSR
30#include <linux/spinlock.h>
31#include <linux/vmalloc.h>
823467e5 32#include <linux/export.h>
3038e353 33
e8ca9702
SR
34#include <asm/byteorder.h>
35
77c9a5da 36#include "core.h"
b1bda4cd
JFSR
37
38/*
39 * Isochronous DMA context management
40 */
3038e353 41
0b6c4857 42int fw_iso_buffer_alloc(struct fw_iso_buffer *buffer, int page_count)
3038e353 43{
0b6c4857 44 int i;
9aad8125 45
0b6c4857
SR
46 buffer->page_count = 0;
47 buffer->page_count_mapped = 0;
6da2ec56
KC
48 buffer->pages = kmalloc_array(page_count, sizeof(buffer->pages[0]),
49 GFP_KERNEL);
9aad8125 50 if (buffer->pages == NULL)
0b6c4857 51 return -ENOMEM;
9aad8125 52
0b6c4857 53 for (i = 0; i < page_count; i++) {
68be3fa1 54 buffer->pages[i] = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO);
9aad8125 55 if (buffer->pages[i] == NULL)
0b6c4857
SR
56 break;
57 }
58 buffer->page_count = i;
59 if (i < page_count) {
60 fw_iso_buffer_destroy(buffer, NULL);
61 return -ENOMEM;
62 }
373b2edd 63
0b6c4857
SR
64 return 0;
65}
66
67int fw_iso_buffer_map_dma(struct fw_iso_buffer *buffer, struct fw_card *card,
68 enum dma_data_direction direction)
69{
70 dma_addr_t address;
71 int i;
72
73 buffer->direction = direction;
74
75 for (i = 0; i < buffer->page_count; i++) {
9aad8125
KH
76 address = dma_map_page(card->device, buffer->pages[i],
77 0, PAGE_SIZE, direction);
0b6c4857
SR
78 if (dma_mapping_error(card->device, address))
79 break;
80
9aad8125 81 set_page_private(buffer->pages[i], address);
3038e353 82 }
0b6c4857
SR
83 buffer->page_count_mapped = i;
84 if (i < buffer->page_count)
85 return -ENOMEM;
3038e353
KH
86
87 return 0;
0b6c4857 88}
82eff9db 89
0b6c4857
SR
90int fw_iso_buffer_init(struct fw_iso_buffer *buffer, struct fw_card *card,
91 int page_count, enum dma_data_direction direction)
92{
93 int ret;
94
95 ret = fw_iso_buffer_alloc(buffer, page_count);
96 if (ret < 0)
97 return ret;
e1eff7a3 98
0b6c4857
SR
99 ret = fw_iso_buffer_map_dma(buffer, card, direction);
100 if (ret < 0)
101 fw_iso_buffer_destroy(buffer, card);
102
103 return ret;
9aad8125 104}
c76acec6 105EXPORT_SYMBOL(fw_iso_buffer_init);
9aad8125 106
0b6c4857
SR
107int fw_iso_buffer_map_vma(struct fw_iso_buffer *buffer,
108 struct vm_area_struct *vma)
9aad8125 109{
22660db8
SJ
110 return vm_map_pages_zero(vma, buffer->pages,
111 buffer->page_count);
3038e353
KH
112}
113
9aad8125
KH
114void fw_iso_buffer_destroy(struct fw_iso_buffer *buffer,
115 struct fw_card *card)
3038e353
KH
116{
117 int i;
9aad8125 118 dma_addr_t address;
3038e353 119
0b6c4857 120 for (i = 0; i < buffer->page_count_mapped; i++) {
9aad8125
KH
121 address = page_private(buffer->pages[i]);
122 dma_unmap_page(card->device, address,
29ad14cd 123 PAGE_SIZE, buffer->direction);
9aad8125 124 }
0b6c4857
SR
125 for (i = 0; i < buffer->page_count; i++)
126 __free_page(buffer->pages[i]);
3038e353 127
9aad8125
KH
128 kfree(buffer->pages);
129 buffer->pages = NULL;
0b6c4857
SR
130 buffer->page_count = 0;
131 buffer->page_count_mapped = 0;
3038e353 132}
c76acec6 133EXPORT_SYMBOL(fw_iso_buffer_destroy);
3038e353 134
872e330e
SR
135/* Convert DMA address to offset into virtually contiguous buffer. */
136size_t fw_iso_buffer_lookup(struct fw_iso_buffer *buffer, dma_addr_t completed)
137{
9d23f9e9 138 size_t i;
872e330e
SR
139 dma_addr_t address;
140 ssize_t offset;
141
142 for (i = 0; i < buffer->page_count; i++) {
143 address = page_private(buffer->pages[i]);
144 offset = (ssize_t)completed - (ssize_t)address;
145 if (offset > 0 && offset <= PAGE_SIZE)
146 return (i << PAGE_SHIFT) + offset;
147 }
148
149 return 0;
150}
151
53dca511
SR
152struct fw_iso_context *fw_iso_context_create(struct fw_card *card,
153 int type, int channel, int speed, size_t header_size,
154 fw_iso_callback_t callback, void *callback_data)
3038e353
KH
155{
156 struct fw_iso_context *ctx;
3038e353 157
4817ed24
SR
158 ctx = card->driver->allocate_iso_context(card,
159 type, channel, header_size);
3038e353
KH
160 if (IS_ERR(ctx))
161 return ctx;
162
163 ctx->card = card;
164 ctx->type = type;
21efb3cf
KH
165 ctx->channel = channel;
166 ctx->speed = speed;
295e3feb 167 ctx->header_size = header_size;
872e330e 168 ctx->callback.sc = callback;
3038e353
KH
169 ctx->callback_data = callback_data;
170
3038e353
KH
171 return ctx;
172}
c76acec6 173EXPORT_SYMBOL(fw_iso_context_create);
3038e353
KH
174
175void fw_iso_context_destroy(struct fw_iso_context *ctx)
176{
872e330e 177 ctx->card->driver->free_iso_context(ctx);
3038e353 178}
c76acec6 179EXPORT_SYMBOL(fw_iso_context_destroy);
3038e353 180
53dca511
SR
181int fw_iso_context_start(struct fw_iso_context *ctx,
182 int cycle, int sync, int tags)
3038e353 183{
eb0306ea 184 return ctx->card->driver->start_iso(ctx, cycle, sync, tags);
3038e353 185}
c76acec6 186EXPORT_SYMBOL(fw_iso_context_start);
3038e353 187
872e330e
SR
188int fw_iso_context_set_channels(struct fw_iso_context *ctx, u64 *channels)
189{
190 return ctx->card->driver->set_iso_channels(ctx, channels);
191}
192
53dca511
SR
193int fw_iso_context_queue(struct fw_iso_context *ctx,
194 struct fw_iso_packet *packet,
195 struct fw_iso_buffer *buffer,
196 unsigned long payload)
3038e353 197{
872e330e 198 return ctx->card->driver->queue_iso(ctx, packet, buffer, payload);
3038e353 199}
c76acec6 200EXPORT_SYMBOL(fw_iso_context_queue);
b8295668 201
13882a82
CL
202void fw_iso_context_queue_flush(struct fw_iso_context *ctx)
203{
204 ctx->card->driver->flush_queue_iso(ctx);
205}
206EXPORT_SYMBOL(fw_iso_context_queue_flush);
207
d1bbd209
CL
208int fw_iso_context_flush_completions(struct fw_iso_context *ctx)
209{
210 return ctx->card->driver->flush_iso_completions(ctx);
211}
212EXPORT_SYMBOL(fw_iso_context_flush_completions);
213
53dca511 214int fw_iso_context_stop(struct fw_iso_context *ctx)
b8295668
KH
215{
216 return ctx->card->driver->stop_iso(ctx);
217}
c76acec6 218EXPORT_SYMBOL(fw_iso_context_stop);
b1bda4cd
JFSR
219
220/*
221 * Isochronous bus resource management (channels, bandwidth), client side
222 */
223
224static int manage_bandwidth(struct fw_card *card, int irm_id, int generation,
f30e6d3e 225 int bandwidth, bool allocate)
b1bda4cd 226{
b1bda4cd 227 int try, new, old = allocate ? BANDWIDTH_AVAILABLE_INITIAL : 0;
f30e6d3e 228 __be32 data[2];
b1bda4cd
JFSR
229
230 /*
231 * On a 1394a IRM with low contention, try < 1 is enough.
232 * On a 1394-1995 IRM, we need at least try < 2.
233 * Let's just do try < 5.
234 */
235 for (try = 0; try < 5; try++) {
236 new = allocate ? old - bandwidth : old + bandwidth;
237 if (new < 0 || new > BANDWIDTH_AVAILABLE_INITIAL)
d6372b6e 238 return -EBUSY;
b1bda4cd
JFSR
239
240 data[0] = cpu_to_be32(old);
241 data[1] = cpu_to_be32(new);
242 switch (fw_run_transaction(card, TCODE_LOCK_COMPARE_SWAP,
243 irm_id, generation, SCODE_100,
244 CSR_REGISTER_BASE + CSR_BANDWIDTH_AVAILABLE,
1821bc19 245 data, 8)) {
b1bda4cd
JFSR
246 case RCODE_GENERATION:
247 /* A generation change frees all bandwidth. */
248 return allocate ? -EAGAIN : bandwidth;
249
250 case RCODE_COMPLETE:
251 if (be32_to_cpup(data) == old)
252 return bandwidth;
253
254 old = be32_to_cpup(data);
255 /* Fall through. */
256 }
257 }
258
259 return -EIO;
260}
261
262static int manage_channel(struct fw_card *card, int irm_id, int generation,
f30e6d3e 263 u32 channels_mask, u64 offset, bool allocate)
b1bda4cd 264{
5aaffc65 265 __be32 bit, all, old;
f30e6d3e 266 __be32 data[2];
5aaffc65 267 int channel, ret = -EIO, retry = 5;
b1bda4cd 268
5d9cb7d2
SR
269 old = all = allocate ? cpu_to_be32(~0) : 0;
270
5aaffc65
CL
271 for (channel = 0; channel < 32; channel++) {
272 if (!(channels_mask & 1 << channel))
b1bda4cd
JFSR
273 continue;
274
d6372b6e
CL
275 ret = -EBUSY;
276
5aaffc65
CL
277 bit = cpu_to_be32(1 << (31 - channel));
278 if ((old & bit) != (all & bit))
b1bda4cd
JFSR
279 continue;
280
281 data[0] = old;
5aaffc65 282 data[1] = old ^ bit;
b1bda4cd
JFSR
283 switch (fw_run_transaction(card, TCODE_LOCK_COMPARE_SWAP,
284 irm_id, generation, SCODE_100,
1821bc19 285 offset, data, 8)) {
b1bda4cd
JFSR
286 case RCODE_GENERATION:
287 /* A generation change frees all channels. */
5aaffc65 288 return allocate ? -EAGAIN : channel;
b1bda4cd
JFSR
289
290 case RCODE_COMPLETE:
291 if (data[0] == old)
5aaffc65 292 return channel;
b1bda4cd
JFSR
293
294 old = data[0];
295
296 /* Is the IRM 1394a-2000 compliant? */
5aaffc65 297 if ((data[0] & bit) == (data[1] & bit))
b1bda4cd
JFSR
298 continue;
299
300 /* 1394-1995 IRM, fall through to retry. */
301 default:
3a1f0a0e
CL
302 if (retry) {
303 retry--;
5aaffc65 304 channel--;
d6372b6e
CL
305 } else {
306 ret = -EIO;
3a1f0a0e 307 }
b1bda4cd
JFSR
308 }
309 }
310
d6372b6e 311 return ret;
b1bda4cd
JFSR
312}
313
314static void deallocate_channel(struct fw_card *card, int irm_id,
f30e6d3e 315 int generation, int channel)
b1bda4cd 316{
5d9cb7d2 317 u32 mask;
b1bda4cd
JFSR
318 u64 offset;
319
5d9cb7d2 320 mask = channel < 32 ? 1 << channel : 1 << (channel - 32);
b1bda4cd
JFSR
321 offset = channel < 32 ? CSR_REGISTER_BASE + CSR_CHANNELS_AVAILABLE_HI :
322 CSR_REGISTER_BASE + CSR_CHANNELS_AVAILABLE_LO;
323
f30e6d3e 324 manage_channel(card, irm_id, generation, mask, offset, false);
b1bda4cd
JFSR
325}
326
327/**
656b7afd 328 * fw_iso_resource_manage() - Allocate or deallocate a channel and/or bandwidth
48f02b88
RD
329 * @card: card interface for this action
330 * @generation: bus generation
331 * @channels_mask: bitmask for channel allocation
332 * @channel: pointer for returning channel allocation result
333 * @bandwidth: pointer for returning bandwidth allocation result
334 * @allocate: whether to allocate (true) or deallocate (false)
b1bda4cd
JFSR
335 *
336 * In parameters: card, generation, channels_mask, bandwidth, allocate
337 * Out parameters: channel, bandwidth
48f02b88 338 *
b1bda4cd 339 * This function blocks (sleeps) during communication with the IRM.
5d9cb7d2 340 *
b1bda4cd 341 * Allocates or deallocates at most one channel out of channels_mask.
5d9cb7d2
SR
342 * channels_mask is a bitfield with MSB for channel 63 and LSB for channel 0.
343 * (Note, the IRM's CHANNELS_AVAILABLE is a big-endian bitfield with MSB for
344 * channel 0 and LSB for channel 63.)
345 * Allocates or deallocates as many bandwidth allocation units as specified.
b1bda4cd
JFSR
346 *
347 * Returns channel < 0 if no channel was allocated or deallocated.
348 * Returns bandwidth = 0 if no bandwidth was allocated or deallocated.
349 *
350 * If generation is stale, deallocations succeed but allocations fail with
351 * channel = -EAGAIN.
352 *
5d9cb7d2 353 * If channel allocation fails, no bandwidth will be allocated either.
b1bda4cd 354 * If bandwidth allocation fails, no channel will be allocated either.
5d9cb7d2
SR
355 * But deallocations of channel and bandwidth are tried independently
356 * of each other's success.
b1bda4cd
JFSR
357 */
358void fw_iso_resource_manage(struct fw_card *card, int generation,
359 u64 channels_mask, int *channel, int *bandwidth,
f30e6d3e 360 bool allocate)
b1bda4cd 361{
5d9cb7d2
SR
362 u32 channels_hi = channels_mask; /* channels 31...0 */
363 u32 channels_lo = channels_mask >> 32; /* channels 63...32 */
b1bda4cd
JFSR
364 int irm_id, ret, c = -EINVAL;
365
366 spin_lock_irq(&card->lock);
367 irm_id = card->irm_node->node_id;
368 spin_unlock_irq(&card->lock);
369
370 if (channels_hi)
371 c = manage_channel(card, irm_id, generation, channels_hi,
6fdc0370 372 CSR_REGISTER_BASE + CSR_CHANNELS_AVAILABLE_HI,
f30e6d3e 373 allocate);
b1bda4cd
JFSR
374 if (channels_lo && c < 0) {
375 c = manage_channel(card, irm_id, generation, channels_lo,
6fdc0370 376 CSR_REGISTER_BASE + CSR_CHANNELS_AVAILABLE_LO,
f30e6d3e 377 allocate);
b1bda4cd
JFSR
378 if (c >= 0)
379 c += 32;
380 }
381 *channel = c;
382
5d9cb7d2 383 if (allocate && channels_mask != 0 && c < 0)
b1bda4cd
JFSR
384 *bandwidth = 0;
385
386 if (*bandwidth == 0)
387 return;
388
f30e6d3e 389 ret = manage_bandwidth(card, irm_id, generation, *bandwidth, allocate);
b1bda4cd
JFSR
390 if (ret < 0)
391 *bandwidth = 0;
392
cf36df6b
CL
393 if (allocate && ret < 0) {
394 if (c >= 0)
f30e6d3e 395 deallocate_channel(card, irm_id, generation, c);
b1bda4cd
JFSR
396 *channel = ret;
397 }
398}
31ef9134 399EXPORT_SYMBOL(fw_iso_resource_manage);