]>
Commit | Line | Data |
---|---|---|
1a59d1b8 | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
c781c06d | 2 | /* |
b1bda4cd JFSR |
3 | * Isochronous I/O functionality: |
4 | * - Isochronous DMA context management | |
5 | * - Isochronous bus resource management (channels, bandwidth), client side | |
3038e353 | 6 | * |
3038e353 | 7 | * Copyright (C) 2006 Kristian Hoegsberg <krh@bitplanet.net> |
3038e353 KH |
8 | */ |
9 | ||
3038e353 | 10 | #include <linux/dma-mapping.h> |
b1bda4cd | 11 | #include <linux/errno.h> |
77c9a5da | 12 | #include <linux/firewire.h> |
b1bda4cd JFSR |
13 | #include <linux/firewire-constants.h> |
14 | #include <linux/kernel.h> | |
3038e353 | 15 | #include <linux/mm.h> |
5a0e3ad6 | 16 | #include <linux/slab.h> |
b1bda4cd JFSR |
17 | #include <linux/spinlock.h> |
18 | #include <linux/vmalloc.h> | |
823467e5 | 19 | #include <linux/export.h> |
3038e353 | 20 | |
e8ca9702 SR |
21 | #include <asm/byteorder.h> |
22 | ||
77c9a5da | 23 | #include "core.h" |
b1bda4cd JFSR |
24 | |
25 | /* | |
26 | * Isochronous DMA context management | |
27 | */ | |
3038e353 | 28 | |
0b6c4857 | 29 | int fw_iso_buffer_alloc(struct fw_iso_buffer *buffer, int page_count) |
3038e353 | 30 | { |
0b6c4857 | 31 | int i; |
9aad8125 | 32 | |
0b6c4857 SR |
33 | buffer->page_count = 0; |
34 | buffer->page_count_mapped = 0; | |
6da2ec56 KC |
35 | buffer->pages = kmalloc_array(page_count, sizeof(buffer->pages[0]), |
36 | GFP_KERNEL); | |
9aad8125 | 37 | if (buffer->pages == NULL) |
0b6c4857 | 38 | return -ENOMEM; |
9aad8125 | 39 | |
0b6c4857 | 40 | for (i = 0; i < page_count; i++) { |
68be3fa1 | 41 | buffer->pages[i] = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO); |
9aad8125 | 42 | if (buffer->pages[i] == NULL) |
0b6c4857 SR |
43 | break; |
44 | } | |
45 | buffer->page_count = i; | |
46 | if (i < page_count) { | |
47 | fw_iso_buffer_destroy(buffer, NULL); | |
48 | return -ENOMEM; | |
49 | } | |
373b2edd | 50 | |
0b6c4857 SR |
51 | return 0; |
52 | } | |
53 | ||
54 | int fw_iso_buffer_map_dma(struct fw_iso_buffer *buffer, struct fw_card *card, | |
55 | enum dma_data_direction direction) | |
56 | { | |
57 | dma_addr_t address; | |
58 | int i; | |
59 | ||
60 | buffer->direction = direction; | |
61 | ||
62 | for (i = 0; i < buffer->page_count; i++) { | |
9aad8125 KH |
63 | address = dma_map_page(card->device, buffer->pages[i], |
64 | 0, PAGE_SIZE, direction); | |
0b6c4857 SR |
65 | if (dma_mapping_error(card->device, address)) |
66 | break; | |
67 | ||
9aad8125 | 68 | set_page_private(buffer->pages[i], address); |
3038e353 | 69 | } |
0b6c4857 SR |
70 | buffer->page_count_mapped = i; |
71 | if (i < buffer->page_count) | |
72 | return -ENOMEM; | |
3038e353 KH |
73 | |
74 | return 0; | |
0b6c4857 | 75 | } |
82eff9db | 76 | |
0b6c4857 SR |
77 | int fw_iso_buffer_init(struct fw_iso_buffer *buffer, struct fw_card *card, |
78 | int page_count, enum dma_data_direction direction) | |
79 | { | |
80 | int ret; | |
81 | ||
82 | ret = fw_iso_buffer_alloc(buffer, page_count); | |
83 | if (ret < 0) | |
84 | return ret; | |
e1eff7a3 | 85 | |
0b6c4857 SR |
86 | ret = fw_iso_buffer_map_dma(buffer, card, direction); |
87 | if (ret < 0) | |
88 | fw_iso_buffer_destroy(buffer, card); | |
89 | ||
90 | return ret; | |
9aad8125 | 91 | } |
c76acec6 | 92 | EXPORT_SYMBOL(fw_iso_buffer_init); |
9aad8125 | 93 | |
9aad8125 KH |
94 | void fw_iso_buffer_destroy(struct fw_iso_buffer *buffer, |
95 | struct fw_card *card) | |
3038e353 KH |
96 | { |
97 | int i; | |
9aad8125 | 98 | dma_addr_t address; |
3038e353 | 99 | |
0b6c4857 | 100 | for (i = 0; i < buffer->page_count_mapped; i++) { |
9aad8125 KH |
101 | address = page_private(buffer->pages[i]); |
102 | dma_unmap_page(card->device, address, | |
29ad14cd | 103 | PAGE_SIZE, buffer->direction); |
9aad8125 | 104 | } |
0b6c4857 SR |
105 | for (i = 0; i < buffer->page_count; i++) |
106 | __free_page(buffer->pages[i]); | |
3038e353 | 107 | |
9aad8125 KH |
108 | kfree(buffer->pages); |
109 | buffer->pages = NULL; | |
0b6c4857 SR |
110 | buffer->page_count = 0; |
111 | buffer->page_count_mapped = 0; | |
3038e353 | 112 | } |
c76acec6 | 113 | EXPORT_SYMBOL(fw_iso_buffer_destroy); |
3038e353 | 114 | |
872e330e SR |
115 | /* Convert DMA address to offset into virtually contiguous buffer. */ |
116 | size_t fw_iso_buffer_lookup(struct fw_iso_buffer *buffer, dma_addr_t completed) | |
117 | { | |
9d23f9e9 | 118 | size_t i; |
872e330e SR |
119 | dma_addr_t address; |
120 | ssize_t offset; | |
121 | ||
122 | for (i = 0; i < buffer->page_count; i++) { | |
123 | address = page_private(buffer->pages[i]); | |
124 | offset = (ssize_t)completed - (ssize_t)address; | |
125 | if (offset > 0 && offset <= PAGE_SIZE) | |
126 | return (i << PAGE_SHIFT) + offset; | |
127 | } | |
128 | ||
129 | return 0; | |
130 | } | |
131 | ||
53dca511 SR |
132 | struct fw_iso_context *fw_iso_context_create(struct fw_card *card, |
133 | int type, int channel, int speed, size_t header_size, | |
134 | fw_iso_callback_t callback, void *callback_data) | |
3038e353 KH |
135 | { |
136 | struct fw_iso_context *ctx; | |
3038e353 | 137 | |
4817ed24 SR |
138 | ctx = card->driver->allocate_iso_context(card, |
139 | type, channel, header_size); | |
3038e353 KH |
140 | if (IS_ERR(ctx)) |
141 | return ctx; | |
142 | ||
143 | ctx->card = card; | |
144 | ctx->type = type; | |
21efb3cf KH |
145 | ctx->channel = channel; |
146 | ctx->speed = speed; | |
295e3feb | 147 | ctx->header_size = header_size; |
872e330e | 148 | ctx->callback.sc = callback; |
3038e353 KH |
149 | ctx->callback_data = callback_data; |
150 | ||
3038e353 KH |
151 | return ctx; |
152 | } | |
c76acec6 | 153 | EXPORT_SYMBOL(fw_iso_context_create); |
3038e353 KH |
154 | |
155 | void fw_iso_context_destroy(struct fw_iso_context *ctx) | |
156 | { | |
872e330e | 157 | ctx->card->driver->free_iso_context(ctx); |
3038e353 | 158 | } |
c76acec6 | 159 | EXPORT_SYMBOL(fw_iso_context_destroy); |
3038e353 | 160 | |
53dca511 SR |
161 | int fw_iso_context_start(struct fw_iso_context *ctx, |
162 | int cycle, int sync, int tags) | |
3038e353 | 163 | { |
eb0306ea | 164 | return ctx->card->driver->start_iso(ctx, cycle, sync, tags); |
3038e353 | 165 | } |
c76acec6 | 166 | EXPORT_SYMBOL(fw_iso_context_start); |
3038e353 | 167 | |
872e330e SR |
168 | int fw_iso_context_set_channels(struct fw_iso_context *ctx, u64 *channels) |
169 | { | |
170 | return ctx->card->driver->set_iso_channels(ctx, channels); | |
171 | } | |
172 | ||
53dca511 SR |
173 | int fw_iso_context_queue(struct fw_iso_context *ctx, |
174 | struct fw_iso_packet *packet, | |
175 | struct fw_iso_buffer *buffer, | |
176 | unsigned long payload) | |
3038e353 | 177 | { |
872e330e | 178 | return ctx->card->driver->queue_iso(ctx, packet, buffer, payload); |
3038e353 | 179 | } |
c76acec6 | 180 | EXPORT_SYMBOL(fw_iso_context_queue); |
b8295668 | 181 | |
13882a82 CL |
182 | void fw_iso_context_queue_flush(struct fw_iso_context *ctx) |
183 | { | |
184 | ctx->card->driver->flush_queue_iso(ctx); | |
185 | } | |
186 | EXPORT_SYMBOL(fw_iso_context_queue_flush); | |
187 | ||
d1bbd209 CL |
188 | int fw_iso_context_flush_completions(struct fw_iso_context *ctx) |
189 | { | |
190 | return ctx->card->driver->flush_iso_completions(ctx); | |
191 | } | |
192 | EXPORT_SYMBOL(fw_iso_context_flush_completions); | |
193 | ||
53dca511 | 194 | int fw_iso_context_stop(struct fw_iso_context *ctx) |
b8295668 KH |
195 | { |
196 | return ctx->card->driver->stop_iso(ctx); | |
197 | } | |
c76acec6 | 198 | EXPORT_SYMBOL(fw_iso_context_stop); |
b1bda4cd JFSR |
199 | |
200 | /* | |
201 | * Isochronous bus resource management (channels, bandwidth), client side | |
202 | */ | |
203 | ||
204 | static int manage_bandwidth(struct fw_card *card, int irm_id, int generation, | |
f30e6d3e | 205 | int bandwidth, bool allocate) |
b1bda4cd | 206 | { |
b1bda4cd | 207 | int try, new, old = allocate ? BANDWIDTH_AVAILABLE_INITIAL : 0; |
f30e6d3e | 208 | __be32 data[2]; |
b1bda4cd JFSR |
209 | |
210 | /* | |
211 | * On a 1394a IRM with low contention, try < 1 is enough. | |
212 | * On a 1394-1995 IRM, we need at least try < 2. | |
213 | * Let's just do try < 5. | |
214 | */ | |
215 | for (try = 0; try < 5; try++) { | |
216 | new = allocate ? old - bandwidth : old + bandwidth; | |
217 | if (new < 0 || new > BANDWIDTH_AVAILABLE_INITIAL) | |
d6372b6e | 218 | return -EBUSY; |
b1bda4cd JFSR |
219 | |
220 | data[0] = cpu_to_be32(old); | |
221 | data[1] = cpu_to_be32(new); | |
222 | switch (fw_run_transaction(card, TCODE_LOCK_COMPARE_SWAP, | |
223 | irm_id, generation, SCODE_100, | |
224 | CSR_REGISTER_BASE + CSR_BANDWIDTH_AVAILABLE, | |
1821bc19 | 225 | data, 8)) { |
b1bda4cd JFSR |
226 | case RCODE_GENERATION: |
227 | /* A generation change frees all bandwidth. */ | |
228 | return allocate ? -EAGAIN : bandwidth; | |
229 | ||
230 | case RCODE_COMPLETE: | |
231 | if (be32_to_cpup(data) == old) | |
232 | return bandwidth; | |
233 | ||
234 | old = be32_to_cpup(data); | |
235 | /* Fall through. */ | |
236 | } | |
237 | } | |
238 | ||
239 | return -EIO; | |
240 | } | |
241 | ||
242 | static int manage_channel(struct fw_card *card, int irm_id, int generation, | |
f30e6d3e | 243 | u32 channels_mask, u64 offset, bool allocate) |
b1bda4cd | 244 | { |
5aaffc65 | 245 | __be32 bit, all, old; |
f30e6d3e | 246 | __be32 data[2]; |
5aaffc65 | 247 | int channel, ret = -EIO, retry = 5; |
b1bda4cd | 248 | |
5d9cb7d2 SR |
249 | old = all = allocate ? cpu_to_be32(~0) : 0; |
250 | ||
5aaffc65 CL |
251 | for (channel = 0; channel < 32; channel++) { |
252 | if (!(channels_mask & 1 << channel)) | |
b1bda4cd JFSR |
253 | continue; |
254 | ||
d6372b6e CL |
255 | ret = -EBUSY; |
256 | ||
5aaffc65 CL |
257 | bit = cpu_to_be32(1 << (31 - channel)); |
258 | if ((old & bit) != (all & bit)) | |
b1bda4cd JFSR |
259 | continue; |
260 | ||
261 | data[0] = old; | |
5aaffc65 | 262 | data[1] = old ^ bit; |
b1bda4cd JFSR |
263 | switch (fw_run_transaction(card, TCODE_LOCK_COMPARE_SWAP, |
264 | irm_id, generation, SCODE_100, | |
1821bc19 | 265 | offset, data, 8)) { |
b1bda4cd JFSR |
266 | case RCODE_GENERATION: |
267 | /* A generation change frees all channels. */ | |
5aaffc65 | 268 | return allocate ? -EAGAIN : channel; |
b1bda4cd JFSR |
269 | |
270 | case RCODE_COMPLETE: | |
271 | if (data[0] == old) | |
5aaffc65 | 272 | return channel; |
b1bda4cd JFSR |
273 | |
274 | old = data[0]; | |
275 | ||
276 | /* Is the IRM 1394a-2000 compliant? */ | |
5aaffc65 | 277 | if ((data[0] & bit) == (data[1] & bit)) |
b1bda4cd JFSR |
278 | continue; |
279 | ||
df561f66 | 280 | fallthrough; /* It's a 1394-1995 IRM, retry */ |
b1bda4cd | 281 | default: |
3a1f0a0e CL |
282 | if (retry) { |
283 | retry--; | |
5aaffc65 | 284 | channel--; |
d6372b6e CL |
285 | } else { |
286 | ret = -EIO; | |
3a1f0a0e | 287 | } |
b1bda4cd JFSR |
288 | } |
289 | } | |
290 | ||
d6372b6e | 291 | return ret; |
b1bda4cd JFSR |
292 | } |
293 | ||
294 | static void deallocate_channel(struct fw_card *card, int irm_id, | |
f30e6d3e | 295 | int generation, int channel) |
b1bda4cd | 296 | { |
5d9cb7d2 | 297 | u32 mask; |
b1bda4cd JFSR |
298 | u64 offset; |
299 | ||
5d9cb7d2 | 300 | mask = channel < 32 ? 1 << channel : 1 << (channel - 32); |
b1bda4cd JFSR |
301 | offset = channel < 32 ? CSR_REGISTER_BASE + CSR_CHANNELS_AVAILABLE_HI : |
302 | CSR_REGISTER_BASE + CSR_CHANNELS_AVAILABLE_LO; | |
303 | ||
f30e6d3e | 304 | manage_channel(card, irm_id, generation, mask, offset, false); |
b1bda4cd JFSR |
305 | } |
306 | ||
307 | /** | |
656b7afd | 308 | * fw_iso_resource_manage() - Allocate or deallocate a channel and/or bandwidth |
48f02b88 RD |
309 | * @card: card interface for this action |
310 | * @generation: bus generation | |
311 | * @channels_mask: bitmask for channel allocation | |
312 | * @channel: pointer for returning channel allocation result | |
313 | * @bandwidth: pointer for returning bandwidth allocation result | |
314 | * @allocate: whether to allocate (true) or deallocate (false) | |
b1bda4cd JFSR |
315 | * |
316 | * In parameters: card, generation, channels_mask, bandwidth, allocate | |
317 | * Out parameters: channel, bandwidth | |
48f02b88 | 318 | * |
b1bda4cd | 319 | * This function blocks (sleeps) during communication with the IRM. |
5d9cb7d2 | 320 | * |
b1bda4cd | 321 | * Allocates or deallocates at most one channel out of channels_mask. |
5d9cb7d2 SR |
322 | * channels_mask is a bitfield with MSB for channel 63 and LSB for channel 0. |
323 | * (Note, the IRM's CHANNELS_AVAILABLE is a big-endian bitfield with MSB for | |
324 | * channel 0 and LSB for channel 63.) | |
325 | * Allocates or deallocates as many bandwidth allocation units as specified. | |
b1bda4cd JFSR |
326 | * |
327 | * Returns channel < 0 if no channel was allocated or deallocated. | |
328 | * Returns bandwidth = 0 if no bandwidth was allocated or deallocated. | |
329 | * | |
330 | * If generation is stale, deallocations succeed but allocations fail with | |
331 | * channel = -EAGAIN. | |
332 | * | |
5d9cb7d2 | 333 | * If channel allocation fails, no bandwidth will be allocated either. |
b1bda4cd | 334 | * If bandwidth allocation fails, no channel will be allocated either. |
5d9cb7d2 SR |
335 | * But deallocations of channel and bandwidth are tried independently |
336 | * of each other's success. | |
b1bda4cd JFSR |
337 | */ |
338 | void fw_iso_resource_manage(struct fw_card *card, int generation, | |
339 | u64 channels_mask, int *channel, int *bandwidth, | |
f30e6d3e | 340 | bool allocate) |
b1bda4cd | 341 | { |
5d9cb7d2 SR |
342 | u32 channels_hi = channels_mask; /* channels 31...0 */ |
343 | u32 channels_lo = channels_mask >> 32; /* channels 63...32 */ | |
b1bda4cd JFSR |
344 | int irm_id, ret, c = -EINVAL; |
345 | ||
346 | spin_lock_irq(&card->lock); | |
347 | irm_id = card->irm_node->node_id; | |
348 | spin_unlock_irq(&card->lock); | |
349 | ||
350 | if (channels_hi) | |
351 | c = manage_channel(card, irm_id, generation, channels_hi, | |
6fdc0370 | 352 | CSR_REGISTER_BASE + CSR_CHANNELS_AVAILABLE_HI, |
f30e6d3e | 353 | allocate); |
b1bda4cd JFSR |
354 | if (channels_lo && c < 0) { |
355 | c = manage_channel(card, irm_id, generation, channels_lo, | |
6fdc0370 | 356 | CSR_REGISTER_BASE + CSR_CHANNELS_AVAILABLE_LO, |
f30e6d3e | 357 | allocate); |
b1bda4cd JFSR |
358 | if (c >= 0) |
359 | c += 32; | |
360 | } | |
361 | *channel = c; | |
362 | ||
5d9cb7d2 | 363 | if (allocate && channels_mask != 0 && c < 0) |
b1bda4cd JFSR |
364 | *bandwidth = 0; |
365 | ||
366 | if (*bandwidth == 0) | |
367 | return; | |
368 | ||
f30e6d3e | 369 | ret = manage_bandwidth(card, irm_id, generation, *bandwidth, allocate); |
b1bda4cd JFSR |
370 | if (ret < 0) |
371 | *bandwidth = 0; | |
372 | ||
cf36df6b CL |
373 | if (allocate && ret < 0) { |
374 | if (c >= 0) | |
f30e6d3e | 375 | deallocate_channel(card, irm_id, generation, c); |
b1bda4cd JFSR |
376 | *channel = ret; |
377 | } | |
378 | } | |
31ef9134 | 379 | EXPORT_SYMBOL(fw_iso_resource_manage); |