]>
Commit | Line | Data |
---|---|---|
ed568912 KH |
1 | /* -*- c-basic-offset: 8 -*- |
2 | * | |
3 | * fw-ohci.c - Driver for OHCI 1394 boards | |
4 | * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software Foundation, | |
18 | * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
19 | */ | |
20 | ||
21 | #include <linux/kernel.h> | |
22 | #include <linux/module.h> | |
23 | #include <linux/init.h> | |
24 | #include <linux/interrupt.h> | |
25 | #include <linux/pci.h> | |
26 | #include <linux/delay.h> | |
27 | #include <linux/poll.h> | |
cf3e72fd AM |
28 | #include <linux/dma-mapping.h> |
29 | ||
ed568912 KH |
30 | #include <asm/uaccess.h> |
31 | #include <asm/semaphore.h> | |
32 | ||
33 | #include "fw-transaction.h" | |
34 | #include "fw-ohci.h" | |
35 | ||
36 | #define descriptor_output_more 0 | |
37 | #define descriptor_output_last (1 << 12) | |
38 | #define descriptor_input_more (2 << 12) | |
39 | #define descriptor_input_last (3 << 12) | |
40 | #define descriptor_status (1 << 11) | |
41 | #define descriptor_key_immediate (2 << 8) | |
42 | #define descriptor_ping (1 << 7) | |
43 | #define descriptor_yy (1 << 6) | |
44 | #define descriptor_no_irq (0 << 4) | |
45 | #define descriptor_irq_error (1 << 4) | |
46 | #define descriptor_irq_always (3 << 4) | |
47 | #define descriptor_branch_always (3 << 2) | |
48 | ||
49 | struct descriptor { | |
50 | __le16 req_count; | |
51 | __le16 control; | |
52 | __le32 data_address; | |
53 | __le32 branch_address; | |
54 | __le16 res_count; | |
55 | __le16 transfer_status; | |
56 | } __attribute__((aligned(16))); | |
57 | ||
32b46093 | 58 | struct ar_buffer { |
ed568912 | 59 | struct descriptor descriptor; |
32b46093 KH |
60 | struct ar_buffer *next; |
61 | __le32 data[0]; | |
62 | }; | |
ed568912 | 63 | |
32b46093 KH |
64 | struct ar_context { |
65 | struct fw_ohci *ohci; | |
66 | struct ar_buffer *current_buffer; | |
67 | struct ar_buffer *last_buffer; | |
68 | void *pointer; | |
ed568912 KH |
69 | u32 command_ptr; |
70 | u32 control_set; | |
71 | u32 control_clear; | |
ed568912 KH |
72 | struct tasklet_struct tasklet; |
73 | }; | |
74 | ||
75 | struct at_context { | |
76 | struct fw_ohci *ohci; | |
77 | dma_addr_t descriptor_bus; | |
78 | dma_addr_t buffer_bus; | |
79 | ||
80 | struct list_head list; | |
81 | ||
82 | struct { | |
83 | struct descriptor more; | |
84 | __le32 header[4]; | |
85 | struct descriptor last; | |
86 | } d; | |
87 | ||
88 | u32 command_ptr; | |
89 | u32 control_set; | |
90 | u32 control_clear; | |
91 | ||
92 | struct tasklet_struct tasklet; | |
93 | }; | |
94 | ||
95 | #define it_header_sy(v) ((v) << 0) | |
96 | #define it_header_tcode(v) ((v) << 4) | |
97 | #define it_header_channel(v) ((v) << 8) | |
98 | #define it_header_tag(v) ((v) << 14) | |
99 | #define it_header_speed(v) ((v) << 16) | |
100 | #define it_header_data_length(v) ((v) << 16) | |
101 | ||
102 | struct iso_context { | |
103 | struct fw_iso_context base; | |
104 | struct tasklet_struct tasklet; | |
105 | u32 control_set; | |
106 | u32 control_clear; | |
107 | u32 command_ptr; | |
108 | u32 context_match; | |
109 | ||
110 | struct descriptor *buffer; | |
111 | dma_addr_t buffer_bus; | |
112 | struct descriptor *head_descriptor; | |
113 | struct descriptor *tail_descriptor; | |
114 | struct descriptor *tail_descriptor_last; | |
115 | struct descriptor *prev_descriptor; | |
116 | }; | |
117 | ||
118 | #define CONFIG_ROM_SIZE 1024 | |
119 | ||
120 | struct fw_ohci { | |
121 | struct fw_card card; | |
122 | ||
123 | __iomem char *registers; | |
124 | dma_addr_t self_id_bus; | |
125 | __le32 *self_id_cpu; | |
126 | struct tasklet_struct bus_reset_tasklet; | |
e636fe25 | 127 | int node_id; |
ed568912 KH |
128 | int generation; |
129 | int request_generation; | |
130 | ||
131 | /* Spinlock for accessing fw_ohci data. Never call out of | |
132 | * this driver with this lock held. */ | |
133 | spinlock_t lock; | |
134 | u32 self_id_buffer[512]; | |
135 | ||
136 | /* Config rom buffers */ | |
137 | __be32 *config_rom; | |
138 | dma_addr_t config_rom_bus; | |
139 | __be32 *next_config_rom; | |
140 | dma_addr_t next_config_rom_bus; | |
141 | u32 next_header; | |
142 | ||
143 | struct ar_context ar_request_ctx; | |
144 | struct ar_context ar_response_ctx; | |
145 | struct at_context at_request_ctx; | |
146 | struct at_context at_response_ctx; | |
147 | ||
148 | u32 it_context_mask; | |
149 | struct iso_context *it_context_list; | |
150 | u32 ir_context_mask; | |
151 | struct iso_context *ir_context_list; | |
152 | }; | |
153 | ||
95688e97 | 154 | static inline struct fw_ohci *fw_ohci(struct fw_card *card) |
ed568912 KH |
155 | { |
156 | return container_of(card, struct fw_ohci, card); | |
157 | } | |
158 | ||
159 | #define CONTEXT_CYCLE_MATCH_ENABLE 0x80000000 | |
160 | ||
161 | #define CONTEXT_RUN 0x8000 | |
162 | #define CONTEXT_WAKE 0x1000 | |
163 | #define CONTEXT_DEAD 0x0800 | |
164 | #define CONTEXT_ACTIVE 0x0400 | |
165 | ||
166 | #define OHCI1394_MAX_AT_REQ_RETRIES 0x2 | |
167 | #define OHCI1394_MAX_AT_RESP_RETRIES 0x2 | |
168 | #define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8 | |
169 | ||
170 | #define FW_OHCI_MAJOR 240 | |
171 | #define OHCI1394_REGISTER_SIZE 0x800 | |
172 | #define OHCI_LOOP_COUNT 500 | |
173 | #define OHCI1394_PCI_HCI_Control 0x40 | |
174 | #define SELF_ID_BUF_SIZE 0x800 | |
32b46093 | 175 | #define OHCI_TCODE_PHY_PACKET 0x0e |
0edeefd9 | 176 | |
ed568912 KH |
177 | static char ohci_driver_name[] = KBUILD_MODNAME; |
178 | ||
95688e97 | 179 | static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data) |
ed568912 KH |
180 | { |
181 | writel(data, ohci->registers + offset); | |
182 | } | |
183 | ||
95688e97 | 184 | static inline u32 reg_read(const struct fw_ohci *ohci, int offset) |
ed568912 KH |
185 | { |
186 | return readl(ohci->registers + offset); | |
187 | } | |
188 | ||
95688e97 | 189 | static inline void flush_writes(const struct fw_ohci *ohci) |
ed568912 KH |
190 | { |
191 | /* Do a dummy read to flush writes. */ | |
192 | reg_read(ohci, OHCI1394_Version); | |
193 | } | |
194 | ||
195 | static int | |
196 | ohci_update_phy_reg(struct fw_card *card, int addr, | |
197 | int clear_bits, int set_bits) | |
198 | { | |
199 | struct fw_ohci *ohci = fw_ohci(card); | |
200 | u32 val, old; | |
201 | ||
202 | reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr)); | |
203 | msleep(2); | |
204 | val = reg_read(ohci, OHCI1394_PhyControl); | |
205 | if ((val & OHCI1394_PhyControl_ReadDone) == 0) { | |
206 | fw_error("failed to set phy reg bits.\n"); | |
207 | return -EBUSY; | |
208 | } | |
209 | ||
210 | old = OHCI1394_PhyControl_ReadData(val); | |
211 | old = (old & ~clear_bits) | set_bits; | |
212 | reg_write(ohci, OHCI1394_PhyControl, | |
213 | OHCI1394_PhyControl_Write(addr, old)); | |
214 | ||
215 | return 0; | |
216 | } | |
217 | ||
32b46093 | 218 | static int ar_context_add_page(struct ar_context *ctx) |
ed568912 | 219 | { |
32b46093 KH |
220 | struct device *dev = ctx->ohci->card.device; |
221 | struct ar_buffer *ab; | |
222 | dma_addr_t ab_bus; | |
223 | size_t offset; | |
224 | ||
225 | ab = (struct ar_buffer *) __get_free_page(GFP_ATOMIC); | |
226 | if (ab == NULL) | |
227 | return -ENOMEM; | |
228 | ||
229 | ab_bus = dma_map_single(dev, ab, PAGE_SIZE, DMA_BIDIRECTIONAL); | |
230 | if (dma_mapping_error(ab_bus)) { | |
231 | free_page((unsigned long) ab); | |
232 | return -ENOMEM; | |
233 | } | |
234 | ||
235 | memset(&ab->descriptor, 0, sizeof ab->descriptor); | |
236 | ab->descriptor.control = cpu_to_le16(descriptor_input_more | | |
237 | descriptor_status | | |
238 | descriptor_branch_always); | |
239 | offset = offsetof(struct ar_buffer, data); | |
240 | ab->descriptor.req_count = cpu_to_le16(PAGE_SIZE - offset); | |
241 | ab->descriptor.data_address = cpu_to_le32(ab_bus + offset); | |
242 | ab->descriptor.res_count = cpu_to_le16(PAGE_SIZE - offset); | |
243 | ab->descriptor.branch_address = 0; | |
244 | ||
245 | dma_sync_single_for_device(dev, ab_bus, PAGE_SIZE, DMA_BIDIRECTIONAL); | |
246 | ||
247 | ctx->last_buffer->descriptor.branch_address = ab_bus | 1; | |
248 | ctx->last_buffer->next = ab; | |
249 | ctx->last_buffer = ab; | |
250 | ||
251 | reg_write(ctx->ohci, ctx->control_set, CONTEXT_WAKE); | |
ed568912 | 252 | flush_writes(ctx->ohci); |
32b46093 KH |
253 | |
254 | return 0; | |
ed568912 KH |
255 | } |
256 | ||
32b46093 | 257 | static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer) |
ed568912 | 258 | { |
ed568912 | 259 | struct fw_ohci *ohci = ctx->ohci; |
2639a6fb KH |
260 | struct fw_packet p; |
261 | u32 status, length, tcode; | |
2639a6fb | 262 | |
32b46093 KH |
263 | p.header[0] = le32_to_cpu(buffer[0]); |
264 | p.header[1] = le32_to_cpu(buffer[1]); | |
265 | p.header[2] = le32_to_cpu(buffer[2]); | |
2639a6fb KH |
266 | |
267 | tcode = (p.header[0] >> 4) & 0x0f; | |
268 | switch (tcode) { | |
269 | case TCODE_WRITE_QUADLET_REQUEST: | |
270 | case TCODE_READ_QUADLET_RESPONSE: | |
32b46093 | 271 | p.header[3] = (__force __u32) buffer[3]; |
2639a6fb | 272 | p.header_length = 16; |
32b46093 | 273 | p.payload_length = 0; |
2639a6fb KH |
274 | break; |
275 | ||
2639a6fb | 276 | case TCODE_READ_BLOCK_REQUEST : |
32b46093 KH |
277 | p.header[3] = le32_to_cpu(buffer[3]); |
278 | p.header_length = 16; | |
279 | p.payload_length = 0; | |
280 | break; | |
281 | ||
282 | case TCODE_WRITE_BLOCK_REQUEST: | |
2639a6fb KH |
283 | case TCODE_READ_BLOCK_RESPONSE: |
284 | case TCODE_LOCK_REQUEST: | |
285 | case TCODE_LOCK_RESPONSE: | |
32b46093 | 286 | p.header[3] = le32_to_cpu(buffer[3]); |
2639a6fb | 287 | p.header_length = 16; |
32b46093 | 288 | p.payload_length = p.header[3] >> 16; |
2639a6fb KH |
289 | break; |
290 | ||
291 | case TCODE_WRITE_RESPONSE: | |
292 | case TCODE_READ_QUADLET_REQUEST: | |
32b46093 | 293 | case OHCI_TCODE_PHY_PACKET: |
2639a6fb | 294 | p.header_length = 12; |
32b46093 | 295 | p.payload_length = 0; |
2639a6fb KH |
296 | break; |
297 | } | |
ed568912 | 298 | |
32b46093 KH |
299 | p.payload = (void *) buffer + p.header_length; |
300 | ||
301 | /* FIXME: What to do about evt_* errors? */ | |
302 | length = (p.header_length + p.payload_length + 3) / 4; | |
303 | status = le32_to_cpu(buffer[length]); | |
304 | ||
305 | p.ack = ((status >> 16) & 0x1f) - 16; | |
306 | p.speed = (status >> 21) & 0x7; | |
307 | p.timestamp = status & 0xffff; | |
308 | p.generation = ohci->request_generation; | |
ed568912 KH |
309 | |
310 | /* The OHCI bus reset handler synthesizes a phy packet with | |
311 | * the new generation number when a bus reset happens (see | |
312 | * section 8.4.2.3). This helps us determine when a request | |
313 | * was received and make sure we send the response in the same | |
314 | * generation. We only need this for requests; for responses | |
315 | * we use the unique tlabel for finding the matching | |
316 | * request. */ | |
317 | ||
2639a6fb | 318 | if (p.ack + 16 == 0x09) |
32b46093 | 319 | ohci->request_generation = (buffer[2] >> 16) & 0xff; |
ed568912 | 320 | else if (ctx == &ohci->ar_request_ctx) |
2639a6fb | 321 | fw_core_handle_request(&ohci->card, &p); |
ed568912 | 322 | else |
2639a6fb | 323 | fw_core_handle_response(&ohci->card, &p); |
ed568912 | 324 | |
32b46093 KH |
325 | return buffer + length + 1; |
326 | } | |
ed568912 | 327 | |
32b46093 KH |
328 | static void ar_context_tasklet(unsigned long data) |
329 | { | |
330 | struct ar_context *ctx = (struct ar_context *)data; | |
331 | struct fw_ohci *ohci = ctx->ohci; | |
332 | struct ar_buffer *ab; | |
333 | struct descriptor *d; | |
334 | void *buffer, *end; | |
335 | ||
336 | ab = ctx->current_buffer; | |
337 | d = &ab->descriptor; | |
338 | ||
339 | if (d->res_count == 0) { | |
340 | size_t size, rest, offset; | |
341 | ||
342 | /* This descriptor is finished and we may have a | |
343 | * packet split across this and the next buffer. We | |
344 | * reuse the page for reassembling the split packet. */ | |
345 | ||
346 | offset = offsetof(struct ar_buffer, data); | |
347 | dma_unmap_single(ohci->card.device, | |
348 | ab->descriptor.data_address - offset, | |
349 | PAGE_SIZE, DMA_BIDIRECTIONAL); | |
350 | ||
351 | buffer = ab; | |
352 | ab = ab->next; | |
353 | d = &ab->descriptor; | |
354 | size = buffer + PAGE_SIZE - ctx->pointer; | |
355 | rest = le16_to_cpu(d->req_count) - le16_to_cpu(d->res_count); | |
356 | memmove(buffer, ctx->pointer, size); | |
357 | memcpy(buffer + size, ab->data, rest); | |
358 | ctx->current_buffer = ab; | |
359 | ctx->pointer = (void *) ab->data + rest; | |
360 | end = buffer + size + rest; | |
361 | ||
362 | while (buffer < end) | |
363 | buffer = handle_ar_packet(ctx, buffer); | |
364 | ||
365 | free_page((unsigned long)buffer); | |
366 | ar_context_add_page(ctx); | |
367 | } else { | |
368 | buffer = ctx->pointer; | |
369 | ctx->pointer = end = | |
370 | (void *) ab + PAGE_SIZE - le16_to_cpu(d->res_count); | |
371 | ||
372 | while (buffer < end) | |
373 | buffer = handle_ar_packet(ctx, buffer); | |
374 | } | |
ed568912 KH |
375 | } |
376 | ||
377 | static int | |
378 | ar_context_init(struct ar_context *ctx, struct fw_ohci *ohci, u32 control_set) | |
379 | { | |
32b46093 | 380 | struct ar_buffer ab; |
ed568912 KH |
381 | |
382 | ctx->control_set = control_set; | |
383 | ctx->control_clear = control_set + 4; | |
384 | ctx->command_ptr = control_set + 12; | |
385 | ctx->ohci = ohci; | |
32b46093 | 386 | ctx->last_buffer = &ab; |
ed568912 KH |
387 | tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx); |
388 | ||
32b46093 KH |
389 | ar_context_add_page(ctx); |
390 | ar_context_add_page(ctx); | |
391 | ctx->current_buffer = ab.next; | |
392 | ctx->pointer = ctx->current_buffer->data; | |
393 | ||
394 | reg_write(ctx->ohci, ctx->command_ptr, ab.descriptor.branch_address); | |
395 | reg_write(ctx->ohci, ctx->control_set, CONTEXT_RUN); | |
396 | flush_writes(ctx->ohci); | |
ed568912 KH |
397 | |
398 | return 0; | |
399 | } | |
400 | ||
401 | static void | |
402 | do_packet_callbacks(struct fw_ohci *ohci, struct list_head *list) | |
403 | { | |
404 | struct fw_packet *p, *next; | |
405 | ||
406 | list_for_each_entry_safe(p, next, list, link) | |
2639a6fb | 407 | p->callback(p, &ohci->card, p->ack); |
ed568912 KH |
408 | } |
409 | ||
410 | static void | |
411 | complete_transmission(struct fw_packet *packet, | |
2639a6fb | 412 | int ack, struct list_head *list) |
ed568912 KH |
413 | { |
414 | list_move_tail(&packet->link, list); | |
2639a6fb | 415 | packet->ack = ack; |
ed568912 KH |
416 | } |
417 | ||
418 | /* This function prepares the first packet in the context queue for | |
419 | * transmission. Must always be called with the ochi->lock held to | |
420 | * ensure proper generation handling and locking around packet queue | |
421 | * manipulation. */ | |
422 | static void | |
423 | at_context_setup_packet(struct at_context *ctx, struct list_head *list) | |
424 | { | |
425 | struct fw_packet *packet; | |
426 | struct fw_ohci *ohci = ctx->ohci; | |
427 | int z, tcode; | |
428 | ||
429 | packet = fw_packet(ctx->list.next); | |
430 | ||
431 | memset(&ctx->d, 0, sizeof ctx->d); | |
432 | if (packet->payload_length > 0) { | |
433 | packet->payload_bus = dma_map_single(ohci->card.device, | |
434 | packet->payload, | |
435 | packet->payload_length, | |
436 | DMA_TO_DEVICE); | |
437 | if (packet->payload_bus == 0) { | |
e5f49c3b | 438 | complete_transmission(packet, RCODE_SEND_ERROR, list); |
ed568912 KH |
439 | return; |
440 | } | |
441 | ||
442 | ctx->d.more.control = | |
443 | cpu_to_le16(descriptor_output_more | | |
444 | descriptor_key_immediate); | |
445 | ctx->d.more.req_count = cpu_to_le16(packet->header_length); | |
446 | ctx->d.more.res_count = cpu_to_le16(packet->timestamp); | |
447 | ctx->d.last.control = | |
448 | cpu_to_le16(descriptor_output_last | | |
449 | descriptor_irq_always | | |
450 | descriptor_branch_always); | |
451 | ctx->d.last.req_count = cpu_to_le16(packet->payload_length); | |
452 | ctx->d.last.data_address = cpu_to_le32(packet->payload_bus); | |
453 | z = 3; | |
454 | } else { | |
455 | ctx->d.more.control = | |
456 | cpu_to_le16(descriptor_output_last | | |
457 | descriptor_key_immediate | | |
458 | descriptor_irq_always | | |
459 | descriptor_branch_always); | |
460 | ctx->d.more.req_count = cpu_to_le16(packet->header_length); | |
461 | ctx->d.more.res_count = cpu_to_le16(packet->timestamp); | |
462 | z = 2; | |
463 | } | |
464 | ||
465 | /* The DMA format for asyncronous link packets is different | |
466 | * from the IEEE1394 layout, so shift the fields around | |
467 | * accordingly. If header_length is 8, it's a PHY packet, to | |
468 | * which we need to prepend an extra quadlet. */ | |
469 | if (packet->header_length > 8) { | |
470 | ctx->d.header[0] = cpu_to_le32((packet->header[0] & 0xffff) | | |
471 | (packet->speed << 16)); | |
472 | ctx->d.header[1] = cpu_to_le32((packet->header[1] & 0xffff) | | |
473 | (packet->header[0] & 0xffff0000)); | |
474 | ctx->d.header[2] = cpu_to_le32(packet->header[2]); | |
475 | ||
476 | tcode = (packet->header[0] >> 4) & 0x0f; | |
477 | if (TCODE_IS_BLOCK_PACKET(tcode)) | |
478 | ctx->d.header[3] = cpu_to_le32(packet->header[3]); | |
479 | else | |
480 | ctx->d.header[3] = packet->header[3]; | |
481 | } else { | |
482 | ctx->d.header[0] = | |
483 | cpu_to_le32((OHCI1394_phy_tcode << 4) | | |
484 | (packet->speed << 16)); | |
485 | ctx->d.header[1] = cpu_to_le32(packet->header[0]); | |
486 | ctx->d.header[2] = cpu_to_le32(packet->header[1]); | |
487 | ctx->d.more.req_count = cpu_to_le16(12); | |
488 | } | |
489 | ||
490 | /* FIXME: Document how the locking works. */ | |
491 | if (ohci->generation == packet->generation) { | |
492 | reg_write(ctx->ohci, ctx->command_ptr, | |
493 | ctx->descriptor_bus | z); | |
494 | reg_write(ctx->ohci, ctx->control_set, | |
495 | CONTEXT_RUN | CONTEXT_WAKE); | |
496 | } else { | |
497 | /* We dont return error codes from this function; all | |
498 | * transmission errors are reported through the | |
499 | * callback. */ | |
e5f49c3b | 500 | complete_transmission(packet, RCODE_GENERATION, list); |
ed568912 KH |
501 | } |
502 | } | |
503 | ||
504 | static void at_context_stop(struct at_context *ctx) | |
505 | { | |
506 | u32 reg; | |
507 | ||
508 | reg_write(ctx->ohci, ctx->control_clear, CONTEXT_RUN); | |
509 | ||
510 | reg = reg_read(ctx->ohci, ctx->control_set); | |
511 | if (reg & CONTEXT_ACTIVE) | |
512 | fw_notify("Tried to stop context, but it is still active " | |
513 | "(0x%08x).\n", reg); | |
514 | } | |
515 | ||
516 | static void at_context_tasklet(unsigned long data) | |
517 | { | |
518 | struct at_context *ctx = (struct at_context *)data; | |
519 | struct fw_ohci *ohci = ctx->ohci; | |
520 | struct fw_packet *packet; | |
521 | LIST_HEAD(list); | |
522 | unsigned long flags; | |
523 | int evt; | |
524 | ||
525 | spin_lock_irqsave(&ohci->lock, flags); | |
526 | ||
527 | packet = fw_packet(ctx->list.next); | |
528 | ||
529 | at_context_stop(ctx); | |
530 | ||
531 | if (packet->payload_length > 0) { | |
532 | dma_unmap_single(ohci->card.device, packet->payload_bus, | |
533 | packet->payload_length, DMA_TO_DEVICE); | |
534 | evt = le16_to_cpu(ctx->d.last.transfer_status) & 0x1f; | |
535 | packet->timestamp = le16_to_cpu(ctx->d.last.res_count); | |
536 | } | |
537 | else { | |
538 | evt = le16_to_cpu(ctx->d.more.transfer_status) & 0x1f; | |
539 | packet->timestamp = le16_to_cpu(ctx->d.more.res_count); | |
540 | } | |
541 | ||
542 | if (evt < 16) { | |
543 | switch (evt) { | |
544 | case OHCI1394_evt_timeout: | |
545 | /* Async response transmit timed out. */ | |
e5f49c3b | 546 | complete_transmission(packet, RCODE_CANCELLED, &list); |
ed568912 KH |
547 | break; |
548 | ||
549 | case OHCI1394_evt_flushed: | |
550 | /* The packet was flushed should give same | |
551 | * error as when we try to use a stale | |
552 | * generation count. */ | |
e5f49c3b KH |
553 | complete_transmission(packet, |
554 | RCODE_GENERATION, &list); | |
ed568912 KH |
555 | break; |
556 | ||
557 | case OHCI1394_evt_missing_ack: | |
e5f49c3b KH |
558 | /* Using a valid (current) generation count, |
559 | * but the node is not on the bus or not | |
560 | * sending acks. */ | |
561 | complete_transmission(packet, RCODE_NO_ACK, &list); | |
ed568912 KH |
562 | break; |
563 | ||
564 | default: | |
e5f49c3b | 565 | complete_transmission(packet, RCODE_SEND_ERROR, &list); |
ed568912 KH |
566 | break; |
567 | } | |
568 | } else | |
569 | complete_transmission(packet, evt - 16, &list); | |
570 | ||
571 | /* If more packets are queued, set up the next one. */ | |
572 | if (!list_empty(&ctx->list)) | |
573 | at_context_setup_packet(ctx, &list); | |
574 | ||
575 | spin_unlock_irqrestore(&ohci->lock, flags); | |
576 | ||
577 | do_packet_callbacks(ohci, &list); | |
578 | } | |
579 | ||
580 | static int | |
581 | at_context_init(struct at_context *ctx, struct fw_ohci *ohci, u32 control_set) | |
582 | { | |
583 | INIT_LIST_HEAD(&ctx->list); | |
584 | ||
585 | ctx->descriptor_bus = | |
586 | dma_map_single(ohci->card.device, &ctx->d, | |
587 | sizeof ctx->d, DMA_TO_DEVICE); | |
588 | if (ctx->descriptor_bus == 0) | |
589 | return -ENOMEM; | |
590 | ||
591 | ctx->control_set = control_set; | |
592 | ctx->control_clear = control_set + 4; | |
593 | ctx->command_ptr = control_set + 12; | |
594 | ctx->ohci = ohci; | |
595 | ||
596 | tasklet_init(&ctx->tasklet, at_context_tasklet, (unsigned long)ctx); | |
597 | ||
598 | return 0; | |
599 | } | |
600 | ||
e636fe25 | 601 | #define header_get_destination(q) (((q) >> 16) & 0xffff) |
93c4cceb KH |
602 | #define header_get_tcode(q) (((q) >> 4) & 0x0f) |
603 | #define header_get_offset_high(q) (((q) >> 0) & 0xffff) | |
604 | #define header_get_data_length(q) (((q) >> 16) & 0xffff) | |
605 | #define header_get_extended_tcode(q) (((q) >> 0) & 0xffff) | |
606 | ||
607 | static void | |
608 | handle_local_rom(struct fw_ohci *ohci, struct fw_packet *packet, u32 csr) | |
609 | { | |
610 | struct fw_packet response; | |
611 | int tcode, length, i; | |
612 | ||
613 | tcode = header_get_tcode(packet->header[0]); | |
614 | if (TCODE_IS_BLOCK_PACKET(tcode)) | |
615 | length = header_get_data_length(packet->header[3]); | |
616 | else | |
617 | length = 4; | |
618 | ||
619 | i = csr - CSR_CONFIG_ROM; | |
620 | if (i + length > CONFIG_ROM_SIZE) { | |
621 | fw_fill_response(&response, packet->header, | |
622 | RCODE_ADDRESS_ERROR, NULL, 0); | |
623 | } else if (!TCODE_IS_READ_REQUEST(tcode)) { | |
624 | fw_fill_response(&response, packet->header, | |
625 | RCODE_TYPE_ERROR, NULL, 0); | |
626 | } else { | |
627 | fw_fill_response(&response, packet->header, RCODE_COMPLETE, | |
628 | (void *) ohci->config_rom + i, length); | |
629 | } | |
630 | ||
631 | fw_core_handle_response(&ohci->card, &response); | |
632 | } | |
633 | ||
634 | static void | |
635 | handle_local_lock(struct fw_ohci *ohci, struct fw_packet *packet, u32 csr) | |
636 | { | |
637 | struct fw_packet response; | |
638 | int tcode, length, ext_tcode, sel; | |
639 | __be32 *payload, lock_old; | |
640 | u32 lock_arg, lock_data; | |
641 | ||
642 | tcode = header_get_tcode(packet->header[0]); | |
643 | length = header_get_data_length(packet->header[3]); | |
644 | payload = packet->payload; | |
645 | ext_tcode = header_get_extended_tcode(packet->header[3]); | |
646 | ||
647 | if (tcode == TCODE_LOCK_REQUEST && | |
648 | ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) { | |
649 | lock_arg = be32_to_cpu(payload[0]); | |
650 | lock_data = be32_to_cpu(payload[1]); | |
651 | } else if (tcode == TCODE_READ_QUADLET_REQUEST) { | |
652 | lock_arg = 0; | |
653 | lock_data = 0; | |
654 | } else { | |
655 | fw_fill_response(&response, packet->header, | |
656 | RCODE_TYPE_ERROR, NULL, 0); | |
657 | goto out; | |
658 | } | |
659 | ||
660 | sel = (csr - CSR_BUS_MANAGER_ID) / 4; | |
661 | reg_write(ohci, OHCI1394_CSRData, lock_data); | |
662 | reg_write(ohci, OHCI1394_CSRCompareData, lock_arg); | |
663 | reg_write(ohci, OHCI1394_CSRControl, sel); | |
664 | ||
665 | if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000) | |
666 | lock_old = cpu_to_be32(reg_read(ohci, OHCI1394_CSRData)); | |
667 | else | |
668 | fw_notify("swap not done yet\n"); | |
669 | ||
670 | fw_fill_response(&response, packet->header, | |
671 | RCODE_COMPLETE, &lock_old, sizeof lock_old); | |
672 | out: | |
673 | fw_core_handle_response(&ohci->card, &response); | |
674 | } | |
675 | ||
676 | static void | |
677 | handle_local_request(struct at_context *ctx, struct fw_packet *packet) | |
678 | { | |
679 | u64 offset; | |
680 | u32 csr; | |
681 | ||
682 | packet->ack = ACK_PENDING; | |
683 | packet->callback(packet, &ctx->ohci->card, packet->ack); | |
684 | ||
685 | offset = | |
686 | ((unsigned long long) | |
687 | header_get_offset_high(packet->header[1]) << 32) | | |
688 | packet->header[2]; | |
689 | csr = offset - CSR_REGISTER_BASE; | |
690 | ||
691 | /* Handle config rom reads. */ | |
692 | if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END) | |
693 | handle_local_rom(ctx->ohci, packet, csr); | |
694 | else switch (csr) { | |
695 | case CSR_BUS_MANAGER_ID: | |
696 | case CSR_BANDWIDTH_AVAILABLE: | |
697 | case CSR_CHANNELS_AVAILABLE_HI: | |
698 | case CSR_CHANNELS_AVAILABLE_LO: | |
699 | handle_local_lock(ctx->ohci, packet, csr); | |
700 | break; | |
701 | default: | |
702 | if (ctx == &ctx->ohci->at_request_ctx) | |
703 | fw_core_handle_request(&ctx->ohci->card, packet); | |
704 | else | |
705 | fw_core_handle_response(&ctx->ohci->card, packet); | |
706 | break; | |
707 | } | |
708 | } | |
e636fe25 | 709 | |
ed568912 KH |
710 | static void |
711 | at_context_transmit(struct at_context *ctx, struct fw_packet *packet) | |
712 | { | |
713 | LIST_HEAD(list); | |
714 | unsigned long flags; | |
ed568912 KH |
715 | |
716 | spin_lock_irqsave(&ctx->ohci->lock, flags); | |
717 | ||
e636fe25 KH |
718 | if (header_get_destination(packet->header[0]) == ctx->ohci->node_id && |
719 | ctx->ohci->generation == packet->generation) { | |
93c4cceb KH |
720 | spin_unlock_irqrestore(&ctx->ohci->lock, flags); |
721 | handle_local_request(ctx, packet); | |
722 | return; | |
e636fe25 | 723 | } |
ed568912 | 724 | |
93c4cceb KH |
725 | list_add_tail(&packet->link, &ctx->list); |
726 | if (ctx->list.next == &packet->link) | |
727 | at_context_setup_packet(ctx, &list); | |
728 | ||
ed568912 KH |
729 | spin_unlock_irqrestore(&ctx->ohci->lock, flags); |
730 | ||
731 | do_packet_callbacks(ctx->ohci, &list); | |
732 | } | |
733 | ||
734 | static void bus_reset_tasklet(unsigned long data) | |
735 | { | |
736 | struct fw_ohci *ohci = (struct fw_ohci *)data; | |
e636fe25 | 737 | int self_id_count, i, j, reg; |
ed568912 KH |
738 | int generation, new_generation; |
739 | unsigned long flags; | |
740 | ||
741 | reg = reg_read(ohci, OHCI1394_NodeID); | |
742 | if (!(reg & OHCI1394_NodeID_idValid)) { | |
743 | fw_error("node ID not valid, new bus reset in progress\n"); | |
744 | return; | |
745 | } | |
e636fe25 | 746 | ohci->node_id = reg & 0xffff; |
ed568912 KH |
747 | |
748 | /* The count in the SelfIDCount register is the number of | |
749 | * bytes in the self ID receive buffer. Since we also receive | |
750 | * the inverted quadlets and a header quadlet, we shift one | |
751 | * bit extra to get the actual number of self IDs. */ | |
752 | ||
753 | self_id_count = (reg_read(ohci, OHCI1394_SelfIDCount) >> 3) & 0x3ff; | |
754 | generation = (le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff; | |
755 | ||
756 | for (i = 1, j = 0; j < self_id_count; i += 2, j++) { | |
757 | if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1]) | |
758 | fw_error("inconsistent self IDs\n"); | |
759 | ohci->self_id_buffer[j] = le32_to_cpu(ohci->self_id_cpu[i]); | |
760 | } | |
761 | ||
762 | /* Check the consistency of the self IDs we just read. The | |
763 | * problem we face is that a new bus reset can start while we | |
764 | * read out the self IDs from the DMA buffer. If this happens, | |
765 | * the DMA buffer will be overwritten with new self IDs and we | |
766 | * will read out inconsistent data. The OHCI specification | |
767 | * (section 11.2) recommends a technique similar to | |
768 | * linux/seqlock.h, where we remember the generation of the | |
769 | * self IDs in the buffer before reading them out and compare | |
770 | * it to the current generation after reading them out. If | |
771 | * the two generations match we know we have a consistent set | |
772 | * of self IDs. */ | |
773 | ||
774 | new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff; | |
775 | if (new_generation != generation) { | |
776 | fw_notify("recursive bus reset detected, " | |
777 | "discarding self ids\n"); | |
778 | return; | |
779 | } | |
780 | ||
781 | /* FIXME: Document how the locking works. */ | |
782 | spin_lock_irqsave(&ohci->lock, flags); | |
783 | ||
784 | ohci->generation = generation; | |
785 | at_context_stop(&ohci->at_request_ctx); | |
786 | at_context_stop(&ohci->at_response_ctx); | |
787 | reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset); | |
788 | ||
789 | /* This next bit is unrelated to the AT context stuff but we | |
790 | * have to do it under the spinlock also. If a new config rom | |
791 | * was set up before this reset, the old one is now no longer | |
792 | * in use and we can free it. Update the config rom pointers | |
793 | * to point to the current config rom and clear the | |
794 | * next_config_rom pointer so a new udpate can take place. */ | |
795 | ||
796 | if (ohci->next_config_rom != NULL) { | |
797 | dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, | |
798 | ohci->config_rom, ohci->config_rom_bus); | |
799 | ohci->config_rom = ohci->next_config_rom; | |
800 | ohci->config_rom_bus = ohci->next_config_rom_bus; | |
801 | ohci->next_config_rom = NULL; | |
802 | ||
803 | /* Restore config_rom image and manually update | |
804 | * config_rom registers. Writing the header quadlet | |
805 | * will indicate that the config rom is ready, so we | |
806 | * do that last. */ | |
807 | reg_write(ohci, OHCI1394_BusOptions, | |
808 | be32_to_cpu(ohci->config_rom[2])); | |
809 | ohci->config_rom[0] = cpu_to_be32(ohci->next_header); | |
810 | reg_write(ohci, OHCI1394_ConfigROMhdr, ohci->next_header); | |
811 | } | |
812 | ||
813 | spin_unlock_irqrestore(&ohci->lock, flags); | |
814 | ||
e636fe25 | 815 | fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation, |
ed568912 KH |
816 | self_id_count, ohci->self_id_buffer); |
817 | } | |
818 | ||
819 | static irqreturn_t irq_handler(int irq, void *data) | |
820 | { | |
821 | struct fw_ohci *ohci = data; | |
822 | u32 event, iso_event; | |
823 | int i; | |
824 | ||
825 | event = reg_read(ohci, OHCI1394_IntEventClear); | |
826 | ||
827 | if (!event) | |
828 | return IRQ_NONE; | |
829 | ||
830 | reg_write(ohci, OHCI1394_IntEventClear, event); | |
831 | ||
832 | if (event & OHCI1394_selfIDComplete) | |
833 | tasklet_schedule(&ohci->bus_reset_tasklet); | |
834 | ||
835 | if (event & OHCI1394_RQPkt) | |
836 | tasklet_schedule(&ohci->ar_request_ctx.tasklet); | |
837 | ||
838 | if (event & OHCI1394_RSPkt) | |
839 | tasklet_schedule(&ohci->ar_response_ctx.tasklet); | |
840 | ||
841 | if (event & OHCI1394_reqTxComplete) | |
842 | tasklet_schedule(&ohci->at_request_ctx.tasklet); | |
843 | ||
844 | if (event & OHCI1394_respTxComplete) | |
845 | tasklet_schedule(&ohci->at_response_ctx.tasklet); | |
846 | ||
847 | iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventSet); | |
848 | reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event); | |
849 | ||
850 | while (iso_event) { | |
851 | i = ffs(iso_event) - 1; | |
852 | tasklet_schedule(&ohci->ir_context_list[i].tasklet); | |
853 | iso_event &= ~(1 << i); | |
854 | } | |
855 | ||
856 | iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventSet); | |
857 | reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event); | |
858 | ||
859 | while (iso_event) { | |
860 | i = ffs(iso_event) - 1; | |
861 | tasklet_schedule(&ohci->it_context_list[i].tasklet); | |
862 | iso_event &= ~(1 << i); | |
863 | } | |
864 | ||
865 | return IRQ_HANDLED; | |
866 | } | |
867 | ||
868 | static int ohci_enable(struct fw_card *card, u32 *config_rom, size_t length) | |
869 | { | |
870 | struct fw_ohci *ohci = fw_ohci(card); | |
871 | struct pci_dev *dev = to_pci_dev(card->device); | |
872 | ||
873 | /* When the link is not yet enabled, the atomic config rom | |
874 | * update mechanism described below in ohci_set_config_rom() | |
875 | * is not active. We have to update ConfigRomHeader and | |
876 | * BusOptions manually, and the write to ConfigROMmap takes | |
877 | * effect immediately. We tie this to the enabling of the | |
878 | * link, so we have a valid config rom before enabling - the | |
879 | * OHCI requires that ConfigROMhdr and BusOptions have valid | |
880 | * values before enabling. | |
881 | * | |
882 | * However, when the ConfigROMmap is written, some controllers | |
883 | * always read back quadlets 0 and 2 from the config rom to | |
884 | * the ConfigRomHeader and BusOptions registers on bus reset. | |
885 | * They shouldn't do that in this initial case where the link | |
886 | * isn't enabled. This means we have to use the same | |
887 | * workaround here, setting the bus header to 0 and then write | |
888 | * the right values in the bus reset tasklet. | |
889 | */ | |
890 | ||
891 | ohci->next_config_rom = | |
892 | dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE, | |
893 | &ohci->next_config_rom_bus, GFP_KERNEL); | |
894 | if (ohci->next_config_rom == NULL) | |
895 | return -ENOMEM; | |
896 | ||
897 | memset(ohci->next_config_rom, 0, CONFIG_ROM_SIZE); | |
898 | fw_memcpy_to_be32(ohci->next_config_rom, config_rom, length * 4); | |
899 | ||
900 | ohci->next_header = config_rom[0]; | |
901 | ohci->next_config_rom[0] = 0; | |
902 | reg_write(ohci, OHCI1394_ConfigROMhdr, 0); | |
903 | reg_write(ohci, OHCI1394_BusOptions, config_rom[2]); | |
904 | reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus); | |
905 | ||
906 | reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000); | |
907 | ||
908 | if (request_irq(dev->irq, irq_handler, | |
909 | SA_SHIRQ, ohci_driver_name, ohci)) { | |
910 | fw_error("Failed to allocate shared interrupt %d.\n", | |
911 | dev->irq); | |
912 | dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, | |
913 | ohci->config_rom, ohci->config_rom_bus); | |
914 | return -EIO; | |
915 | } | |
916 | ||
917 | reg_write(ohci, OHCI1394_HCControlSet, | |
918 | OHCI1394_HCControl_linkEnable | | |
919 | OHCI1394_HCControl_BIBimageValid); | |
920 | flush_writes(ohci); | |
921 | ||
922 | /* We are ready to go, initiate bus reset to finish the | |
923 | * initialization. */ | |
924 | ||
925 | fw_core_initiate_bus_reset(&ohci->card, 1); | |
926 | ||
927 | return 0; | |
928 | } | |
929 | ||
930 | static int | |
931 | ohci_set_config_rom(struct fw_card *card, u32 *config_rom, size_t length) | |
932 | { | |
933 | struct fw_ohci *ohci; | |
934 | unsigned long flags; | |
935 | int retval = 0; | |
936 | __be32 *next_config_rom; | |
937 | dma_addr_t next_config_rom_bus; | |
938 | ||
939 | ohci = fw_ohci(card); | |
940 | ||
941 | /* When the OHCI controller is enabled, the config rom update | |
942 | * mechanism is a bit tricky, but easy enough to use. See | |
943 | * section 5.5.6 in the OHCI specification. | |
944 | * | |
945 | * The OHCI controller caches the new config rom address in a | |
946 | * shadow register (ConfigROMmapNext) and needs a bus reset | |
947 | * for the changes to take place. When the bus reset is | |
948 | * detected, the controller loads the new values for the | |
949 | * ConfigRomHeader and BusOptions registers from the specified | |
950 | * config rom and loads ConfigROMmap from the ConfigROMmapNext | |
951 | * shadow register. All automatically and atomically. | |
952 | * | |
953 | * Now, there's a twist to this story. The automatic load of | |
954 | * ConfigRomHeader and BusOptions doesn't honor the | |
955 | * noByteSwapData bit, so with a be32 config rom, the | |
956 | * controller will load be32 values in to these registers | |
957 | * during the atomic update, even on litte endian | |
958 | * architectures. The workaround we use is to put a 0 in the | |
959 | * header quadlet; 0 is endian agnostic and means that the | |
960 | * config rom isn't ready yet. In the bus reset tasklet we | |
961 | * then set up the real values for the two registers. | |
962 | * | |
963 | * We use ohci->lock to avoid racing with the code that sets | |
964 | * ohci->next_config_rom to NULL (see bus_reset_tasklet). | |
965 | */ | |
966 | ||
967 | next_config_rom = | |
968 | dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE, | |
969 | &next_config_rom_bus, GFP_KERNEL); | |
970 | if (next_config_rom == NULL) | |
971 | return -ENOMEM; | |
972 | ||
973 | spin_lock_irqsave(&ohci->lock, flags); | |
974 | ||
975 | if (ohci->next_config_rom == NULL) { | |
976 | ohci->next_config_rom = next_config_rom; | |
977 | ohci->next_config_rom_bus = next_config_rom_bus; | |
978 | ||
979 | memset(ohci->next_config_rom, 0, CONFIG_ROM_SIZE); | |
980 | fw_memcpy_to_be32(ohci->next_config_rom, config_rom, | |
981 | length * 4); | |
982 | ||
983 | ohci->next_header = config_rom[0]; | |
984 | ohci->next_config_rom[0] = 0; | |
985 | ||
986 | reg_write(ohci, OHCI1394_ConfigROMmap, | |
987 | ohci->next_config_rom_bus); | |
988 | } else { | |
989 | dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, | |
990 | next_config_rom, next_config_rom_bus); | |
991 | retval = -EBUSY; | |
992 | } | |
993 | ||
994 | spin_unlock_irqrestore(&ohci->lock, flags); | |
995 | ||
996 | /* Now initiate a bus reset to have the changes take | |
997 | * effect. We clean up the old config rom memory and DMA | |
998 | * mappings in the bus reset tasklet, since the OHCI | |
999 | * controller could need to access it before the bus reset | |
1000 | * takes effect. */ | |
1001 | if (retval == 0) | |
1002 | fw_core_initiate_bus_reset(&ohci->card, 1); | |
1003 | ||
1004 | return retval; | |
1005 | } | |
1006 | ||
1007 | static void ohci_send_request(struct fw_card *card, struct fw_packet *packet) | |
1008 | { | |
1009 | struct fw_ohci *ohci = fw_ohci(card); | |
1010 | ||
1011 | at_context_transmit(&ohci->at_request_ctx, packet); | |
1012 | } | |
1013 | ||
1014 | static void ohci_send_response(struct fw_card *card, struct fw_packet *packet) | |
1015 | { | |
1016 | struct fw_ohci *ohci = fw_ohci(card); | |
1017 | ||
1018 | at_context_transmit(&ohci->at_response_ctx, packet); | |
1019 | } | |
1020 | ||
1021 | static int | |
1022 | ohci_enable_phys_dma(struct fw_card *card, int node_id, int generation) | |
1023 | { | |
1024 | struct fw_ohci *ohci = fw_ohci(card); | |
1025 | unsigned long flags; | |
907293d7 | 1026 | int n, retval = 0; |
ed568912 | 1027 | |
907293d7 SR |
1028 | /* FIXME: Make sure this bitmask is cleared when we clear the busReset |
1029 | * interrupt bit. Clear physReqResourceAllBuses on bus reset. */ | |
ed568912 KH |
1030 | |
1031 | spin_lock_irqsave(&ohci->lock, flags); | |
1032 | ||
1033 | if (ohci->generation != generation) { | |
1034 | retval = -ESTALE; | |
1035 | goto out; | |
1036 | } | |
1037 | ||
907293d7 SR |
1038 | /* NOTE, if the node ID contains a non-local bus ID, physical DMA is |
1039 | * enabled for _all_ nodes on remote buses. */ | |
1040 | ||
1041 | n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63; | |
1042 | if (n < 32) | |
1043 | reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n); | |
1044 | else | |
1045 | reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32)); | |
1046 | ||
ed568912 | 1047 | flush_writes(ohci); |
ed568912 | 1048 | out: |
6cad95fe | 1049 | spin_unlock_irqrestore(&ohci->lock, flags); |
ed568912 KH |
1050 | return retval; |
1051 | } | |
1052 | ||
1053 | static void ir_context_tasklet(unsigned long data) | |
1054 | { | |
1055 | struct iso_context *ctx = (struct iso_context *)data; | |
1056 | ||
1057 | (void)ctx; | |
1058 | } | |
1059 | ||
1060 | #define ISO_BUFFER_SIZE (64 * 1024) | |
1061 | ||
1062 | static void flush_iso_context(struct iso_context *ctx) | |
1063 | { | |
1064 | struct fw_ohci *ohci = fw_ohci(ctx->base.card); | |
1065 | struct descriptor *d, *last; | |
1066 | u32 address; | |
1067 | int z; | |
1068 | ||
1069 | dma_sync_single_for_cpu(ohci->card.device, ctx->buffer_bus, | |
1070 | ISO_BUFFER_SIZE, DMA_TO_DEVICE); | |
1071 | ||
1072 | d = ctx->tail_descriptor; | |
1073 | last = ctx->tail_descriptor_last; | |
1074 | ||
1075 | while (last->branch_address != 0 && last->transfer_status != 0) { | |
1076 | address = le32_to_cpu(last->branch_address); | |
1077 | z = address & 0xf; | |
1078 | d = ctx->buffer + (address - ctx->buffer_bus) / sizeof *d; | |
1079 | ||
1080 | if (z == 2) | |
1081 | last = d; | |
1082 | else | |
1083 | last = d + z - 1; | |
1084 | ||
1085 | if (le16_to_cpu(last->control) & descriptor_irq_always) | |
1086 | ctx->base.callback(&ctx->base, | |
1087 | 0, le16_to_cpu(last->res_count), | |
1088 | ctx->base.callback_data); | |
1089 | } | |
1090 | ||
1091 | ctx->tail_descriptor = d; | |
1092 | ctx->tail_descriptor_last = last; | |
1093 | } | |
1094 | ||
1095 | static void it_context_tasklet(unsigned long data) | |
1096 | { | |
1097 | struct iso_context *ctx = (struct iso_context *)data; | |
1098 | ||
1099 | flush_iso_context(ctx); | |
1100 | } | |
1101 | ||
1102 | static struct fw_iso_context *ohci_allocate_iso_context(struct fw_card *card, | |
1103 | int type) | |
1104 | { | |
1105 | struct fw_ohci *ohci = fw_ohci(card); | |
1106 | struct iso_context *ctx, *list; | |
1107 | void (*tasklet) (unsigned long data); | |
1108 | u32 *mask; | |
1109 | unsigned long flags; | |
1110 | int index; | |
1111 | ||
1112 | if (type == FW_ISO_CONTEXT_TRANSMIT) { | |
1113 | mask = &ohci->it_context_mask; | |
1114 | list = ohci->it_context_list; | |
1115 | tasklet = it_context_tasklet; | |
1116 | } else { | |
1117 | mask = &ohci->ir_context_mask; | |
1118 | list = ohci->ir_context_list; | |
1119 | tasklet = ir_context_tasklet; | |
1120 | } | |
1121 | ||
1122 | spin_lock_irqsave(&ohci->lock, flags); | |
1123 | index = ffs(*mask) - 1; | |
1124 | if (index >= 0) | |
1125 | *mask &= ~(1 << index); | |
1126 | spin_unlock_irqrestore(&ohci->lock, flags); | |
1127 | ||
1128 | if (index < 0) | |
1129 | return ERR_PTR(-EBUSY); | |
1130 | ||
1131 | ctx = &list[index]; | |
1132 | memset(ctx, 0, sizeof *ctx); | |
1133 | tasklet_init(&ctx->tasklet, tasklet, (unsigned long)ctx); | |
1134 | ||
1135 | ctx->buffer = kmalloc(ISO_BUFFER_SIZE, GFP_KERNEL); | |
1136 | if (ctx->buffer == NULL) { | |
1137 | spin_lock_irqsave(&ohci->lock, flags); | |
1138 | *mask |= 1 << index; | |
1139 | spin_unlock_irqrestore(&ohci->lock, flags); | |
1140 | return ERR_PTR(-ENOMEM); | |
1141 | } | |
1142 | ||
1143 | ctx->buffer_bus = | |
1144 | dma_map_single(card->device, ctx->buffer, | |
1145 | ISO_BUFFER_SIZE, DMA_TO_DEVICE); | |
1146 | ||
1147 | ctx->head_descriptor = ctx->buffer; | |
1148 | ctx->prev_descriptor = ctx->buffer; | |
1149 | ctx->tail_descriptor = ctx->buffer; | |
1150 | ctx->tail_descriptor_last = ctx->buffer; | |
1151 | ||
1152 | /* We put a dummy descriptor in the buffer that has a NULL | |
1153 | * branch address and looks like it's been sent. That way we | |
1154 | * have a descriptor to append DMA programs to. Also, the | |
1155 | * ring buffer invariant is that it always has at least one | |
1156 | * element so that head == tail means buffer full. */ | |
1157 | ||
1158 | memset(ctx->head_descriptor, 0, sizeof *ctx->head_descriptor); | |
5e20c282 SR |
1159 | ctx->head_descriptor->control = cpu_to_le16(descriptor_output_last); |
1160 | ctx->head_descriptor->transfer_status = cpu_to_le16(0x8011); | |
ed568912 KH |
1161 | ctx->head_descriptor++; |
1162 | ||
1163 | return &ctx->base; | |
1164 | } | |
1165 | ||
1166 | static int ohci_send_iso(struct fw_iso_context *base, s32 cycle) | |
1167 | { | |
1168 | struct iso_context *ctx = (struct iso_context *)base; | |
1169 | struct fw_ohci *ohci = fw_ohci(ctx->base.card); | |
1170 | u32 cycle_match = 0; | |
1171 | int index; | |
1172 | ||
1173 | index = ctx - ohci->it_context_list; | |
1174 | if (cycle > 0) | |
1175 | cycle_match = CONTEXT_CYCLE_MATCH_ENABLE | | |
1176 | (cycle & 0x7fff) << 16; | |
1177 | ||
1178 | reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index); | |
1179 | reg_write(ohci, OHCI1394_IsoXmitCommandPtr(index), | |
1180 | le32_to_cpu(ctx->tail_descriptor_last->branch_address)); | |
1181 | reg_write(ohci, OHCI1394_IsoXmitContextControlClear(index), ~0); | |
1182 | reg_write(ohci, OHCI1394_IsoXmitContextControlSet(index), | |
1183 | CONTEXT_RUN | cycle_match); | |
1184 | flush_writes(ohci); | |
1185 | ||
1186 | return 0; | |
1187 | } | |
1188 | ||
1189 | static void ohci_free_iso_context(struct fw_iso_context *base) | |
1190 | { | |
1191 | struct fw_ohci *ohci = fw_ohci(base->card); | |
1192 | struct iso_context *ctx = (struct iso_context *)base; | |
1193 | unsigned long flags; | |
1194 | int index; | |
1195 | ||
1196 | flush_iso_context(ctx); | |
1197 | ||
1198 | spin_lock_irqsave(&ohci->lock, flags); | |
1199 | ||
1200 | if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) { | |
1201 | index = ctx - ohci->it_context_list; | |
1202 | reg_write(ohci, OHCI1394_IsoXmitContextControlClear(index), ~0); | |
1203 | reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index); | |
1204 | ohci->it_context_mask |= 1 << index; | |
1205 | } else { | |
1206 | index = ctx - ohci->ir_context_list; | |
1207 | reg_write(ohci, OHCI1394_IsoRcvContextControlClear(index), ~0); | |
1208 | reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index); | |
1209 | ohci->ir_context_mask |= 1 << index; | |
1210 | } | |
1211 | flush_writes(ohci); | |
1212 | ||
1213 | dma_unmap_single(ohci->card.device, ctx->buffer_bus, | |
1214 | ISO_BUFFER_SIZE, DMA_TO_DEVICE); | |
1215 | ||
1216 | spin_unlock_irqrestore(&ohci->lock, flags); | |
1217 | } | |
1218 | ||
1219 | static int | |
1220 | ohci_queue_iso(struct fw_iso_context *base, | |
1221 | struct fw_iso_packet *packet, void *payload) | |
1222 | { | |
1223 | struct iso_context *ctx = (struct iso_context *)base; | |
1224 | struct fw_ohci *ohci = fw_ohci(ctx->base.card); | |
1225 | struct descriptor *d, *end, *last, *tail, *pd; | |
1226 | struct fw_iso_packet *p; | |
1227 | __le32 *header; | |
1228 | dma_addr_t d_bus; | |
1229 | u32 z, header_z, payload_z, irq; | |
1230 | u32 payload_index, payload_end_index, next_page_index; | |
1231 | int index, page, end_page, i, length, offset; | |
1232 | ||
1233 | /* FIXME: Cycle lost behavior should be configurable: lose | |
1234 | * packet, retransmit or terminate.. */ | |
1235 | ||
1236 | p = packet; | |
1237 | payload_index = payload - ctx->base.buffer; | |
1238 | d = ctx->head_descriptor; | |
1239 | tail = ctx->tail_descriptor; | |
1240 | end = ctx->buffer + ISO_BUFFER_SIZE / sizeof(struct descriptor); | |
1241 | ||
1242 | if (p->skip) | |
1243 | z = 1; | |
1244 | else | |
1245 | z = 2; | |
1246 | if (p->header_length > 0) | |
1247 | z++; | |
1248 | ||
1249 | /* Determine the first page the payload isn't contained in. */ | |
1250 | end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT; | |
1251 | if (p->payload_length > 0) | |
1252 | payload_z = end_page - (payload_index >> PAGE_SHIFT); | |
1253 | else | |
1254 | payload_z = 0; | |
1255 | ||
1256 | z += payload_z; | |
1257 | ||
1258 | /* Get header size in number of descriptors. */ | |
1259 | header_z = DIV_ROUND_UP(p->header_length, sizeof *d); | |
1260 | ||
1261 | if (d + z + header_z <= tail) { | |
1262 | goto has_space; | |
1263 | } else if (d > tail && d + z + header_z <= end) { | |
1264 | goto has_space; | |
1265 | } else if (d > tail && ctx->buffer + z + header_z <= tail) { | |
1266 | d = ctx->buffer; | |
1267 | goto has_space; | |
1268 | } | |
1269 | ||
1270 | /* No space in buffer */ | |
1271 | return -1; | |
1272 | ||
1273 | has_space: | |
1274 | memset(d, 0, (z + header_z) * sizeof *d); | |
1275 | d_bus = ctx->buffer_bus + (d - ctx->buffer) * sizeof *d; | |
1276 | ||
1277 | if (!p->skip) { | |
1278 | d[0].control = cpu_to_le16(descriptor_key_immediate); | |
1279 | d[0].req_count = cpu_to_le16(8); | |
1280 | ||
1281 | header = (__le32 *) &d[1]; | |
1282 | header[0] = cpu_to_le32(it_header_sy(p->sy) | | |
1283 | it_header_tag(p->tag) | | |
1284 | it_header_tcode(TCODE_STREAM_DATA) | | |
1285 | it_header_channel(ctx->base.channel) | | |
1286 | it_header_speed(ctx->base.speed)); | |
1287 | header[1] = | |
1288 | cpu_to_le32(it_header_data_length(p->header_length + | |
1289 | p->payload_length)); | |
1290 | } | |
1291 | ||
1292 | if (p->header_length > 0) { | |
1293 | d[2].req_count = cpu_to_le16(p->header_length); | |
1294 | d[2].data_address = cpu_to_le32(d_bus + z * sizeof *d); | |
1295 | memcpy(&d[z], p->header, p->header_length); | |
1296 | } | |
1297 | ||
1298 | pd = d + z - payload_z; | |
1299 | payload_end_index = payload_index + p->payload_length; | |
1300 | for (i = 0; i < payload_z; i++) { | |
1301 | page = payload_index >> PAGE_SHIFT; | |
1302 | offset = payload_index & ~PAGE_MASK; | |
1303 | next_page_index = (page + 1) << PAGE_SHIFT; | |
1304 | length = | |
1305 | min(next_page_index, payload_end_index) - payload_index; | |
1306 | pd[i].req_count = cpu_to_le16(length); | |
1307 | pd[i].data_address = cpu_to_le32(ctx->base.pages[page] + offset); | |
1308 | ||
1309 | payload_index += length; | |
1310 | } | |
1311 | ||
1312 | if (z == 2) | |
1313 | last = d; | |
1314 | else | |
1315 | last = d + z - 1; | |
1316 | ||
1317 | if (p->interrupt) | |
1318 | irq = descriptor_irq_always; | |
1319 | else | |
1320 | irq = descriptor_no_irq; | |
1321 | ||
1322 | last->control = cpu_to_le16(descriptor_output_last | | |
1323 | descriptor_status | | |
1324 | descriptor_branch_always | | |
1325 | irq); | |
1326 | ||
1327 | dma_sync_single_for_device(ohci->card.device, ctx->buffer_bus, | |
1328 | ISO_BUFFER_SIZE, DMA_TO_DEVICE); | |
1329 | ||
1330 | ctx->head_descriptor = d + z + header_z; | |
1331 | ctx->prev_descriptor->branch_address = cpu_to_le32(d_bus | z); | |
1332 | ctx->prev_descriptor = last; | |
1333 | ||
1334 | index = ctx - ohci->it_context_list; | |
1335 | reg_write(ohci, OHCI1394_IsoXmitContextControlSet(index), CONTEXT_WAKE); | |
1336 | flush_writes(ohci); | |
1337 | ||
1338 | return 0; | |
1339 | } | |
1340 | ||
21ebcd12 | 1341 | static const struct fw_card_driver ohci_driver = { |
ed568912 KH |
1342 | .name = ohci_driver_name, |
1343 | .enable = ohci_enable, | |
1344 | .update_phy_reg = ohci_update_phy_reg, | |
1345 | .set_config_rom = ohci_set_config_rom, | |
1346 | .send_request = ohci_send_request, | |
1347 | .send_response = ohci_send_response, | |
1348 | .enable_phys_dma = ohci_enable_phys_dma, | |
1349 | ||
1350 | .allocate_iso_context = ohci_allocate_iso_context, | |
1351 | .free_iso_context = ohci_free_iso_context, | |
1352 | .queue_iso = ohci_queue_iso, | |
5af4e5ea | 1353 | .send_iso = ohci_send_iso, |
ed568912 KH |
1354 | }; |
1355 | ||
1356 | static int software_reset(struct fw_ohci *ohci) | |
1357 | { | |
1358 | int i; | |
1359 | ||
1360 | reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset); | |
1361 | ||
1362 | for (i = 0; i < OHCI_LOOP_COUNT; i++) { | |
1363 | if ((reg_read(ohci, OHCI1394_HCControlSet) & | |
1364 | OHCI1394_HCControl_softReset) == 0) | |
1365 | return 0; | |
1366 | msleep(1); | |
1367 | } | |
1368 | ||
1369 | return -EBUSY; | |
1370 | } | |
1371 | ||
1372 | /* ---------- pci subsystem interface ---------- */ | |
1373 | ||
1374 | enum { | |
1375 | CLEANUP_SELF_ID, | |
1376 | CLEANUP_REGISTERS, | |
1377 | CLEANUP_IOMEM, | |
1378 | CLEANUP_DISABLE, | |
1379 | CLEANUP_PUT_CARD, | |
1380 | }; | |
1381 | ||
1382 | static int cleanup(struct fw_ohci *ohci, int stage, int code) | |
1383 | { | |
1384 | struct pci_dev *dev = to_pci_dev(ohci->card.device); | |
1385 | ||
1386 | switch (stage) { | |
1387 | case CLEANUP_SELF_ID: | |
1388 | dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE, | |
1389 | ohci->self_id_cpu, ohci->self_id_bus); | |
1390 | case CLEANUP_REGISTERS: | |
1391 | kfree(ohci->it_context_list); | |
1392 | kfree(ohci->ir_context_list); | |
1393 | pci_iounmap(dev, ohci->registers); | |
1394 | case CLEANUP_IOMEM: | |
1395 | pci_release_region(dev, 0); | |
1396 | case CLEANUP_DISABLE: | |
1397 | pci_disable_device(dev); | |
1398 | case CLEANUP_PUT_CARD: | |
1399 | fw_card_put(&ohci->card); | |
1400 | } | |
1401 | ||
1402 | return code; | |
1403 | } | |
1404 | ||
1405 | static int __devinit | |
1406 | pci_probe(struct pci_dev *dev, const struct pci_device_id *ent) | |
1407 | { | |
1408 | struct fw_ohci *ohci; | |
1409 | u32 bus_options, max_receive, link_speed; | |
1410 | u64 guid; | |
1411 | int error_code; | |
1412 | size_t size; | |
1413 | ||
1414 | ohci = kzalloc(sizeof *ohci, GFP_KERNEL); | |
1415 | if (ohci == NULL) { | |
1416 | fw_error("Could not malloc fw_ohci data.\n"); | |
1417 | return -ENOMEM; | |
1418 | } | |
1419 | ||
1420 | fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev); | |
1421 | ||
1422 | if (pci_enable_device(dev)) { | |
1423 | fw_error("Failed to enable OHCI hardware.\n"); | |
1424 | return cleanup(ohci, CLEANUP_PUT_CARD, -ENODEV); | |
1425 | } | |
1426 | ||
1427 | pci_set_master(dev); | |
1428 | pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0); | |
1429 | pci_set_drvdata(dev, ohci); | |
1430 | ||
1431 | spin_lock_init(&ohci->lock); | |
1432 | ||
1433 | tasklet_init(&ohci->bus_reset_tasklet, | |
1434 | bus_reset_tasklet, (unsigned long)ohci); | |
1435 | ||
1436 | if (pci_request_region(dev, 0, ohci_driver_name)) { | |
1437 | fw_error("MMIO resource unavailable\n"); | |
1438 | return cleanup(ohci, CLEANUP_DISABLE, -EBUSY); | |
1439 | } | |
1440 | ||
1441 | ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE); | |
1442 | if (ohci->registers == NULL) { | |
1443 | fw_error("Failed to remap registers\n"); | |
1444 | return cleanup(ohci, CLEANUP_IOMEM, -ENXIO); | |
1445 | } | |
1446 | ||
1447 | if (software_reset(ohci)) { | |
1448 | fw_error("Failed to reset ohci card.\n"); | |
1449 | return cleanup(ohci, CLEANUP_REGISTERS, -EBUSY); | |
1450 | } | |
1451 | ||
1452 | /* Now enable LPS, which we need in order to start accessing | |
1453 | * most of the registers. In fact, on some cards (ALI M5251), | |
1454 | * accessing registers in the SClk domain without LPS enabled | |
1455 | * will lock up the machine. Wait 50msec to make sure we have | |
1456 | * full link enabled. */ | |
1457 | reg_write(ohci, OHCI1394_HCControlSet, | |
1458 | OHCI1394_HCControl_LPS | | |
1459 | OHCI1394_HCControl_postedWriteEnable); | |
1460 | flush_writes(ohci); | |
1461 | msleep(50); | |
1462 | ||
1463 | reg_write(ohci, OHCI1394_HCControlClear, | |
1464 | OHCI1394_HCControl_noByteSwapData); | |
1465 | ||
1466 | reg_write(ohci, OHCI1394_LinkControlSet, | |
1467 | OHCI1394_LinkControl_rcvSelfID | | |
1468 | OHCI1394_LinkControl_cycleTimerEnable | | |
1469 | OHCI1394_LinkControl_cycleMaster); | |
1470 | ||
1471 | ar_context_init(&ohci->ar_request_ctx, ohci, | |
1472 | OHCI1394_AsReqRcvContextControlSet); | |
1473 | ||
1474 | ar_context_init(&ohci->ar_response_ctx, ohci, | |
1475 | OHCI1394_AsRspRcvContextControlSet); | |
1476 | ||
1477 | at_context_init(&ohci->at_request_ctx, ohci, | |
1478 | OHCI1394_AsReqTrContextControlSet); | |
1479 | ||
1480 | at_context_init(&ohci->at_response_ctx, ohci, | |
1481 | OHCI1394_AsRspTrContextControlSet); | |
1482 | ||
1483 | reg_write(ohci, OHCI1394_ATRetries, | |
1484 | OHCI1394_MAX_AT_REQ_RETRIES | | |
1485 | (OHCI1394_MAX_AT_RESP_RETRIES << 4) | | |
1486 | (OHCI1394_MAX_PHYS_RESP_RETRIES << 8)); | |
1487 | ||
1488 | reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0); | |
1489 | ohci->it_context_mask = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet); | |
1490 | reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0); | |
1491 | size = sizeof(struct iso_context) * hweight32(ohci->it_context_mask); | |
1492 | ohci->it_context_list = kzalloc(size, GFP_KERNEL); | |
1493 | ||
1494 | reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0); | |
1495 | ohci->ir_context_mask = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet); | |
1496 | reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0); | |
1497 | size = sizeof(struct iso_context) * hweight32(ohci->ir_context_mask); | |
1498 | ohci->ir_context_list = kzalloc(size, GFP_KERNEL); | |
1499 | ||
1500 | if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) { | |
1501 | fw_error("Out of memory for it/ir contexts.\n"); | |
1502 | return cleanup(ohci, CLEANUP_REGISTERS, -ENOMEM); | |
1503 | } | |
1504 | ||
1505 | /* self-id dma buffer allocation */ | |
1506 | ohci->self_id_cpu = dma_alloc_coherent(ohci->card.device, | |
1507 | SELF_ID_BUF_SIZE, | |
1508 | &ohci->self_id_bus, | |
1509 | GFP_KERNEL); | |
1510 | if (ohci->self_id_cpu == NULL) { | |
1511 | fw_error("Out of memory for self ID buffer.\n"); | |
1512 | return cleanup(ohci, CLEANUP_REGISTERS, -ENOMEM); | |
1513 | } | |
1514 | ||
1515 | reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus); | |
1516 | reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000); | |
1517 | reg_write(ohci, OHCI1394_IntEventClear, ~0); | |
1518 | reg_write(ohci, OHCI1394_IntMaskClear, ~0); | |
1519 | reg_write(ohci, OHCI1394_IntMaskSet, | |
1520 | OHCI1394_selfIDComplete | | |
1521 | OHCI1394_RQPkt | OHCI1394_RSPkt | | |
1522 | OHCI1394_reqTxComplete | OHCI1394_respTxComplete | | |
1523 | OHCI1394_isochRx | OHCI1394_isochTx | | |
1524 | OHCI1394_masterIntEnable); | |
1525 | ||
1526 | bus_options = reg_read(ohci, OHCI1394_BusOptions); | |
1527 | max_receive = (bus_options >> 12) & 0xf; | |
1528 | link_speed = bus_options & 0x7; | |
1529 | guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) | | |
1530 | reg_read(ohci, OHCI1394_GUIDLo); | |
1531 | ||
1532 | error_code = fw_card_add(&ohci->card, max_receive, link_speed, guid); | |
1533 | if (error_code < 0) | |
1534 | return cleanup(ohci, CLEANUP_SELF_ID, error_code); | |
1535 | ||
1536 | fw_notify("Added fw-ohci device %s.\n", dev->dev.bus_id); | |
1537 | ||
1538 | return 0; | |
1539 | } | |
1540 | ||
1541 | static void pci_remove(struct pci_dev *dev) | |
1542 | { | |
1543 | struct fw_ohci *ohci; | |
1544 | ||
1545 | ohci = pci_get_drvdata(dev); | |
1546 | reg_write(ohci, OHCI1394_IntMaskClear, OHCI1394_masterIntEnable); | |
1547 | fw_core_remove_card(&ohci->card); | |
1548 | ||
1549 | /* FIXME: Fail all pending packets here, now that the upper | |
1550 | * layers can't queue any more. */ | |
1551 | ||
1552 | software_reset(ohci); | |
1553 | free_irq(dev->irq, ohci); | |
1554 | cleanup(ohci, CLEANUP_SELF_ID, 0); | |
1555 | ||
1556 | fw_notify("Removed fw-ohci device.\n"); | |
1557 | } | |
1558 | ||
1559 | static struct pci_device_id pci_table[] = { | |
1560 | { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) }, | |
1561 | { } | |
1562 | }; | |
1563 | ||
1564 | MODULE_DEVICE_TABLE(pci, pci_table); | |
1565 | ||
1566 | static struct pci_driver fw_ohci_pci_driver = { | |
1567 | .name = ohci_driver_name, | |
1568 | .id_table = pci_table, | |
1569 | .probe = pci_probe, | |
1570 | .remove = pci_remove, | |
1571 | }; | |
1572 | ||
1573 | MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>"); | |
1574 | MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers"); | |
1575 | MODULE_LICENSE("GPL"); | |
1576 | ||
1577 | static int __init fw_ohci_init(void) | |
1578 | { | |
1579 | return pci_register_driver(&fw_ohci_pci_driver); | |
1580 | } | |
1581 | ||
1582 | static void __exit fw_ohci_cleanup(void) | |
1583 | { | |
1584 | pci_unregister_driver(&fw_ohci_pci_driver); | |
1585 | } | |
1586 | ||
1587 | module_init(fw_ohci_init); | |
1588 | module_exit(fw_ohci_cleanup); |