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b5e47729 SR |
1 | /* |
2 | * Chip register definitions for PCILynx chipset. Based on pcilynx.h | |
28646821 SR |
3 | * from the Linux 1394 drivers, but modified a bit so the names here |
4 | * match the specification exactly (even though they have weird names, | |
5 | * like xxx_OVER_FLOW, or arbitrary abbreviations like SNTRJ for "sent | |
6 | * reject" etc.) | |
7 | */ | |
8 | ||
9 | #define PCILYNX_MAX_REGISTER 0xfff | |
10 | #define PCILYNX_MAX_MEMORY 0xffff | |
11 | ||
12 | #define PCI_LATENCY_CACHELINE 0x0c | |
13 | ||
14 | #define MISC_CONTROL 0x40 | |
15 | #define MISC_CONTROL_SWRESET (1<<0) | |
16 | ||
17 | #define SERIAL_EEPROM_CONTROL 0x44 | |
18 | ||
19 | #define PCI_INT_STATUS 0x48 | |
b5e47729 | 20 | #define PCI_INT_ENABLE 0x4c |
28646821 SR |
21 | /* status and enable have identical bit numbers */ |
22 | #define PCI_INT_INT_PEND (1<<31) | |
23 | #define PCI_INT_FRC_INT (1<<30) | |
24 | #define PCI_INT_SLV_ADR_PERR (1<<28) | |
25 | #define PCI_INT_SLV_DAT_PERR (1<<27) | |
26 | #define PCI_INT_MST_DAT_PERR (1<<26) | |
27 | #define PCI_INT_MST_DEV_TO (1<<25) | |
28 | #define PCI_INT_INT_SLV_TO (1<<23) | |
29 | #define PCI_INT_AUX_TO (1<<18) | |
30 | #define PCI_INT_AUX_INT (1<<17) | |
31 | #define PCI_INT_P1394_INT (1<<16) | |
32 | #define PCI_INT_DMA4_PCL (1<<9) | |
33 | #define PCI_INT_DMA4_HLT (1<<8) | |
34 | #define PCI_INT_DMA3_PCL (1<<7) | |
35 | #define PCI_INT_DMA3_HLT (1<<6) | |
36 | #define PCI_INT_DMA2_PCL (1<<5) | |
37 | #define PCI_INT_DMA2_HLT (1<<4) | |
38 | #define PCI_INT_DMA1_PCL (1<<3) | |
39 | #define PCI_INT_DMA1_HLT (1<<2) | |
40 | #define PCI_INT_DMA0_PCL (1<<1) | |
41 | #define PCI_INT_DMA0_HLT (1<<0) | |
42 | /* all DMA interrupts combined: */ | |
43 | #define PCI_INT_DMA_ALL 0x3ff | |
44 | ||
45 | #define PCI_INT_DMA_HLT(chan) (1 << (chan * 2)) | |
46 | #define PCI_INT_DMA_PCL(chan) (1 << (chan * 2 + 1)) | |
47 | ||
48 | #define LBUS_ADDR 0xb4 | |
49 | #define LBUS_ADDR_SEL_RAM (0x0<<16) | |
50 | #define LBUS_ADDR_SEL_ROM (0x1<<16) | |
51 | #define LBUS_ADDR_SEL_AUX (0x2<<16) | |
b5e47729 | 52 | #define LBUS_ADDR_SEL_ZV (0x3<<16) |
28646821 SR |
53 | |
54 | #define GPIO_CTRL_A 0xb8 | |
55 | #define GPIO_CTRL_B 0xbc | |
56 | #define GPIO_DATA_BASE 0xc0 | |
57 | ||
58 | #define DMA_BREG(base, chan) (base + chan * 0x20) | |
59 | #define DMA_SREG(base, chan) (base + chan * 0x10) | |
60 | ||
61 | #define PCL_NEXT_INVALID (1<<0) | |
62 | ||
63 | /* transfer commands */ | |
64 | #define PCL_CMD_RCV (0x1<<24) | |
65 | #define PCL_CMD_RCV_AND_UPDATE (0xa<<24) | |
66 | #define PCL_CMD_XMT (0x2<<24) | |
67 | #define PCL_CMD_UNFXMT (0xc<<24) | |
68 | #define PCL_CMD_PCI_TO_LBUS (0x8<<24) | |
69 | #define PCL_CMD_LBUS_TO_PCI (0x9<<24) | |
70 | ||
71 | /* aux commands */ | |
72 | #define PCL_CMD_NOP (0x0<<24) | |
73 | #define PCL_CMD_LOAD (0x3<<24) | |
74 | #define PCL_CMD_STOREQ (0x4<<24) | |
75 | #define PCL_CMD_STORED (0xb<<24) | |
76 | #define PCL_CMD_STORE0 (0x5<<24) | |
77 | #define PCL_CMD_STORE1 (0x6<<24) | |
78 | #define PCL_CMD_COMPARE (0xe<<24) | |
79 | #define PCL_CMD_SWAP_COMPARE (0xf<<24) | |
80 | #define PCL_CMD_ADD (0xd<<24) | |
81 | #define PCL_CMD_BRANCH (0x7<<24) | |
82 | ||
83 | /* BRANCH condition codes */ | |
84 | #define PCL_COND_DMARDY_SET (0x1<<20) | |
85 | #define PCL_COND_DMARDY_CLEAR (0x2<<20) | |
86 | ||
87 | #define PCL_GEN_INTR (1<<19) | |
88 | #define PCL_LAST_BUFF (1<<18) | |
89 | #define PCL_LAST_CMD (PCL_LAST_BUFF) | |
90 | #define PCL_WAITSTAT (1<<17) | |
91 | #define PCL_BIGENDIAN (1<<16) | |
92 | #define PCL_ISOMODE (1<<12) | |
93 | ||
b5e47729 | 94 | #define DMA0_PREV_PCL 0x100 |
28646821 SR |
95 | #define DMA1_PREV_PCL 0x120 |
96 | #define DMA2_PREV_PCL 0x140 | |
97 | #define DMA3_PREV_PCL 0x160 | |
98 | #define DMA4_PREV_PCL 0x180 | |
99 | #define DMA_PREV_PCL(chan) (DMA_BREG(DMA0_PREV_PCL, chan)) | |
100 | ||
b5e47729 | 101 | #define DMA0_CURRENT_PCL 0x104 |
28646821 SR |
102 | #define DMA1_CURRENT_PCL 0x124 |
103 | #define DMA2_CURRENT_PCL 0x144 | |
104 | #define DMA3_CURRENT_PCL 0x164 | |
105 | #define DMA4_CURRENT_PCL 0x184 | |
106 | #define DMA_CURRENT_PCL(chan) (DMA_BREG(DMA0_CURRENT_PCL, chan)) | |
107 | ||
108 | #define DMA0_CHAN_STAT 0x10c | |
109 | #define DMA1_CHAN_STAT 0x12c | |
110 | #define DMA2_CHAN_STAT 0x14c | |
111 | #define DMA3_CHAN_STAT 0x16c | |
112 | #define DMA4_CHAN_STAT 0x18c | |
113 | #define DMA_CHAN_STAT(chan) (DMA_BREG(DMA0_CHAN_STAT, chan)) | |
114 | /* CHAN_STATUS registers share bits */ | |
115 | #define DMA_CHAN_STAT_SELFID (1<<31) | |
116 | #define DMA_CHAN_STAT_ISOPKT (1<<30) | |
117 | #define DMA_CHAN_STAT_PCIERR (1<<29) | |
118 | #define DMA_CHAN_STAT_PKTERR (1<<28) | |
119 | #define DMA_CHAN_STAT_PKTCMPL (1<<27) | |
120 | #define DMA_CHAN_STAT_SPECIALACK (1<<14) | |
121 | ||
b5e47729 | 122 | #define DMA0_CHAN_CTRL 0x110 |
28646821 SR |
123 | #define DMA1_CHAN_CTRL 0x130 |
124 | #define DMA2_CHAN_CTRL 0x150 | |
125 | #define DMA3_CHAN_CTRL 0x170 | |
126 | #define DMA4_CHAN_CTRL 0x190 | |
127 | #define DMA_CHAN_CTRL(chan) (DMA_BREG(DMA0_CHAN_CTRL, chan)) | |
128 | /* CHAN_CTRL registers share bits */ | |
b5e47729 | 129 | #define DMA_CHAN_CTRL_ENABLE (1<<31) |
28646821 SR |
130 | #define DMA_CHAN_CTRL_BUSY (1<<30) |
131 | #define DMA_CHAN_CTRL_LINK (1<<29) | |
132 | ||
133 | #define DMA0_READY 0x114 | |
134 | #define DMA1_READY 0x134 | |
135 | #define DMA2_READY 0x154 | |
136 | #define DMA3_READY 0x174 | |
137 | #define DMA4_READY 0x194 | |
138 | #define DMA_READY(chan) (DMA_BREG(DMA0_READY, chan)) | |
139 | ||
140 | #define DMA_GLOBAL_REGISTER 0x908 | |
141 | ||
142 | #define FIFO_SIZES 0xa00 | |
143 | ||
144 | #define FIFO_CONTROL 0xa10 | |
145 | #define FIFO_CONTROL_GRF_FLUSH (1<<4) | |
146 | #define FIFO_CONTROL_ITF_FLUSH (1<<3) | |
147 | #define FIFO_CONTROL_ATF_FLUSH (1<<2) | |
148 | ||
149 | #define FIFO_XMIT_THRESHOLD 0xa14 | |
150 | ||
151 | #define DMA0_WORD0_CMP_VALUE 0xb00 | |
152 | #define DMA1_WORD0_CMP_VALUE 0xb10 | |
153 | #define DMA2_WORD0_CMP_VALUE 0xb20 | |
154 | #define DMA3_WORD0_CMP_VALUE 0xb30 | |
155 | #define DMA4_WORD0_CMP_VALUE 0xb40 | |
b5e47729 | 156 | #define DMA_WORD0_CMP_VALUE(chan) (DMA_SREG(DMA0_WORD0_CMP_VALUE, chan)) |
28646821 SR |
157 | |
158 | #define DMA0_WORD0_CMP_ENABLE 0xb04 | |
159 | #define DMA1_WORD0_CMP_ENABLE 0xb14 | |
160 | #define DMA2_WORD0_CMP_ENABLE 0xb24 | |
161 | #define DMA3_WORD0_CMP_ENABLE 0xb34 | |
162 | #define DMA4_WORD0_CMP_ENABLE 0xb44 | |
b5e47729 | 163 | #define DMA_WORD0_CMP_ENABLE(chan) (DMA_SREG(DMA0_WORD0_CMP_ENABLE, chan)) |
28646821 SR |
164 | |
165 | #define DMA0_WORD1_CMP_VALUE 0xb08 | |
166 | #define DMA1_WORD1_CMP_VALUE 0xb18 | |
167 | #define DMA2_WORD1_CMP_VALUE 0xb28 | |
168 | #define DMA3_WORD1_CMP_VALUE 0xb38 | |
169 | #define DMA4_WORD1_CMP_VALUE 0xb48 | |
b5e47729 | 170 | #define DMA_WORD1_CMP_VALUE(chan) (DMA_SREG(DMA0_WORD1_CMP_VALUE, chan)) |
28646821 SR |
171 | |
172 | #define DMA0_WORD1_CMP_ENABLE 0xb0c | |
173 | #define DMA1_WORD1_CMP_ENABLE 0xb1c | |
174 | #define DMA2_WORD1_CMP_ENABLE 0xb2c | |
175 | #define DMA3_WORD1_CMP_ENABLE 0xb3c | |
176 | #define DMA4_WORD1_CMP_ENABLE 0xb4c | |
b5e47729 | 177 | #define DMA_WORD1_CMP_ENABLE(chan) (DMA_SREG(DMA0_WORD1_CMP_ENABLE, chan)) |
28646821 SR |
178 | /* word 1 compare enable flags */ |
179 | #define DMA_WORD1_CMP_MATCH_OTHERBUS (1<<15) | |
180 | #define DMA_WORD1_CMP_MATCH_BROADCAST (1<<14) | |
181 | #define DMA_WORD1_CMP_MATCH_BUS_BCAST (1<<13) | |
182 | #define DMA_WORD1_CMP_MATCH_LOCAL_NODE (1<<12) | |
183 | #define DMA_WORD1_CMP_MATCH_EXACT (1<<11) | |
184 | #define DMA_WORD1_CMP_ENABLE_SELF_ID (1<<10) | |
185 | #define DMA_WORD1_CMP_ENABLE_MASTER (1<<8) | |
186 | ||
187 | #define LINK_ID 0xf00 | |
188 | #define LINK_ID_BUS(id) (id<<22) | |
189 | #define LINK_ID_NODE(id) (id<<16) | |
190 | ||
191 | #define LINK_CONTROL 0xf04 | |
192 | #define LINK_CONTROL_BUSY (1<<29) | |
193 | #define LINK_CONTROL_TX_ISO_EN (1<<26) | |
194 | #define LINK_CONTROL_RX_ISO_EN (1<<25) | |
195 | #define LINK_CONTROL_TX_ASYNC_EN (1<<24) | |
196 | #define LINK_CONTROL_RX_ASYNC_EN (1<<23) | |
197 | #define LINK_CONTROL_RESET_TX (1<<21) | |
198 | #define LINK_CONTROL_RESET_RX (1<<20) | |
199 | #define LINK_CONTROL_CYCMASTER (1<<11) | |
200 | #define LINK_CONTROL_CYCSOURCE (1<<10) | |
201 | #define LINK_CONTROL_CYCTIMEREN (1<<9) | |
202 | #define LINK_CONTROL_RCV_CMP_VALID (1<<7) | |
203 | #define LINK_CONTROL_SNOOP_ENABLE (1<<6) | |
204 | ||
205 | #define CYCLE_TIMER 0xf08 | |
206 | ||
207 | #define LINK_PHY 0xf0c | |
208 | #define LINK_PHY_READ (1<<31) | |
209 | #define LINK_PHY_WRITE (1<<30) | |
210 | #define LINK_PHY_ADDR(addr) (addr<<24) | |
211 | #define LINK_PHY_WDATA(data) (data<<16) | |
212 | #define LINK_PHY_RADDR(addr) (addr<<8) | |
213 | ||
28646821 SR |
214 | #define LINK_INT_STATUS 0xf14 |
215 | #define LINK_INT_ENABLE 0xf18 | |
216 | /* status and enable have identical bit numbers */ | |
217 | #define LINK_INT_LINK_INT (1<<31) | |
218 | #define LINK_INT_PHY_TIME_OUT (1<<30) | |
219 | #define LINK_INT_PHY_REG_RCVD (1<<29) | |
220 | #define LINK_INT_PHY_BUSRESET (1<<28) | |
221 | #define LINK_INT_TX_RDY (1<<26) | |
222 | #define LINK_INT_RX_DATA_RDY (1<<25) | |
223 | #define LINK_INT_IT_STUCK (1<<20) | |
224 | #define LINK_INT_AT_STUCK (1<<19) | |
225 | #define LINK_INT_SNTRJ (1<<17) | |
226 | #define LINK_INT_HDR_ERR (1<<16) | |
227 | #define LINK_INT_TC_ERR (1<<15) | |
228 | #define LINK_INT_CYC_SEC (1<<11) | |
229 | #define LINK_INT_CYC_STRT (1<<10) | |
230 | #define LINK_INT_CYC_DONE (1<<9) | |
231 | #define LINK_INT_CYC_PEND (1<<8) | |
232 | #define LINK_INT_CYC_LOST (1<<7) | |
233 | #define LINK_INT_CYC_ARB_FAILED (1<<6) | |
234 | #define LINK_INT_GRF_OVER_FLOW (1<<5) | |
235 | #define LINK_INT_ITF_UNDER_FLOW (1<<4) | |
236 | #define LINK_INT_ATF_UNDER_FLOW (1<<3) | |
b5e47729 | 237 | #define LINK_INT_IARB_FAILED (1<<0) |