]> git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blame - drivers/firewire/ohci.c
projects / mirror_ubuntu-artful-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
btrfs: fix comment typos
[mirror_ubuntu-artful-kernel.git] / drivers / firewire / ohci.c
CommitLineData
c781c06d
KH		 1/*
2 * Driver for OHCI 1394 controllers
ed568912 3 *
ed568912
KH		 4 * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software Foundation,
18 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
dd23736e 21#include <linux/bitops.h>
65b2742a 22#include <linux/bug.h>
e524f616 23#include <linux/compiler.h>
ed568912 24#include <linux/delay.h>
e8ca9702 25#include <linux/device.h>
cf3e72fd 26#include <linux/dma-mapping.h>
77c9a5da 27#include <linux/firewire.h>
e8ca9702 28#include <linux/firewire-constants.h>
a7fb60db
SR		 29#include <linux/init.h>
30#include <linux/interrupt.h>
e8ca9702 31#include <linux/io.h>
a7fb60db 32#include <linux/kernel.h>
e8ca9702 33#include <linux/list.h>
faa2fb4e 34#include <linux/mm.h>
a7fb60db 35#include <linux/module.h>
ad3c0fe8 36#include <linux/moduleparam.h>
02d37bed 37#include <linux/mutex.h>
a7fb60db 38#include <linux/pci.h>
fc383796 39#include <linux/pci_ids.h>
5a0e3ad6 40#include <linux/slab.h>
c26f0234 41#include <linux/spinlock.h>
e8ca9702 42#include <linux/string.h>
e78483c5 43#include <linux/time.h>
7a39d8b8 44#include <linux/vmalloc.h>
2d7a36e2 45#include <linux/workqueue.h>
cf3e72fd 46
e8ca9702 47#include <asm/byteorder.h>
c26f0234 48#include <asm/page.h>
ed568912 49
ea8d006b
SR		 50#ifdef CONFIG_PPC_PMAC
51#include <asm/pmac_feature.h>
52#endif
53
77c9a5da
SR		 54#include "core.h"
55#include "ohci.h"
ed568912 56
a77754a7
KH		 57#define DESCRIPTOR_OUTPUT_MORE 0
58#define DESCRIPTOR_OUTPUT_LAST (1 << 12)
59#define DESCRIPTOR_INPUT_MORE (2 << 12)
60#define DESCRIPTOR_INPUT_LAST (3 << 12)
61#define DESCRIPTOR_STATUS (1 << 11)
62#define DESCRIPTOR_KEY_IMMEDIATE (2 << 8)
63#define DESCRIPTOR_PING (1 << 7)
64#define DESCRIPTOR_YY (1 << 6)
65#define DESCRIPTOR_NO_IRQ (0 << 4)
66#define DESCRIPTOR_IRQ_ERROR (1 << 4)
67#define DESCRIPTOR_IRQ_ALWAYS (3 << 4)
68#define DESCRIPTOR_BRANCH_ALWAYS (3 << 2)
69#define DESCRIPTOR_WAIT (3 << 0)
ed568912
KH		 70
71struct descriptor {
72 __le16 req_count;
73 __le16 control;
74 __le32 data_address;
75 __le32 branch_address;
76 __le16 res_count;
77 __le16 transfer_status;
78} __attribute__((aligned(16)));
79
a77754a7
KH		 80#define CONTROL_SET(regs) (regs)
81#define CONTROL_CLEAR(regs) ((regs) + 4)
82#define COMMAND_PTR(regs) ((regs) + 12)
83#define CONTEXT_MATCH(regs) ((regs) + 16)
72e318e0 84
7a39d8b8
CL		 85#define AR_BUFFER_SIZE (32*1024)
86#define AR_BUFFERS_MIN DIV_ROUND_UP(AR_BUFFER_SIZE, PAGE_SIZE)
87/* we need at least two pages for proper list management */
88#define AR_BUFFERS (AR_BUFFERS_MIN >= 2 ? AR_BUFFERS_MIN : 2)
89
90#define MAX_ASYNC_PAYLOAD 4096
91#define MAX_AR_PACKET_SIZE (16 + MAX_ASYNC_PAYLOAD + 4)
92#define AR_WRAPAROUND_PAGES DIV_ROUND_UP(MAX_AR_PACKET_SIZE, PAGE_SIZE)
ed568912 93
32b46093
KH		 94struct ar_context {
95 struct fw_ohci *ohci;
7a39d8b8
CL		 96 struct page *pages[AR_BUFFERS];
97 void *buffer;
98 struct descriptor *descriptors;
99 dma_addr_t descriptors_bus;
32b46093 100 void *pointer;
7a39d8b8 101 unsigned int last_buffer_index;
72e318e0 102 u32 regs;
ed568912
KH		 103 struct tasklet_struct tasklet;
104};
105
30200739
KH		 106struct context;
107
108typedef int (*descriptor_callback_t)(struct context *ctx,
109 struct descriptor *d,
110 struct descriptor *last);
fe5ca634
DM		 111
112/*
113 * A buffer that contains a block of DMA-able coherent memory used for
114 * storing a portion of a DMA descriptor program.
115 */
116struct descriptor_buffer {
117 struct list_head list;
118 dma_addr_t buffer_bus;
119 size_t buffer_size;
120 size_t used;
121 struct descriptor buffer[0];
122};
123
30200739 124struct context {
373b2edd 125 struct fw_ohci *ohci;
30200739 126 u32 regs;
fe5ca634 127 int total_allocation;
a572e688 128 u32 current_bus;
386a4153 129 bool running;
82b662dc 130 bool flushing;
373b2edd 131
fe5ca634
DM		 132 /*
133 * List of page-sized buffers for storing DMA descriptors.
134 * Head of list contains buffers in use and tail of list contains
135 * free buffers.
136 */
137 struct list_head buffer_list;
138
139 /*
140 * Pointer to a buffer inside buffer_list that contains the tail
141 * end of the current DMA program.
142 */
143 struct descriptor_buffer *buffer_tail;
144
145 /*
146 * The descriptor containing the branch address of the first
147 * descriptor that has not yet been filled by the device.
148 */
149 struct descriptor *last;
150
151 /*
152 * The last descriptor in the DMA program. It contains the branch
153 * address that must be updated upon appending a new descriptor.
154 */
155 struct descriptor *prev;
30200739
KH		 156
157 descriptor_callback_t callback;
158
373b2edd 159 struct tasklet_struct tasklet;
30200739 160};
30200739 161
a77754a7
KH		 162#define IT_HEADER_SY(v) ((v) << 0)
163#define IT_HEADER_TCODE(v) ((v) << 4)
164#define IT_HEADER_CHANNEL(v) ((v) << 8)
165#define IT_HEADER_TAG(v) ((v) << 14)
166#define IT_HEADER_SPEED(v) ((v) << 16)
167#define IT_HEADER_DATA_LENGTH(v) ((v) << 16)
ed568912
KH		 168
169struct iso_context {
170 struct fw_iso_context base;
30200739 171 struct context context;
9b32d5f3
KH		 172 void *header;
173 size_t header_length;
d1bbd209
CL		 174 unsigned long flushing_completions;
175 u32 mc_buffer_bus;
176 u16 mc_completed;
910e76c6 177 u16 last_timestamp;
dd23736e
ML		 178 u8 sync;
179 u8 tags;
ed568912
KH		 180};
181
182#define CONFIG_ROM_SIZE 1024
183
184struct fw_ohci {
185 struct fw_card card;
186
187 __iomem char *registers;
e636fe25 188 int node_id;
ed568912 189 int generation;
e09770db 190 int request_generation; /* for timestamping incoming requests */
4a635593 191 unsigned quirks;
a1a1132b 192 unsigned int pri_req_max;
a48777e0 193 u32 bus_time;
9d60ef2b 194 bool bus_time_running;
4ffb7a6a 195 bool is_root;
c8a94ded 196 bool csr_state_setclear_abdicate;
dd23736e
ML		 197 int n_ir;
198 int n_it;
c781c06d
KH		 199 /*
200 * Spinlock for accessing fw_ohci data. Never call out of
201 * this driver with this lock held.
202 */
ed568912 203 spinlock_t lock;
ed568912 204
02d37bed
SR		 205 struct mutex phy_reg_mutex;
206
ec766a79
CL		 207 void *misc_buffer;
208 dma_addr_t misc_buffer_bus;
209
ed568912
KH		 210 struct ar_context ar_request_ctx;
211 struct ar_context ar_response_ctx;
f319b6a0
KH		 212 struct context at_request_ctx;
213 struct context at_response_ctx;
ed568912 214
f117a3e3 215 u32 it_context_support;
872e330e 216 u32 it_context_mask; /* unoccupied IT contexts */
ed568912 217 struct iso_context *it_context_list;
872e330e 218 u64 ir_context_channels; /* unoccupied channels */
f117a3e3 219 u32 ir_context_support;
872e330e 220 u32 ir_context_mask; /* unoccupied IR contexts */
ed568912 221 struct iso_context *ir_context_list;
872e330e
SR		 222 u64 mc_channels; /* channels in use by the multichannel IR context */
223 bool mc_allocated;
ecb1cf9c
SR		 224
225 __be32 *config_rom;
226 dma_addr_t config_rom_bus;
227 __be32 *next_config_rom;
228 dma_addr_t next_config_rom_bus;
229 __be32 next_header;
230
231 __le32 *self_id_cpu;
232 dma_addr_t self_id_bus;
2d7a36e2 233 struct work_struct bus_reset_work;
ecb1cf9c
SR		 234
235 u32 self_id_buffer[512];
ed568912
KH		 236};
237
95688e97 238static inline struct fw_ohci *fw_ohci(struct fw_card *card)
ed568912
KH		 239{
240 return container_of(card, struct fw_ohci, card);
241}
242
295e3feb
KH		 243#define IT_CONTEXT_CYCLE_MATCH_ENABLE 0x80000000
244#define IR_CONTEXT_BUFFER_FILL 0x80000000
245#define IR_CONTEXT_ISOCH_HEADER 0x40000000
246#define IR_CONTEXT_CYCLE_MATCH_ENABLE 0x20000000
247#define IR_CONTEXT_MULTI_CHANNEL_MODE 0x10000000
248#define IR_CONTEXT_DUAL_BUFFER_MODE 0x08000000
ed568912
KH		 249
250#define CONTEXT_RUN 0x8000
251#define CONTEXT_WAKE 0x1000
252#define CONTEXT_DEAD 0x0800
253#define CONTEXT_ACTIVE 0x0400
254
8b7b6afa 255#define OHCI1394_MAX_AT_REQ_RETRIES 0xf
ed568912
KH		 256#define OHCI1394_MAX_AT_RESP_RETRIES 0x2
257#define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8
258
ed568912 259#define OHCI1394_REGISTER_SIZE 0x800
ed568912
KH		 260#define OHCI1394_PCI_HCI_Control 0x40
261#define SELF_ID_BUF_SIZE 0x800
32b46093 262#define OHCI_TCODE_PHY_PACKET 0x0e
e364cf4e 263#define OHCI_VERSION_1_1 0x010010
0edeefd9 264
ed568912
KH		 265static char ohci_driver_name[] = KBUILD_MODNAME;
266
9993e0fe 267#define PCI_DEVICE_ID_AGERE_FW643 0x5901
d1bb399a 268#define PCI_DEVICE_ID_CREATIVE_SB1394 0x4001
262444ee 269#define PCI_DEVICE_ID_JMICRON_JMB38X_FW 0x2380
8301b91b 270#define PCI_DEVICE_ID_TI_TSB12LV22 0x8009
25935ebe
SG		 271#define PCI_DEVICE_ID_TI_TSB12LV26 0x8020
272#define PCI_DEVICE_ID_TI_TSB82AA2 0x8025
7f7e3711 273#define PCI_VENDOR_ID_PINNACLE_SYSTEMS 0x11bd
8301b91b 274
4a635593
SR		 275#define QUIRK_CYCLE_TIMER 1
276#define QUIRK_RESET_PACKET 2
277#define QUIRK_BE_HEADERS 4
925e7a65 278#define QUIRK_NO_1394A 8
262444ee 279#define QUIRK_NO_MSI 16
25935ebe 280#define QUIRK_TI_SLLZ059 32
4a635593
SR		 281
282/* In case of multiple matches in ohci_quirks[], only the first one is used. */
283static const struct {
9993e0fe 284 unsigned short vendor, device, revision, flags;
4a635593 285} ohci_quirks[] = {
9993e0fe
SR		 286 {PCI_VENDOR_ID_AL, PCI_ANY_ID, PCI_ANY_ID,
287 QUIRK_CYCLE_TIMER},
288
289 {PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_FW, PCI_ANY_ID,
290 QUIRK_BE_HEADERS},
291
292 {PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_AGERE_FW643, 6,
293 QUIRK_NO_MSI},
294
d1bb399a
CL		 295 {PCI_VENDOR_ID_CREATIVE, PCI_DEVICE_ID_CREATIVE_SB1394, PCI_ANY_ID,
296 QUIRK_RESET_PACKET},
297
9993e0fe
SR		 298 {PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB38X_FW, PCI_ANY_ID,
299 QUIRK_NO_MSI},
300
301 {PCI_VENDOR_ID_NEC, PCI_ANY_ID, PCI_ANY_ID,
302 QUIRK_CYCLE_TIMER},
303
f39aa30d
ML		 304 {PCI_VENDOR_ID_O2, PCI_ANY_ID, PCI_ANY_ID,
305 QUIRK_NO_MSI},
306
9993e0fe 307 {PCI_VENDOR_ID_RICOH, PCI_ANY_ID, PCI_ANY_ID,
320cfa6c 308 QUIRK_CYCLE_TIMER | QUIRK_NO_MSI},
9993e0fe
SR		 309
310 {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV22, PCI_ANY_ID,
311 QUIRK_CYCLE_TIMER | QUIRK_RESET_PACKET | QUIRK_NO_1394A},
312
25935ebe
SG		 313 {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV26, PCI_ANY_ID,
314 QUIRK_RESET_PACKET | QUIRK_TI_SLLZ059},
315
316 {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB82AA2, PCI_ANY_ID,
317 QUIRK_RESET_PACKET | QUIRK_TI_SLLZ059},
318
9993e0fe
SR		 319 {PCI_VENDOR_ID_TI, PCI_ANY_ID, PCI_ANY_ID,
320 QUIRK_RESET_PACKET},
321
322 {PCI_VENDOR_ID_VIA, PCI_ANY_ID, PCI_ANY_ID,
323 QUIRK_CYCLE_TIMER | QUIRK_NO_MSI},
4a635593
SR		 324};
325
3e9cc2f3
SR		 326/* This overrides anything that was found in ohci_quirks[]. */
327static int param_quirks;
328module_param_named(quirks, param_quirks, int, 0644);
329MODULE_PARM_DESC(quirks, "Chip quirks (default = 0"
330 ", nonatomic cycle timer = " __stringify(QUIRK_CYCLE_TIMER)
331 ", reset packet generation = " __stringify(QUIRK_RESET_PACKET)
332 ", AR/selfID endianess = " __stringify(QUIRK_BE_HEADERS)
925e7a65 333 ", no 1394a enhancements = " __stringify(QUIRK_NO_1394A)
262444ee 334 ", disable MSI = " __stringify(QUIRK_NO_MSI)
28897fb7 335 ", TI SLLZ059 erratum = " __stringify(QUIRK_TI_SLLZ059)
3e9cc2f3
SR		 336 ")");
337
a007bb85 338#define OHCI_PARAM_DEBUG_AT_AR 1
ad3c0fe8 339#define OHCI_PARAM_DEBUG_SELFIDS 2
a007bb85
SR		 340#define OHCI_PARAM_DEBUG_IRQS 4
341#define OHCI_PARAM_DEBUG_BUSRESETS 8 /* only effective before chip init */
ad3c0fe8
SR		 342
343static int param_debug;
344module_param_named(debug, param_debug, int, 0644);
345MODULE_PARM_DESC(debug, "Verbose logging (default = 0"
ad3c0fe8 346 ", AT/AR events = " __stringify(OHCI_PARAM_DEBUG_AT_AR)
a007bb85
SR		 347 ", self-IDs = " __stringify(OHCI_PARAM_DEBUG_SELFIDS)
348 ", IRQs = " __stringify(OHCI_PARAM_DEBUG_IRQS)
349 ", busReset events = " __stringify(OHCI_PARAM_DEBUG_BUSRESETS)
ad3c0fe8
SR		 350 ", or a combination, or all = -1)");
351
64d21720 352static void log_irqs(struct fw_ohci *ohci, u32 evt)
ad3c0fe8 353{
a007bb85
SR		 354 if (likely(!(param_debug &
355 (OHCI_PARAM_DEBUG_IRQS | OHCI_PARAM_DEBUG_BUSRESETS))))
356 return;
357
358 if (!(param_debug & OHCI_PARAM_DEBUG_IRQS) &&
359 !(evt & OHCI1394_busReset))
ad3c0fe8
SR		 360 return;
361
64d21720
SR		 362 dev_notice(ohci->card.device,
363 "IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt,
161b96e7
SR		 364 evt & OHCI1394_selfIDComplete ? " selfID" : "",
365 evt & OHCI1394_RQPkt ? " AR_req" : "",
366 evt & OHCI1394_RSPkt ? " AR_resp" : "",
367 evt & OHCI1394_reqTxComplete ? " AT_req" : "",
368 evt & OHCI1394_respTxComplete ? " AT_resp" : "",
369 evt & OHCI1394_isochRx ? " IR" : "",
370 evt & OHCI1394_isochTx ? " IT" : "",
371 evt & OHCI1394_postedWriteErr ? " postedWriteErr" : "",
372 evt & OHCI1394_cycleTooLong ? " cycleTooLong" : "",
a48777e0 373 evt & OHCI1394_cycle64Seconds ? " cycle64Seconds" : "",
5ed1f321 374 evt & OHCI1394_cycleInconsistent ? " cycleInconsistent" : "",
161b96e7 375 evt & OHCI1394_regAccessFail ? " regAccessFail" : "",
f117a3e3 376 evt & OHCI1394_unrecoverableError ? " unrecoverableError" : "",
161b96e7
SR		 377 evt & OHCI1394_busReset ? " busReset" : "",
378 evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt |
379 OHCI1394_RSPkt | OHCI1394_reqTxComplete |
380 OHCI1394_respTxComplete | OHCI1394_isochRx |
381 OHCI1394_isochTx | OHCI1394_postedWriteErr |
a48777e0
CL		 382 OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds |
383 OHCI1394_cycleInconsistent |
161b96e7 384 OHCI1394_regAccessFail | OHCI1394_busReset)
ad3c0fe8
SR		 385 ? " ?" : "");
386}
387
388static const char *speed[] = {
389 [0] = "S100", [1] = "S200", [2] = "S400", [3] = "beta",
390};
391static const char *power[] = {
392 [0] = "+0W", [1] = "+15W", [2] = "+30W", [3] = "+45W",
393 [4] = "-3W", [5] = " ?W", [6] = "-3..-6W", [7] = "-3..-10W",
394};
395static const char port[] = { '.', '-', 'p', 'c', };
396
397static char _p(u32 *s, int shift)
398{
399 return port[*s >> shift & 3];
400}
401
64d21720 402static void log_selfids(struct fw_ohci *ohci, int generation, int self_id_count)
ad3c0fe8 403{
64d21720
SR		 404 u32 *s;
405
ad3c0fe8
SR		 406 if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS)))
407 return;
408
64d21720
SR		 409 dev_notice(ohci->card.device,
410 "%d selfIDs, generation %d, local node ID %04x\n",
411 self_id_count, generation, ohci->node_id);
ad3c0fe8 412
64d21720 413 for (s = ohci->self_id_buffer; self_id_count--; ++s)
ad3c0fe8 414 if ((*s & 1 << 23) == 0)
64d21720
SR		 415 dev_notice(ohci->card.device,
416 "selfID 0: %08x, phy %d [%c%c%c] "
161b96e7
SR		 417 "%s gc=%d %s %s%s%s\n",
418 *s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2),
419 speed[*s >> 14 & 3], *s >> 16 & 63,
420 power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "",
421 *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : "");
ad3c0fe8 422 else
64d21720
SR		 423 dev_notice(ohci->card.device,
424 "selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n",
161b96e7
SR		 425 *s, *s >> 24 & 63,
426 _p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10),
427 _p(s, 8), _p(s, 6), _p(s, 4), _p(s, 2));
ad3c0fe8
SR		 428}
429
430static const char *evts[] = {
431 [0x00] = "evt_no_status", [0x01] = "-reserved-",
432 [0x02] = "evt_long_packet", [0x03] = "evt_missing_ack",
433 [0x04] = "evt_underrun", [0x05] = "evt_overrun",
434 [0x06] = "evt_descriptor_read", [0x07] = "evt_data_read",
435 [0x08] = "evt_data_write", [0x09] = "evt_bus_reset",
436 [0x0a] = "evt_timeout", [0x0b] = "evt_tcode_err",
437 [0x0c] = "-reserved-", [0x0d] = "-reserved-",
438 [0x0e] = "evt_unknown", [0x0f] = "evt_flushed",
439 [0x10] = "-reserved-", [0x11] = "ack_complete",
440 [0x12] = "ack_pending ", [0x13] = "-reserved-",
441 [0x14] = "ack_busy_X", [0x15] = "ack_busy_A",
442 [0x16] = "ack_busy_B", [0x17] = "-reserved-",
443 [0x18] = "-reserved-", [0x19] = "-reserved-",
444 [0x1a] = "-reserved-", [0x1b] = "ack_tardy",
445 [0x1c] = "-reserved-", [0x1d] = "ack_data_error",
446 [0x1e] = "ack_type_error", [0x1f] = "-reserved-",
447 [0x20] = "pending/cancelled",
448};
449static const char *tcodes[] = {
450 [0x0] = "QW req", [0x1] = "BW req",
451 [0x2] = "W resp", [0x3] = "-reserved-",
452 [0x4] = "QR req", [0x5] = "BR req",
453 [0x6] = "QR resp", [0x7] = "BR resp",
454 [0x8] = "cycle start", [0x9] = "Lk req",
455 [0xa] = "async stream packet", [0xb] = "Lk resp",
456 [0xc] = "-reserved-", [0xd] = "-reserved-",
457 [0xe] = "link internal", [0xf] = "-reserved-",
458};
ad3c0fe8 459
64d21720
SR		 460static void log_ar_at_event(struct fw_ohci *ohci,
461 char dir, int speed, u32 *header, int evt)
ad3c0fe8
SR		 462{
463 int tcode = header[0] >> 4 & 0xf;
464 char specific[12];
465
466 if (likely(!(param_debug & OHCI_PARAM_DEBUG_AT_AR)))
467 return;
468
469 if (unlikely(evt >= ARRAY_SIZE(evts)))
470 evt = 0x1f;
471
08ddb2f4 472 if (evt == OHCI1394_evt_bus_reset) {
64d21720
SR		 473 dev_notice(ohci->card.device,
474 "A%c evt_bus_reset, generation %d\n",
475 dir, (header[2] >> 16) & 0xff);
08ddb2f4
SR		 476 return;
477 }
478
ad3c0fe8
SR		 479 switch (tcode) {
480 case 0x0: case 0x6: case 0x8:
481 snprintf(specific, sizeof(specific), " = %08x",
482 be32_to_cpu((__force __be32)header[3]));
483 break;
484 case 0x1: case 0x5: case 0x7: case 0x9: case 0xb:
485 snprintf(specific, sizeof(specific), " %x,%x",
486 header[3] >> 16, header[3] & 0xffff);
487 break;
488 default:
489 specific[0] = '\0';
490 }
491
492 switch (tcode) {
5b06db16 493 case 0xa:
64d21720
SR		 494 dev_notice(ohci->card.device,
495 "A%c %s, %s\n",
496 dir, evts[evt], tcodes[tcode]);
ad3c0fe8 497 break;
5b06db16 498 case 0xe:
64d21720
SR		 499 dev_notice(ohci->card.device,
500 "A%c %s, PHY %08x %08x\n",
501 dir, evts[evt], header[1], header[2]);
5b06db16 502 break;
ad3c0fe8 503 case 0x0: case 0x1: case 0x4: case 0x5: case 0x9:
64d21720
SR		 504 dev_notice(ohci->card.device,
505 "A%c spd %x tl %02x, "
506 "%04x -> %04x, %s, "
507 "%s, %04x%08x%s\n",
508 dir, speed, header[0] >> 10 & 0x3f,
509 header[1] >> 16, header[0] >> 16, evts[evt],
510 tcodes[tcode], header[1] & 0xffff, header[2], specific);
ad3c0fe8
SR		 511 break;
512 default:
64d21720
SR		 513 dev_notice(ohci->card.device,
514 "A%c spd %x tl %02x, "
515 "%04x -> %04x, %s, "
516 "%s%s\n",
517 dir, speed, header[0] >> 10 & 0x3f,
518 header[1] >> 16, header[0] >> 16, evts[evt],
519 tcodes[tcode], specific);
ad3c0fe8
SR		 520 }
521}
522
95688e97 523static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data)
ed568912
KH		 524{
525 writel(data, ohci->registers + offset);
526}
527
95688e97 528static inline u32 reg_read(const struct fw_ohci *ohci, int offset)
ed568912
KH		 529{
530 return readl(ohci->registers + offset);
531}
532
95688e97 533static inline void flush_writes(const struct fw_ohci *ohci)
ed568912
KH		 534{
535 /* Do a dummy read to flush writes. */
536 reg_read(ohci, OHCI1394_Version);
537}
538
b14c369d
SR		 539/*
540 * Beware! read_phy_reg(), write_phy_reg(), update_phy_reg(), and
541 * read_paged_phy_reg() require the caller to hold ohci->phy_reg_mutex.
542 * In other words, only use ohci_read_phy_reg() and ohci_update_phy_reg()
543 * directly. Exceptions are intrinsically serialized contexts like pci_probe.
544 */
35d999b1 545static int read_phy_reg(struct fw_ohci *ohci, int addr)
ed568912 546{
4a96b4fc 547 u32 val;
35d999b1 548 int i;
ed568912
KH		 549
550 reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr));
153e3979 551 for (i = 0; i < 3 + 100; i++) {
35d999b1 552 val = reg_read(ohci, OHCI1394_PhyControl);
215fa444
SR		 553 if (!~val)
554 return -ENODEV; /* Card was ejected. */
555
35d999b1
SR		 556 if (val & OHCI1394_PhyControl_ReadDone)
557 return OHCI1394_PhyControl_ReadData(val);
558
153e3979
CL		 559 /*
560 * Try a few times without waiting. Sleeping is necessary
561 * only when the link/PHY interface is busy.
562 */
563 if (i >= 3)
564 msleep(1);
ed568912 565 }
64d21720 566 dev_err(ohci->card.device, "failed to read phy reg\n");
ed568912 567
35d999b1
SR		 568 return -EBUSY;
569}
4a96b4fc 570
35d999b1
SR		 571static int write_phy_reg(const struct fw_ohci *ohci, int addr, u32 val)
572{
573 int i;
ed568912 574
ed568912 575 reg_write(ohci, OHCI1394_PhyControl,
35d999b1 576 OHCI1394_PhyControl_Write(addr, val));
153e3979 577 for (i = 0; i < 3 + 100; i++) {
35d999b1 578 val = reg_read(ohci, OHCI1394_PhyControl);
215fa444
SR		 579 if (!~val)
580 return -ENODEV; /* Card was ejected. */
581
35d999b1
SR		 582 if (!(val & OHCI1394_PhyControl_WritePending))
583 return 0;
ed568912 584
153e3979
CL		 585 if (i >= 3)
586 msleep(1);
35d999b1 587 }
64d21720 588 dev_err(ohci->card.device, "failed to write phy reg\n");
35d999b1
SR		 589
590 return -EBUSY;
4a96b4fc
CL		 591}
592
02d37bed
SR		 593static int update_phy_reg(struct fw_ohci *ohci, int addr,
594 int clear_bits, int set_bits)
4a96b4fc 595{
02d37bed 596 int ret = read_phy_reg(ohci, addr);
35d999b1
SR		 597 if (ret < 0)
598 return ret;
4a96b4fc 599
e7014dad
CL		 600 /*
601 * The interrupt status bits are cleared by writing a one bit.
602 * Avoid clearing them unless explicitly requested in set_bits.
603 */
604 if (addr == 5)
605 clear_bits |= PHY_INT_STATUS_BITS;
606
35d999b1 607 return write_phy_reg(ohci, addr, (ret & ~clear_bits) | set_bits);
ed568912
KH		 608}
609
35d999b1 610static int read_paged_phy_reg(struct fw_ohci *ohci, int page, int addr)
925e7a65 611{
35d999b1 612 int ret;
925e7a65 613
02d37bed 614 ret = update_phy_reg(ohci, 7, PHY_PAGE_SELECT, page << 5);
35d999b1
SR		 615 if (ret < 0)
616 return ret;
925e7a65 617
35d999b1 618 return read_phy_reg(ohci, addr);
ed568912
KH		 619}
620
02d37bed
SR		 621static int ohci_read_phy_reg(struct fw_card *card, int addr)
622{
623 struct fw_ohci *ohci = fw_ohci(card);
624 int ret;
625
626 mutex_lock(&ohci->phy_reg_mutex);
627 ret = read_phy_reg(ohci, addr);
628 mutex_unlock(&ohci->phy_reg_mutex);
629
630 return ret;
631}
632
633static int ohci_update_phy_reg(struct fw_card *card, int addr,
634 int clear_bits, int set_bits)
635{
636 struct fw_ohci *ohci = fw_ohci(card);
637 int ret;
638
639 mutex_lock(&ohci->phy_reg_mutex);
640 ret = update_phy_reg(ohci, addr, clear_bits, set_bits);
641 mutex_unlock(&ohci->phy_reg_mutex);
642
643 return ret;
ed568912
KH		 644}
645
7a39d8b8
CL		 646static inline dma_addr_t ar_buffer_bus(struct ar_context *ctx, unsigned int i)
647{
648 return page_private(ctx->pages[i]);
649}
650
651static void ar_context_link_page(struct ar_context *ctx, unsigned int index)
ed568912 652{
7a39d8b8 653 struct descriptor *d;
32b46093 654
7a39d8b8
CL		 655 d = &ctx->descriptors[index];
656 d->branch_address &= cpu_to_le32(~0xf);
657 d->res_count = cpu_to_le16(PAGE_SIZE);
658 d->transfer_status = 0;
32b46093 659
071595eb 660 wmb(); /* finish init of new descriptors before branch_address update */
7a39d8b8
CL		 661 d = &ctx->descriptors[ctx->last_buffer_index];
662 d->branch_address |= cpu_to_le32(1);
663
664 ctx->last_buffer_index = index;
32b46093 665
a77754a7 666 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
837596a6
CL		 667}
668
7a39d8b8 669static void ar_context_release(struct ar_context *ctx)
837596a6 670{
7a39d8b8 671 unsigned int i;
837596a6 672
7a39d8b8
CL		 673 if (ctx->buffer)
674 vm_unmap_ram(ctx->buffer, AR_BUFFERS + AR_WRAPAROUND_PAGES);
32b46093 675
7a39d8b8
CL		 676 for (i = 0; i < AR_BUFFERS; i++)
677 if (ctx->pages[i]) {
678 dma_unmap_page(ctx->ohci->card.device,
679 ar_buffer_bus(ctx, i),
680 PAGE_SIZE, DMA_FROM_DEVICE);
681 __free_page(ctx->pages[i]);
682 }
ed568912
KH		 683}
684
7a39d8b8 685static void ar_context_abort(struct ar_context *ctx, const char *error_msg)
a55709ba 686{
64d21720 687 struct fw_ohci *ohci = ctx->ohci;
a55709ba 688
64d21720
SR		 689 if (reg_read(ohci, CONTROL_CLEAR(ctx->regs)) & CONTEXT_RUN) {
690 reg_write(ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
691 flush_writes(ohci);
a55709ba 692
64d21720
SR		 693 dev_err(ohci->card.device, "AR error: %s; DMA stopped\n",
694 error_msg);
a55709ba 695 }
7a39d8b8
CL		 696 /* FIXME: restart? */
697}
698
699static inline unsigned int ar_next_buffer_index(unsigned int index)
700{
701 return (index + 1) % AR_BUFFERS;
702}
703
704static inline unsigned int ar_prev_buffer_index(unsigned int index)
705{
706 return (index - 1 + AR_BUFFERS) % AR_BUFFERS;
707}
708
709static inline unsigned int ar_first_buffer_index(struct ar_context *ctx)
710{
711 return ar_next_buffer_index(ctx->last_buffer_index);
712}
713
714/*
715 * We search for the buffer that contains the last AR packet DMA data written
716 * by the controller.
717 */
718static unsigned int ar_search_last_active_buffer(struct ar_context *ctx,
719 unsigned int *buffer_offset)
720{
721 unsigned int i, next_i, last = ctx->last_buffer_index;
722 __le16 res_count, next_res_count;
723
724 i = ar_first_buffer_index(ctx);
725 res_count = ACCESS_ONCE(ctx->descriptors[i].res_count);
726
727 /* A buffer that is not yet completely filled must be the last one. */
728 while (i != last && res_count == 0) {
729
730 /* Peek at the next descriptor. */
731 next_i = ar_next_buffer_index(i);
732 rmb(); /* read descriptors in order */
733 next_res_count = ACCESS_ONCE(
734 ctx->descriptors[next_i].res_count);
735 /*
736 * If the next descriptor is still empty, we must stop at this
737 * descriptor.
738 */
739 if (next_res_count == cpu_to_le16(PAGE_SIZE)) {
740 /*
741 * The exception is when the DMA data for one packet is
742 * split over three buffers; in this case, the middle
743 * buffer's descriptor might be never updated by the
744 * controller and look still empty, and we have to peek
745 * at the third one.
746 */
747 if (MAX_AR_PACKET_SIZE > PAGE_SIZE && i != last) {
748 next_i = ar_next_buffer_index(next_i);
749 rmb();
750 next_res_count = ACCESS_ONCE(
751 ctx->descriptors[next_i].res_count);
752 if (next_res_count != cpu_to_le16(PAGE_SIZE))
753 goto next_buffer_is_active;
754 }
755
756 break;
757 }
758
759next_buffer_is_active:
760 i = next_i;
761 res_count = next_res_count;
762 }
763
764 rmb(); /* read res_count before the DMA data */
765
766 *buffer_offset = PAGE_SIZE - le16_to_cpu(res_count);
767 if (*buffer_offset > PAGE_SIZE) {
768 *buffer_offset = 0;
769 ar_context_abort(ctx, "corrupted descriptor");
770 }
771
772 return i;
773}
774
775static void ar_sync_buffers_for_cpu(struct ar_context *ctx,
776 unsigned int end_buffer_index,
777 unsigned int end_buffer_offset)
778{
779 unsigned int i;
780
781 i = ar_first_buffer_index(ctx);
782 while (i != end_buffer_index) {
783 dma_sync_single_for_cpu(ctx->ohci->card.device,
784 ar_buffer_bus(ctx, i),
785 PAGE_SIZE, DMA_FROM_DEVICE);
786 i = ar_next_buffer_index(i);
787 }
788 if (end_buffer_offset > 0)
789 dma_sync_single_for_cpu(ctx->ohci->card.device,
790 ar_buffer_bus(ctx, i),
791 end_buffer_offset, DMA_FROM_DEVICE);
a55709ba
JF		 792}
793
11bf20ad
SR		 794#if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
795#define cond_le32_to_cpu(v) \
4a635593 796 (ohci->quirks & QUIRK_BE_HEADERS ? (__force __u32)(v) : le32_to_cpu(v))
11bf20ad
SR		 797#else
798#define cond_le32_to_cpu(v) le32_to_cpu(v)
799#endif
800
32b46093 801static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer)
ed568912 802{
ed568912 803 struct fw_ohci *ohci = ctx->ohci;
2639a6fb
KH		 804 struct fw_packet p;
805 u32 status, length, tcode;
43286568 806 int evt;
2639a6fb 807
11bf20ad
SR		 808 p.header[0] = cond_le32_to_cpu(buffer[0]);
809 p.header[1] = cond_le32_to_cpu(buffer[1]);
810 p.header[2] = cond_le32_to_cpu(buffer[2]);
2639a6fb
KH		 811
812 tcode = (p.header[0] >> 4) & 0x0f;
813 switch (tcode) {
814 case TCODE_WRITE_QUADLET_REQUEST:
815 case TCODE_READ_QUADLET_RESPONSE:
32b46093 816 p.header[3] = (__force __u32) buffer[3];
2639a6fb 817 p.header_length = 16;
32b46093 818 p.payload_length = 0;
2639a6fb
KH		 819 break;
820
2639a6fb 821 case TCODE_READ_BLOCK_REQUEST :
11bf20ad 822 p.header[3] = cond_le32_to_cpu(buffer[3]);
32b46093
KH		 823 p.header_length = 16;
824 p.payload_length = 0;
825 break;
826
827 case TCODE_WRITE_BLOCK_REQUEST:
2639a6fb
KH		 828 case TCODE_READ_BLOCK_RESPONSE:
829 case TCODE_LOCK_REQUEST:
830 case TCODE_LOCK_RESPONSE:
11bf20ad 831 p.header[3] = cond_le32_to_cpu(buffer[3]);
2639a6fb 832 p.header_length = 16;
32b46093 833 p.payload_length = p.header[3] >> 16;
7a39d8b8
CL		 834 if (p.payload_length > MAX_ASYNC_PAYLOAD) {
835 ar_context_abort(ctx, "invalid packet length");
836 return NULL;
837 }
2639a6fb
KH		 838 break;
839
840 case TCODE_WRITE_RESPONSE:
841 case TCODE_READ_QUADLET_REQUEST:
32b46093 842 case OHCI_TCODE_PHY_PACKET:
2639a6fb 843 p.header_length = 12;
32b46093 844 p.payload_length = 0;
2639a6fb 845 break;
ccff9629
SR		 846
847 default:
7a39d8b8
CL		 848 ar_context_abort(ctx, "invalid tcode");
849 return NULL;
2639a6fb 850 }
ed568912 851
32b46093
KH		 852 p.payload = (void *) buffer + p.header_length;
853
854 /* FIXME: What to do about evt_* errors? */
855 length = (p.header_length + p.payload_length + 3) / 4;
11bf20ad 856 status = cond_le32_to_cpu(buffer[length]);
43286568 857 evt = (status >> 16) & 0x1f;
32b46093 858
43286568 859 p.ack = evt - 16;
32b46093
KH		 860 p.speed = (status >> 21) & 0x7;
861 p.timestamp = status & 0xffff;
862 p.generation = ohci->request_generation;
ed568912 863
64d21720 864 log_ar_at_event(ohci, 'R', p.speed, p.header, evt);
ad3c0fe8 865
c781c06d 866 /*
a4dc090b
SR		 867 * Several controllers, notably from NEC and VIA, forget to
868 * write ack_complete status at PHY packet reception.
869 */
870 if (evt == OHCI1394_evt_no_status &&
871 (p.header[0] & 0xff) == (OHCI1394_phy_tcode << 4))
872 p.ack = ACK_COMPLETE;
873
874 /*
875 * The OHCI bus reset handler synthesizes a PHY packet with
ed568912
KH		 876 * the new generation number when a bus reset happens (see
877 * section 8.4.2.3). This helps us determine when a request
878 * was received and make sure we send the response in the same
879 * generation. We only need this for requests; for responses
880 * we use the unique tlabel for finding the matching
c781c06d 881 * request.
d34316a4
SR		 882 *
883 * Alas some chips sometimes emit bus reset packets with a
884 * wrong generation. We set the correct generation for these
2d7a36e2 885 * at a slightly incorrect time (in bus_reset_work).
c781c06d 886 */
d34316a4 887 if (evt == OHCI1394_evt_bus_reset) {
4a635593 888 if (!(ohci->quirks & QUIRK_RESET_PACKET))
d34316a4
SR		 889 ohci->request_generation = (p.header[2] >> 16) & 0xff;
890 } else if (ctx == &ohci->ar_request_ctx) {
2639a6fb 891 fw_core_handle_request(&ohci->card, &p);
d34316a4 892 } else {
2639a6fb 893 fw_core_handle_response(&ohci->card, &p);
d34316a4 894 }
ed568912 895
32b46093
KH		 896 return buffer + length + 1;
897}
ed568912 898
7a39d8b8
CL		 899static void *handle_ar_packets(struct ar_context *ctx, void *p, void *end)
900{
901 void *next;
902
903 while (p < end) {
904 next = handle_ar_packet(ctx, p);
905 if (!next)
906 return p;
907 p = next;
908 }
909
910 return p;
911}
912
913static void ar_recycle_buffers(struct ar_context *ctx, unsigned int end_buffer)
914{
915 unsigned int i;
916
917 i = ar_first_buffer_index(ctx);
918 while (i != end_buffer) {
919 dma_sync_single_for_device(ctx->ohci->card.device,
920 ar_buffer_bus(ctx, i),
921 PAGE_SIZE, DMA_FROM_DEVICE);
922 ar_context_link_page(ctx, i);
923 i = ar_next_buffer_index(i);
924 }
925}
926
32b46093
KH		 927static void ar_context_tasklet(unsigned long data)
928{
929 struct ar_context *ctx = (struct ar_context *)data;
7a39d8b8
CL		 930 unsigned int end_buffer_index, end_buffer_offset;
931 void *p, *end;
32b46093 932
7a39d8b8
CL		 933 p = ctx->pointer;
934 if (!p)
935 return;
32b46093 936
7a39d8b8
CL		 937 end_buffer_index = ar_search_last_active_buffer(ctx,
938 &end_buffer_offset);
939 ar_sync_buffers_for_cpu(ctx, end_buffer_index, end_buffer_offset);
940 end = ctx->buffer + end_buffer_index * PAGE_SIZE + end_buffer_offset;
32b46093 941
7a39d8b8 942 if (end_buffer_index < ar_first_buffer_index(ctx)) {
c781c06d 943 /*
7a39d8b8
CL		 944 * The filled part of the overall buffer wraps around; handle
945 * all packets up to the buffer end here. If the last packet
946 * wraps around, its tail will be visible after the buffer end
947 * because the buffer start pages are mapped there again.
c781c06d 948 */
7a39d8b8
CL		 949 void *buffer_end = ctx->buffer + AR_BUFFERS * PAGE_SIZE;
950 p = handle_ar_packets(ctx, p, buffer_end);
951 if (p < buffer_end)
952 goto error;
953 /* adjust p to point back into the actual buffer */
954 p -= AR_BUFFERS * PAGE_SIZE;
955 }
32b46093 956
7a39d8b8
CL		 957 p = handle_ar_packets(ctx, p, end);
958 if (p != end) {
959 if (p > end)
960 ar_context_abort(ctx, "inconsistent descriptor");
961 goto error;
962 }
32b46093 963
7a39d8b8
CL		 964 ctx->pointer = p;
965 ar_recycle_buffers(ctx, end_buffer_index);
32b46093 966
7a39d8b8 967 return;
a1f805e5 968
7a39d8b8
CL		 969error:
970 ctx->pointer = NULL;
ed568912
KH		 971}
972
ec766a79
CL		 973static int ar_context_init(struct ar_context *ctx, struct fw_ohci *ohci,
974 unsigned int descriptors_offset, u32 regs)
ed568912 975{
7a39d8b8
CL		 976 unsigned int i;
977 dma_addr_t dma_addr;
978 struct page *pages[AR_BUFFERS + AR_WRAPAROUND_PAGES];
979 struct descriptor *d;
ed568912 980
72e318e0
KH		 981 ctx->regs = regs;
982 ctx->ohci = ohci;
ed568912
KH		 983 tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx);
984
7a39d8b8
CL		 985 for (i = 0; i < AR_BUFFERS; i++) {
986 ctx->pages[i] = alloc_page(GFP_KERNEL | GFP_DMA32);
987 if (!ctx->pages[i])
988 goto out_of_memory;
989 dma_addr = dma_map_page(ohci->card.device, ctx->pages[i],
990 0, PAGE_SIZE, DMA_FROM_DEVICE);
991 if (dma_mapping_error(ohci->card.device, dma_addr)) {
992 __free_page(ctx->pages[i]);
993 ctx->pages[i] = NULL;
994 goto out_of_memory;
995 }
996 set_page_private(ctx->pages[i], dma_addr);
997 }
998
999 for (i = 0; i < AR_BUFFERS; i++)
1000 pages[i] = ctx->pages[i];
1001 for (i = 0; i < AR_WRAPAROUND_PAGES; i++)
1002 pages[AR_BUFFERS + i] = ctx->pages[i];
1003 ctx->buffer = vm_map_ram(pages, AR_BUFFERS + AR_WRAPAROUND_PAGES,
14271304 1004 -1, PAGE_KERNEL);
7a39d8b8
CL		 1005 if (!ctx->buffer)
1006 goto out_of_memory;
1007
ec766a79
CL		 1008 ctx->descriptors = ohci->misc_buffer + descriptors_offset;
1009 ctx->descriptors_bus = ohci->misc_buffer_bus + descriptors_offset;
7a39d8b8
CL		 1010
1011 for (i = 0; i < AR_BUFFERS; i++) {
1012 d = &ctx->descriptors[i];
1013 d->req_count = cpu_to_le16(PAGE_SIZE);
1014 d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
1015 DESCRIPTOR_STATUS |
1016 DESCRIPTOR_BRANCH_ALWAYS);
1017 d->data_address = cpu_to_le32(ar_buffer_bus(ctx, i));
1018 d->branch_address = cpu_to_le32(ctx->descriptors_bus +
1019 ar_next_buffer_index(i) * sizeof(struct descriptor));
1020 }
32b46093 1021
2aef469a 1022 return 0;
7a39d8b8
CL		 1023
1024out_of_memory:
1025 ar_context_release(ctx);
1026
1027 return -ENOMEM;
2aef469a
KH		 1028}
1029
1030static void ar_context_run(struct ar_context *ctx)
1031{
7a39d8b8
CL		 1032 unsigned int i;
1033
1034 for (i = 0; i < AR_BUFFERS; i++)
1035 ar_context_link_page(ctx, i);
2aef469a 1036
7a39d8b8 1037 ctx->pointer = ctx->buffer;
2aef469a 1038
7a39d8b8 1039 reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ctx->descriptors_bus | 1);
a77754a7 1040 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN);
ed568912 1041}
373b2edd 1042
53dca511 1043static struct descriptor *find_branch_descriptor(struct descriptor *d, int z)
a186b4a6 1044{
0ff8fbc6 1045 __le16 branch;
a186b4a6 1046
0ff8fbc6 1047 branch = d->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS);
a186b4a6
JW		 1048
1049 /* figure out which descriptor the branch address goes in */
0ff8fbc6 1050 if (z == 2 && branch == cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))
a186b4a6
JW		 1051 return d;
1052 else
1053 return d + z - 1;
1054}
1055
30200739
KH		 1056static void context_tasklet(unsigned long data)
1057{
1058 struct context *ctx = (struct context *) data;
30200739
KH		 1059 struct descriptor *d, *last;
1060 u32 address;
1061 int z;
fe5ca634 1062 struct descriptor_buffer *desc;
30200739 1063
fe5ca634
DM		 1064 desc = list_entry(ctx->buffer_list.next,
1065 struct descriptor_buffer, list);
1066 last = ctx->last;
30200739 1067 while (last->branch_address != 0) {
fe5ca634 1068 struct descriptor_buffer *old_desc = desc;
30200739
KH		 1069 address = le32_to_cpu(last->branch_address);
1070 z = address & 0xf;
fe5ca634 1071 address &= ~0xf;
a572e688 1072 ctx->current_bus = address;
fe5ca634
DM		 1073
1074 /* If the branch address points to a buffer outside of the
1075 * current buffer, advance to the next buffer. */
1076 if (address < desc->buffer_bus ||
1077 address >= desc->buffer_bus + desc->used)
1078 desc = list_entry(desc->list.next,
1079 struct descriptor_buffer, list);
1080 d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d);
a186b4a6 1081 last = find_branch_descriptor(d, z);
30200739
KH		 1082
1083 if (!ctx->callback(ctx, d, last))
1084 break;
1085
fe5ca634
DM		 1086 if (old_desc != desc) {
1087 /* If we've advanced to the next buffer, move the
1088 * previous buffer to the free list. */
1089 unsigned long flags;
1090 old_desc->used = 0;
1091 spin_lock_irqsave(&ctx->ohci->lock, flags);
1092 list_move_tail(&old_desc->list, &ctx->buffer_list);
1093 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1094 }
1095 ctx->last = last;
30200739
KH		 1096 }
1097}
1098
fe5ca634
DM		 1099/*
1100 * Allocate a new buffer and add it to the list of free buffers for this
1101 * context. Must be called with ohci->lock held.
1102 */
53dca511 1103static int context_add_buffer(struct context *ctx)
fe5ca634
DM		 1104{
1105 struct descriptor_buffer *desc;
f5101d58 1106 dma_addr_t uninitialized_var(bus_addr);
fe5ca634
DM		 1107 int offset;
1108
1109 /*
1110 * 16MB of descriptors should be far more than enough for any DMA
1111 * program. This will catch run-away userspace or DoS attacks.
1112 */
1113 if (ctx->total_allocation >= 16*1024*1024)
1114 return -ENOMEM;
1115
1116 desc = dma_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE,
1117 &bus_addr, GFP_ATOMIC);
1118 if (!desc)
1119 return -ENOMEM;
1120
1121 offset = (void *)&desc->buffer - (void *)desc;
1122 desc->buffer_size = PAGE_SIZE - offset;
1123 desc->buffer_bus = bus_addr + offset;
1124 desc->used = 0;
1125
1126 list_add_tail(&desc->list, &ctx->buffer_list);
1127 ctx->total_allocation += PAGE_SIZE;
1128
1129 return 0;
1130}
1131
53dca511
SR		 1132static int context_init(struct context *ctx, struct fw_ohci *ohci,
1133 u32 regs, descriptor_callback_t callback)
30200739
KH		 1134{
1135 ctx->ohci = ohci;
1136 ctx->regs = regs;
fe5ca634
DM		 1137 ctx->total_allocation = 0;
1138
1139 INIT_LIST_HEAD(&ctx->buffer_list);
1140 if (context_add_buffer(ctx) < 0)
30200739
KH		 1141 return -ENOMEM;
1142
fe5ca634
DM		 1143 ctx->buffer_tail = list_entry(ctx->buffer_list.next,
1144 struct descriptor_buffer, list);
1145
30200739
KH		 1146 tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx);
1147 ctx->callback = callback;
1148
c781c06d
KH		 1149 /*
1150 * We put a dummy descriptor in the buffer that has a NULL
30200739 1151 * branch address and looks like it's been sent. That way we
fe5ca634 1152 * have a descriptor to append DMA programs to.
c781c06d 1153 */
fe5ca634
DM		 1154 memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer));
1155 ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST);
1156 ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011);
1157 ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer);
1158 ctx->last = ctx->buffer_tail->buffer;
1159 ctx->prev = ctx->buffer_tail->buffer;
30200739
KH		 1160
1161 return 0;
1162}
1163
53dca511 1164static void context_release(struct context *ctx)
30200739
KH		 1165{
1166 struct fw_card *card = &ctx->ohci->card;
fe5ca634 1167 struct descriptor_buffer *desc, *tmp;
30200739 1168
fe5ca634
DM		 1169 list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list)
1170 dma_free_coherent(card->device, PAGE_SIZE, desc,
1171 desc->buffer_bus -
1172 ((void *)&desc->buffer - (void *)desc));
30200739
KH		 1173}
1174
fe5ca634 1175/* Must be called with ohci->lock held */
53dca511
SR		 1176static struct descriptor *context_get_descriptors(struct context *ctx,
1177 int z, dma_addr_t *d_bus)
30200739 1178{
fe5ca634
DM		 1179 struct descriptor *d = NULL;
1180 struct descriptor_buffer *desc = ctx->buffer_tail;
1181
1182 if (z * sizeof(*d) > desc->buffer_size)
1183 return NULL;
1184
1185 if (z * sizeof(*d) > desc->buffer_size - desc->used) {
1186 /* No room for the descriptor in this buffer, so advance to the
1187 * next one. */
30200739 1188
fe5ca634
DM		 1189 if (desc->list.next == &ctx->buffer_list) {
1190 /* If there is no free buffer next in the list,
1191 * allocate one. */
1192 if (context_add_buffer(ctx) < 0)
1193 return NULL;
1194 }
1195 desc = list_entry(desc->list.next,
1196 struct descriptor_buffer, list);
1197 ctx->buffer_tail = desc;
1198 }
30200739 1199
fe5ca634 1200 d = desc->buffer + desc->used / sizeof(*d);
2d826cc5 1201 memset(d, 0, z * sizeof(*d));
fe5ca634 1202 *d_bus = desc->buffer_bus + desc->used;
30200739
KH		 1203
1204 return d;
1205}
1206
295e3feb 1207static void context_run(struct context *ctx, u32 extra)
30200739
KH		 1208{
1209 struct fw_ohci *ohci = ctx->ohci;
1210
a77754a7 1211 reg_write(ohci, COMMAND_PTR(ctx->regs),
fe5ca634 1212 le32_to_cpu(ctx->last->branch_address));
a77754a7
KH		 1213 reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0);
1214 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra);
386a4153 1215 ctx->running = true;
30200739
KH		 1216 flush_writes(ohci);
1217}
1218
1219static void context_append(struct context *ctx,
1220 struct descriptor *d, int z, int extra)
1221{
1222 dma_addr_t d_bus;
fe5ca634 1223 struct descriptor_buffer *desc = ctx->buffer_tail;
30200739 1224
fe5ca634 1225 d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d);
30200739 1226
fe5ca634 1227 desc->used += (z + extra) * sizeof(*d);
071595eb
SR		 1228
1229 wmb(); /* finish init of new descriptors before branch_address update */
fe5ca634
DM		 1230 ctx->prev->branch_address = cpu_to_le32(d_bus | z);
1231 ctx->prev = find_branch_descriptor(d, z);
30200739
KH		 1232}
1233
1234static void context_stop(struct context *ctx)
1235{
64d21720 1236 struct fw_ohci *ohci = ctx->ohci;
30200739 1237 u32 reg;
b8295668 1238 int i;
30200739 1239
64d21720 1240 reg_write(ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
386a4153 1241 ctx->running = false;
30200739 1242
9ef28ccd 1243 for (i = 0; i < 1000; i++) {
64d21720 1244 reg = reg_read(ohci, CONTROL_SET(ctx->regs));
b8295668 1245 if ((reg & CONTEXT_ACTIVE) == 0)
b0068549 1246 return;
b8295668 1247
9ef28ccd
SR		 1248 if (i)
1249 udelay(10);
b8295668 1250 }
64d21720 1251 dev_err(ohci->card.device, "DMA context still active (0x%08x)\n", reg);
30200739 1252}
ed568912 1253
f319b6a0 1254struct driver_data {
da28947e 1255 u8 inline_data[8];
f319b6a0
KH		 1256 struct fw_packet *packet;
1257};
ed568912 1258
c781c06d
KH		 1259/*
1260 * This function apppends a packet to the DMA queue for transmission.
f319b6a0 1261 * Must always be called with the ochi->lock held to ensure proper
c781c06d
KH		 1262 * generation handling and locking around packet queue manipulation.
1263 */
53dca511
SR		 1264static int at_context_queue_packet(struct context *ctx,
1265 struct fw_packet *packet)
ed568912 1266{
ed568912 1267 struct fw_ohci *ohci = ctx->ohci;
4b6d51ec 1268 dma_addr_t d_bus, uninitialized_var(payload_bus);
f319b6a0
KH		 1269 struct driver_data *driver_data;
1270 struct descriptor *d, *last;
1271 __le32 *header;
ed568912
KH		 1272 int z, tcode;
1273
f319b6a0
KH		 1274 d = context_get_descriptors(ctx, 4, &d_bus);
1275 if (d == NULL) {
1276 packet->ack = RCODE_SEND_ERROR;
1277 return -1;
ed568912
KH		 1278 }
1279
a77754a7 1280 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
f319b6a0
KH		 1281 d[0].res_count = cpu_to_le16(packet->timestamp);
1282
c781c06d 1283 /*
b3834be5 1284 * The DMA format for asynchronous link packets is different
ed568912 1285 * from the IEEE1394 layout, so shift the fields around
5b06db16 1286 * accordingly.
c781c06d 1287 */
f319b6a0 1288
5b06db16 1289 tcode = (packet->header[0] >> 4) & 0x0f;
f319b6a0 1290 header = (__le32 *) &d[1];
5b06db16
CL		 1291 switch (tcode) {
1292 case TCODE_WRITE_QUADLET_REQUEST:
1293 case TCODE_WRITE_BLOCK_REQUEST:
1294 case TCODE_WRITE_RESPONSE:
1295 case TCODE_READ_QUADLET_REQUEST:
1296 case TCODE_READ_BLOCK_REQUEST:
1297 case TCODE_READ_QUADLET_RESPONSE:
1298 case TCODE_READ_BLOCK_RESPONSE:
1299 case TCODE_LOCK_REQUEST:
1300 case TCODE_LOCK_RESPONSE:
f319b6a0
KH		 1301 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1302 (packet->speed << 16));
1303 header[1] = cpu_to_le32((packet->header[1] & 0xffff) |
1304 (packet->header[0] & 0xffff0000));
1305 header[2] = cpu_to_le32(packet->header[2]);
ed568912 1306
ed568912 1307 if (TCODE_IS_BLOCK_PACKET(tcode))
f319b6a0 1308 header[3] = cpu_to_le32(packet->header[3]);
ed568912 1309 else
f319b6a0
KH		 1310 header[3] = (__force __le32) packet->header[3];
1311
1312 d[0].req_count = cpu_to_le16(packet->header_length);
f8c2287c
JF		 1313 break;
1314
5b06db16 1315 case TCODE_LINK_INTERNAL:
f319b6a0
KH		 1316 header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) |
1317 (packet->speed << 16));
5b06db16
CL		 1318 header[1] = cpu_to_le32(packet->header[1]);
1319 header[2] = cpu_to_le32(packet->header[2]);
f319b6a0 1320 d[0].req_count = cpu_to_le16(12);
cc550216 1321
5b06db16 1322 if (is_ping_packet(&packet->header[1]))
cc550216 1323 d[0].control |= cpu_to_le16(DESCRIPTOR_PING);
f8c2287c
JF		 1324 break;
1325
5b06db16 1326 case TCODE_STREAM_DATA:
f8c2287c
JF		 1327 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1328 (packet->speed << 16));
1329 header[1] = cpu_to_le32(packet->header[0] & 0xffff0000);
1330 d[0].req_count = cpu_to_le16(8);
1331 break;
1332
1333 default:
1334 /* BUG(); */
1335 packet->ack = RCODE_SEND_ERROR;
1336 return -1;
ed568912
KH		 1337 }
1338
da28947e 1339 BUILD_BUG_ON(sizeof(struct driver_data) > sizeof(struct descriptor));
f319b6a0
KH		 1340 driver_data = (struct driver_data *) &d[3];
1341 driver_data->packet = packet;
20d11673 1342 packet->driver_data = driver_data;
a186b4a6 1343
f319b6a0 1344 if (packet->payload_length > 0) {
da28947e
CL		 1345 if (packet->payload_length > sizeof(driver_data->inline_data)) {
1346 payload_bus = dma_map_single(ohci->card.device,
1347 packet->payload,
1348 packet->payload_length,
1349 DMA_TO_DEVICE);
1350 if (dma_mapping_error(ohci->card.device, payload_bus)) {
1351 packet->ack = RCODE_SEND_ERROR;
1352 return -1;
1353 }
1354 packet->payload_bus = payload_bus;
1355 packet->payload_mapped = true;
1356 } else {
1357 memcpy(driver_data->inline_data, packet->payload,
1358 packet->payload_length);
1359 payload_bus = d_bus + 3 * sizeof(*d);
f319b6a0
KH		 1360 }
1361
1362 d[2].req_count = cpu_to_le16(packet->payload_length);
1363 d[2].data_address = cpu_to_le32(payload_bus);
1364 last = &d[2];
1365 z = 3;
ed568912 1366 } else {
f319b6a0
KH		 1367 last = &d[0];
1368 z = 2;
ed568912 1369 }
ed568912 1370
a77754a7
KH		 1371 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
1372 DESCRIPTOR_IRQ_ALWAYS |
1373 DESCRIPTOR_BRANCH_ALWAYS);
ed568912 1374
b6258fc1
SR		 1375 /* FIXME: Document how the locking works. */
1376 if (ohci->generation != packet->generation) {
19593ffd 1377 if (packet->payload_mapped)
ab88ca48
SR		 1378 dma_unmap_single(ohci->card.device, payload_bus,
1379 packet->payload_length, DMA_TO_DEVICE);
f319b6a0
KH		 1380 packet->ack = RCODE_GENERATION;
1381 return -1;
1382 }
1383
1384 context_append(ctx, d, z, 4 - z);
ed568912 1385
dd6254e5 1386 if (ctx->running)
13882a82 1387 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
dd6254e5 1388 else
f319b6a0
KH		 1389 context_run(ctx, 0);
1390
1391 return 0;
ed568912
KH		 1392}
1393
82b662dc
CL		 1394static void at_context_flush(struct context *ctx)
1395{
1396 tasklet_disable(&ctx->tasklet);
1397
1398 ctx->flushing = true;
1399 context_tasklet((unsigned long)ctx);
1400 ctx->flushing = false;
1401
1402 tasklet_enable(&ctx->tasklet);
1403}
1404
f319b6a0
KH		 1405static int handle_at_packet(struct context *context,
1406 struct descriptor *d,
1407 struct descriptor *last)
ed568912 1408{
f319b6a0 1409 struct driver_data *driver_data;
ed568912 1410 struct fw_packet *packet;
f319b6a0 1411 struct fw_ohci *ohci = context->ohci;
ed568912
KH		 1412 int evt;
1413
82b662dc 1414 if (last->transfer_status == 0 && !context->flushing)
f319b6a0
KH		 1415 /* This descriptor isn't done yet, stop iteration. */
1416 return 0;
ed568912 1417
f319b6a0
KH		 1418 driver_data = (struct driver_data *) &d[3];
1419 packet = driver_data->packet;
1420 if (packet == NULL)
1421 /* This packet was cancelled, just continue. */
1422 return 1;
730c32f5 1423
19593ffd 1424 if (packet->payload_mapped)
1d1dc5e8 1425 dma_unmap_single(ohci->card.device, packet->payload_bus,
ed568912 1426 packet->payload_length, DMA_TO_DEVICE);
ed568912 1427
f319b6a0
KH		 1428 evt = le16_to_cpu(last->transfer_status) & 0x1f;
1429 packet->timestamp = le16_to_cpu(last->res_count);
ed568912 1430
64d21720 1431 log_ar_at_event(ohci, 'T', packet->speed, packet->header, evt);
ad3c0fe8 1432
f319b6a0
KH		 1433 switch (evt) {
1434 case OHCI1394_evt_timeout:
1435 /* Async response transmit timed out. */
1436 packet->ack = RCODE_CANCELLED;
1437 break;
ed568912 1438
f319b6a0 1439 case OHCI1394_evt_flushed:
c781c06d
KH		 1440 /*
1441 * The packet was flushed should give same error as
1442 * when we try to use a stale generation count.
1443 */
f319b6a0
KH		 1444 packet->ack = RCODE_GENERATION;
1445 break;
ed568912 1446
f319b6a0 1447 case OHCI1394_evt_missing_ack:
82b662dc
CL		 1448 if (context->flushing)
1449 packet->ack = RCODE_GENERATION;
1450 else {
1451 /*
1452 * Using a valid (current) generation count, but the
1453 * node is not on the bus or not sending acks.
1454 */
1455 packet->ack = RCODE_NO_ACK;
1456 }
f319b6a0 1457 break;
ed568912 1458
f319b6a0
KH		 1459 case ACK_COMPLETE + 0x10:
1460 case ACK_PENDING + 0x10:
1461 case ACK_BUSY_X + 0x10:
1462 case ACK_BUSY_A + 0x10:
1463 case ACK_BUSY_B + 0x10:
1464 case ACK_DATA_ERROR + 0x10:
1465 case ACK_TYPE_ERROR + 0x10:
1466 packet->ack = evt - 0x10;
1467 break;
ed568912 1468
82b662dc
CL		 1469 case OHCI1394_evt_no_status:
1470 if (context->flushing) {
1471 packet->ack = RCODE_GENERATION;
1472 break;
1473 }
1474 /* fall through */
1475
f319b6a0
KH		 1476 default:
1477 packet->ack = RCODE_SEND_ERROR;
1478 break;
1479 }
ed568912 1480
f319b6a0 1481 packet->callback(packet, &ohci->card, packet->ack);
ed568912 1482
f319b6a0 1483 return 1;
ed568912
KH		 1484}
1485
a77754a7
KH		 1486#define HEADER_GET_DESTINATION(q) (((q) >> 16) & 0xffff)
1487#define HEADER_GET_TCODE(q) (((q) >> 4) & 0x0f)
1488#define HEADER_GET_OFFSET_HIGH(q) (((q) >> 0) & 0xffff)
1489#define HEADER_GET_DATA_LENGTH(q) (((q) >> 16) & 0xffff)
1490#define HEADER_GET_EXTENDED_TCODE(q) (((q) >> 0) & 0xffff)
93c4cceb 1491
53dca511
SR		 1492static void handle_local_rom(struct fw_ohci *ohci,
1493 struct fw_packet *packet, u32 csr)
93c4cceb
KH		 1494{
1495 struct fw_packet response;
1496 int tcode, length, i;
1497
a77754a7 1498 tcode = HEADER_GET_TCODE(packet->header[0]);
93c4cceb 1499 if (TCODE_IS_BLOCK_PACKET(tcode))
a77754a7 1500 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
93c4cceb
KH		 1501 else
1502 length = 4;
1503
1504 i = csr - CSR_CONFIG_ROM;
1505 if (i + length > CONFIG_ROM_SIZE) {
1506 fw_fill_response(&response, packet->header,
1507 RCODE_ADDRESS_ERROR, NULL, 0);
1508 } else if (!TCODE_IS_READ_REQUEST(tcode)) {
1509 fw_fill_response(&response, packet->header,
1510 RCODE_TYPE_ERROR, NULL, 0);
1511 } else {
1512 fw_fill_response(&response, packet->header, RCODE_COMPLETE,
1513 (void *) ohci->config_rom + i, length);
1514 }
1515
1516 fw_core_handle_response(&ohci->card, &response);
1517}
1518
53dca511
SR		 1519static void handle_local_lock(struct fw_ohci *ohci,
1520 struct fw_packet *packet, u32 csr)
93c4cceb
KH		 1521{
1522 struct fw_packet response;
e1393667 1523 int tcode, length, ext_tcode, sel, try;
93c4cceb
KH		 1524 __be32 *payload, lock_old;
1525 u32 lock_arg, lock_data;
1526
a77754a7
KH		 1527 tcode = HEADER_GET_TCODE(packet->header[0]);
1528 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
93c4cceb 1529 payload = packet->payload;
a77754a7 1530 ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]);
93c4cceb
KH		 1531
1532 if (tcode == TCODE_LOCK_REQUEST &&
1533 ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) {
1534 lock_arg = be32_to_cpu(payload[0]);
1535 lock_data = be32_to_cpu(payload[1]);
1536 } else if (tcode == TCODE_READ_QUADLET_REQUEST) {
1537 lock_arg = 0;
1538 lock_data = 0;
1539 } else {
1540 fw_fill_response(&response, packet->header,
1541 RCODE_TYPE_ERROR, NULL, 0);
1542 goto out;
1543 }
1544
1545 sel = (csr - CSR_BUS_MANAGER_ID) / 4;
1546 reg_write(ohci, OHCI1394_CSRData, lock_data);
1547 reg_write(ohci, OHCI1394_CSRCompareData, lock_arg);
1548 reg_write(ohci, OHCI1394_CSRControl, sel);
1549
e1393667
CL		 1550 for (try = 0; try < 20; try++)
1551 if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000) {
1552 lock_old = cpu_to_be32(reg_read(ohci,
1553 OHCI1394_CSRData));
1554 fw_fill_response(&response, packet->header,
1555 RCODE_COMPLETE,
1556 &lock_old, sizeof(lock_old));
1557 goto out;
1558 }
1559
64d21720 1560 dev_err(ohci->card.device, "swap not done (CSR lock timeout)\n");
e1393667 1561 fw_fill_response(&response, packet->header, RCODE_BUSY, NULL, 0);
93c4cceb 1562
93c4cceb
KH		 1563 out:
1564 fw_core_handle_response(&ohci->card, &response);
1565}
1566
53dca511 1567static void handle_local_request(struct context *ctx, struct fw_packet *packet)
93c4cceb 1568{
2608203d 1569 u64 offset, csr;
93c4cceb 1570
473d28c7
KH		 1571 if (ctx == &ctx->ohci->at_request_ctx) {
1572 packet->ack = ACK_PENDING;
1573 packet->callback(packet, &ctx->ohci->card, packet->ack);
1574 }
93c4cceb
KH		 1575
1576 offset =
1577 ((unsigned long long)
a77754a7 1578 HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) |
93c4cceb
KH		 1579 packet->header[2];
1580 csr = offset - CSR_REGISTER_BASE;
1581
1582 /* Handle config rom reads. */
1583 if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END)
1584 handle_local_rom(ctx->ohci, packet, csr);
1585 else switch (csr) {
1586 case CSR_BUS_MANAGER_ID:
1587 case CSR_BANDWIDTH_AVAILABLE:
1588 case CSR_CHANNELS_AVAILABLE_HI:
1589 case CSR_CHANNELS_AVAILABLE_LO:
1590 handle_local_lock(ctx->ohci, packet, csr);
1591 break;
1592 default:
1593 if (ctx == &ctx->ohci->at_request_ctx)
1594 fw_core_handle_request(&ctx->ohci->card, packet);
1595 else
1596 fw_core_handle_response(&ctx->ohci->card, packet);
1597 break;
1598 }
473d28c7
KH		 1599
1600 if (ctx == &ctx->ohci->at_response_ctx) {
1601 packet->ack = ACK_COMPLETE;
1602 packet->callback(packet, &ctx->ohci->card, packet->ack);
1603 }
93c4cceb 1604}
e636fe25 1605
53dca511 1606static void at_context_transmit(struct context *ctx, struct fw_packet *packet)
ed568912 1607{
ed568912 1608 unsigned long flags;
2dbd7d7e 1609 int ret;
ed568912
KH		 1610
1611 spin_lock_irqsave(&ctx->ohci->lock, flags);
1612
a77754a7 1613 if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id &&
e636fe25 1614 ctx->ohci->generation == packet->generation) {
93c4cceb
KH		 1615 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1616 handle_local_request(ctx, packet);
1617 return;
e636fe25 1618 }
ed568912 1619
2dbd7d7e 1620 ret = at_context_queue_packet(ctx, packet);
ed568912
KH		 1621 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1622
2dbd7d7e 1623 if (ret < 0)
f319b6a0 1624 packet->callback(packet, &ctx->ohci->card, packet->ack);
a186b4a6 1625
ed568912
KH		 1626}
1627
f117a3e3
CL		 1628static void detect_dead_context(struct fw_ohci *ohci,
1629 const char *name, unsigned int regs)
1630{
1631 u32 ctl;
1632
1633 ctl = reg_read(ohci, CONTROL_SET(regs));
cfda62ba 1634 if (ctl & CONTEXT_DEAD)
64d21720
SR		 1635 dev_err(ohci->card.device,
1636 "DMA context %s has stopped, error code: %s\n",
1637 name, evts[ctl & 0x1f]);
f117a3e3
CL		 1638}
1639
1640static void handle_dead_contexts(struct fw_ohci *ohci)
1641{
1642 unsigned int i;
1643 char name[8];
1644
1645 detect_dead_context(ohci, "ATReq", OHCI1394_AsReqTrContextBase);
1646 detect_dead_context(ohci, "ATRsp", OHCI1394_AsRspTrContextBase);
1647 detect_dead_context(ohci, "ARReq", OHCI1394_AsReqRcvContextBase);
1648 detect_dead_context(ohci, "ARRsp", OHCI1394_AsRspRcvContextBase);
1649 for (i = 0; i < 32; ++i) {
1650 if (!(ohci->it_context_support & (1 << i)))
1651 continue;
1652 sprintf(name, "IT%u", i);
1653 detect_dead_context(ohci, name, OHCI1394_IsoXmitContextBase(i));
1654 }
1655 for (i = 0; i < 32; ++i) {
1656 if (!(ohci->ir_context_support & (1 << i)))
1657 continue;
1658 sprintf(name, "IR%u", i);
1659 detect_dead_context(ohci, name, OHCI1394_IsoRcvContextBase(i));
1660 }
1661 /* TODO: maybe try to flush and restart the dead contexts */
1662}
1663
a48777e0
CL		 1664static u32 cycle_timer_ticks(u32 cycle_timer)
1665{
1666 u32 ticks;
1667
1668 ticks = cycle_timer & 0xfff;
1669 ticks += 3072 * ((cycle_timer >> 12) & 0x1fff);
1670 ticks += (3072 * 8000) * (cycle_timer >> 25);
1671
1672 return ticks;
1673}
1674
1675/*
1676 * Some controllers exhibit one or more of the following bugs when updating the
1677 * iso cycle timer register:
1678 * - When the lowest six bits are wrapping around to zero, a read that happens
1679 * at the same time will return garbage in the lowest ten bits.
1680 * - When the cycleOffset field wraps around to zero, the cycleCount field is
1681 * not incremented for about 60 ns.
1682 * - Occasionally, the entire register reads zero.
1683 *
1684 * To catch these, we read the register three times and ensure that the
1685 * difference between each two consecutive reads is approximately the same, i.e.
1686 * less than twice the other. Furthermore, any negative difference indicates an
1687 * error. (A PCI read should take at least 20 ticks of the 24.576 MHz timer to
1688 * execute, so we have enough precision to compute the ratio of the differences.)
1689 */
1690static u32 get_cycle_time(struct fw_ohci *ohci)
1691{
1692 u32 c0, c1, c2;
1693 u32 t0, t1, t2;
1694 s32 diff01, diff12;
1695 int i;
1696
1697 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1698
1699 if (ohci->quirks & QUIRK_CYCLE_TIMER) {
1700 i = 0;
1701 c1 = c2;
1702 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1703 do {
1704 c0 = c1;
1705 c1 = c2;
1706 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1707 t0 = cycle_timer_ticks(c0);
1708 t1 = cycle_timer_ticks(c1);
1709 t2 = cycle_timer_ticks(c2);
1710 diff01 = t1 - t0;
1711 diff12 = t2 - t1;
1712 } while ((diff01 <= 0 || diff12 <= 0 ||
1713 diff01 / diff12 >= 2 || diff12 / diff01 >= 2)
1714 && i++ < 20);
1715 }
1716
1717 return c2;
1718}
1719
1720/*
1721 * This function has to be called at least every 64 seconds. The bus_time
1722 * field stores not only the upper 25 bits of the BUS_TIME register but also
1723 * the most significant bit of the cycle timer in bit 6 so that we can detect
1724 * changes in this bit.
1725 */
1726static u32 update_bus_time(struct fw_ohci *ohci)
1727{
1728 u32 cycle_time_seconds = get_cycle_time(ohci) >> 25;
1729
9d60ef2b
CL		 1730 if (unlikely(!ohci->bus_time_running)) {
1731 reg_write(ohci, OHCI1394_IntMaskSet, OHCI1394_cycle64Seconds);
1732 ohci->bus_time = (lower_32_bits(get_seconds()) & ~0x7f) |
1733 (cycle_time_seconds & 0x40);
1734 ohci->bus_time_running = true;
1735 }
1736
a48777e0
CL		 1737 if ((ohci->bus_time & 0x40) != (cycle_time_seconds & 0x40))
1738 ohci->bus_time += 0x40;
1739
1740 return ohci->bus_time | cycle_time_seconds;
1741}
1742
25935ebe
SG		 1743static int get_status_for_port(struct fw_ohci *ohci, int port_index)
1744{
1745 int reg;
1746
1747 mutex_lock(&ohci->phy_reg_mutex);
1748 reg = write_phy_reg(ohci, 7, port_index);
28897fb7
SR		 1749 if (reg >= 0)
1750 reg = read_phy_reg(ohci, 8);
25935ebe
SG		 1751 mutex_unlock(&ohci->phy_reg_mutex);
1752 if (reg < 0)
1753 return reg;
1754
1755 switch (reg & 0x0f) {
1756 case 0x06:
1757 return 2; /* is child node (connected to parent node) */
1758 case 0x0e:
1759 return 3; /* is parent node (connected to child node) */
1760 }
1761 return 1; /* not connected */
1762}
1763
1764static int get_self_id_pos(struct fw_ohci *ohci, u32 self_id,
1765 int self_id_count)
1766{
1767 int i;
1768 u32 entry;
28897fb7 1769
25935ebe
SG		 1770 for (i = 0; i < self_id_count; i++) {
1771 entry = ohci->self_id_buffer[i];
1772 if ((self_id & 0xff000000) == (entry & 0xff000000))
1773 return -1;
1774 if ((self_id & 0xff000000) < (entry & 0xff000000))
1775 return i;
1776 }
1777 return i;
1778}
1779
52439d60
SG		 1780static int initiated_reset(struct fw_ohci *ohci)
1781{
1782 int reg;
1783 int ret = 0;
1784
1785 mutex_lock(&ohci->phy_reg_mutex);
1786 reg = write_phy_reg(ohci, 7, 0xe0); /* Select page 7 */
1787 if (reg >= 0) {
1788 reg = read_phy_reg(ohci, 8);
1789 reg |= 0x40;
1790 reg = write_phy_reg(ohci, 8, reg); /* set PMODE bit */
1791 if (reg >= 0) {
1792 reg = read_phy_reg(ohci, 12); /* read register 12 */
1793 if (reg >= 0) {
1794 if ((reg & 0x08) == 0x08) {
1795 /* bit 3 indicates "initiated reset" */
1796 ret = 0x2;
1797 }
1798 }
1799 }
1800 }
1801 mutex_unlock(&ohci->phy_reg_mutex);
1802 return ret;
1803}
1804
25935ebe 1805/*
28897fb7
SR		 1806 * TI TSB82AA2B and TSB12LV26 do not receive the selfID of a locally
1807 * attached TSB41BA3D phy; see http://www.ti.com/litv/pdf/sllz059.
1808 * Construct the selfID from phy register contents.
25935ebe 1809 */
25935ebe
SG		 1810static int find_and_insert_self_id(struct fw_ohci *ohci, int self_id_count)
1811{
28897fb7
SR		 1812 int reg, i, pos, status;
1813 /* link active 1, speed 3, bridge 0, contender 1, more packets 0 */
1814 u32 self_id = 0x8040c800;
25935ebe
SG		 1815
1816 reg = reg_read(ohci, OHCI1394_NodeID);
1817 if (!(reg & OHCI1394_NodeID_idValid)) {
64d21720
SR		 1818 dev_notice(ohci->card.device,
1819 "node ID not valid, new bus reset in progress\n");
25935ebe
SG		 1820 return -EBUSY;
1821 }
1822 self_id |= ((reg & 0x3f) << 24); /* phy ID */
1823
28897fb7 1824 reg = ohci_read_phy_reg(&ohci->card, 4);
25935ebe
SG		 1825 if (reg < 0)
1826 return reg;
1827 self_id |= ((reg & 0x07) << 8); /* power class */
1828
28897fb7 1829 reg = ohci_read_phy_reg(&ohci->card, 1);
25935ebe
SG		 1830 if (reg < 0)
1831 return reg;
1832 self_id |= ((reg & 0x3f) << 16); /* gap count */
1833
1834 for (i = 0; i < 3; i++) {
1835 status = get_status_for_port(ohci, i);
1836 if (status < 0)
1837 return status;
1838 self_id |= ((status & 0x3) << (6 - (i * 2)));
1839 }
1840
52439d60
SG		 1841 self_id |= initiated_reset(ohci);
1842
25935ebe
SG		 1843 pos = get_self_id_pos(ohci, self_id, self_id_count);
1844 if (pos >= 0) {
1845 memmove(&(ohci->self_id_buffer[pos+1]),
1846 &(ohci->self_id_buffer[pos]),
1847 (self_id_count - pos) * sizeof(*ohci->self_id_buffer));
1848 ohci->self_id_buffer[pos] = self_id;
1849 self_id_count++;
1850 }
1851 return self_id_count;
1852}
1853
2d7a36e2 1854static void bus_reset_work(struct work_struct *work)
ed568912 1855{
2d7a36e2
SG		 1856 struct fw_ohci *ohci =
1857 container_of(work, struct fw_ohci, bus_reset_work);
d713dfa7
SR		 1858 int self_id_count, generation, new_generation, i, j;
1859 u32 reg;
4eaff7d6
SR		 1860 void *free_rom = NULL;
1861 dma_addr_t free_rom_bus = 0;
4ffb7a6a 1862 bool is_new_root;
ed568912
KH		 1863
1864 reg = reg_read(ohci, OHCI1394_NodeID);
1865 if (!(reg & OHCI1394_NodeID_idValid)) {
64d21720
SR		 1866 dev_notice(ohci->card.device,
1867 "node ID not valid, new bus reset in progress\n");
ed568912
KH		 1868 return;
1869 }
02ff8f8e 1870 if ((reg & OHCI1394_NodeID_nodeNumber) == 63) {
64d21720 1871 dev_notice(ohci->card.device, "malconfigured bus\n");
02ff8f8e
SR		 1872 return;
1873 }
1874 ohci->node_id = reg & (OHCI1394_NodeID_busNumber |
1875 OHCI1394_NodeID_nodeNumber);
ed568912 1876
4ffb7a6a
CL		 1877 is_new_root = (reg & OHCI1394_NodeID_root) != 0;
1878 if (!(ohci->is_root && is_new_root))
1879 reg_write(ohci, OHCI1394_LinkControlSet,
1880 OHCI1394_LinkControl_cycleMaster);
1881 ohci->is_root = is_new_root;
1882
c8a9a498
SR		 1883 reg = reg_read(ohci, OHCI1394_SelfIDCount);
1884 if (reg & OHCI1394_SelfIDCount_selfIDError) {
64d21720 1885 dev_notice(ohci->card.device, "inconsistent self IDs\n");
c8a9a498
SR		 1886 return;
1887 }
c781c06d
KH		 1888 /*
1889 * The count in the SelfIDCount register is the number of
ed568912
KH		 1890 * bytes in the self ID receive buffer. Since we also receive
1891 * the inverted quadlets and a header quadlet, we shift one
c781c06d
KH		 1892 * bit extra to get the actual number of self IDs.
1893 */
928ec5f1 1894 self_id_count = (reg >> 3) & 0xff;
25935ebe
SG		 1895
1896 if (self_id_count > 252) {
64d21720 1897 dev_notice(ohci->card.device, "inconsistent self IDs\n");
016bf3df
SR		 1898 return;
1899 }
25935ebe 1900
11bf20ad 1901 generation = (cond_le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff;
ee71c2f9 1902 rmb();
ed568912
KH		 1903
1904 for (i = 1, j = 0; j < self_id_count; i += 2, j++) {
c8a9a498 1905 if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1]) {
32eaeae1
CL		 1906 /*
1907 * If the invalid data looks like a cycle start packet,
1908 * it's likely to be the result of the cycle master
1909 * having a wrong gap count. In this case, the self IDs
1910 * so far are valid and should be processed so that the
1911 * bus manager can then correct the gap count.
1912 */
1913 if (cond_le32_to_cpu(ohci->self_id_cpu[i])
1914 == 0xffff008f) {
64d21720
SR		 1915 dev_notice(ohci->card.device,
1916 "ignoring spurious self IDs\n");
32eaeae1
CL		 1917 self_id_count = j;
1918 break;
1919 } else {
64d21720
SR		 1920 dev_notice(ohci->card.device,
1921 "inconsistent self IDs\n");
32eaeae1
CL		 1922 return;
1923 }
c8a9a498 1924 }
11bf20ad
SR		 1925 ohci->self_id_buffer[j] =
1926 cond_le32_to_cpu(ohci->self_id_cpu[i]);
ed568912 1927 }
25935ebe
SG		 1928
1929 if (ohci->quirks & QUIRK_TI_SLLZ059) {
1930 self_id_count = find_and_insert_self_id(ohci, self_id_count);
1931 if (self_id_count < 0) {
64d21720
SR		 1932 dev_notice(ohci->card.device,
1933 "could not construct local self ID\n");
25935ebe
SG		 1934 return;
1935 }
1936 }
1937
1938 if (self_id_count == 0) {
64d21720 1939 dev_notice(ohci->card.device, "inconsistent self IDs\n");
25935ebe
SG		 1940 return;
1941 }
ee71c2f9 1942 rmb();
ed568912 1943
c781c06d
KH		 1944 /*
1945 * Check the consistency of the self IDs we just read. The
ed568912
KH		 1946 * problem we face is that a new bus reset can start while we
1947 * read out the self IDs from the DMA buffer. If this happens,
1948 * the DMA buffer will be overwritten with new self IDs and we
1949 * will read out inconsistent data. The OHCI specification
1950 * (section 11.2) recommends a technique similar to
1951 * linux/seqlock.h, where we remember the generation of the
1952 * self IDs in the buffer before reading them out and compare
1953 * it to the current generation after reading them out. If
1954 * the two generations match we know we have a consistent set
c781c06d
KH		 1955 * of self IDs.
1956 */
ed568912
KH		 1957
1958 new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff;
1959 if (new_generation != generation) {
64d21720
SR		 1960 dev_notice(ohci->card.device,
1961 "new bus reset, discarding self ids\n");
ed568912
KH		 1962 return;
1963 }
1964
1965 /* FIXME: Document how the locking works. */
8a8c4736 1966 spin_lock_irq(&ohci->lock);
ed568912 1967
82b662dc 1968 ohci->generation = -1; /* prevent AT packet queueing */
f319b6a0
KH		 1969 context_stop(&ohci->at_request_ctx);
1970 context_stop(&ohci->at_response_ctx);
82b662dc 1971
8a8c4736 1972 spin_unlock_irq(&ohci->lock);
82b662dc 1973
78dec56d
SR		 1974 /*
1975 * Per OHCI 1.2 draft, clause 7.2.3.3, hardware may leave unsent
1976 * packets in the AT queues and software needs to drain them.
1977 * Some OHCI 1.1 controllers (JMicron) apparently require this too.
1978 */
82b662dc
CL		 1979 at_context_flush(&ohci->at_request_ctx);
1980 at_context_flush(&ohci->at_response_ctx);
1981
8a8c4736 1982 spin_lock_irq(&ohci->lock);
82b662dc
CL		 1983
1984 ohci->generation = generation;
ed568912
KH		 1985 reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
1986
4a635593 1987 if (ohci->quirks & QUIRK_RESET_PACKET)
d34316a4
SR		 1988 ohci->request_generation = generation;
1989
c781c06d
KH		 1990 /*
1991 * This next bit is unrelated to the AT context stuff but we
ed568912
KH		 1992 * have to do it under the spinlock also. If a new config rom
1993 * was set up before this reset, the old one is now no longer
1994 * in use and we can free it. Update the config rom pointers
1995 * to point to the current config rom and clear the
88393161 1996 * next_config_rom pointer so a new update can take place.
c781c06d 1997 */
ed568912
KH		 1998
1999 if (ohci->next_config_rom != NULL) {
0bd243c4
KH		 2000 if (ohci->next_config_rom != ohci->config_rom) {
2001 free_rom = ohci->config_rom;
2002 free_rom_bus = ohci->config_rom_bus;
2003 }
ed568912
KH		 2004 ohci->config_rom = ohci->next_config_rom;
2005 ohci->config_rom_bus = ohci->next_config_rom_bus;
2006 ohci->next_config_rom = NULL;
2007
c781c06d
KH		 2008 /*
2009 * Restore config_rom image and manually update
ed568912
KH		 2010 * config_rom registers. Writing the header quadlet
2011 * will indicate that the config rom is ready, so we
c781c06d
KH		 2012 * do that last.
2013 */
ed568912
KH		 2014 reg_write(ohci, OHCI1394_BusOptions,
2015 be32_to_cpu(ohci->config_rom[2]));
8e85973e
SR		 2016 ohci->config_rom[0] = ohci->next_header;
2017 reg_write(ohci, OHCI1394_ConfigROMhdr,
2018 be32_to_cpu(ohci->next_header));
ed568912
KH		 2019 }
2020
080de8c2
SR		 2021#ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
2022 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0);
2023 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0);
2024#endif
2025
8a8c4736 2026 spin_unlock_irq(&ohci->lock);
ed568912 2027
4eaff7d6
SR		 2028 if (free_rom)
2029 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2030 free_rom, free_rom_bus);
2031
64d21720 2032 log_selfids(ohci, generation, self_id_count);
ad3c0fe8 2033
e636fe25 2034 fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation,
c8a94ded
SR		 2035 self_id_count, ohci->self_id_buffer,
2036 ohci->csr_state_setclear_abdicate);
2037 ohci->csr_state_setclear_abdicate = false;
ed568912
KH		 2038}
2039
2040static irqreturn_t irq_handler(int irq, void *data)
2041{
2042 struct fw_ohci *ohci = data;
168cf9af 2043 u32 event, iso_event;
ed568912
KH		 2044 int i;
2045
2046 event = reg_read(ohci, OHCI1394_IntEventClear);
2047
a515958d 2048 if (!event || !~event)
ed568912
KH		 2049 return IRQ_NONE;
2050
8327b37b
CL		 2051 /*
2052 * busReset and postedWriteErr must not be cleared yet
2053 * (OHCI 1.1 clauses 7.2.3.2 and 13.2.8.1)
2054 */
2055 reg_write(ohci, OHCI1394_IntEventClear,
2056 event & ~(OHCI1394_busReset | OHCI1394_postedWriteErr));
64d21720 2057 log_irqs(ohci, event);
ed568912
KH		 2058
2059 if (event & OHCI1394_selfIDComplete)
2d7a36e2 2060 queue_work(fw_workqueue, &ohci->bus_reset_work);
ed568912
KH		 2061
2062 if (event & OHCI1394_RQPkt)
2063 tasklet_schedule(&ohci->ar_request_ctx.tasklet);
2064
2065 if (event & OHCI1394_RSPkt)
2066 tasklet_schedule(&ohci->ar_response_ctx.tasklet);
2067
2068 if (event & OHCI1394_reqTxComplete)
2069 tasklet_schedule(&ohci->at_request_ctx.tasklet);
2070
2071 if (event & OHCI1394_respTxComplete)
2072 tasklet_schedule(&ohci->at_response_ctx.tasklet);
2073
2dd5bed5
CL		 2074 if (event & OHCI1394_isochRx) {
2075 iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear);
2076 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event);
2077
2078 while (iso_event) {
2079 i = ffs(iso_event) - 1;
2080 tasklet_schedule(
2081 &ohci->ir_context_list[i].context.tasklet);
2082 iso_event &= ~(1 << i);
2083 }
ed568912
KH		 2084 }
2085
2dd5bed5
CL		 2086 if (event & OHCI1394_isochTx) {
2087 iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear);
2088 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event);
ed568912 2089
2dd5bed5
CL		 2090 while (iso_event) {
2091 i = ffs(iso_event) - 1;
2092 tasklet_schedule(
2093 &ohci->it_context_list[i].context.tasklet);
2094 iso_event &= ~(1 << i);
2095 }
ed568912
KH		 2096 }
2097
75f7832e 2098 if (unlikely(event & OHCI1394_regAccessFail))
98466cc4 2099 dev_err(ohci->card.device, "register access failure\n");
75f7832e 2100
8327b37b
CL		 2101 if (unlikely(event & OHCI1394_postedWriteErr)) {
2102 reg_read(ohci, OHCI1394_PostedWriteAddressHi);
2103 reg_read(ohci, OHCI1394_PostedWriteAddressLo);
2104 reg_write(ohci, OHCI1394_IntEventClear,
2105 OHCI1394_postedWriteErr);
a74477db 2106 if (printk_ratelimit())
64d21720 2107 dev_err(ohci->card.device, "PCI posted write error\n");
8327b37b 2108 }
e524f616 2109
bb9f2206
SR		 2110 if (unlikely(event & OHCI1394_cycleTooLong)) {
2111 if (printk_ratelimit())
64d21720
SR		 2112 dev_notice(ohci->card.device,
2113 "isochronous cycle too long\n");
bb9f2206
SR		 2114 reg_write(ohci, OHCI1394_LinkControlSet,
2115 OHCI1394_LinkControl_cycleMaster);
2116 }
2117
5ed1f321
JF		 2118 if (unlikely(event & OHCI1394_cycleInconsistent)) {
2119 /*
2120 * We need to clear this event bit in order to make
2121 * cycleMatch isochronous I/O work. In theory we should
2122 * stop active cycleMatch iso contexts now and restart
2123 * them at least two cycles later. (FIXME?)
2124 */
2125 if (printk_ratelimit())
64d21720
SR		 2126 dev_notice(ohci->card.device,
2127 "isochronous cycle inconsistent\n");
5ed1f321
JF		 2128 }
2129
f117a3e3
CL		 2130 if (unlikely(event & OHCI1394_unrecoverableError))
2131 handle_dead_contexts(ohci);
2132
a48777e0
CL		 2133 if (event & OHCI1394_cycle64Seconds) {
2134 spin_lock(&ohci->lock);
2135 update_bus_time(ohci);
2136 spin_unlock(&ohci->lock);
e597e989
CL		 2137 } else
2138 flush_writes(ohci);
a48777e0 2139
ed568912
KH		 2140 return IRQ_HANDLED;
2141}
2142
2aef469a
KH		 2143static int software_reset(struct fw_ohci *ohci)
2144{
9f426173 2145 u32 val;
2aef469a
KH		 2146 int i;
2147
2148 reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
9f426173
SR		 2149 for (i = 0; i < 500; i++) {
2150 val = reg_read(ohci, OHCI1394_HCControlSet);
2151 if (!~val)
2152 return -ENODEV; /* Card was ejected. */
2aef469a 2153
9f426173 2154 if (!(val & OHCI1394_HCControl_softReset))
2aef469a 2155 return 0;
9f426173 2156
2aef469a
KH		 2157 msleep(1);
2158 }
2159
2160 return -EBUSY;
2161}
2162
8e85973e
SR		 2163static void copy_config_rom(__be32 *dest, const __be32 *src, size_t length)
2164{
2165 size_t size = length * 4;
2166
2167 memcpy(dest, src, size);
2168 if (size < CONFIG_ROM_SIZE)
2169 memset(&dest[length], 0, CONFIG_ROM_SIZE - size);
2170}
2171
925e7a65
CL		 2172static int configure_1394a_enhancements(struct fw_ohci *ohci)
2173{
2174 bool enable_1394a;
35d999b1 2175 int ret, clear, set, offset;
925e7a65
CL		 2176
2177 /* Check if the driver should configure link and PHY. */
2178 if (!(reg_read(ohci, OHCI1394_HCControlSet) &
2179 OHCI1394_HCControl_programPhyEnable))
2180 return 0;
2181
2182 /* Paranoia: check whether the PHY supports 1394a, too. */
2183 enable_1394a = false;
35d999b1
SR		 2184 ret = read_phy_reg(ohci, 2);
2185 if (ret < 0)
2186 return ret;
2187 if ((ret & PHY_EXTENDED_REGISTERS) == PHY_EXTENDED_REGISTERS) {
2188 ret = read_paged_phy_reg(ohci, 1, 8);
2189 if (ret < 0)
2190 return ret;
2191 if (ret >= 1)
925e7a65
CL		 2192 enable_1394a = true;
2193 }
2194
2195 if (ohci->quirks & QUIRK_NO_1394A)
2196 enable_1394a = false;
2197
2198 /* Configure PHY and link consistently. */
2199 if (enable_1394a) {
2200 clear = 0;
2201 set = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
2202 } else {
2203 clear = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
2204 set = 0;
2205 }
02d37bed 2206 ret = update_phy_reg(ohci, 5, clear, set);
35d999b1
SR		 2207 if (ret < 0)
2208 return ret;
925e7a65
CL		 2209
2210 if (enable_1394a)
2211 offset = OHCI1394_HCControlSet;
2212 else
2213 offset = OHCI1394_HCControlClear;
2214 reg_write(ohci, offset, OHCI1394_HCControl_aPhyEnhanceEnable);
2215
2216 /* Clean up: configuration has been taken care of. */
2217 reg_write(ohci, OHCI1394_HCControlClear,
2218 OHCI1394_HCControl_programPhyEnable);
2219
2220 return 0;
2221}
2222
25935ebe
SG		 2223static int probe_tsb41ba3d(struct fw_ohci *ohci)
2224{
b810e4ae
SR		 2225 /* TI vendor ID = 0x080028, TSB41BA3D product ID = 0x833005 (sic) */
2226 static const u8 id[] = { 0x08, 0x00, 0x28, 0x83, 0x30, 0x05, };
2227 int reg, i;
25935ebe
SG		 2228
2229 reg = read_phy_reg(ohci, 2);
2230 if (reg < 0)
2231 return reg;
b810e4ae
SR		 2232 if ((reg & PHY_EXTENDED_REGISTERS) != PHY_EXTENDED_REGISTERS)
2233 return 0;
25935ebe 2234
b810e4ae
SR		 2235 for (i = ARRAY_SIZE(id) - 1; i >= 0; i--) {
2236 reg = read_paged_phy_reg(ohci, 1, i + 10);
2237 if (reg < 0)
2238 return reg;
2239 if (reg != id[i])
2240 return 0;
25935ebe 2241 }
b810e4ae 2242 return 1;
25935ebe
SG		 2243}
2244
8e85973e
SR		 2245static int ohci_enable(struct fw_card *card,
2246 const __be32 *config_rom, size_t length)
ed568912
KH		 2247{
2248 struct fw_ohci *ohci = fw_ohci(card);
2249 struct pci_dev *dev = to_pci_dev(card->device);
9d60ef2b 2250 u32 lps, version, irqs;
28897fb7 2251 int i, ret;
ed568912 2252
2aef469a 2253 if (software_reset(ohci)) {
64d21720 2254 dev_err(card->device, "failed to reset ohci card\n");
2aef469a
KH		 2255 return -EBUSY;
2256 }
2257
2258 /*
2259 * Now enable LPS, which we need in order to start accessing
2260 * most of the registers. In fact, on some cards (ALI M5251),
2261 * accessing registers in the SClk domain without LPS enabled
2262 * will lock up the machine. Wait 50msec to make sure we have
02214724
JW		 2263 * full link enabled. However, with some cards (well, at least
2264 * a JMicron PCIe card), we have to try again sometimes.
2aef469a
KH		 2265 */
2266 reg_write(ohci, OHCI1394_HCControlSet,
2267 OHCI1394_HCControl_LPS |
2268 OHCI1394_HCControl_postedWriteEnable);
2269 flush_writes(ohci);
02214724
JW		 2270
2271 for (lps = 0, i = 0; !lps && i < 3; i++) {
2272 msleep(50);
2273 lps = reg_read(ohci, OHCI1394_HCControlSet) &
2274 OHCI1394_HCControl_LPS;
2275 }
2276
2277 if (!lps) {
64d21720 2278 dev_err(card->device, "failed to set Link Power Status\n");
02214724
JW		 2279 return -EIO;
2280 }
2aef469a 2281
25935ebe 2282 if (ohci->quirks & QUIRK_TI_SLLZ059) {
28897fb7
SR		 2283 ret = probe_tsb41ba3d(ohci);
2284 if (ret < 0)
2285 return ret;
2286 if (ret)
64d21720 2287 dev_notice(card->device, "local TSB41BA3D phy\n");
28897fb7 2288 else
25935ebe 2289 ohci->quirks &= ~QUIRK_TI_SLLZ059;
25935ebe
SG		 2290 }
2291
2aef469a
KH		 2292 reg_write(ohci, OHCI1394_HCControlClear,
2293 OHCI1394_HCControl_noByteSwapData);
2294
affc9c24 2295 reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
2aef469a 2296 reg_write(ohci, OHCI1394_LinkControlSet,
2aef469a
KH		 2297 OHCI1394_LinkControl_cycleTimerEnable |
2298 OHCI1394_LinkControl_cycleMaster);
2299
2300 reg_write(ohci, OHCI1394_ATRetries,
2301 OHCI1394_MAX_AT_REQ_RETRIES |
2302 (OHCI1394_MAX_AT_RESP_RETRIES << 4) |
27a2329f
CL		 2303 (OHCI1394_MAX_PHYS_RESP_RETRIES << 8) |
2304 (200 << 16));
2aef469a 2305
9d60ef2b 2306 ohci->bus_time_running = false;
a48777e0 2307
e18907cc
CL		 2308 for (i = 0; i < 32; i++)
2309 if (ohci->ir_context_support & (1 << i))
2310 reg_write(ohci, OHCI1394_IsoRcvContextControlClear(i),
2311 IR_CONTEXT_MULTI_CHANNEL_MODE);
2312
e91b2787
CL		 2313 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
2314 if (version >= OHCI_VERSION_1_1) {
2315 reg_write(ohci, OHCI1394_InitialChannelsAvailableHi,
2316 0xfffffffe);
db3c9cc1 2317 card->broadcast_channel_auto_allocated = true;
e91b2787
CL		 2318 }
2319
a1a1132b
CL		 2320 /* Get implemented bits of the priority arbitration request counter. */
2321 reg_write(ohci, OHCI1394_FairnessControl, 0x3f);
2322 ohci->pri_req_max = reg_read(ohci, OHCI1394_FairnessControl) & 0x3f;
2323 reg_write(ohci, OHCI1394_FairnessControl, 0);
db3c9cc1 2324 card->priority_budget_implemented = ohci->pri_req_max != 0;
2aef469a 2325
2aef469a
KH		 2326 reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000);
2327 reg_write(ohci, OHCI1394_IntEventClear, ~0);
2328 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
2aef469a 2329
35d999b1
SR		 2330 ret = configure_1394a_enhancements(ohci);
2331 if (ret < 0)
2332 return ret;
925e7a65 2333
2aef469a 2334 /* Activate link_on bit and contender bit in our self ID packets.*/
35d999b1
SR		 2335 ret = ohci_update_phy_reg(card, 4, 0, PHY_LINK_ACTIVE | PHY_CONTENDER);
2336 if (ret < 0)
2337 return ret;
2aef469a 2338
c781c06d
KH		 2339 /*
2340 * When the link is not yet enabled, the atomic config rom
ed568912
KH		 2341 * update mechanism described below in ohci_set_config_rom()
2342 * is not active. We have to update ConfigRomHeader and
2343 * BusOptions manually, and the write to ConfigROMmap takes
2344 * effect immediately. We tie this to the enabling of the
2345 * link, so we have a valid config rom before enabling - the
2346 * OHCI requires that ConfigROMhdr and BusOptions have valid
2347 * values before enabling.
2348 *
2349 * However, when the ConfigROMmap is written, some controllers
2350 * always read back quadlets 0 and 2 from the config rom to
2351 * the ConfigRomHeader and BusOptions registers on bus reset.
2352 * They shouldn't do that in this initial case where the link
2353 * isn't enabled. This means we have to use the same
2354 * workaround here, setting the bus header to 0 and then write
2355 * the right values in the bus reset tasklet.
2356 */
2357
0bd243c4
KH		 2358 if (config_rom) {
2359 ohci->next_config_rom =
2360 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2361 &ohci->next_config_rom_bus,
2362 GFP_KERNEL);
2363 if (ohci->next_config_rom == NULL)
2364 return -ENOMEM;
ed568912 2365
8e85973e 2366 copy_config_rom(ohci->next_config_rom, config_rom, length);
0bd243c4
KH		 2367 } else {
2368 /*
2369 * In the suspend case, config_rom is NULL, which
2370 * means that we just reuse the old config rom.
2371 */
2372 ohci->next_config_rom = ohci->config_rom;
2373 ohci->next_config_rom_bus = ohci->config_rom_bus;
2374 }
ed568912 2375
8e85973e 2376 ohci->next_header = ohci->next_config_rom[0];
ed568912
KH		 2377 ohci->next_config_rom[0] = 0;
2378 reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
0bd243c4
KH		 2379 reg_write(ohci, OHCI1394_BusOptions,
2380 be32_to_cpu(ohci->next_config_rom[2]));
ed568912
KH		 2381 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
2382
2383 reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
2384
262444ee
CL		 2385 if (!(ohci->quirks & QUIRK_NO_MSI))
2386 pci_enable_msi(dev);
ed568912 2387 if (request_irq(dev->irq, irq_handler,
262444ee
CL		 2388 pci_dev_msi_enabled(dev) ? 0 : IRQF_SHARED,
2389 ohci_driver_name, ohci)) {
64d21720
SR		 2390 dev_err(card->device, "failed to allocate interrupt %d\n",
2391 dev->irq);
262444ee 2392 pci_disable_msi(dev);
a01e8360
SR		 2393
2394 if (config_rom) {
2395 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2396 ohci->next_config_rom,
2397 ohci->next_config_rom_bus);
2398 ohci->next_config_rom = NULL;
2399 }
ed568912
KH		 2400 return -EIO;
2401 }
2402
148c7866
SR		 2403 irqs = OHCI1394_reqTxComplete | OHCI1394_respTxComplete |
2404 OHCI1394_RQPkt | OHCI1394_RSPkt |
2405 OHCI1394_isochTx | OHCI1394_isochRx |
2406 OHCI1394_postedWriteErr |
2407 OHCI1394_selfIDComplete |
2408 OHCI1394_regAccessFail |
f117a3e3
CL		 2409 OHCI1394_cycleInconsistent |
2410 OHCI1394_unrecoverableError |
2411 OHCI1394_cycleTooLong |
148c7866
SR		 2412 OHCI1394_masterIntEnable;
2413 if (param_debug & OHCI_PARAM_DEBUG_BUSRESETS)
2414 irqs |= OHCI1394_busReset;
2415 reg_write(ohci, OHCI1394_IntMaskSet, irqs);
2416
ed568912
KH		 2417 reg_write(ohci, OHCI1394_HCControlSet,
2418 OHCI1394_HCControl_linkEnable |
2419 OHCI1394_HCControl_BIBimageValid);
ecf8328e
CL		 2420
2421 reg_write(ohci, OHCI1394_LinkControlSet,
2422 OHCI1394_LinkControl_rcvSelfID |
2423 OHCI1394_LinkControl_rcvPhyPkt);
2424
2425 ar_context_run(&ohci->ar_request_ctx);
dd6254e5
CL		 2426 ar_context_run(&ohci->ar_response_ctx);
2427
2428 flush_writes(ohci);
ed568912 2429
02d37bed
SR		 2430 /* We are ready to go, reset bus to finish initialization. */
2431 fw_schedule_bus_reset(&ohci->card, false, true);
ed568912
KH		 2432
2433 return 0;
2434}
2435
53dca511 2436static int ohci_set_config_rom(struct fw_card *card,
8e85973e 2437 const __be32 *config_rom, size_t length)
ed568912
KH		 2438{
2439 struct fw_ohci *ohci;
ed568912 2440 __be32 *next_config_rom;
f5101d58 2441 dma_addr_t uninitialized_var(next_config_rom_bus);
ed568912
KH		 2442
2443 ohci = fw_ohci(card);
2444
c781c06d
KH		 2445 /*
2446 * When the OHCI controller is enabled, the config rom update
ed568912
KH		 2447 * mechanism is a bit tricky, but easy enough to use. See
2448 * section 5.5.6 in the OHCI specification.
2449 *
2450 * The OHCI controller caches the new config rom address in a
2451 * shadow register (ConfigROMmapNext) and needs a bus reset
2452 * for the changes to take place. When the bus reset is
2453 * detected, the controller loads the new values for the
2454 * ConfigRomHeader and BusOptions registers from the specified
2455 * config rom and loads ConfigROMmap from the ConfigROMmapNext
2456 * shadow register. All automatically and atomically.
2457 *
2458 * Now, there's a twist to this story. The automatic load of
2459 * ConfigRomHeader and BusOptions doesn't honor the
2460 * noByteSwapData bit, so with a be32 config rom, the
2461 * controller will load be32 values in to these registers
2462 * during the atomic update, even on litte endian
2463 * architectures. The workaround we use is to put a 0 in the
2464 * header quadlet; 0 is endian agnostic and means that the
2465 * config rom isn't ready yet. In the bus reset tasklet we
2466 * then set up the real values for the two registers.
2467 *
2468 * We use ohci->lock to avoid racing with the code that sets
2d7a36e2 2469 * ohci->next_config_rom to NULL (see bus_reset_work).
ed568912
KH		 2470 */
2471
2472 next_config_rom =
2473 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2474 &next_config_rom_bus, GFP_KERNEL);
2475 if (next_config_rom == NULL)
2476 return -ENOMEM;
2477
8a8c4736 2478 spin_lock_irq(&ohci->lock);
ed568912 2479
2e053a27
B		 2480 /*
2481 * If there is not an already pending config_rom update,
2482 * push our new allocation into the ohci->next_config_rom
2483 * and then mark the local variable as null so that we
2484 * won't deallocate the new buffer.
2485 *
2486 * OTOH, if there is a pending config_rom update, just
2487 * use that buffer with the new config_rom data, and
2488 * let this routine free the unused DMA allocation.
2489 */
2490
ed568912
KH		 2491 if (ohci->next_config_rom == NULL) {
2492 ohci->next_config_rom = next_config_rom;
2493 ohci->next_config_rom_bus = next_config_rom_bus;
2e053a27
B		 2494 next_config_rom = NULL;
2495 }
ed568912 2496
2e053a27 2497 copy_config_rom(ohci->next_config_rom, config_rom, length);
ed568912 2498
2e053a27
B		 2499 ohci->next_header = config_rom[0];
2500 ohci->next_config_rom[0] = 0;
ed568912 2501
2e053a27 2502 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
ed568912 2503
8a8c4736 2504 spin_unlock_irq(&ohci->lock);
ed568912 2505
2e053a27
B		 2506 /* If we didn't use the DMA allocation, delete it. */
2507 if (next_config_rom != NULL)
2508 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2509 next_config_rom, next_config_rom_bus);
2510
c781c06d
KH		 2511 /*
2512 * Now initiate a bus reset to have the changes take
ed568912
KH		 2513 * effect. We clean up the old config rom memory and DMA
2514 * mappings in the bus reset tasklet, since the OHCI
2515 * controller could need to access it before the bus reset
c781c06d
KH		 2516 * takes effect.
2517 */
ed568912 2518
2e053a27
B		 2519 fw_schedule_bus_reset(&ohci->card, true, true);
2520
2521 return 0;
ed568912
KH		 2522}
2523
2524static void ohci_send_request(struct fw_card *card, struct fw_packet *packet)
2525{
2526 struct fw_ohci *ohci = fw_ohci(card);
2527
2528 at_context_transmit(&ohci->at_request_ctx, packet);
2529}
2530
2531static void ohci_send_response(struct fw_card *card, struct fw_packet *packet)
2532{
2533 struct fw_ohci *ohci = fw_ohci(card);
2534
2535 at_context_transmit(&ohci->at_response_ctx, packet);
2536}
2537
730c32f5
KH		 2538static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet)
2539{
2540 struct fw_ohci *ohci = fw_ohci(card);
f319b6a0
KH		 2541 struct context *ctx = &ohci->at_request_ctx;
2542 struct driver_data *driver_data = packet->driver_data;
2dbd7d7e 2543 int ret = -ENOENT;
730c32f5 2544
f319b6a0 2545 tasklet_disable(&ctx->tasklet);
730c32f5 2546
f319b6a0
KH		 2547 if (packet->ack != 0)
2548 goto out;
730c32f5 2549
19593ffd 2550 if (packet->payload_mapped)
1d1dc5e8
SR		 2551 dma_unmap_single(ohci->card.device, packet->payload_bus,
2552 packet->payload_length, DMA_TO_DEVICE);
2553
64d21720 2554 log_ar_at_event(ohci, 'T', packet->speed, packet->header, 0x20);
f319b6a0
KH		 2555 driver_data->packet = NULL;
2556 packet->ack = RCODE_CANCELLED;
2557 packet->callback(packet, &ohci->card, packet->ack);
2dbd7d7e 2558 ret = 0;
f319b6a0
KH		 2559 out:
2560 tasklet_enable(&ctx->tasklet);
730c32f5 2561
2dbd7d7e 2562 return ret;
730c32f5
KH		 2563}
2564
53dca511
SR		 2565static int ohci_enable_phys_dma(struct fw_card *card,
2566 int node_id, int generation)
ed568912 2567{
080de8c2
SR		 2568#ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
2569 return 0;
2570#else
ed568912
KH		 2571 struct fw_ohci *ohci = fw_ohci(card);
2572 unsigned long flags;
2dbd7d7e 2573 int n, ret = 0;
ed568912 2574
c781c06d
KH		 2575 /*
2576 * FIXME: Make sure this bitmask is cleared when we clear the busReset
2577 * interrupt bit. Clear physReqResourceAllBuses on bus reset.
2578 */
ed568912
KH		 2579
2580 spin_lock_irqsave(&ohci->lock, flags);
2581
2582 if (ohci->generation != generation) {
2dbd7d7e 2583 ret = -ESTALE;
ed568912
KH		 2584 goto out;
2585 }
2586
c781c06d
KH		 2587 /*
2588 * Note, if the node ID contains a non-local bus ID, physical DMA is
2589 * enabled for _all_ nodes on remote buses.
2590 */
907293d7
SR		 2591
2592 n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63;
2593 if (n < 32)
2594 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n);
2595 else
2596 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32));
2597
ed568912 2598 flush_writes(ohci);
ed568912 2599 out:
6cad95fe 2600 spin_unlock_irqrestore(&ohci->lock, flags);
2dbd7d7e
SR		 2601
2602 return ret;
080de8c2 2603#endif /* CONFIG_FIREWIRE_OHCI_REMOTE_DMA */
ed568912 2604}
373b2edd 2605
0fcff4e3 2606static u32 ohci_read_csr(struct fw_card *card, int csr_offset)
b677532b 2607{
60d32970 2608 struct fw_ohci *ohci = fw_ohci(card);
a48777e0
CL		 2609 unsigned long flags;
2610 u32 value;
60d32970
CL		 2611
2612 switch (csr_offset) {
4ffb7a6a
CL		 2613 case CSR_STATE_CLEAR:
2614 case CSR_STATE_SET:
4ffb7a6a
CL		 2615 if (ohci->is_root &&
2616 (reg_read(ohci, OHCI1394_LinkControlSet) &
2617 OHCI1394_LinkControl_cycleMaster))
c8a94ded 2618 value = CSR_STATE_BIT_CMSTR;
4ffb7a6a 2619 else
c8a94ded
SR		 2620 value = 0;
2621 if (ohci->csr_state_setclear_abdicate)
2622 value |= CSR_STATE_BIT_ABDICATE;
b677532b 2623
c8a94ded 2624 return value;
4a9bde9b 2625
506f1a31
CL		 2626 case CSR_NODE_IDS:
2627 return reg_read(ohci, OHCI1394_NodeID) << 16;
2628
60d32970
CL		 2629 case CSR_CYCLE_TIME:
2630 return get_cycle_time(ohci);
2631
a48777e0
CL		 2632 case CSR_BUS_TIME:
2633 /*
2634 * We might be called just after the cycle timer has wrapped
2635 * around but just before the cycle64Seconds handler, so we
2636 * better check here, too, if the bus time needs to be updated.
2637 */
2638 spin_lock_irqsave(&ohci->lock, flags);
2639 value = update_bus_time(ohci);
2640 spin_unlock_irqrestore(&ohci->lock, flags);
2641 return value;
2642
27a2329f
CL		 2643 case CSR_BUSY_TIMEOUT:
2644 value = reg_read(ohci, OHCI1394_ATRetries);
2645 return (value >> 4) & 0x0ffff00f;
2646
a1a1132b
CL		 2647 case CSR_PRIORITY_BUDGET:
2648 return (reg_read(ohci, OHCI1394_FairnessControl) & 0x3f) |
2649 (ohci->pri_req_max << 8);
2650
60d32970
CL		 2651 default:
2652 WARN_ON(1);
2653 return 0;
2654 }
b677532b
CL		 2655}
2656
0fcff4e3 2657static void ohci_write_csr(struct fw_card *card, int csr_offset, u32 value)
d60d7f1d
KH		 2658{
2659 struct fw_ohci *ohci = fw_ohci(card);
a48777e0 2660 unsigned long flags;
d60d7f1d 2661
506f1a31 2662 switch (csr_offset) {
4ffb7a6a 2663 case CSR_STATE_CLEAR:
4ffb7a6a
CL		 2664 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
2665 reg_write(ohci, OHCI1394_LinkControlClear,
2666 OHCI1394_LinkControl_cycleMaster);
2667 flush_writes(ohci);
2668 }
c8a94ded
SR		 2669 if (value & CSR_STATE_BIT_ABDICATE)
2670 ohci->csr_state_setclear_abdicate = false;
4ffb7a6a 2671 break;
4a9bde9b 2672
4ffb7a6a
CL		 2673 case CSR_STATE_SET:
2674 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
2675 reg_write(ohci, OHCI1394_LinkControlSet,
2676 OHCI1394_LinkControl_cycleMaster);
2677 flush_writes(ohci);
2678 }
c8a94ded
SR		 2679 if (value & CSR_STATE_BIT_ABDICATE)
2680 ohci->csr_state_setclear_abdicate = true;
4ffb7a6a 2681 break;
d60d7f1d 2682
506f1a31
CL		 2683 case CSR_NODE_IDS:
2684 reg_write(ohci, OHCI1394_NodeID, value >> 16);
2685 flush_writes(ohci);
2686 break;
2687
9ab5071c
CL		 2688 case CSR_CYCLE_TIME:
2689 reg_write(ohci, OHCI1394_IsochronousCycleTimer, value);
2690 reg_write(ohci, OHCI1394_IntEventSet,
2691 OHCI1394_cycleInconsistent);
2692 flush_writes(ohci);
2693 break;
2694
a48777e0
CL		 2695 case CSR_BUS_TIME:
2696 spin_lock_irqsave(&ohci->lock, flags);
9d60ef2b
CL		 2697 ohci->bus_time = (update_bus_time(ohci) & 0x40) |
2698 (value & ~0x7f);
a48777e0
CL		 2699 spin_unlock_irqrestore(&ohci->lock, flags);
2700 break;
2701
27a2329f
CL		 2702 case CSR_BUSY_TIMEOUT:
2703 value = (value & 0xf) | ((value & 0xf) << 4) |
2704 ((value & 0xf) << 8) | ((value & 0x0ffff000) << 4);
2705 reg_write(ohci, OHCI1394_ATRetries, value);
2706 flush_writes(ohci);
2707 break;
2708
a1a1132b
CL		 2709 case CSR_PRIORITY_BUDGET:
2710 reg_write(ohci, OHCI1394_FairnessControl, value & 0x3f);
2711 flush_writes(ohci);
2712 break;
2713
506f1a31
CL		 2714 default:
2715 WARN_ON(1);
2716 break;
2717 }
d60d7f1d
KH		 2718}
2719
910e76c6 2720static void flush_iso_completions(struct iso_context *ctx)
1aa292bb 2721{
910e76c6
CL		 2722 ctx->base.callback.sc(&ctx->base, ctx->last_timestamp,
2723 ctx->header_length, ctx->header,
2724 ctx->base.callback_data);
2725 ctx->header_length = 0;
2726}
1aa292bb 2727
73864012 2728static void copy_iso_headers(struct iso_context *ctx, const u32 *dma_hdr)
1aa292bb 2729{
73864012 2730 u32 *ctx_hdr;
1aa292bb 2731
73864012 2732 if (ctx->header_length + ctx->base.header_size > PAGE_SIZE)
18d62711 2733 flush_iso_completions(ctx);
1aa292bb 2734
73864012 2735 ctx_hdr = ctx->header + ctx->header_length;
910e76c6 2736 ctx->last_timestamp = (u16)le32_to_cpu((__force __le32)dma_hdr[0]);
1aa292bb
DM		 2737
2738 /*
32c507f7
CL		 2739 * The two iso header quadlets are byteswapped to little
2740 * endian by the controller, but we want to present them
2741 * as big endian for consistency with the bus endianness.
1aa292bb
DM		 2742 */
2743 if (ctx->base.header_size > 0)
73864012 2744 ctx_hdr[0] = swab32(dma_hdr[1]); /* iso packet header */
1aa292bb 2745 if (ctx->base.header_size > 4)
73864012 2746 ctx_hdr[1] = swab32(dma_hdr[0]); /* timestamp */
1aa292bb 2747 if (ctx->base.header_size > 8)
73864012 2748 memcpy(&ctx_hdr[2], &dma_hdr[2], ctx->base.header_size - 8);
1aa292bb
DM		 2749 ctx->header_length += ctx->base.header_size;
2750}
2751
a186b4a6
JW		 2752static int handle_ir_packet_per_buffer(struct context *context,
2753 struct descriptor *d,
2754 struct descriptor *last)
2755{
2756 struct iso_context *ctx =
2757 container_of(context, struct iso_context, context);
bcee893c 2758 struct descriptor *pd;
a572e688 2759 u32 buffer_dma;
a186b4a6 2760
872e330e 2761 for (pd = d; pd <= last; pd++)
bcee893c
DM		 2762 if (pd->transfer_status)
2763 break;
bcee893c 2764 if (pd > last)
a186b4a6
JW		 2765 /* Descriptor(s) not done yet, stop iteration */
2766 return 0;
2767
a572e688
CL		 2768 while (!(d->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))) {
2769 d++;
2770 buffer_dma = le32_to_cpu(d->data_address);
2771 dma_sync_single_range_for_cpu(context->ohci->card.device,
2772 buffer_dma & PAGE_MASK,
2773 buffer_dma & ~PAGE_MASK,
2774 le16_to_cpu(d->req_count),
2775 DMA_FROM_DEVICE);
2776 }
2777
910e76c6 2778 copy_iso_headers(ctx, (u32 *) (last + 1));
a186b4a6 2779
910e76c6
CL		 2780 if (last->control & cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS))
2781 flush_iso_completions(ctx);
a186b4a6 2782
a186b4a6
JW		 2783 return 1;
2784}
2785
872e330e
SR		 2786/* d == last because each descriptor block is only a single descriptor. */
2787static int handle_ir_buffer_fill(struct context *context,
2788 struct descriptor *d,
2789 struct descriptor *last)
2790{
2791 struct iso_context *ctx =
2792 container_of(context, struct iso_context, context);
d1bbd209 2793 unsigned int req_count, res_count, completed;
a572e688 2794 u32 buffer_dma;
872e330e 2795
d1bbd209
CL		 2796 req_count = le16_to_cpu(last->req_count);
2797 res_count = le16_to_cpu(ACCESS_ONCE(last->res_count));
2798 completed = req_count - res_count;
2799 buffer_dma = le32_to_cpu(last->data_address);
2800
2801 if (completed > 0) {
2802 ctx->mc_buffer_bus = buffer_dma;
2803 ctx->mc_completed = completed;
2804 }
2805
2806 if (res_count != 0)
872e330e
SR		 2807 /* Descriptor(s) not done yet, stop iteration */
2808 return 0;
2809
a572e688
CL		 2810 dma_sync_single_range_for_cpu(context->ohci->card.device,
2811 buffer_dma & PAGE_MASK,
2812 buffer_dma & ~PAGE_MASK,
d1bbd209 2813 completed, DMA_FROM_DEVICE);
a572e688 2814
d1bbd209 2815 if (last->control & cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS)) {
872e330e 2816 ctx->base.callback.mc(&ctx->base,
d1bbd209 2817 buffer_dma + completed,
872e330e 2818 ctx->base.callback_data);
d1bbd209
CL		 2819 ctx->mc_completed = 0;
2820 }
872e330e
SR		 2821
2822 return 1;
2823}
2824
d1bbd209
CL		 2825static void flush_ir_buffer_fill(struct iso_context *ctx)
2826{
2827 dma_sync_single_range_for_cpu(ctx->context.ohci->card.device,
2828 ctx->mc_buffer_bus & PAGE_MASK,
2829 ctx->mc_buffer_bus & ~PAGE_MASK,
2830 ctx->mc_completed, DMA_FROM_DEVICE);
2831
2832 ctx->base.callback.mc(&ctx->base,
2833 ctx->mc_buffer_bus + ctx->mc_completed,
2834 ctx->base.callback_data);
2835 ctx->mc_completed = 0;
2836}
2837
a572e688
CL		 2838static inline void sync_it_packet_for_cpu(struct context *context,
2839 struct descriptor *pd)
2840{
2841 __le16 control;
2842 u32 buffer_dma;
2843
2844 /* only packets beginning with OUTPUT_MORE* have data buffers */
2845 if (pd->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))
2846 return;
2847
2848 /* skip over the OUTPUT_MORE_IMMEDIATE descriptor */
2849 pd += 2;
2850
2851 /*
2852 * If the packet has a header, the first OUTPUT_MORE/LAST descriptor's
2853 * data buffer is in the context program's coherent page and must not
2854 * be synced.
2855 */
2856 if ((le32_to_cpu(pd->data_address) & PAGE_MASK) ==
2857 (context->current_bus & PAGE_MASK)) {
2858 if (pd->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))
2859 return;
2860 pd++;
2861 }
2862
2863 do {
2864 buffer_dma = le32_to_cpu(pd->data_address);
2865 dma_sync_single_range_for_cpu(context->ohci->card.device,
2866 buffer_dma & PAGE_MASK,
2867 buffer_dma & ~PAGE_MASK,
2868 le16_to_cpu(pd->req_count),
2869 DMA_TO_DEVICE);
2870 control = pd->control;
2871 pd++;
2872 } while (!(control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS)));
2873}
2874
30200739
KH		 2875static int handle_it_packet(struct context *context,
2876 struct descriptor *d,
2877 struct descriptor *last)
ed568912 2878{
30200739
KH		 2879 struct iso_context *ctx =
2880 container_of(context, struct iso_context, context);
31769cef 2881 struct descriptor *pd;
73864012 2882 __be32 *ctx_hdr;
373b2edd 2883
31769cef
JF		 2884 for (pd = d; pd <= last; pd++)
2885 if (pd->transfer_status)
2886 break;
2887 if (pd > last)
2888 /* Descriptor(s) not done yet, stop iteration */
30200739
KH		 2889 return 0;
2890
a572e688
CL		 2891 sync_it_packet_for_cpu(context, d);
2892
18d62711
CL		 2893 if (ctx->header_length + 4 > PAGE_SIZE)
2894 flush_iso_completions(ctx);
910e76c6 2895
18d62711 2896 ctx_hdr = ctx->header + ctx->header_length;
910e76c6 2897 ctx->last_timestamp = le16_to_cpu(last->res_count);
18d62711
CL		 2898 /* Present this value as big-endian to match the receive code */
2899 *ctx_hdr = cpu_to_be32((le16_to_cpu(pd->transfer_status) << 16) |
2900 le16_to_cpu(pd->res_count));
2901 ctx->header_length += 4;
2902
910e76c6
CL		 2903 if (last->control & cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS))
2904 flush_iso_completions(ctx);
2905
30200739 2906 return 1;
ed568912
KH		 2907}
2908
872e330e
SR		 2909static void set_multichannel_mask(struct fw_ohci *ohci, u64 channels)
2910{
2911 u32 hi = channels >> 32, lo = channels;
2912
2913 reg_write(ohci, OHCI1394_IRMultiChanMaskHiClear, ~hi);
2914 reg_write(ohci, OHCI1394_IRMultiChanMaskLoClear, ~lo);
2915 reg_write(ohci, OHCI1394_IRMultiChanMaskHiSet, hi);
2916 reg_write(ohci, OHCI1394_IRMultiChanMaskLoSet, lo);
2917 mmiowb();
2918 ohci->mc_channels = channels;
2919}
2920
53dca511 2921static struct fw_iso_context *ohci_allocate_iso_context(struct fw_card *card,
4817ed24 2922 int type, int channel, size_t header_size)
ed568912
KH		 2923{
2924 struct fw_ohci *ohci = fw_ohci(card);
872e330e
SR		 2925 struct iso_context *uninitialized_var(ctx);
2926 descriptor_callback_t uninitialized_var(callback);
2927 u64 *uninitialized_var(channels);
2928 u32 *uninitialized_var(mask), uninitialized_var(regs);
872e330e 2929 int index, ret = -EBUSY;
ed568912 2930
8a8c4736 2931 spin_lock_irq(&ohci->lock);
ed568912 2932
872e330e
SR		 2933 switch (type) {
2934 case FW_ISO_CONTEXT_TRANSMIT:
2935 mask = &ohci->it_context_mask;
30200739 2936 callback = handle_it_packet;
872e330e
SR		 2937 index = ffs(*mask) - 1;
2938 if (index >= 0) {
2939 *mask &= ~(1 << index);
2940 regs = OHCI1394_IsoXmitContextBase(index);
2941 ctx = &ohci->it_context_list[index];
2942 }
2943 break;
2944
2945 case FW_ISO_CONTEXT_RECEIVE:
4817ed24 2946 channels = &ohci->ir_context_channels;
872e330e 2947 mask = &ohci->ir_context_mask;
6498ba04 2948 callback = handle_ir_packet_per_buffer;
872e330e
SR		 2949 index = *channels & 1ULL << channel ? ffs(*mask) - 1 : -1;
2950 if (index >= 0) {
2951 *channels &= ~(1ULL << channel);
2952 *mask &= ~(1 << index);
2953 regs = OHCI1394_IsoRcvContextBase(index);
2954 ctx = &ohci->ir_context_list[index];
2955 }
2956 break;
ed568912 2957
872e330e
SR		 2958 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2959 mask = &ohci->ir_context_mask;
2960 callback = handle_ir_buffer_fill;
2961 index = !ohci->mc_allocated ? ffs(*mask) - 1 : -1;
2962 if (index >= 0) {
2963 ohci->mc_allocated = true;
2964 *mask &= ~(1 << index);
2965 regs = OHCI1394_IsoRcvContextBase(index);
2966 ctx = &ohci->ir_context_list[index];
2967 }
2968 break;
2969
2970 default:
2971 index = -1;
2972 ret = -ENOSYS;
4817ed24 2973 }
872e330e 2974
8a8c4736 2975 spin_unlock_irq(&ohci->lock);
ed568912
KH		 2976
2977 if (index < 0)
872e330e 2978 return ERR_PTR(ret);
373b2edd 2979
2d826cc5 2980 memset(ctx, 0, sizeof(*ctx));
9b32d5f3
KH		 2981 ctx->header_length = 0;
2982 ctx->header = (void *) __get_free_page(GFP_KERNEL);
872e330e
SR		 2983 if (ctx->header == NULL) {
2984 ret = -ENOMEM;
9b32d5f3 2985 goto out;
872e330e 2986 }
2dbd7d7e
SR		 2987 ret = context_init(&ctx->context, ohci, regs, callback);
2988 if (ret < 0)
9b32d5f3 2989 goto out_with_header;
ed568912 2990
d1bbd209 2991 if (type == FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL) {
872e330e 2992 set_multichannel_mask(ohci, 0);
d1bbd209
CL		 2993 ctx->mc_completed = 0;
2994 }
872e330e 2995
ed568912 2996 return &ctx->base;
9b32d5f3
KH		 2997
2998 out_with_header:
2999 free_page((unsigned long)ctx->header);
3000 out:
8a8c4736 3001 spin_lock_irq(&ohci->lock);
872e330e
SR		 3002
3003 switch (type) {
3004 case FW_ISO_CONTEXT_RECEIVE:
3005 *channels |= 1ULL << channel;
3006 break;
3007
3008 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3009 ohci->mc_allocated = false;
3010 break;
3011 }
9b32d5f3 3012 *mask |= 1 << index;
872e330e 3013
8a8c4736 3014 spin_unlock_irq(&ohci->lock);
9b32d5f3 3015
2dbd7d7e 3016 return ERR_PTR(ret);
ed568912
KH		 3017}
3018
eb0306ea
KH		 3019static int ohci_start_iso(struct fw_iso_context *base,
3020 s32 cycle, u32 sync, u32 tags)
ed568912 3021{
373b2edd 3022 struct iso_context *ctx = container_of(base, struct iso_context, base);
30200739 3023 struct fw_ohci *ohci = ctx->context.ohci;
872e330e 3024 u32 control = IR_CONTEXT_ISOCH_HEADER, match;
ed568912
KH		 3025 int index;
3026
44b74d90
CL		 3027 /* the controller cannot start without any queued packets */
3028 if (ctx->context.last->branch_address == 0)
3029 return -ENODATA;
3030
872e330e
SR		 3031 switch (ctx->base.type) {
3032 case FW_ISO_CONTEXT_TRANSMIT:
295e3feb 3033 index = ctx - ohci->it_context_list;
8a2f7d93
KH		 3034 match = 0;
3035 if (cycle >= 0)
3036 match = IT_CONTEXT_CYCLE_MATCH_ENABLE |
295e3feb 3037 (cycle & 0x7fff) << 16;
21efb3cf 3038
295e3feb
KH		 3039 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index);
3040 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index);
8a2f7d93 3041 context_run(&ctx->context, match);
872e330e
SR		 3042 break;
3043
3044 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3045 control |= IR_CONTEXT_BUFFER_FILL|IR_CONTEXT_MULTI_CHANNEL_MODE;
3046 /* fall through */
3047 case FW_ISO_CONTEXT_RECEIVE:
295e3feb 3048 index = ctx - ohci->ir_context_list;
8a2f7d93
KH		 3049 match = (tags << 28) | (sync << 8) | ctx->base.channel;
3050 if (cycle >= 0) {
3051 match |= (cycle & 0x07fff) << 12;
3052 control |= IR_CONTEXT_CYCLE_MATCH_ENABLE;
3053 }
ed568912 3054
295e3feb
KH		 3055 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index);
3056 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index);
a77754a7 3057 reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match);
8a2f7d93 3058 context_run(&ctx->context, control);
dd23736e
ML		 3059
3060 ctx->sync = sync;
3061 ctx->tags = tags;
3062
872e330e 3063 break;
295e3feb 3064 }
ed568912
KH		 3065
3066 return 0;
3067}
3068
b8295668
KH		 3069static int ohci_stop_iso(struct fw_iso_context *base)
3070{
3071 struct fw_ohci *ohci = fw_ohci(base->card);
373b2edd 3072 struct iso_context *ctx = container_of(base, struct iso_context, base);
b8295668
KH		 3073 int index;
3074
872e330e
SR		 3075 switch (ctx->base.type) {
3076 case FW_ISO_CONTEXT_TRANSMIT:
b8295668
KH		 3077 index = ctx - ohci->it_context_list;
3078 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index);
872e330e
SR		 3079 break;
3080
3081 case FW_ISO_CONTEXT_RECEIVE:
3082 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
b8295668
KH		 3083 index = ctx - ohci->ir_context_list;
3084 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index);
872e330e 3085 break;
b8295668
KH		 3086 }
3087 flush_writes(ohci);
3088 context_stop(&ctx->context);
e81cbebd 3089 tasklet_kill(&ctx->context.tasklet);
b8295668
KH		 3090
3091 return 0;
3092}
3093
ed568912
KH		 3094static void ohci_free_iso_context(struct fw_iso_context *base)
3095{
3096 struct fw_ohci *ohci = fw_ohci(base->card);
373b2edd 3097 struct iso_context *ctx = container_of(base, struct iso_context, base);
ed568912
KH		 3098 unsigned long flags;
3099 int index;
3100
b8295668
KH		 3101 ohci_stop_iso(base);
3102 context_release(&ctx->context);
9b32d5f3 3103 free_page((unsigned long)ctx->header);
b8295668 3104
ed568912
KH		 3105 spin_lock_irqsave(&ohci->lock, flags);
3106
872e330e
SR		 3107 switch (base->type) {
3108 case FW_ISO_CONTEXT_TRANSMIT:
ed568912 3109 index = ctx - ohci->it_context_list;
ed568912 3110 ohci->it_context_mask |= 1 << index;
872e330e
SR		 3111 break;
3112
3113 case FW_ISO_CONTEXT_RECEIVE:
ed568912 3114 index = ctx - ohci->ir_context_list;
ed568912 3115 ohci->ir_context_mask |= 1 << index;
4817ed24 3116 ohci->ir_context_channels |= 1ULL << base->channel;
872e330e
SR		 3117 break;
3118
3119 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3120 index = ctx - ohci->ir_context_list;
3121 ohci->ir_context_mask |= 1 << index;
3122 ohci->ir_context_channels |= ohci->mc_channels;
3123 ohci->mc_channels = 0;
3124 ohci->mc_allocated = false;
3125 break;
ed568912 3126 }
ed568912
KH		 3127
3128 spin_unlock_irqrestore(&ohci->lock, flags);
3129}
3130
872e330e
SR		 3131static int ohci_set_iso_channels(struct fw_iso_context *base, u64 *channels)
3132{
3133 struct fw_ohci *ohci = fw_ohci(base->card);
3134 unsigned long flags;
3135 int ret;
3136
3137 switch (base->type) {
3138 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3139
3140 spin_lock_irqsave(&ohci->lock, flags);
3141
3142 /* Don't allow multichannel to grab other contexts' channels. */
3143 if (~ohci->ir_context_channels & ~ohci->mc_channels & *channels) {
3144 *channels = ohci->ir_context_channels;
3145 ret = -EBUSY;
3146 } else {
3147 set_multichannel_mask(ohci, *channels);
3148 ret = 0;
3149 }
3150
3151 spin_unlock_irqrestore(&ohci->lock, flags);
3152
3153 break;
3154 default:
3155 ret = -EINVAL;
3156 }
3157
3158 return ret;
3159}
3160
dd23736e
ML		 3161#ifdef CONFIG_PM
3162static void ohci_resume_iso_dma(struct fw_ohci *ohci)
3163{
3164 int i;
3165 struct iso_context *ctx;
3166
3167 for (i = 0 ; i < ohci->n_ir ; i++) {
3168 ctx = &ohci->ir_context_list[i];
693a50b5 3169 if (ctx->context.running)
dd23736e
ML		 3170 ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags);
3171 }
3172
3173 for (i = 0 ; i < ohci->n_it ; i++) {
3174 ctx = &ohci->it_context_list[i];
693a50b5 3175 if (ctx->context.running)
dd23736e
ML		 3176 ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags);
3177 }
3178}
3179#endif
3180
872e330e
SR		 3181static int queue_iso_transmit(struct iso_context *ctx,
3182 struct fw_iso_packet *packet,
3183 struct fw_iso_buffer *buffer,
3184 unsigned long payload)
ed568912 3185{
30200739 3186 struct descriptor *d, *last, *pd;
ed568912
KH		 3187 struct fw_iso_packet *p;
3188 __le32 *header;
9aad8125 3189 dma_addr_t d_bus, page_bus;
ed568912
KH		 3190 u32 z, header_z, payload_z, irq;
3191 u32 payload_index, payload_end_index, next_page_index;
30200739 3192 int page, end_page, i, length, offset;
ed568912 3193
ed568912 3194 p = packet;
9aad8125 3195 payload_index = payload;
ed568912
KH		 3196
3197 if (p->skip)
3198 z = 1;
3199 else
3200 z = 2;
3201 if (p->header_length > 0)
3202 z++;
3203
3204 /* Determine the first page the payload isn't contained in. */
3205 end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT;
3206 if (p->payload_length > 0)
3207 payload_z = end_page - (payload_index >> PAGE_SHIFT);
3208 else
3209 payload_z = 0;
3210
3211 z += payload_z;
3212
3213 /* Get header size in number of descriptors. */
2d826cc5 3214 header_z = DIV_ROUND_UP(p->header_length, sizeof(*d));
ed568912 3215
30200739
KH		 3216 d = context_get_descriptors(&ctx->context, z + header_z, &d_bus);
3217 if (d == NULL)
3218 return -ENOMEM;
ed568912
KH		 3219
3220 if (!p->skip) {
a77754a7 3221 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
ed568912 3222 d[0].req_count = cpu_to_le16(8);
7f51a100
CL		 3223 /*
3224 * Link the skip address to this descriptor itself. This causes
3225 * a context to skip a cycle whenever lost cycles or FIFO
3226 * overruns occur, without dropping the data. The application
3227 * should then decide whether this is an error condition or not.
3228 * FIXME: Make the context's cycle-lost behaviour configurable?
3229 */
3230 d[0].branch_address = cpu_to_le32(d_bus | z);
ed568912
KH		 3231
3232 header = (__le32 *) &d[1];
a77754a7
KH		 3233 header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) |
3234 IT_HEADER_TAG(p->tag) |
3235 IT_HEADER_TCODE(TCODE_STREAM_DATA) |
3236 IT_HEADER_CHANNEL(ctx->base.channel) |
3237 IT_HEADER_SPEED(ctx->base.speed));
ed568912 3238 header[1] =
a77754a7 3239 cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length +
ed568912
KH		 3240 p->payload_length));
3241 }
3242
3243 if (p->header_length > 0) {
3244 d[2].req_count = cpu_to_le16(p->header_length);
2d826cc5 3245 d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d));
ed568912
KH		 3246 memcpy(&d[z], p->header, p->header_length);
3247 }
3248
3249 pd = d + z - payload_z;
3250 payload_end_index = payload_index + p->payload_length;
3251 for (i = 0; i < payload_z; i++) {
3252 page = payload_index >> PAGE_SHIFT;
3253 offset = payload_index & ~PAGE_MASK;
3254 next_page_index = (page + 1) << PAGE_SHIFT;
3255 length =
3256 min(next_page_index, payload_end_index) - payload_index;
3257 pd[i].req_count = cpu_to_le16(length);
9aad8125
KH		 3258
3259 page_bus = page_private(buffer->pages[page]);
3260 pd[i].data_address = cpu_to_le32(page_bus + offset);
ed568912 3261
a572e688
CL		 3262 dma_sync_single_range_for_device(ctx->context.ohci->card.device,
3263 page_bus, offset, length,
3264 DMA_TO_DEVICE);
3265
ed568912
KH		 3266 payload_index += length;
3267 }
3268
ed568912 3269 if (p->interrupt)
a77754a7 3270 irq = DESCRIPTOR_IRQ_ALWAYS;
ed568912 3271 else
a77754a7 3272 irq = DESCRIPTOR_NO_IRQ;
ed568912 3273
30200739 3274 last = z == 2 ? d : d + z - 1;
a77754a7
KH		 3275 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
3276 DESCRIPTOR_STATUS |
3277 DESCRIPTOR_BRANCH_ALWAYS |
cbb59da7 3278 irq);
ed568912 3279
30200739 3280 context_append(&ctx->context, d, z, header_z);
ed568912
KH		 3281
3282 return 0;
3283}
373b2edd 3284
872e330e
SR		 3285static int queue_iso_packet_per_buffer(struct iso_context *ctx,
3286 struct fw_iso_packet *packet,
3287 struct fw_iso_buffer *buffer,
3288 unsigned long payload)
a186b4a6 3289{
a572e688 3290 struct device *device = ctx->context.ohci->card.device;
8c0c0cc2 3291 struct descriptor *d, *pd;
a186b4a6
JW		 3292 dma_addr_t d_bus, page_bus;
3293 u32 z, header_z, rest;
bcee893c
DM		 3294 int i, j, length;
3295 int page, offset, packet_count, header_size, payload_per_buffer;
a186b4a6
JW		 3296
3297 /*
1aa292bb
DM		 3298 * The OHCI controller puts the isochronous header and trailer in the
3299 * buffer, so we need at least 8 bytes.
a186b4a6 3300 */
872e330e 3301 packet_count = packet->header_length / ctx->base.header_size;
1aa292bb 3302 header_size = max(ctx->base.header_size, (size_t)8);
a186b4a6
JW		 3303
3304 /* Get header size in number of descriptors. */
3305 header_z = DIV_ROUND_UP(header_size, sizeof(*d));
3306 page = payload >> PAGE_SHIFT;
3307 offset = payload & ~PAGE_MASK;
872e330e 3308 payload_per_buffer = packet->payload_length / packet_count;
a186b4a6
JW		 3309
3310 for (i = 0; i < packet_count; i++) {
3311 /* d points to the header descriptor */
bcee893c 3312 z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1;
a186b4a6 3313 d = context_get_descriptors(&ctx->context,
bcee893c 3314 z + header_z, &d_bus);
a186b4a6
JW		 3315 if (d == NULL)
3316 return -ENOMEM;
3317
bcee893c
DM		 3318 d->control = cpu_to_le16(DESCRIPTOR_STATUS |
3319 DESCRIPTOR_INPUT_MORE);
872e330e 3320 if (packet->skip && i == 0)
bcee893c 3321 d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
a186b4a6
JW		 3322 d->req_count = cpu_to_le16(header_size);
3323 d->res_count = d->req_count;
bcee893c 3324 d->transfer_status = 0;
a186b4a6
JW		 3325 d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d)));
3326
bcee893c 3327 rest = payload_per_buffer;
8c0c0cc2 3328 pd = d;
bcee893c 3329 for (j = 1; j < z; j++) {
8c0c0cc2 3330 pd++;
bcee893c
DM		 3331 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
3332 DESCRIPTOR_INPUT_MORE);
3333
3334 if (offset + rest < PAGE_SIZE)
3335 length = rest;
3336 else
3337 length = PAGE_SIZE - offset;
3338 pd->req_count = cpu_to_le16(length);
3339 pd->res_count = pd->req_count;
3340 pd->transfer_status = 0;
3341
3342 page_bus = page_private(buffer->pages[page]);
3343 pd->data_address = cpu_to_le32(page_bus + offset);
3344
a572e688
CL		 3345 dma_sync_single_range_for_device(device, page_bus,
3346 offset, length,
3347 DMA_FROM_DEVICE);
3348
bcee893c
DM		 3349 offset = (offset + length) & ~PAGE_MASK;
3350 rest -= length;
3351 if (offset == 0)
3352 page++;
3353 }
a186b4a6
JW		 3354 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
3355 DESCRIPTOR_INPUT_LAST |
3356 DESCRIPTOR_BRANCH_ALWAYS);
872e330e 3357 if (packet->interrupt && i == packet_count - 1)
a186b4a6
JW		 3358 pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
3359
a186b4a6
JW		 3360 context_append(&ctx->context, d, z, header_z);
3361 }
3362
3363 return 0;
3364}
3365
872e330e
SR		 3366static int queue_iso_buffer_fill(struct iso_context *ctx,
3367 struct fw_iso_packet *packet,
3368 struct fw_iso_buffer *buffer,
3369 unsigned long payload)
3370{
3371 struct descriptor *d;
3372 dma_addr_t d_bus, page_bus;
3373 int page, offset, rest, z, i, length;
3374
3375 page = payload >> PAGE_SHIFT;
3376 offset = payload & ~PAGE_MASK;
3377 rest = packet->payload_length;
3378
3379 /* We need one descriptor for each page in the buffer. */
3380 z = DIV_ROUND_UP(offset + rest, PAGE_SIZE);
3381
3382 if (WARN_ON(offset & 3 || rest & 3 || page + z > buffer->page_count))
3383 return -EFAULT;
3384
3385 for (i = 0; i < z; i++) {
3386 d = context_get_descriptors(&ctx->context, 1, &d_bus);
3387 if (d == NULL)
3388 return -ENOMEM;
3389
3390 d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
3391 DESCRIPTOR_BRANCH_ALWAYS);
3392 if (packet->skip && i == 0)
3393 d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
3394 if (packet->interrupt && i == z - 1)
3395 d->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
3396
3397 if (offset + rest < PAGE_SIZE)
3398 length = rest;
3399 else
3400 length = PAGE_SIZE - offset;
3401 d->req_count = cpu_to_le16(length);
3402 d->res_count = d->req_count;
3403 d->transfer_status = 0;
3404
3405 page_bus = page_private(buffer->pages[page]);
3406 d->data_address = cpu_to_le32(page_bus + offset);
3407
a572e688
CL		 3408 dma_sync_single_range_for_device(ctx->context.ohci->card.device,
3409 page_bus, offset, length,
3410 DMA_FROM_DEVICE);
3411
872e330e
SR		 3412 rest -= length;
3413 offset = 0;
3414 page++;
3415
3416 context_append(&ctx->context, d, 1, 0);
3417 }
3418
3419 return 0;
3420}
3421
53dca511
SR		 3422static int ohci_queue_iso(struct fw_iso_context *base,
3423 struct fw_iso_packet *packet,
3424 struct fw_iso_buffer *buffer,
3425 unsigned long payload)
295e3feb 3426{
e364cf4e 3427 struct iso_context *ctx = container_of(base, struct iso_context, base);
fe5ca634 3428 unsigned long flags;
872e330e 3429 int ret = -ENOSYS;
e364cf4e 3430
fe5ca634 3431 spin_lock_irqsave(&ctx->context.ohci->lock, flags);
872e330e
SR		 3432 switch (base->type) {
3433 case FW_ISO_CONTEXT_TRANSMIT:
3434 ret = queue_iso_transmit(ctx, packet, buffer, payload);
3435 break;
3436 case FW_ISO_CONTEXT_RECEIVE:
3437 ret = queue_iso_packet_per_buffer(ctx, packet, buffer, payload);
3438 break;
3439 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3440 ret = queue_iso_buffer_fill(ctx, packet, buffer, payload);
3441 break;
3442 }
fe5ca634
DM		 3443 spin_unlock_irqrestore(&ctx->context.ohci->lock, flags);
3444
2dbd7d7e 3445 return ret;
295e3feb
KH		 3446}
3447
13882a82
CL		 3448static void ohci_flush_queue_iso(struct fw_iso_context *base)
3449{
3450 struct context *ctx =
3451 &container_of(base, struct iso_context, base)->context;
3452
3453 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
13882a82
CL		 3454}
3455
d1bbd209
CL		 3456static int ohci_flush_iso_completions(struct fw_iso_context *base)
3457{
3458 struct iso_context *ctx = container_of(base, struct iso_context, base);
3459 int ret = 0;
3460
3461 tasklet_disable(&ctx->context.tasklet);
3462
3463 if (!test_and_set_bit_lock(0, &ctx->flushing_completions)) {
3464 context_tasklet((unsigned long)&ctx->context);
3465
3466 switch (base->type) {
3467 case FW_ISO_CONTEXT_TRANSMIT:
3468 case FW_ISO_CONTEXT_RECEIVE:
3469 if (ctx->header_length != 0)
3470 flush_iso_completions(ctx);
3471 break;
3472 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3473 if (ctx->mc_completed != 0)
3474 flush_ir_buffer_fill(ctx);
3475 break;
3476 default:
3477 ret = -ENOSYS;
3478 }
3479
3480 clear_bit_unlock(0, &ctx->flushing_completions);
3481 smp_mb__after_clear_bit();
3482 }
3483
3484 tasklet_enable(&ctx->context.tasklet);
3485
3486 return ret;
3487}
3488
21ebcd12 3489static const struct fw_card_driver ohci_driver = {
ed568912 3490 .enable = ohci_enable,
02d37bed 3491 .read_phy_reg = ohci_read_phy_reg,
ed568912
KH		 3492 .update_phy_reg = ohci_update_phy_reg,
3493 .set_config_rom = ohci_set_config_rom,
3494 .send_request = ohci_send_request,
3495 .send_response = ohci_send_response,
730c32f5 3496 .cancel_packet = ohci_cancel_packet,
ed568912 3497 .enable_phys_dma = ohci_enable_phys_dma,
0fcff4e3
SR		 3498 .read_csr = ohci_read_csr,
3499 .write_csr = ohci_write_csr,
ed568912
KH		 3500
3501 .allocate_iso_context = ohci_allocate_iso_context,
3502 .free_iso_context = ohci_free_iso_context,
872e330e 3503 .set_iso_channels = ohci_set_iso_channels,
ed568912 3504 .queue_iso = ohci_queue_iso,
13882a82 3505 .flush_queue_iso = ohci_flush_queue_iso,
d1bbd209 3506 .flush_iso_completions = ohci_flush_iso_completions,
69cdb726 3507 .start_iso = ohci_start_iso,
b8295668 3508 .stop_iso = ohci_stop_iso,
ed568912
KH		 3509};
3510
ea8d006b 3511#ifdef CONFIG_PPC_PMAC
5da3dac8 3512static void pmac_ohci_on(struct pci_dev *dev)
2ed0f181 3513{
ea8d006b
SR		 3514 if (machine_is(powermac)) {
3515 struct device_node *ofn = pci_device_to_OF_node(dev);
3516
3517 if (ofn) {
3518 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1);
3519 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1);
3520 }
3521 }
2ed0f181
SR		 3522}
3523
5da3dac8 3524static void pmac_ohci_off(struct pci_dev *dev)
2ed0f181
SR		 3525{
3526 if (machine_is(powermac)) {
3527 struct device_node *ofn = pci_device_to_OF_node(dev);
3528
3529 if (ofn) {
3530 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0);
3531 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0);
3532 }
3533 }
3534}
3535#else
5da3dac8
SR		 3536static inline void pmac_ohci_on(struct pci_dev *dev) {}
3537static inline void pmac_ohci_off(struct pci_dev *dev) {}
ea8d006b
SR		 3538#endif /* CONFIG_PPC_PMAC */
3539
53dca511
SR		 3540static int __devinit pci_probe(struct pci_dev *dev,
3541 const struct pci_device_id *ent)
2ed0f181
SR		 3542{
3543 struct fw_ohci *ohci;
aa0170ff 3544 u32 bus_options, max_receive, link_speed, version;
2ed0f181 3545 u64 guid;
dd23736e 3546 int i, err;
2ed0f181
SR		 3547 size_t size;
3548
7f7e3711
SR		 3549 if (dev->vendor == PCI_VENDOR_ID_PINNACLE_SYSTEMS) {
3550 dev_err(&dev->dev, "Pinnacle MovieBoard is not yet supported\n");
3551 return -ENOSYS;
3552 }
3553
2d826cc5 3554 ohci = kzalloc(sizeof(*ohci), GFP_KERNEL);
ed568912 3555 if (ohci == NULL) {
7007a076
SR		 3556 err = -ENOMEM;
3557 goto fail;
ed568912
KH		 3558 }
3559
3560 fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev);
3561
5da3dac8 3562 pmac_ohci_on(dev);
130d5496 3563
d79406dd
KH		 3564 err = pci_enable_device(dev);
3565 if (err) {
64d21720 3566 dev_err(&dev->dev, "failed to enable OHCI hardware\n");
bd7dee63 3567 goto fail_free;
ed568912
KH		 3568 }
3569
3570 pci_set_master(dev);
3571 pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0);
3572 pci_set_drvdata(dev, ohci);
3573
3574 spin_lock_init(&ohci->lock);
02d37bed 3575 mutex_init(&ohci->phy_reg_mutex);
ed568912 3576
2d7a36e2 3577 INIT_WORK(&ohci->bus_reset_work, bus_reset_work);
ed568912 3578
7baab9ac
CL		 3579 if (!(pci_resource_flags(dev, 0) & IORESOURCE_MEM) ||
3580 pci_resource_len(dev, 0) < OHCI1394_REGISTER_SIZE) {
3581 dev_err(&dev->dev, "invalid MMIO resource\n");
3582 err = -ENXIO;
3583 goto fail_disable;
3584 }
3585
d79406dd
KH		 3586 err = pci_request_region(dev, 0, ohci_driver_name);
3587 if (err) {
64d21720 3588 dev_err(&dev->dev, "MMIO resource unavailable\n");
d79406dd 3589 goto fail_disable;
ed568912
KH		 3590 }
3591
3592 ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE);
3593 if (ohci->registers == NULL) {
64d21720 3594 dev_err(&dev->dev, "failed to remap registers\n");
d79406dd
KH		 3595 err = -ENXIO;
3596 goto fail_iomem;
ed568912
KH		 3597 }
3598
4a635593 3599 for (i = 0; i < ARRAY_SIZE(ohci_quirks); i++)
9993e0fe
SR		 3600 if ((ohci_quirks[i].vendor == dev->vendor) &&
3601 (ohci_quirks[i].device == (unsigned short)PCI_ANY_ID ||
3602 ohci_quirks[i].device == dev->device) &&
3603 (ohci_quirks[i].revision == (unsigned short)PCI_ANY_ID ||
3604 ohci_quirks[i].revision >= dev->revision)) {
4a635593
SR		 3605 ohci->quirks = ohci_quirks[i].flags;
3606 break;
3607 }
3e9cc2f3
SR		 3608 if (param_quirks)
3609 ohci->quirks = param_quirks;
b677532b 3610
ec766a79
CL		 3611 /*
3612 * Because dma_alloc_coherent() allocates at least one page,
3613 * we save space by using a common buffer for the AR request/
3614 * response descriptors and the self IDs buffer.
3615 */
3616 BUILD_BUG_ON(AR_BUFFERS * sizeof(struct descriptor) > PAGE_SIZE/4);
3617 BUILD_BUG_ON(SELF_ID_BUF_SIZE > PAGE_SIZE/2);
3618 ohci->misc_buffer = dma_alloc_coherent(ohci->card.device,
3619 PAGE_SIZE,
3620 &ohci->misc_buffer_bus,
3621 GFP_KERNEL);
3622 if (!ohci->misc_buffer) {
3623 err = -ENOMEM;
3624 goto fail_iounmap;
3625 }
3626
3627 err = ar_context_init(&ohci->ar_request_ctx, ohci, 0,
7a39d8b8
CL		 3628 OHCI1394_AsReqRcvContextControlSet);
3629 if (err < 0)
ec766a79 3630 goto fail_misc_buf;
ed568912 3631
ec766a79 3632 err = ar_context_init(&ohci->ar_response_ctx, ohci, PAGE_SIZE/4,
7a39d8b8
CL		 3633 OHCI1394_AsRspRcvContextControlSet);
3634 if (err < 0)
3635 goto fail_arreq_ctx;
ed568912 3636
c088ab30
CL		 3637 err = context_init(&ohci->at_request_ctx, ohci,
3638 OHCI1394_AsReqTrContextControlSet, handle_at_packet);
3639 if (err < 0)
3640 goto fail_arrsp_ctx;
ed568912 3641
c088ab30
CL		 3642 err = context_init(&ohci->at_response_ctx, ohci,
3643 OHCI1394_AsRspTrContextControlSet, handle_at_packet);
3644 if (err < 0)
3645 goto fail_atreq_ctx;
ed568912 3646
ed568912 3647 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0);
4802f16d 3648 ohci->ir_context_channels = ~0ULL;
f117a3e3 3649 ohci->ir_context_support = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet);
ed568912 3650 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0);
f117a3e3 3651 ohci->ir_context_mask = ohci->ir_context_support;
dd23736e
ML		 3652 ohci->n_ir = hweight32(ohci->ir_context_mask);
3653 size = sizeof(struct iso_context) * ohci->n_ir;
4802f16d 3654 ohci->ir_context_list = kzalloc(size, GFP_KERNEL);
ed568912
KH		 3655
3656 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0);
f117a3e3 3657 ohci->it_context_support = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet);
ed568912 3658 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0);
f117a3e3 3659 ohci->it_context_mask = ohci->it_context_support;
dd23736e
ML		 3660 ohci->n_it = hweight32(ohci->it_context_mask);
3661 size = sizeof(struct iso_context) * ohci->n_it;
4802f16d 3662 ohci->it_context_list = kzalloc(size, GFP_KERNEL);
ed568912
KH		 3663
3664 if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) {
d79406dd 3665 err = -ENOMEM;
7007a076 3666 goto fail_contexts;
ed568912
KH		 3667 }
3668
ec766a79
CL		 3669 ohci->self_id_cpu = ohci->misc_buffer + PAGE_SIZE/2;
3670 ohci->self_id_bus = ohci->misc_buffer_bus + PAGE_SIZE/2;
ed568912 3671
ed568912
KH		 3672 bus_options = reg_read(ohci, OHCI1394_BusOptions);
3673 max_receive = (bus_options >> 12) & 0xf;
3674 link_speed = bus_options & 0x7;
3675 guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) |
3676 reg_read(ohci, OHCI1394_GUIDLo);
3677
d79406dd 3678 err = fw_card_add(&ohci->card, max_receive, link_speed, guid);
e1eff7a3 3679 if (err)
ec766a79 3680 goto fail_contexts;
ed568912 3681
6fdb2ee2 3682 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
64d21720
SR		 3683 dev_notice(&dev->dev,
3684 "added OHCI v%x.%x device as card %d, "
6fdb2ee2 3685 "%d IR + %d IT contexts, quirks 0x%x\n",
64d21720 3686 version >> 16, version & 0xff, ohci->card.index,
dd23736e 3687 ohci->n_ir, ohci->n_it, ohci->quirks);
e1eff7a3 3688
ed568912 3689 return 0;
d79406dd 3690
7007a076 3691 fail_contexts:
d79406dd 3692 kfree(ohci->ir_context_list);
7007a076
SR		 3693 kfree(ohci->it_context_list);
3694 context_release(&ohci->at_response_ctx);
c088ab30 3695 fail_atreq_ctx:
7007a076 3696 context_release(&ohci->at_request_ctx);
c088ab30 3697 fail_arrsp_ctx:
7007a076 3698 ar_context_release(&ohci->ar_response_ctx);
7a39d8b8 3699 fail_arreq_ctx:
7007a076 3700 ar_context_release(&ohci->ar_request_ctx);
ec766a79
CL		 3701 fail_misc_buf:
3702 dma_free_coherent(ohci->card.device, PAGE_SIZE,
3703 ohci->misc_buffer, ohci->misc_buffer_bus);
7a39d8b8 3704 fail_iounmap:
d79406dd
KH		 3705 pci_iounmap(dev, ohci->registers);
3706 fail_iomem:
3707 pci_release_region(dev, 0);
3708 fail_disable:
3709 pci_disable_device(dev);
bd7dee63 3710 fail_free:
d838d2c0 3711 kfree(ohci);
5da3dac8 3712 pmac_ohci_off(dev);
7007a076
SR		 3713 fail:
3714 if (err == -ENOMEM)
64d21720 3715 dev_err(&dev->dev, "out of memory\n");
d79406dd
KH		 3716
3717 return err;
ed568912
KH		 3718}
3719
3720static void pci_remove(struct pci_dev *dev)
3721{
3722 struct fw_ohci *ohci;
3723
3724 ohci = pci_get_drvdata(dev);
e254a4b4
KH		 3725 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
3726 flush_writes(ohci);
2d7a36e2 3727 cancel_work_sync(&ohci->bus_reset_work);
ed568912
KH		 3728 fw_core_remove_card(&ohci->card);
3729
c781c06d
KH		 3730 /*
3731 * FIXME: Fail all pending packets here, now that the upper
3732 * layers can't queue any more.
3733 */
ed568912
KH		 3734
3735 software_reset(ohci);
3736 free_irq(dev->irq, ohci);
a55709ba
JF		 3737
3738 if (ohci->next_config_rom && ohci->next_config_rom != ohci->config_rom)
3739 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
3740 ohci->next_config_rom, ohci->next_config_rom_bus);
3741 if (ohci->config_rom)
3742 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
3743 ohci->config_rom, ohci->config_rom_bus);
a55709ba
JF		 3744 ar_context_release(&ohci->ar_request_ctx);
3745 ar_context_release(&ohci->ar_response_ctx);
ec766a79
CL		 3746 dma_free_coherent(ohci->card.device, PAGE_SIZE,
3747 ohci->misc_buffer, ohci->misc_buffer_bus);
a55709ba
JF		 3748 context_release(&ohci->at_request_ctx);
3749 context_release(&ohci->at_response_ctx);
d79406dd
KH		 3750 kfree(ohci->it_context_list);
3751 kfree(ohci->ir_context_list);
262444ee 3752 pci_disable_msi(dev);
d79406dd
KH		 3753 pci_iounmap(dev, ohci->registers);
3754 pci_release_region(dev, 0);
3755 pci_disable_device(dev);
d838d2c0 3756 kfree(ohci);
5da3dac8 3757 pmac_ohci_off(dev);
ea8d006b 3758
64d21720 3759 dev_notice(&dev->dev, "removed fw-ohci device\n");
ed568912
KH		 3760}
3761
2aef469a 3762#ifdef CONFIG_PM
2ed0f181 3763static int pci_suspend(struct pci_dev *dev, pm_message_t state)
2aef469a 3764{
2ed0f181 3765 struct fw_ohci *ohci = pci_get_drvdata(dev);
2aef469a
KH		 3766 int err;
3767
3768 software_reset(ohci);
2ed0f181 3769 free_irq(dev->irq, ohci);
262444ee 3770 pci_disable_msi(dev);
2ed0f181 3771 err = pci_save_state(dev);
2aef469a 3772 if (err) {
64d21720 3773 dev_err(&dev->dev, "pci_save_state failed\n");
2aef469a
KH		 3774 return err;
3775 }
2ed0f181 3776 err = pci_set_power_state(dev, pci_choose_state(dev, state));
55111428 3777 if (err)
64d21720 3778 dev_err(&dev->dev, "pci_set_power_state failed with %d\n", err);
5da3dac8 3779 pmac_ohci_off(dev);
ea8d006b 3780
2aef469a
KH		 3781 return 0;
3782}
3783
2ed0f181 3784static int pci_resume(struct pci_dev *dev)
2aef469a 3785{
2ed0f181 3786 struct fw_ohci *ohci = pci_get_drvdata(dev);
2aef469a
KH		 3787 int err;
3788
5da3dac8 3789 pmac_ohci_on(dev);
2ed0f181
SR		 3790 pci_set_power_state(dev, PCI_D0);
3791 pci_restore_state(dev);
3792 err = pci_enable_device(dev);
2aef469a 3793 if (err) {
64d21720 3794 dev_err(&dev->dev, "pci_enable_device failed\n");
2aef469a
KH		 3795 return err;
3796 }
3797
8662b6b0
ML		 3798 /* Some systems don't setup GUID register on resume from ram */
3799 if (!reg_read(ohci, OHCI1394_GUIDLo) &&
3800 !reg_read(ohci, OHCI1394_GUIDHi)) {
3801 reg_write(ohci, OHCI1394_GUIDLo, (u32)ohci->card.guid);
3802 reg_write(ohci, OHCI1394_GUIDHi, (u32)(ohci->card.guid >> 32));
3803 }
3804
dd23736e 3805 err = ohci_enable(&ohci->card, NULL, 0);
dd23736e
ML		 3806 if (err)
3807 return err;
3808
3809 ohci_resume_iso_dma(ohci);
693a50b5 3810
dd23736e 3811 return 0;
2aef469a
KH		 3812}
3813#endif
3814
a67483d2 3815static const struct pci_device_id pci_table[] = {
ed568912
KH		 3816 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) },
3817 { }
3818};
3819
3820MODULE_DEVICE_TABLE(pci, pci_table);
3821
3822static struct pci_driver fw_ohci_pci_driver = {
3823 .name = ohci_driver_name,
3824 .id_table = pci_table,
3825 .probe = pci_probe,
3826 .remove = pci_remove,
2aef469a
KH		 3827#ifdef CONFIG_PM
3828 .resume = pci_resume,
3829 .suspend = pci_suspend,
3830#endif
ed568912
KH		 3831};
3832
fe2af11c
AL		 3833module_pci_driver(fw_ohci_pci_driver);
3834
ed568912
KH		 3835MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
3836MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
3837MODULE_LICENSE("GPL");
3838
1e4c7b0d
OH		 3839/* Provide a module alias so root-on-sbp2 initrds don't break. */
3840#ifndef CONFIG_IEEE1394_OHCI1394_MODULE
3841MODULE_ALIAS("ohci1394");
3842#endif
Ubuntu Artful kernel mirror