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firewire: ohci: cache the context run bit
[mirror_ubuntu-artful-kernel.git] / drivers / firewire / ohci.c
CommitLineData
c781c06d
KH		 1/*
2 * Driver for OHCI 1394 controllers
ed568912 3 *
ed568912
KH		 4 * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software Foundation,
18 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
dd23736e 21#include <linux/bitops.h>
65b2742a 22#include <linux/bug.h>
e524f616 23#include <linux/compiler.h>
ed568912 24#include <linux/delay.h>
e8ca9702 25#include <linux/device.h>
cf3e72fd 26#include <linux/dma-mapping.h>
77c9a5da 27#include <linux/firewire.h>
e8ca9702 28#include <linux/firewire-constants.h>
a7fb60db
SR		 29#include <linux/init.h>
30#include <linux/interrupt.h>
e8ca9702 31#include <linux/io.h>
a7fb60db 32#include <linux/kernel.h>
e8ca9702 33#include <linux/list.h>
faa2fb4e 34#include <linux/mm.h>
a7fb60db 35#include <linux/module.h>
ad3c0fe8 36#include <linux/moduleparam.h>
02d37bed 37#include <linux/mutex.h>
a7fb60db 38#include <linux/pci.h>
fc383796 39#include <linux/pci_ids.h>
5a0e3ad6 40#include <linux/slab.h>
c26f0234 41#include <linux/spinlock.h>
e8ca9702 42#include <linux/string.h>
e78483c5 43#include <linux/time.h>
7a39d8b8 44#include <linux/vmalloc.h>
cf3e72fd 45
e8ca9702 46#include <asm/byteorder.h>
c26f0234 47#include <asm/page.h>
ee71c2f9 48#include <asm/system.h>
ed568912 49
ea8d006b
SR		 50#ifdef CONFIG_PPC_PMAC
51#include <asm/pmac_feature.h>
52#endif
53
77c9a5da
SR		 54#include "core.h"
55#include "ohci.h"
ed568912 56
a77754a7
KH		 57#define DESCRIPTOR_OUTPUT_MORE 0
58#define DESCRIPTOR_OUTPUT_LAST (1 << 12)
59#define DESCRIPTOR_INPUT_MORE (2 << 12)
60#define DESCRIPTOR_INPUT_LAST (3 << 12)
61#define DESCRIPTOR_STATUS (1 << 11)
62#define DESCRIPTOR_KEY_IMMEDIATE (2 << 8)
63#define DESCRIPTOR_PING (1 << 7)
64#define DESCRIPTOR_YY (1 << 6)
65#define DESCRIPTOR_NO_IRQ (0 << 4)
66#define DESCRIPTOR_IRQ_ERROR (1 << 4)
67#define DESCRIPTOR_IRQ_ALWAYS (3 << 4)
68#define DESCRIPTOR_BRANCH_ALWAYS (3 << 2)
69#define DESCRIPTOR_WAIT (3 << 0)
ed568912
KH		 70
71struct descriptor {
72 __le16 req_count;
73 __le16 control;
74 __le32 data_address;
75 __le32 branch_address;
76 __le16 res_count;
77 __le16 transfer_status;
78} __attribute__((aligned(16)));
79
a77754a7
KH		 80#define CONTROL_SET(regs) (regs)
81#define CONTROL_CLEAR(regs) ((regs) + 4)
82#define COMMAND_PTR(regs) ((regs) + 12)
83#define CONTEXT_MATCH(regs) ((regs) + 16)
72e318e0 84
7a39d8b8
CL		 85#define AR_BUFFER_SIZE (32*1024)
86#define AR_BUFFERS_MIN DIV_ROUND_UP(AR_BUFFER_SIZE, PAGE_SIZE)
87/* we need at least two pages for proper list management */
88#define AR_BUFFERS (AR_BUFFERS_MIN >= 2 ? AR_BUFFERS_MIN : 2)
89
90#define MAX_ASYNC_PAYLOAD 4096
91#define MAX_AR_PACKET_SIZE (16 + MAX_ASYNC_PAYLOAD + 4)
92#define AR_WRAPAROUND_PAGES DIV_ROUND_UP(MAX_AR_PACKET_SIZE, PAGE_SIZE)
ed568912 93
32b46093
KH		 94struct ar_context {
95 struct fw_ohci *ohci;
7a39d8b8
CL		 96 struct page *pages[AR_BUFFERS];
97 void *buffer;
98 struct descriptor *descriptors;
99 dma_addr_t descriptors_bus;
32b46093 100 void *pointer;
7a39d8b8 101 unsigned int last_buffer_index;
72e318e0 102 u32 regs;
ed568912
KH		 103 struct tasklet_struct tasklet;
104};
105
30200739
KH		 106struct context;
107
108typedef int (*descriptor_callback_t)(struct context *ctx,
109 struct descriptor *d,
110 struct descriptor *last);
fe5ca634
DM		 111
112/*
113 * A buffer that contains a block of DMA-able coherent memory used for
114 * storing a portion of a DMA descriptor program.
115 */
116struct descriptor_buffer {
117 struct list_head list;
118 dma_addr_t buffer_bus;
119 size_t buffer_size;
120 size_t used;
121 struct descriptor buffer[0];
122};
123
30200739 124struct context {
373b2edd 125 struct fw_ohci *ohci;
30200739 126 u32 regs;
fe5ca634 127 int total_allocation;
386a4153 128 bool running;
82b662dc 129 bool flushing;
373b2edd 130
fe5ca634
DM		 131 /*
132 * List of page-sized buffers for storing DMA descriptors.
133 * Head of list contains buffers in use and tail of list contains
134 * free buffers.
135 */
136 struct list_head buffer_list;
137
138 /*
139 * Pointer to a buffer inside buffer_list that contains the tail
140 * end of the current DMA program.
141 */
142 struct descriptor_buffer *buffer_tail;
143
144 /*
145 * The descriptor containing the branch address of the first
146 * descriptor that has not yet been filled by the device.
147 */
148 struct descriptor *last;
149
150 /*
151 * The last descriptor in the DMA program. It contains the branch
152 * address that must be updated upon appending a new descriptor.
153 */
154 struct descriptor *prev;
30200739
KH		 155
156 descriptor_callback_t callback;
157
373b2edd 158 struct tasklet_struct tasklet;
dd23736e 159 bool active;
30200739 160};
30200739 161
a77754a7
KH		 162#define IT_HEADER_SY(v) ((v) << 0)
163#define IT_HEADER_TCODE(v) ((v) << 4)
164#define IT_HEADER_CHANNEL(v) ((v) << 8)
165#define IT_HEADER_TAG(v) ((v) << 14)
166#define IT_HEADER_SPEED(v) ((v) << 16)
167#define IT_HEADER_DATA_LENGTH(v) ((v) << 16)
ed568912
KH		 168
169struct iso_context {
170 struct fw_iso_context base;
30200739 171 struct context context;
0642b657 172 int excess_bytes;
9b32d5f3
KH		 173 void *header;
174 size_t header_length;
dd23736e
ML		 175
176 u8 sync;
177 u8 tags;
ed568912
KH		 178};
179
180#define CONFIG_ROM_SIZE 1024
181
182struct fw_ohci {
183 struct fw_card card;
184
185 __iomem char *registers;
e636fe25 186 int node_id;
ed568912 187 int generation;
e09770db 188 int request_generation; /* for timestamping incoming requests */
4a635593 189 unsigned quirks;
a1a1132b 190 unsigned int pri_req_max;
a48777e0 191 u32 bus_time;
4ffb7a6a 192 bool is_root;
c8a94ded 193 bool csr_state_setclear_abdicate;
dd23736e
ML		 194 int n_ir;
195 int n_it;
c781c06d
KH		 196 /*
197 * Spinlock for accessing fw_ohci data. Never call out of
198 * this driver with this lock held.
199 */
ed568912 200 spinlock_t lock;
ed568912 201
02d37bed
SR		 202 struct mutex phy_reg_mutex;
203
ec766a79
CL		 204 void *misc_buffer;
205 dma_addr_t misc_buffer_bus;
206
ed568912
KH		 207 struct ar_context ar_request_ctx;
208 struct ar_context ar_response_ctx;
f319b6a0
KH		 209 struct context at_request_ctx;
210 struct context at_response_ctx;
ed568912 211
872e330e 212 u32 it_context_mask; /* unoccupied IT contexts */
ed568912 213 struct iso_context *it_context_list;
872e330e
SR		 214 u64 ir_context_channels; /* unoccupied channels */
215 u32 ir_context_mask; /* unoccupied IR contexts */
ed568912 216 struct iso_context *ir_context_list;
872e330e
SR		 217 u64 mc_channels; /* channels in use by the multichannel IR context */
218 bool mc_allocated;
ecb1cf9c
SR		 219
220 __be32 *config_rom;
221 dma_addr_t config_rom_bus;
222 __be32 *next_config_rom;
223 dma_addr_t next_config_rom_bus;
224 __be32 next_header;
225
226 __le32 *self_id_cpu;
227 dma_addr_t self_id_bus;
228 struct tasklet_struct bus_reset_tasklet;
229
230 u32 self_id_buffer[512];
ed568912
KH		 231};
232
95688e97 233static inline struct fw_ohci *fw_ohci(struct fw_card *card)
ed568912
KH		 234{
235 return container_of(card, struct fw_ohci, card);
236}
237
295e3feb
KH		 238#define IT_CONTEXT_CYCLE_MATCH_ENABLE 0x80000000
239#define IR_CONTEXT_BUFFER_FILL 0x80000000
240#define IR_CONTEXT_ISOCH_HEADER 0x40000000
241#define IR_CONTEXT_CYCLE_MATCH_ENABLE 0x20000000
242#define IR_CONTEXT_MULTI_CHANNEL_MODE 0x10000000
243#define IR_CONTEXT_DUAL_BUFFER_MODE 0x08000000
ed568912
KH		 244
245#define CONTEXT_RUN 0x8000
246#define CONTEXT_WAKE 0x1000
247#define CONTEXT_DEAD 0x0800
248#define CONTEXT_ACTIVE 0x0400
249
8b7b6afa 250#define OHCI1394_MAX_AT_REQ_RETRIES 0xf
ed568912
KH		 251#define OHCI1394_MAX_AT_RESP_RETRIES 0x2
252#define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8
253
ed568912
KH		 254#define OHCI1394_REGISTER_SIZE 0x800
255#define OHCI_LOOP_COUNT 500
256#define OHCI1394_PCI_HCI_Control 0x40
257#define SELF_ID_BUF_SIZE 0x800
32b46093 258#define OHCI_TCODE_PHY_PACKET 0x0e
e364cf4e 259#define OHCI_VERSION_1_1 0x010010
0edeefd9 260
ed568912
KH		 261static char ohci_driver_name[] = KBUILD_MODNAME;
262
9993e0fe 263#define PCI_DEVICE_ID_AGERE_FW643 0x5901
262444ee 264#define PCI_DEVICE_ID_JMICRON_JMB38X_FW 0x2380
8301b91b
CL		 265#define PCI_DEVICE_ID_TI_TSB12LV22 0x8009
266
4a635593
SR		 267#define QUIRK_CYCLE_TIMER 1
268#define QUIRK_RESET_PACKET 2
269#define QUIRK_BE_HEADERS 4
925e7a65 270#define QUIRK_NO_1394A 8
262444ee 271#define QUIRK_NO_MSI 16
4a635593
SR		 272
273/* In case of multiple matches in ohci_quirks[], only the first one is used. */
274static const struct {
9993e0fe 275 unsigned short vendor, device, revision, flags;
4a635593 276} ohci_quirks[] = {
9993e0fe
SR		 277 {PCI_VENDOR_ID_AL, PCI_ANY_ID, PCI_ANY_ID,
278 QUIRK_CYCLE_TIMER},
279
280 {PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_FW, PCI_ANY_ID,
281 QUIRK_BE_HEADERS},
282
283 {PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_AGERE_FW643, 6,
284 QUIRK_NO_MSI},
285
286 {PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB38X_FW, PCI_ANY_ID,
287 QUIRK_NO_MSI},
288
289 {PCI_VENDOR_ID_NEC, PCI_ANY_ID, PCI_ANY_ID,
290 QUIRK_CYCLE_TIMER},
291
292 {PCI_VENDOR_ID_RICOH, PCI_ANY_ID, PCI_ANY_ID,
293 QUIRK_CYCLE_TIMER},
294
295 {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV22, PCI_ANY_ID,
296 QUIRK_CYCLE_TIMER | QUIRK_RESET_PACKET | QUIRK_NO_1394A},
297
298 {PCI_VENDOR_ID_TI, PCI_ANY_ID, PCI_ANY_ID,
299 QUIRK_RESET_PACKET},
300
301 {PCI_VENDOR_ID_VIA, PCI_ANY_ID, PCI_ANY_ID,
302 QUIRK_CYCLE_TIMER | QUIRK_NO_MSI},
4a635593
SR		 303};
304
3e9cc2f3
SR		 305/* This overrides anything that was found in ohci_quirks[]. */
306static int param_quirks;
307module_param_named(quirks, param_quirks, int, 0644);
308MODULE_PARM_DESC(quirks, "Chip quirks (default = 0"
309 ", nonatomic cycle timer = " __stringify(QUIRK_CYCLE_TIMER)
310 ", reset packet generation = " __stringify(QUIRK_RESET_PACKET)
311 ", AR/selfID endianess = " __stringify(QUIRK_BE_HEADERS)
925e7a65 312 ", no 1394a enhancements = " __stringify(QUIRK_NO_1394A)
262444ee 313 ", disable MSI = " __stringify(QUIRK_NO_MSI)
3e9cc2f3
SR		 314 ")");
315
a007bb85 316#define OHCI_PARAM_DEBUG_AT_AR 1
ad3c0fe8 317#define OHCI_PARAM_DEBUG_SELFIDS 2
a007bb85
SR		 318#define OHCI_PARAM_DEBUG_IRQS 4
319#define OHCI_PARAM_DEBUG_BUSRESETS 8 /* only effective before chip init */
ad3c0fe8 320
5da3dac8
SR		 321#ifdef CONFIG_FIREWIRE_OHCI_DEBUG
322
ad3c0fe8
SR		 323static int param_debug;
324module_param_named(debug, param_debug, int, 0644);
325MODULE_PARM_DESC(debug, "Verbose logging (default = 0"
ad3c0fe8 326 ", AT/AR events = " __stringify(OHCI_PARAM_DEBUG_AT_AR)
a007bb85
SR		 327 ", self-IDs = " __stringify(OHCI_PARAM_DEBUG_SELFIDS)
328 ", IRQs = " __stringify(OHCI_PARAM_DEBUG_IRQS)
329 ", busReset events = " __stringify(OHCI_PARAM_DEBUG_BUSRESETS)
ad3c0fe8
SR		 330 ", or a combination, or all = -1)");
331
332static void log_irqs(u32 evt)
333{
a007bb85
SR		 334 if (likely(!(param_debug &
335 (OHCI_PARAM_DEBUG_IRQS | OHCI_PARAM_DEBUG_BUSRESETS))))
336 return;
337
338 if (!(param_debug & OHCI_PARAM_DEBUG_IRQS) &&
339 !(evt & OHCI1394_busReset))
ad3c0fe8
SR		 340 return;
341
a48777e0 342 fw_notify("IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt,
161b96e7
SR		 343 evt & OHCI1394_selfIDComplete ? " selfID" : "",
344 evt & OHCI1394_RQPkt ? " AR_req" : "",
345 evt & OHCI1394_RSPkt ? " AR_resp" : "",
346 evt & OHCI1394_reqTxComplete ? " AT_req" : "",
347 evt & OHCI1394_respTxComplete ? " AT_resp" : "",
348 evt & OHCI1394_isochRx ? " IR" : "",
349 evt & OHCI1394_isochTx ? " IT" : "",
350 evt & OHCI1394_postedWriteErr ? " postedWriteErr" : "",
351 evt & OHCI1394_cycleTooLong ? " cycleTooLong" : "",
a48777e0 352 evt & OHCI1394_cycle64Seconds ? " cycle64Seconds" : "",
5ed1f321 353 evt & OHCI1394_cycleInconsistent ? " cycleInconsistent" : "",
161b96e7
SR		 354 evt & OHCI1394_regAccessFail ? " regAccessFail" : "",
355 evt & OHCI1394_busReset ? " busReset" : "",
356 evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt |
357 OHCI1394_RSPkt | OHCI1394_reqTxComplete |
358 OHCI1394_respTxComplete | OHCI1394_isochRx |
359 OHCI1394_isochTx | OHCI1394_postedWriteErr |
a48777e0
CL		 360 OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds |
361 OHCI1394_cycleInconsistent |
161b96e7 362 OHCI1394_regAccessFail | OHCI1394_busReset)
ad3c0fe8
SR		 363 ? " ?" : "");
364}
365
366static const char *speed[] = {
367 [0] = "S100", [1] = "S200", [2] = "S400", [3] = "beta",
368};
369static const char *power[] = {
370 [0] = "+0W", [1] = "+15W", [2] = "+30W", [3] = "+45W",
371 [4] = "-3W", [5] = " ?W", [6] = "-3..-6W", [7] = "-3..-10W",
372};
373static const char port[] = { '.', '-', 'p', 'c', };
374
375static char _p(u32 *s, int shift)
376{
377 return port[*s >> shift & 3];
378}
379
08ddb2f4 380static void log_selfids(int node_id, int generation, int self_id_count, u32 *s)
ad3c0fe8
SR		 381{
382 if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS)))
383 return;
384
161b96e7
SR		 385 fw_notify("%d selfIDs, generation %d, local node ID %04x\n",
386 self_id_count, generation, node_id);
ad3c0fe8
SR		 387
388 for (; self_id_count--; ++s)
389 if ((*s & 1 << 23) == 0)
161b96e7
SR		 390 fw_notify("selfID 0: %08x, phy %d [%c%c%c] "
391 "%s gc=%d %s %s%s%s\n",
392 *s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2),
393 speed[*s >> 14 & 3], *s >> 16 & 63,
394 power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "",
395 *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : "");
ad3c0fe8 396 else
161b96e7
SR		 397 fw_notify("selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n",
398 *s, *s >> 24 & 63,
399 _p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10),
400 _p(s, 8), _p(s, 6), _p(s, 4), _p(s, 2));
ad3c0fe8
SR		 401}
402
403static const char *evts[] = {
404 [0x00] = "evt_no_status", [0x01] = "-reserved-",
405 [0x02] = "evt_long_packet", [0x03] = "evt_missing_ack",
406 [0x04] = "evt_underrun", [0x05] = "evt_overrun",
407 [0x06] = "evt_descriptor_read", [0x07] = "evt_data_read",
408 [0x08] = "evt_data_write", [0x09] = "evt_bus_reset",
409 [0x0a] = "evt_timeout", [0x0b] = "evt_tcode_err",
410 [0x0c] = "-reserved-", [0x0d] = "-reserved-",
411 [0x0e] = "evt_unknown", [0x0f] = "evt_flushed",
412 [0x10] = "-reserved-", [0x11] = "ack_complete",
413 [0x12] = "ack_pending ", [0x13] = "-reserved-",
414 [0x14] = "ack_busy_X", [0x15] = "ack_busy_A",
415 [0x16] = "ack_busy_B", [0x17] = "-reserved-",
416 [0x18] = "-reserved-", [0x19] = "-reserved-",
417 [0x1a] = "-reserved-", [0x1b] = "ack_tardy",
418 [0x1c] = "-reserved-", [0x1d] = "ack_data_error",
419 [0x1e] = "ack_type_error", [0x1f] = "-reserved-",
420 [0x20] = "pending/cancelled",
421};
422static const char *tcodes[] = {
423 [0x0] = "QW req", [0x1] = "BW req",
424 [0x2] = "W resp", [0x3] = "-reserved-",
425 [0x4] = "QR req", [0x5] = "BR req",
426 [0x6] = "QR resp", [0x7] = "BR resp",
427 [0x8] = "cycle start", [0x9] = "Lk req",
428 [0xa] = "async stream packet", [0xb] = "Lk resp",
429 [0xc] = "-reserved-", [0xd] = "-reserved-",
430 [0xe] = "link internal", [0xf] = "-reserved-",
431};
ad3c0fe8
SR		 432
433static void log_ar_at_event(char dir, int speed, u32 *header, int evt)
434{
435 int tcode = header[0] >> 4 & 0xf;
436 char specific[12];
437
438 if (likely(!(param_debug & OHCI_PARAM_DEBUG_AT_AR)))
439 return;
440
441 if (unlikely(evt >= ARRAY_SIZE(evts)))
442 evt = 0x1f;
443
08ddb2f4 444 if (evt == OHCI1394_evt_bus_reset) {
161b96e7
SR		 445 fw_notify("A%c evt_bus_reset, generation %d\n",
446 dir, (header[2] >> 16) & 0xff);
08ddb2f4
SR		 447 return;
448 }
449
ad3c0fe8
SR		 450 switch (tcode) {
451 case 0x0: case 0x6: case 0x8:
452 snprintf(specific, sizeof(specific), " = %08x",
453 be32_to_cpu((__force __be32)header[3]));
454 break;
455 case 0x1: case 0x5: case 0x7: case 0x9: case 0xb:
456 snprintf(specific, sizeof(specific), " %x,%x",
457 header[3] >> 16, header[3] & 0xffff);
458 break;
459 default:
460 specific[0] = '\0';
461 }
462
463 switch (tcode) {
5b06db16 464 case 0xa:
161b96e7 465 fw_notify("A%c %s, %s\n", dir, evts[evt], tcodes[tcode]);
ad3c0fe8 466 break;
5b06db16
CL		 467 case 0xe:
468 fw_notify("A%c %s, PHY %08x %08x\n",
469 dir, evts[evt], header[1], header[2]);
470 break;
ad3c0fe8 471 case 0x0: case 0x1: case 0x4: case 0x5: case 0x9:
161b96e7
SR		 472 fw_notify("A%c spd %x tl %02x, "
473 "%04x -> %04x, %s, "
474 "%s, %04x%08x%s\n",
475 dir, speed, header[0] >> 10 & 0x3f,
476 header[1] >> 16, header[0] >> 16, evts[evt],
477 tcodes[tcode], header[1] & 0xffff, header[2], specific);
ad3c0fe8
SR		 478 break;
479 default:
161b96e7
SR		 480 fw_notify("A%c spd %x tl %02x, "
481 "%04x -> %04x, %s, "
482 "%s%s\n",
483 dir, speed, header[0] >> 10 & 0x3f,
484 header[1] >> 16, header[0] >> 16, evts[evt],
485 tcodes[tcode], specific);
ad3c0fe8
SR		 486 }
487}
488
489#else
490
5da3dac8
SR		 491#define param_debug 0
492static inline void log_irqs(u32 evt) {}
493static inline void log_selfids(int node_id, int generation, int self_id_count, u32 *s) {}
494static inline void log_ar_at_event(char dir, int speed, u32 *header, int evt) {}
ad3c0fe8
SR		 495
496#endif /* CONFIG_FIREWIRE_OHCI_DEBUG */
497
95688e97 498static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data)
ed568912
KH		 499{
500 writel(data, ohci->registers + offset);
501}
502
95688e97 503static inline u32 reg_read(const struct fw_ohci *ohci, int offset)
ed568912
KH		 504{
505 return readl(ohci->registers + offset);
506}
507
95688e97 508static inline void flush_writes(const struct fw_ohci *ohci)
ed568912
KH		 509{
510 /* Do a dummy read to flush writes. */
511 reg_read(ohci, OHCI1394_Version);
512}
513
35d999b1 514static int read_phy_reg(struct fw_ohci *ohci, int addr)
ed568912 515{
4a96b4fc 516 u32 val;
35d999b1 517 int i;
ed568912
KH		 518
519 reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr));
153e3979 520 for (i = 0; i < 3 + 100; i++) {
35d999b1
SR		 521 val = reg_read(ohci, OHCI1394_PhyControl);
522 if (val & OHCI1394_PhyControl_ReadDone)
523 return OHCI1394_PhyControl_ReadData(val);
524
153e3979
CL		 525 /*
526 * Try a few times without waiting. Sleeping is necessary
527 * only when the link/PHY interface is busy.
528 */
529 if (i >= 3)
530 msleep(1);
ed568912 531 }
35d999b1 532 fw_error("failed to read phy reg\n");
ed568912 533
35d999b1
SR		 534 return -EBUSY;
535}
4a96b4fc 536
35d999b1
SR		 537static int write_phy_reg(const struct fw_ohci *ohci, int addr, u32 val)
538{
539 int i;
ed568912 540
ed568912 541 reg_write(ohci, OHCI1394_PhyControl,
35d999b1 542 OHCI1394_PhyControl_Write(addr, val));
153e3979 543 for (i = 0; i < 3 + 100; i++) {
35d999b1
SR		 544 val = reg_read(ohci, OHCI1394_PhyControl);
545 if (!(val & OHCI1394_PhyControl_WritePending))
546 return 0;
ed568912 547
153e3979
CL		 548 if (i >= 3)
549 msleep(1);
35d999b1
SR		 550 }
551 fw_error("failed to write phy reg\n");
552
553 return -EBUSY;
4a96b4fc
CL		 554}
555
02d37bed
SR		 556static int update_phy_reg(struct fw_ohci *ohci, int addr,
557 int clear_bits, int set_bits)
4a96b4fc 558{
02d37bed 559 int ret = read_phy_reg(ohci, addr);
35d999b1
SR		 560 if (ret < 0)
561 return ret;
4a96b4fc 562
e7014dad
CL		 563 /*
564 * The interrupt status bits are cleared by writing a one bit.
565 * Avoid clearing them unless explicitly requested in set_bits.
566 */
567 if (addr == 5)
568 clear_bits |= PHY_INT_STATUS_BITS;
569
35d999b1 570 return write_phy_reg(ohci, addr, (ret & ~clear_bits) | set_bits);
ed568912
KH		 571}
572
35d999b1 573static int read_paged_phy_reg(struct fw_ohci *ohci, int page, int addr)
925e7a65 574{
35d999b1 575 int ret;
925e7a65 576
02d37bed 577 ret = update_phy_reg(ohci, 7, PHY_PAGE_SELECT, page << 5);
35d999b1
SR		 578 if (ret < 0)
579 return ret;
925e7a65 580
35d999b1 581 return read_phy_reg(ohci, addr);
ed568912
KH		 582}
583
02d37bed
SR		 584static int ohci_read_phy_reg(struct fw_card *card, int addr)
585{
586 struct fw_ohci *ohci = fw_ohci(card);
587 int ret;
588
589 mutex_lock(&ohci->phy_reg_mutex);
590 ret = read_phy_reg(ohci, addr);
591 mutex_unlock(&ohci->phy_reg_mutex);
592
593 return ret;
594}
595
596static int ohci_update_phy_reg(struct fw_card *card, int addr,
597 int clear_bits, int set_bits)
598{
599 struct fw_ohci *ohci = fw_ohci(card);
600 int ret;
601
602 mutex_lock(&ohci->phy_reg_mutex);
603 ret = update_phy_reg(ohci, addr, clear_bits, set_bits);
604 mutex_unlock(&ohci->phy_reg_mutex);
605
606 return ret;
ed568912
KH		 607}
608
7a39d8b8
CL		 609static inline dma_addr_t ar_buffer_bus(struct ar_context *ctx, unsigned int i)
610{
611 return page_private(ctx->pages[i]);
612}
613
614static void ar_context_link_page(struct ar_context *ctx, unsigned int index)
ed568912 615{
7a39d8b8 616 struct descriptor *d;
32b46093 617
7a39d8b8
CL		 618 d = &ctx->descriptors[index];
619 d->branch_address &= cpu_to_le32(~0xf);
620 d->res_count = cpu_to_le16(PAGE_SIZE);
621 d->transfer_status = 0;
32b46093 622
071595eb 623 wmb(); /* finish init of new descriptors before branch_address update */
7a39d8b8
CL		 624 d = &ctx->descriptors[ctx->last_buffer_index];
625 d->branch_address |= cpu_to_le32(1);
626
627 ctx->last_buffer_index = index;
32b46093 628
a77754a7 629 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
ed568912 630 flush_writes(ctx->ohci);
837596a6
CL		 631}
632
7a39d8b8 633static void ar_context_release(struct ar_context *ctx)
837596a6 634{
7a39d8b8 635 unsigned int i;
837596a6 636
7a39d8b8
CL		 637 if (ctx->buffer)
638 vm_unmap_ram(ctx->buffer, AR_BUFFERS + AR_WRAPAROUND_PAGES);
32b46093 639
7a39d8b8
CL		 640 for (i = 0; i < AR_BUFFERS; i++)
641 if (ctx->pages[i]) {
642 dma_unmap_page(ctx->ohci->card.device,
643 ar_buffer_bus(ctx, i),
644 PAGE_SIZE, DMA_FROM_DEVICE);
645 __free_page(ctx->pages[i]);
646 }
ed568912
KH		 647}
648
7a39d8b8 649static void ar_context_abort(struct ar_context *ctx, const char *error_msg)
a55709ba 650{
7a39d8b8
CL		 651 if (reg_read(ctx->ohci, CONTROL_CLEAR(ctx->regs)) & CONTEXT_RUN) {
652 reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
653 flush_writes(ctx->ohci);
a55709ba 654
7a39d8b8 655 fw_error("AR error: %s; DMA stopped\n", error_msg);
a55709ba 656 }
7a39d8b8
CL		 657 /* FIXME: restart? */
658}
659
660static inline unsigned int ar_next_buffer_index(unsigned int index)
661{
662 return (index + 1) % AR_BUFFERS;
663}
664
665static inline unsigned int ar_prev_buffer_index(unsigned int index)
666{
667 return (index - 1 + AR_BUFFERS) % AR_BUFFERS;
668}
669
670static inline unsigned int ar_first_buffer_index(struct ar_context *ctx)
671{
672 return ar_next_buffer_index(ctx->last_buffer_index);
673}
674
675/*
676 * We search for the buffer that contains the last AR packet DMA data written
677 * by the controller.
678 */
679static unsigned int ar_search_last_active_buffer(struct ar_context *ctx,
680 unsigned int *buffer_offset)
681{
682 unsigned int i, next_i, last = ctx->last_buffer_index;
683 __le16 res_count, next_res_count;
684
685 i = ar_first_buffer_index(ctx);
686 res_count = ACCESS_ONCE(ctx->descriptors[i].res_count);
687
688 /* A buffer that is not yet completely filled must be the last one. */
689 while (i != last && res_count == 0) {
690
691 /* Peek at the next descriptor. */
692 next_i = ar_next_buffer_index(i);
693 rmb(); /* read descriptors in order */
694 next_res_count = ACCESS_ONCE(
695 ctx->descriptors[next_i].res_count);
696 /*
697 * If the next descriptor is still empty, we must stop at this
698 * descriptor.
699 */
700 if (next_res_count == cpu_to_le16(PAGE_SIZE)) {
701 /*
702 * The exception is when the DMA data for one packet is
703 * split over three buffers; in this case, the middle
704 * buffer's descriptor might be never updated by the
705 * controller and look still empty, and we have to peek
706 * at the third one.
707 */
708 if (MAX_AR_PACKET_SIZE > PAGE_SIZE && i != last) {
709 next_i = ar_next_buffer_index(next_i);
710 rmb();
711 next_res_count = ACCESS_ONCE(
712 ctx->descriptors[next_i].res_count);
713 if (next_res_count != cpu_to_le16(PAGE_SIZE))
714 goto next_buffer_is_active;
715 }
716
717 break;
718 }
719
720next_buffer_is_active:
721 i = next_i;
722 res_count = next_res_count;
723 }
724
725 rmb(); /* read res_count before the DMA data */
726
727 *buffer_offset = PAGE_SIZE - le16_to_cpu(res_count);
728 if (*buffer_offset > PAGE_SIZE) {
729 *buffer_offset = 0;
730 ar_context_abort(ctx, "corrupted descriptor");
731 }
732
733 return i;
734}
735
736static void ar_sync_buffers_for_cpu(struct ar_context *ctx,
737 unsigned int end_buffer_index,
738 unsigned int end_buffer_offset)
739{
740 unsigned int i;
741
742 i = ar_first_buffer_index(ctx);
743 while (i != end_buffer_index) {
744 dma_sync_single_for_cpu(ctx->ohci->card.device,
745 ar_buffer_bus(ctx, i),
746 PAGE_SIZE, DMA_FROM_DEVICE);
747 i = ar_next_buffer_index(i);
748 }
749 if (end_buffer_offset > 0)
750 dma_sync_single_for_cpu(ctx->ohci->card.device,
751 ar_buffer_bus(ctx, i),
752 end_buffer_offset, DMA_FROM_DEVICE);
a55709ba
JF		 753}
754
11bf20ad
SR		 755#if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
756#define cond_le32_to_cpu(v) \
4a635593 757 (ohci->quirks & QUIRK_BE_HEADERS ? (__force __u32)(v) : le32_to_cpu(v))
11bf20ad
SR		 758#else
759#define cond_le32_to_cpu(v) le32_to_cpu(v)
760#endif
761
32b46093 762static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer)
ed568912 763{
ed568912 764 struct fw_ohci *ohci = ctx->ohci;
2639a6fb
KH		 765 struct fw_packet p;
766 u32 status, length, tcode;
43286568 767 int evt;
2639a6fb 768
11bf20ad
SR		 769 p.header[0] = cond_le32_to_cpu(buffer[0]);
770 p.header[1] = cond_le32_to_cpu(buffer[1]);
771 p.header[2] = cond_le32_to_cpu(buffer[2]);
2639a6fb
KH		 772
773 tcode = (p.header[0] >> 4) & 0x0f;
774 switch (tcode) {
775 case TCODE_WRITE_QUADLET_REQUEST:
776 case TCODE_READ_QUADLET_RESPONSE:
32b46093 777 p.header[3] = (__force __u32) buffer[3];
2639a6fb 778 p.header_length = 16;
32b46093 779 p.payload_length = 0;
2639a6fb
KH		 780 break;
781
2639a6fb 782 case TCODE_READ_BLOCK_REQUEST :
11bf20ad 783 p.header[3] = cond_le32_to_cpu(buffer[3]);
32b46093
KH		 784 p.header_length = 16;
785 p.payload_length = 0;
786 break;
787
788 case TCODE_WRITE_BLOCK_REQUEST:
2639a6fb
KH		 789 case TCODE_READ_BLOCK_RESPONSE:
790 case TCODE_LOCK_REQUEST:
791 case TCODE_LOCK_RESPONSE:
11bf20ad 792 p.header[3] = cond_le32_to_cpu(buffer[3]);
2639a6fb 793 p.header_length = 16;
32b46093 794 p.payload_length = p.header[3] >> 16;
7a39d8b8
CL		 795 if (p.payload_length > MAX_ASYNC_PAYLOAD) {
796 ar_context_abort(ctx, "invalid packet length");
797 return NULL;
798 }
2639a6fb
KH		 799 break;
800
801 case TCODE_WRITE_RESPONSE:
802 case TCODE_READ_QUADLET_REQUEST:
32b46093 803 case OHCI_TCODE_PHY_PACKET:
2639a6fb 804 p.header_length = 12;
32b46093 805 p.payload_length = 0;
2639a6fb 806 break;
ccff9629
SR		 807
808 default:
7a39d8b8
CL		 809 ar_context_abort(ctx, "invalid tcode");
810 return NULL;
2639a6fb 811 }
ed568912 812
32b46093
KH		 813 p.payload = (void *) buffer + p.header_length;
814
815 /* FIXME: What to do about evt_* errors? */
816 length = (p.header_length + p.payload_length + 3) / 4;
11bf20ad 817 status = cond_le32_to_cpu(buffer[length]);
43286568 818 evt = (status >> 16) & 0x1f;
32b46093 819
43286568 820 p.ack = evt - 16;
32b46093
KH		 821 p.speed = (status >> 21) & 0x7;
822 p.timestamp = status & 0xffff;
823 p.generation = ohci->request_generation;
ed568912 824
43286568 825 log_ar_at_event('R', p.speed, p.header, evt);
ad3c0fe8 826
c781c06d 827 /*
a4dc090b
SR		 828 * Several controllers, notably from NEC and VIA, forget to
829 * write ack_complete status at PHY packet reception.
830 */
831 if (evt == OHCI1394_evt_no_status &&
832 (p.header[0] & 0xff) == (OHCI1394_phy_tcode << 4))
833 p.ack = ACK_COMPLETE;
834
835 /*
836 * The OHCI bus reset handler synthesizes a PHY packet with
ed568912
KH		 837 * the new generation number when a bus reset happens (see
838 * section 8.4.2.3). This helps us determine when a request
839 * was received and make sure we send the response in the same
840 * generation. We only need this for requests; for responses
841 * we use the unique tlabel for finding the matching
c781c06d 842 * request.
d34316a4
SR		 843 *
844 * Alas some chips sometimes emit bus reset packets with a
845 * wrong generation. We set the correct generation for these
846 * at a slightly incorrect time (in bus_reset_tasklet).
c781c06d 847 */
d34316a4 848 if (evt == OHCI1394_evt_bus_reset) {
4a635593 849 if (!(ohci->quirks & QUIRK_RESET_PACKET))
d34316a4
SR		 850 ohci->request_generation = (p.header[2] >> 16) & 0xff;
851 } else if (ctx == &ohci->ar_request_ctx) {
2639a6fb 852 fw_core_handle_request(&ohci->card, &p);
d34316a4 853 } else {
2639a6fb 854 fw_core_handle_response(&ohci->card, &p);
d34316a4 855 }
ed568912 856
32b46093
KH		 857 return buffer + length + 1;
858}
ed568912 859
7a39d8b8
CL		 860static void *handle_ar_packets(struct ar_context *ctx, void *p, void *end)
861{
862 void *next;
863
864 while (p < end) {
865 next = handle_ar_packet(ctx, p);
866 if (!next)
867 return p;
868 p = next;
869 }
870
871 return p;
872}
873
874static void ar_recycle_buffers(struct ar_context *ctx, unsigned int end_buffer)
875{
876 unsigned int i;
877
878 i = ar_first_buffer_index(ctx);
879 while (i != end_buffer) {
880 dma_sync_single_for_device(ctx->ohci->card.device,
881 ar_buffer_bus(ctx, i),
882 PAGE_SIZE, DMA_FROM_DEVICE);
883 ar_context_link_page(ctx, i);
884 i = ar_next_buffer_index(i);
885 }
886}
887
32b46093
KH		 888static void ar_context_tasklet(unsigned long data)
889{
890 struct ar_context *ctx = (struct ar_context *)data;
7a39d8b8
CL		 891 unsigned int end_buffer_index, end_buffer_offset;
892 void *p, *end;
32b46093 893
7a39d8b8
CL		 894 p = ctx->pointer;
895 if (!p)
896 return;
32b46093 897
7a39d8b8
CL		 898 end_buffer_index = ar_search_last_active_buffer(ctx,
899 &end_buffer_offset);
900 ar_sync_buffers_for_cpu(ctx, end_buffer_index, end_buffer_offset);
901 end = ctx->buffer + end_buffer_index * PAGE_SIZE + end_buffer_offset;
32b46093 902
7a39d8b8 903 if (end_buffer_index < ar_first_buffer_index(ctx)) {
c781c06d 904 /*
7a39d8b8
CL		 905 * The filled part of the overall buffer wraps around; handle
906 * all packets up to the buffer end here. If the last packet
907 * wraps around, its tail will be visible after the buffer end
908 * because the buffer start pages are mapped there again.
c781c06d 909 */
7a39d8b8
CL		 910 void *buffer_end = ctx->buffer + AR_BUFFERS * PAGE_SIZE;
911 p = handle_ar_packets(ctx, p, buffer_end);
912 if (p < buffer_end)
913 goto error;
914 /* adjust p to point back into the actual buffer */
915 p -= AR_BUFFERS * PAGE_SIZE;
916 }
32b46093 917
7a39d8b8
CL		 918 p = handle_ar_packets(ctx, p, end);
919 if (p != end) {
920 if (p > end)
921 ar_context_abort(ctx, "inconsistent descriptor");
922 goto error;
923 }
32b46093 924
7a39d8b8
CL		 925 ctx->pointer = p;
926 ar_recycle_buffers(ctx, end_buffer_index);
32b46093 927
7a39d8b8 928 return;
a1f805e5 929
7a39d8b8
CL		 930error:
931 ctx->pointer = NULL;
ed568912
KH		 932}
933
ec766a79
CL		 934static int ar_context_init(struct ar_context *ctx, struct fw_ohci *ohci,
935 unsigned int descriptors_offset, u32 regs)
ed568912 936{
7a39d8b8
CL		 937 unsigned int i;
938 dma_addr_t dma_addr;
939 struct page *pages[AR_BUFFERS + AR_WRAPAROUND_PAGES];
940 struct descriptor *d;
ed568912 941
72e318e0
KH		 942 ctx->regs = regs;
943 ctx->ohci = ohci;
ed568912
KH		 944 tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx);
945
7a39d8b8
CL		 946 for (i = 0; i < AR_BUFFERS; i++) {
947 ctx->pages[i] = alloc_page(GFP_KERNEL | GFP_DMA32);
948 if (!ctx->pages[i])
949 goto out_of_memory;
950 dma_addr = dma_map_page(ohci->card.device, ctx->pages[i],
951 0, PAGE_SIZE, DMA_FROM_DEVICE);
952 if (dma_mapping_error(ohci->card.device, dma_addr)) {
953 __free_page(ctx->pages[i]);
954 ctx->pages[i] = NULL;
955 goto out_of_memory;
956 }
957 set_page_private(ctx->pages[i], dma_addr);
958 }
959
960 for (i = 0; i < AR_BUFFERS; i++)
961 pages[i] = ctx->pages[i];
962 for (i = 0; i < AR_WRAPAROUND_PAGES; i++)
963 pages[AR_BUFFERS + i] = ctx->pages[i];
964 ctx->buffer = vm_map_ram(pages, AR_BUFFERS + AR_WRAPAROUND_PAGES,
965 -1, PAGE_KERNEL_RO);
966 if (!ctx->buffer)
967 goto out_of_memory;
968
ec766a79
CL		 969 ctx->descriptors = ohci->misc_buffer + descriptors_offset;
970 ctx->descriptors_bus = ohci->misc_buffer_bus + descriptors_offset;
7a39d8b8
CL		 971
972 for (i = 0; i < AR_BUFFERS; i++) {
973 d = &ctx->descriptors[i];
974 d->req_count = cpu_to_le16(PAGE_SIZE);
975 d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
976 DESCRIPTOR_STATUS |
977 DESCRIPTOR_BRANCH_ALWAYS);
978 d->data_address = cpu_to_le32(ar_buffer_bus(ctx, i));
979 d->branch_address = cpu_to_le32(ctx->descriptors_bus +
980 ar_next_buffer_index(i) * sizeof(struct descriptor));
981 }
32b46093 982
2aef469a 983 return 0;
7a39d8b8
CL		 984
985out_of_memory:
986 ar_context_release(ctx);
987
988 return -ENOMEM;
2aef469a
KH		 989}
990
991static void ar_context_run(struct ar_context *ctx)
992{
7a39d8b8
CL		 993 unsigned int i;
994
995 for (i = 0; i < AR_BUFFERS; i++)
996 ar_context_link_page(ctx, i);
2aef469a 997
7a39d8b8 998 ctx->pointer = ctx->buffer;
2aef469a 999
7a39d8b8 1000 reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ctx->descriptors_bus | 1);
a77754a7 1001 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN);
32b46093 1002 flush_writes(ctx->ohci);
ed568912 1003}
373b2edd 1004
53dca511 1005static struct descriptor *find_branch_descriptor(struct descriptor *d, int z)
a186b4a6
JW		 1006{
1007 int b, key;
1008
1009 b = (le16_to_cpu(d->control) & DESCRIPTOR_BRANCH_ALWAYS) >> 2;
1010 key = (le16_to_cpu(d->control) & DESCRIPTOR_KEY_IMMEDIATE) >> 8;
1011
1012 /* figure out which descriptor the branch address goes in */
1013 if (z == 2 && (b == 3 || key == 2))
1014 return d;
1015 else
1016 return d + z - 1;
1017}
1018
30200739
KH		 1019static void context_tasklet(unsigned long data)
1020{
1021 struct context *ctx = (struct context *) data;
30200739
KH		 1022 struct descriptor *d, *last;
1023 u32 address;
1024 int z;
fe5ca634 1025 struct descriptor_buffer *desc;
30200739 1026
fe5ca634
DM		 1027 desc = list_entry(ctx->buffer_list.next,
1028 struct descriptor_buffer, list);
1029 last = ctx->last;
30200739 1030 while (last->branch_address != 0) {
fe5ca634 1031 struct descriptor_buffer *old_desc = desc;
30200739
KH		 1032 address = le32_to_cpu(last->branch_address);
1033 z = address & 0xf;
fe5ca634
DM		 1034 address &= ~0xf;
1035
1036 /* If the branch address points to a buffer outside of the
1037 * current buffer, advance to the next buffer. */
1038 if (address < desc->buffer_bus ||
1039 address >= desc->buffer_bus + desc->used)
1040 desc = list_entry(desc->list.next,
1041 struct descriptor_buffer, list);
1042 d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d);
a186b4a6 1043 last = find_branch_descriptor(d, z);
30200739
KH		 1044
1045 if (!ctx->callback(ctx, d, last))
1046 break;
1047
fe5ca634
DM		 1048 if (old_desc != desc) {
1049 /* If we've advanced to the next buffer, move the
1050 * previous buffer to the free list. */
1051 unsigned long flags;
1052 old_desc->used = 0;
1053 spin_lock_irqsave(&ctx->ohci->lock, flags);
1054 list_move_tail(&old_desc->list, &ctx->buffer_list);
1055 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1056 }
1057 ctx->last = last;
30200739
KH		 1058 }
1059}
1060
fe5ca634
DM		 1061/*
1062 * Allocate a new buffer and add it to the list of free buffers for this
1063 * context. Must be called with ohci->lock held.
1064 */
53dca511 1065static int context_add_buffer(struct context *ctx)
fe5ca634
DM		 1066{
1067 struct descriptor_buffer *desc;
f5101d58 1068 dma_addr_t uninitialized_var(bus_addr);
fe5ca634
DM		 1069 int offset;
1070
1071 /*
1072 * 16MB of descriptors should be far more than enough for any DMA
1073 * program. This will catch run-away userspace or DoS attacks.
1074 */
1075 if (ctx->total_allocation >= 16*1024*1024)
1076 return -ENOMEM;
1077
1078 desc = dma_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE,
1079 &bus_addr, GFP_ATOMIC);
1080 if (!desc)
1081 return -ENOMEM;
1082
1083 offset = (void *)&desc->buffer - (void *)desc;
1084 desc->buffer_size = PAGE_SIZE - offset;
1085 desc->buffer_bus = bus_addr + offset;
1086 desc->used = 0;
1087
1088 list_add_tail(&desc->list, &ctx->buffer_list);
1089 ctx->total_allocation += PAGE_SIZE;
1090
1091 return 0;
1092}
1093
53dca511
SR		 1094static int context_init(struct context *ctx, struct fw_ohci *ohci,
1095 u32 regs, descriptor_callback_t callback)
30200739
KH		 1096{
1097 ctx->ohci = ohci;
1098 ctx->regs = regs;
fe5ca634
DM		 1099 ctx->total_allocation = 0;
1100
1101 INIT_LIST_HEAD(&ctx->buffer_list);
1102 if (context_add_buffer(ctx) < 0)
30200739
KH		 1103 return -ENOMEM;
1104
fe5ca634
DM		 1105 ctx->buffer_tail = list_entry(ctx->buffer_list.next,
1106 struct descriptor_buffer, list);
1107
30200739
KH		 1108 tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx);
1109 ctx->callback = callback;
1110
c781c06d
KH		 1111 /*
1112 * We put a dummy descriptor in the buffer that has a NULL
30200739 1113 * branch address and looks like it's been sent. That way we
fe5ca634 1114 * have a descriptor to append DMA programs to.
c781c06d 1115 */
fe5ca634
DM		 1116 memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer));
1117 ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST);
1118 ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011);
1119 ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer);
1120 ctx->last = ctx->buffer_tail->buffer;
1121 ctx->prev = ctx->buffer_tail->buffer;
30200739
KH		 1122
1123 return 0;
1124}
1125
53dca511 1126static void context_release(struct context *ctx)
30200739
KH		 1127{
1128 struct fw_card *card = &ctx->ohci->card;
fe5ca634 1129 struct descriptor_buffer *desc, *tmp;
30200739 1130
fe5ca634
DM		 1131 list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list)
1132 dma_free_coherent(card->device, PAGE_SIZE, desc,
1133 desc->buffer_bus -
1134 ((void *)&desc->buffer - (void *)desc));
30200739
KH		 1135}
1136
fe5ca634 1137/* Must be called with ohci->lock held */
53dca511
SR		 1138static struct descriptor *context_get_descriptors(struct context *ctx,
1139 int z, dma_addr_t *d_bus)
30200739 1140{
fe5ca634
DM		 1141 struct descriptor *d = NULL;
1142 struct descriptor_buffer *desc = ctx->buffer_tail;
1143
1144 if (z * sizeof(*d) > desc->buffer_size)
1145 return NULL;
1146
1147 if (z * sizeof(*d) > desc->buffer_size - desc->used) {
1148 /* No room for the descriptor in this buffer, so advance to the
1149 * next one. */
30200739 1150
fe5ca634
DM		 1151 if (desc->list.next == &ctx->buffer_list) {
1152 /* If there is no free buffer next in the list,
1153 * allocate one. */
1154 if (context_add_buffer(ctx) < 0)
1155 return NULL;
1156 }
1157 desc = list_entry(desc->list.next,
1158 struct descriptor_buffer, list);
1159 ctx->buffer_tail = desc;
1160 }
30200739 1161
fe5ca634 1162 d = desc->buffer + desc->used / sizeof(*d);
2d826cc5 1163 memset(d, 0, z * sizeof(*d));
fe5ca634 1164 *d_bus = desc->buffer_bus + desc->used;
30200739
KH		 1165
1166 return d;
1167}
1168
295e3feb 1169static void context_run(struct context *ctx, u32 extra)
30200739
KH		 1170{
1171 struct fw_ohci *ohci = ctx->ohci;
dd23736e 1172 ctx->active = true;
30200739 1173
a77754a7 1174 reg_write(ohci, COMMAND_PTR(ctx->regs),
fe5ca634 1175 le32_to_cpu(ctx->last->branch_address));
a77754a7
KH		 1176 reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0);
1177 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra);
386a4153 1178 ctx->running = true;
30200739
KH		 1179 flush_writes(ohci);
1180}
1181
1182static void context_append(struct context *ctx,
1183 struct descriptor *d, int z, int extra)
1184{
1185 dma_addr_t d_bus;
fe5ca634 1186 struct descriptor_buffer *desc = ctx->buffer_tail;
30200739 1187
fe5ca634 1188 d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d);
30200739 1189
fe5ca634 1190 desc->used += (z + extra) * sizeof(*d);
071595eb
SR		 1191
1192 wmb(); /* finish init of new descriptors before branch_address update */
fe5ca634
DM		 1193 ctx->prev->branch_address = cpu_to_le32(d_bus | z);
1194 ctx->prev = find_branch_descriptor(d, z);
30200739 1195
a77754a7 1196 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
30200739
KH		 1197 flush_writes(ctx->ohci);
1198}
1199
1200static void context_stop(struct context *ctx)
1201{
1202 u32 reg;
b8295668 1203 int i;
30200739 1204
dd23736e 1205 ctx->active = false;
a77754a7 1206 reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
386a4153 1207 ctx->running = false;
b8295668 1208 flush_writes(ctx->ohci);
30200739 1209
b8295668 1210 for (i = 0; i < 10; i++) {
a77754a7 1211 reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
b8295668 1212 if ((reg & CONTEXT_ACTIVE) == 0)
b0068549 1213 return;
b8295668 1214
b980f5a2 1215 mdelay(1);
b8295668 1216 }
b0068549 1217 fw_error("Error: DMA context still active (0x%08x)\n", reg);
30200739 1218}
ed568912 1219
f319b6a0
KH		 1220struct driver_data {
1221 struct fw_packet *packet;
1222};
ed568912 1223
c781c06d
KH		 1224/*
1225 * This function apppends a packet to the DMA queue for transmission.
f319b6a0 1226 * Must always be called with the ochi->lock held to ensure proper
c781c06d
KH		 1227 * generation handling and locking around packet queue manipulation.
1228 */
53dca511
SR		 1229static int at_context_queue_packet(struct context *ctx,
1230 struct fw_packet *packet)
ed568912 1231{
ed568912 1232 struct fw_ohci *ohci = ctx->ohci;
4b6d51ec 1233 dma_addr_t d_bus, uninitialized_var(payload_bus);
f319b6a0
KH		 1234 struct driver_data *driver_data;
1235 struct descriptor *d, *last;
1236 __le32 *header;
ed568912
KH		 1237 int z, tcode;
1238
f319b6a0
KH		 1239 d = context_get_descriptors(ctx, 4, &d_bus);
1240 if (d == NULL) {
1241 packet->ack = RCODE_SEND_ERROR;
1242 return -1;
ed568912
KH		 1243 }
1244
a77754a7 1245 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
f319b6a0
KH		 1246 d[0].res_count = cpu_to_le16(packet->timestamp);
1247
c781c06d
KH		 1248 /*
1249 * The DMA format for asyncronous link packets is different
ed568912 1250 * from the IEEE1394 layout, so shift the fields around
5b06db16 1251 * accordingly.
c781c06d 1252 */
f319b6a0 1253
5b06db16 1254 tcode = (packet->header[0] >> 4) & 0x0f;
f319b6a0 1255 header = (__le32 *) &d[1];
5b06db16
CL		 1256 switch (tcode) {
1257 case TCODE_WRITE_QUADLET_REQUEST:
1258 case TCODE_WRITE_BLOCK_REQUEST:
1259 case TCODE_WRITE_RESPONSE:
1260 case TCODE_READ_QUADLET_REQUEST:
1261 case TCODE_READ_BLOCK_REQUEST:
1262 case TCODE_READ_QUADLET_RESPONSE:
1263 case TCODE_READ_BLOCK_RESPONSE:
1264 case TCODE_LOCK_REQUEST:
1265 case TCODE_LOCK_RESPONSE:
f319b6a0
KH		 1266 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1267 (packet->speed << 16));
1268 header[1] = cpu_to_le32((packet->header[1] & 0xffff) |
1269 (packet->header[0] & 0xffff0000));
1270 header[2] = cpu_to_le32(packet->header[2]);
ed568912 1271
ed568912 1272 if (TCODE_IS_BLOCK_PACKET(tcode))
f319b6a0 1273 header[3] = cpu_to_le32(packet->header[3]);
ed568912 1274 else
f319b6a0
KH		 1275 header[3] = (__force __le32) packet->header[3];
1276
1277 d[0].req_count = cpu_to_le16(packet->header_length);
f8c2287c
JF		 1278 break;
1279
5b06db16 1280 case TCODE_LINK_INTERNAL:
f319b6a0
KH		 1281 header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) |
1282 (packet->speed << 16));
5b06db16
CL		 1283 header[1] = cpu_to_le32(packet->header[1]);
1284 header[2] = cpu_to_le32(packet->header[2]);
f319b6a0 1285 d[0].req_count = cpu_to_le16(12);
cc550216 1286
5b06db16 1287 if (is_ping_packet(&packet->header[1]))
cc550216 1288 d[0].control |= cpu_to_le16(DESCRIPTOR_PING);
f8c2287c
JF		 1289 break;
1290
5b06db16 1291 case TCODE_STREAM_DATA:
f8c2287c
JF		 1292 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1293 (packet->speed << 16));
1294 header[1] = cpu_to_le32(packet->header[0] & 0xffff0000);
1295 d[0].req_count = cpu_to_le16(8);
1296 break;
1297
1298 default:
1299 /* BUG(); */
1300 packet->ack = RCODE_SEND_ERROR;
1301 return -1;
ed568912
KH		 1302 }
1303
f319b6a0
KH		 1304 driver_data = (struct driver_data *) &d[3];
1305 driver_data->packet = packet;
20d11673 1306 packet->driver_data = driver_data;
a186b4a6 1307
f319b6a0
KH		 1308 if (packet->payload_length > 0) {
1309 payload_bus =
1310 dma_map_single(ohci->card.device, packet->payload,
1311 packet->payload_length, DMA_TO_DEVICE);
8d8bb39b 1312 if (dma_mapping_error(ohci->card.device, payload_bus)) {
f319b6a0
KH		 1313 packet->ack = RCODE_SEND_ERROR;
1314 return -1;
1315 }
19593ffd
SR		 1316 packet->payload_bus = payload_bus;
1317 packet->payload_mapped = true;
f319b6a0
KH		 1318
1319 d[2].req_count = cpu_to_le16(packet->payload_length);
1320 d[2].data_address = cpu_to_le32(payload_bus);
1321 last = &d[2];
1322 z = 3;
ed568912 1323 } else {
f319b6a0
KH		 1324 last = &d[0];
1325 z = 2;
ed568912 1326 }
ed568912 1327
a77754a7
KH		 1328 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
1329 DESCRIPTOR_IRQ_ALWAYS |
1330 DESCRIPTOR_BRANCH_ALWAYS);
ed568912 1331
76f73ca1
JW		 1332 /*
1333 * If the controller and packet generations don't match, we need to
1334 * bail out and try again. If IntEvent.busReset is set, the AT context
1335 * is halted, so appending to the context and trying to run it is
1336 * futile. Most controllers do the right thing and just flush the AT
1337 * queue (per section 7.2.3.2 of the OHCI 1.1 specification), but
1338 * some controllers (like a JMicron JMB381 PCI-e) misbehave and wind
1339 * up stalling out. So we just bail out in software and try again
1340 * later, and everyone is happy.
78dec56d
SR		 1341 * FIXME: Test of IntEvent.busReset may no longer be necessary since we
1342 * flush AT queues in bus_reset_tasklet.
76f73ca1
JW		 1343 * FIXME: Document how the locking works.
1344 */
1345 if (ohci->generation != packet->generation ||
1346 reg_read(ohci, OHCI1394_IntEventSet) & OHCI1394_busReset) {
19593ffd 1347 if (packet->payload_mapped)
ab88ca48
SR		 1348 dma_unmap_single(ohci->card.device, payload_bus,
1349 packet->payload_length, DMA_TO_DEVICE);
f319b6a0
KH		 1350 packet->ack = RCODE_GENERATION;
1351 return -1;
1352 }
1353
1354 context_append(ctx, d, z, 4 - z);
ed568912 1355
386a4153 1356 if (!ctx->running)
f319b6a0
KH		 1357 context_run(ctx, 0);
1358
1359 return 0;
ed568912
KH		 1360}
1361
82b662dc
CL		 1362static void at_context_flush(struct context *ctx)
1363{
1364 tasklet_disable(&ctx->tasklet);
1365
1366 ctx->flushing = true;
1367 context_tasklet((unsigned long)ctx);
1368 ctx->flushing = false;
1369
1370 tasklet_enable(&ctx->tasklet);
1371}
1372
f319b6a0
KH		 1373static int handle_at_packet(struct context *context,
1374 struct descriptor *d,
1375 struct descriptor *last)
ed568912 1376{
f319b6a0 1377 struct driver_data *driver_data;
ed568912 1378 struct fw_packet *packet;
f319b6a0 1379 struct fw_ohci *ohci = context->ohci;
ed568912
KH		 1380 int evt;
1381
82b662dc 1382 if (last->transfer_status == 0 && !context->flushing)
f319b6a0
KH		 1383 /* This descriptor isn't done yet, stop iteration. */
1384 return 0;
ed568912 1385
f319b6a0
KH		 1386 driver_data = (struct driver_data *) &d[3];
1387 packet = driver_data->packet;
1388 if (packet == NULL)
1389 /* This packet was cancelled, just continue. */
1390 return 1;
730c32f5 1391
19593ffd 1392 if (packet->payload_mapped)
1d1dc5e8 1393 dma_unmap_single(ohci->card.device, packet->payload_bus,
ed568912 1394 packet->payload_length, DMA_TO_DEVICE);
ed568912 1395
f319b6a0
KH		 1396 evt = le16_to_cpu(last->transfer_status) & 0x1f;
1397 packet->timestamp = le16_to_cpu(last->res_count);
ed568912 1398
ad3c0fe8
SR		 1399 log_ar_at_event('T', packet->speed, packet->header, evt);
1400
f319b6a0
KH		 1401 switch (evt) {
1402 case OHCI1394_evt_timeout:
1403 /* Async response transmit timed out. */
1404 packet->ack = RCODE_CANCELLED;
1405 break;
ed568912 1406
f319b6a0 1407 case OHCI1394_evt_flushed:
c781c06d
KH		 1408 /*
1409 * The packet was flushed should give same error as
1410 * when we try to use a stale generation count.
1411 */
f319b6a0
KH		 1412 packet->ack = RCODE_GENERATION;
1413 break;
ed568912 1414
f319b6a0 1415 case OHCI1394_evt_missing_ack:
82b662dc
CL		 1416 if (context->flushing)
1417 packet->ack = RCODE_GENERATION;
1418 else {
1419 /*
1420 * Using a valid (current) generation count, but the
1421 * node is not on the bus or not sending acks.
1422 */
1423 packet->ack = RCODE_NO_ACK;
1424 }
f319b6a0 1425 break;
ed568912 1426
f319b6a0
KH		 1427 case ACK_COMPLETE + 0x10:
1428 case ACK_PENDING + 0x10:
1429 case ACK_BUSY_X + 0x10:
1430 case ACK_BUSY_A + 0x10:
1431 case ACK_BUSY_B + 0x10:
1432 case ACK_DATA_ERROR + 0x10:
1433 case ACK_TYPE_ERROR + 0x10:
1434 packet->ack = evt - 0x10;
1435 break;
ed568912 1436
82b662dc
CL		 1437 case OHCI1394_evt_no_status:
1438 if (context->flushing) {
1439 packet->ack = RCODE_GENERATION;
1440 break;
1441 }
1442 /* fall through */
1443
f319b6a0
KH		 1444 default:
1445 packet->ack = RCODE_SEND_ERROR;
1446 break;
1447 }
ed568912 1448
f319b6a0 1449 packet->callback(packet, &ohci->card, packet->ack);
ed568912 1450
f319b6a0 1451 return 1;
ed568912
KH		 1452}
1453
a77754a7
KH		 1454#define HEADER_GET_DESTINATION(q) (((q) >> 16) & 0xffff)
1455#define HEADER_GET_TCODE(q) (((q) >> 4) & 0x0f)
1456#define HEADER_GET_OFFSET_HIGH(q) (((q) >> 0) & 0xffff)
1457#define HEADER_GET_DATA_LENGTH(q) (((q) >> 16) & 0xffff)
1458#define HEADER_GET_EXTENDED_TCODE(q) (((q) >> 0) & 0xffff)
93c4cceb 1459
53dca511
SR		 1460static void handle_local_rom(struct fw_ohci *ohci,
1461 struct fw_packet *packet, u32 csr)
93c4cceb
KH		 1462{
1463 struct fw_packet response;
1464 int tcode, length, i;
1465
a77754a7 1466 tcode = HEADER_GET_TCODE(packet->header[0]);
93c4cceb 1467 if (TCODE_IS_BLOCK_PACKET(tcode))
a77754a7 1468 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
93c4cceb
KH		 1469 else
1470 length = 4;
1471
1472 i = csr - CSR_CONFIG_ROM;
1473 if (i + length > CONFIG_ROM_SIZE) {
1474 fw_fill_response(&response, packet->header,
1475 RCODE_ADDRESS_ERROR, NULL, 0);
1476 } else if (!TCODE_IS_READ_REQUEST(tcode)) {
1477 fw_fill_response(&response, packet->header,
1478 RCODE_TYPE_ERROR, NULL, 0);
1479 } else {
1480 fw_fill_response(&response, packet->header, RCODE_COMPLETE,
1481 (void *) ohci->config_rom + i, length);
1482 }
1483
1484 fw_core_handle_response(&ohci->card, &response);
1485}
1486
53dca511
SR		 1487static void handle_local_lock(struct fw_ohci *ohci,
1488 struct fw_packet *packet, u32 csr)
93c4cceb
KH		 1489{
1490 struct fw_packet response;
e1393667 1491 int tcode, length, ext_tcode, sel, try;
93c4cceb
KH		 1492 __be32 *payload, lock_old;
1493 u32 lock_arg, lock_data;
1494
a77754a7
KH		 1495 tcode = HEADER_GET_TCODE(packet->header[0]);
1496 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
93c4cceb 1497 payload = packet->payload;
a77754a7 1498 ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]);
93c4cceb
KH		 1499
1500 if (tcode == TCODE_LOCK_REQUEST &&
1501 ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) {
1502 lock_arg = be32_to_cpu(payload[0]);
1503 lock_data = be32_to_cpu(payload[1]);
1504 } else if (tcode == TCODE_READ_QUADLET_REQUEST) {
1505 lock_arg = 0;
1506 lock_data = 0;
1507 } else {
1508 fw_fill_response(&response, packet->header,
1509 RCODE_TYPE_ERROR, NULL, 0);
1510 goto out;
1511 }
1512
1513 sel = (csr - CSR_BUS_MANAGER_ID) / 4;
1514 reg_write(ohci, OHCI1394_CSRData, lock_data);
1515 reg_write(ohci, OHCI1394_CSRCompareData, lock_arg);
1516 reg_write(ohci, OHCI1394_CSRControl, sel);
1517
e1393667
CL		 1518 for (try = 0; try < 20; try++)
1519 if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000) {
1520 lock_old = cpu_to_be32(reg_read(ohci,
1521 OHCI1394_CSRData));
1522 fw_fill_response(&response, packet->header,
1523 RCODE_COMPLETE,
1524 &lock_old, sizeof(lock_old));
1525 goto out;
1526 }
1527
1528 fw_error("swap not done (CSR lock timeout)\n");
1529 fw_fill_response(&response, packet->header, RCODE_BUSY, NULL, 0);
93c4cceb 1530
93c4cceb
KH		 1531 out:
1532 fw_core_handle_response(&ohci->card, &response);
1533}
1534
53dca511 1535static void handle_local_request(struct context *ctx, struct fw_packet *packet)
93c4cceb 1536{
2608203d 1537 u64 offset, csr;
93c4cceb 1538
473d28c7
KH		 1539 if (ctx == &ctx->ohci->at_request_ctx) {
1540 packet->ack = ACK_PENDING;
1541 packet->callback(packet, &ctx->ohci->card, packet->ack);
1542 }
93c4cceb
KH		 1543
1544 offset =
1545 ((unsigned long long)
a77754a7 1546 HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) |
93c4cceb
KH		 1547 packet->header[2];
1548 csr = offset - CSR_REGISTER_BASE;
1549
1550 /* Handle config rom reads. */
1551 if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END)
1552 handle_local_rom(ctx->ohci, packet, csr);
1553 else switch (csr) {
1554 case CSR_BUS_MANAGER_ID:
1555 case CSR_BANDWIDTH_AVAILABLE:
1556 case CSR_CHANNELS_AVAILABLE_HI:
1557 case CSR_CHANNELS_AVAILABLE_LO:
1558 handle_local_lock(ctx->ohci, packet, csr);
1559 break;
1560 default:
1561 if (ctx == &ctx->ohci->at_request_ctx)
1562 fw_core_handle_request(&ctx->ohci->card, packet);
1563 else
1564 fw_core_handle_response(&ctx->ohci->card, packet);
1565 break;
1566 }
473d28c7
KH		 1567
1568 if (ctx == &ctx->ohci->at_response_ctx) {
1569 packet->ack = ACK_COMPLETE;
1570 packet->callback(packet, &ctx->ohci->card, packet->ack);
1571 }
93c4cceb 1572}
e636fe25 1573
53dca511 1574static void at_context_transmit(struct context *ctx, struct fw_packet *packet)
ed568912 1575{
ed568912 1576 unsigned long flags;
2dbd7d7e 1577 int ret;
ed568912
KH		 1578
1579 spin_lock_irqsave(&ctx->ohci->lock, flags);
1580
a77754a7 1581 if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id &&
e636fe25 1582 ctx->ohci->generation == packet->generation) {
93c4cceb
KH		 1583 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1584 handle_local_request(ctx, packet);
1585 return;
e636fe25 1586 }
ed568912 1587
2dbd7d7e 1588 ret = at_context_queue_packet(ctx, packet);
ed568912
KH		 1589 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1590
2dbd7d7e 1591 if (ret < 0)
f319b6a0 1592 packet->callback(packet, &ctx->ohci->card, packet->ack);
a186b4a6 1593
ed568912
KH		 1594}
1595
a48777e0
CL		 1596static u32 cycle_timer_ticks(u32 cycle_timer)
1597{
1598 u32 ticks;
1599
1600 ticks = cycle_timer & 0xfff;
1601 ticks += 3072 * ((cycle_timer >> 12) & 0x1fff);
1602 ticks += (3072 * 8000) * (cycle_timer >> 25);
1603
1604 return ticks;
1605}
1606
1607/*
1608 * Some controllers exhibit one or more of the following bugs when updating the
1609 * iso cycle timer register:
1610 * - When the lowest six bits are wrapping around to zero, a read that happens
1611 * at the same time will return garbage in the lowest ten bits.
1612 * - When the cycleOffset field wraps around to zero, the cycleCount field is
1613 * not incremented for about 60 ns.
1614 * - Occasionally, the entire register reads zero.
1615 *
1616 * To catch these, we read the register three times and ensure that the
1617 * difference between each two consecutive reads is approximately the same, i.e.
1618 * less than twice the other. Furthermore, any negative difference indicates an
1619 * error. (A PCI read should take at least 20 ticks of the 24.576 MHz timer to
1620 * execute, so we have enough precision to compute the ratio of the differences.)
1621 */
1622static u32 get_cycle_time(struct fw_ohci *ohci)
1623{
1624 u32 c0, c1, c2;
1625 u32 t0, t1, t2;
1626 s32 diff01, diff12;
1627 int i;
1628
1629 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1630
1631 if (ohci->quirks & QUIRK_CYCLE_TIMER) {
1632 i = 0;
1633 c1 = c2;
1634 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1635 do {
1636 c0 = c1;
1637 c1 = c2;
1638 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1639 t0 = cycle_timer_ticks(c0);
1640 t1 = cycle_timer_ticks(c1);
1641 t2 = cycle_timer_ticks(c2);
1642 diff01 = t1 - t0;
1643 diff12 = t2 - t1;
1644 } while ((diff01 <= 0 || diff12 <= 0 ||
1645 diff01 / diff12 >= 2 || diff12 / diff01 >= 2)
1646 && i++ < 20);
1647 }
1648
1649 return c2;
1650}
1651
1652/*
1653 * This function has to be called at least every 64 seconds. The bus_time
1654 * field stores not only the upper 25 bits of the BUS_TIME register but also
1655 * the most significant bit of the cycle timer in bit 6 so that we can detect
1656 * changes in this bit.
1657 */
1658static u32 update_bus_time(struct fw_ohci *ohci)
1659{
1660 u32 cycle_time_seconds = get_cycle_time(ohci) >> 25;
1661
1662 if ((ohci->bus_time & 0x40) != (cycle_time_seconds & 0x40))
1663 ohci->bus_time += 0x40;
1664
1665 return ohci->bus_time | cycle_time_seconds;
1666}
1667
ed568912
KH		 1668static void bus_reset_tasklet(unsigned long data)
1669{
1670 struct fw_ohci *ohci = (struct fw_ohci *)data;
e636fe25 1671 int self_id_count, i, j, reg;
ed568912
KH		 1672 int generation, new_generation;
1673 unsigned long flags;
4eaff7d6
SR		 1674 void *free_rom = NULL;
1675 dma_addr_t free_rom_bus = 0;
4ffb7a6a 1676 bool is_new_root;
ed568912
KH		 1677
1678 reg = reg_read(ohci, OHCI1394_NodeID);
1679 if (!(reg & OHCI1394_NodeID_idValid)) {
02ff8f8e 1680 fw_notify("node ID not valid, new bus reset in progress\n");
ed568912
KH		 1681 return;
1682 }
02ff8f8e
SR		 1683 if ((reg & OHCI1394_NodeID_nodeNumber) == 63) {
1684 fw_notify("malconfigured bus\n");
1685 return;
1686 }
1687 ohci->node_id = reg & (OHCI1394_NodeID_busNumber |
1688 OHCI1394_NodeID_nodeNumber);
ed568912 1689
4ffb7a6a
CL		 1690 is_new_root = (reg & OHCI1394_NodeID_root) != 0;
1691 if (!(ohci->is_root && is_new_root))
1692 reg_write(ohci, OHCI1394_LinkControlSet,
1693 OHCI1394_LinkControl_cycleMaster);
1694 ohci->is_root = is_new_root;
1695
c8a9a498
SR		 1696 reg = reg_read(ohci, OHCI1394_SelfIDCount);
1697 if (reg & OHCI1394_SelfIDCount_selfIDError) {
1698 fw_notify("inconsistent self IDs\n");
1699 return;
1700 }
c781c06d
KH		 1701 /*
1702 * The count in the SelfIDCount register is the number of
ed568912
KH		 1703 * bytes in the self ID receive buffer. Since we also receive
1704 * the inverted quadlets and a header quadlet, we shift one
c781c06d
KH		 1705 * bit extra to get the actual number of self IDs.
1706 */
928ec5f1
SR		 1707 self_id_count = (reg >> 3) & 0xff;
1708 if (self_id_count == 0 || self_id_count > 252) {
016bf3df
SR		 1709 fw_notify("inconsistent self IDs\n");
1710 return;
1711 }
11bf20ad 1712 generation = (cond_le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff;
ee71c2f9 1713 rmb();
ed568912
KH		 1714
1715 for (i = 1, j = 0; j < self_id_count; i += 2, j++) {
c8a9a498
SR		 1716 if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1]) {
1717 fw_notify("inconsistent self IDs\n");
1718 return;
1719 }
11bf20ad
SR		 1720 ohci->self_id_buffer[j] =
1721 cond_le32_to_cpu(ohci->self_id_cpu[i]);
ed568912 1722 }
ee71c2f9 1723 rmb();
ed568912 1724
c781c06d
KH		 1725 /*
1726 * Check the consistency of the self IDs we just read. The
ed568912
KH		 1727 * problem we face is that a new bus reset can start while we
1728 * read out the self IDs from the DMA buffer. If this happens,
1729 * the DMA buffer will be overwritten with new self IDs and we
1730 * will read out inconsistent data. The OHCI specification
1731 * (section 11.2) recommends a technique similar to
1732 * linux/seqlock.h, where we remember the generation of the
1733 * self IDs in the buffer before reading them out and compare
1734 * it to the current generation after reading them out. If
1735 * the two generations match we know we have a consistent set
c781c06d
KH		 1736 * of self IDs.
1737 */
ed568912
KH		 1738
1739 new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff;
1740 if (new_generation != generation) {
1741 fw_notify("recursive bus reset detected, "
1742 "discarding self ids\n");
1743 return;
1744 }
1745
1746 /* FIXME: Document how the locking works. */
1747 spin_lock_irqsave(&ohci->lock, flags);
1748
82b662dc 1749 ohci->generation = -1; /* prevent AT packet queueing */
f319b6a0
KH		 1750 context_stop(&ohci->at_request_ctx);
1751 context_stop(&ohci->at_response_ctx);
82b662dc
CL		 1752
1753 spin_unlock_irqrestore(&ohci->lock, flags);
1754
78dec56d
SR		 1755 /*
1756 * Per OHCI 1.2 draft, clause 7.2.3.3, hardware may leave unsent
1757 * packets in the AT queues and software needs to drain them.
1758 * Some OHCI 1.1 controllers (JMicron) apparently require this too.
1759 */
82b662dc
CL		 1760 at_context_flush(&ohci->at_request_ctx);
1761 at_context_flush(&ohci->at_response_ctx);
1762
1763 spin_lock_irqsave(&ohci->lock, flags);
1764
1765 ohci->generation = generation;
ed568912
KH		 1766 reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
1767
4a635593 1768 if (ohci->quirks & QUIRK_RESET_PACKET)
d34316a4
SR		 1769 ohci->request_generation = generation;
1770
c781c06d
KH		 1771 /*
1772 * This next bit is unrelated to the AT context stuff but we
ed568912
KH		 1773 * have to do it under the spinlock also. If a new config rom
1774 * was set up before this reset, the old one is now no longer
1775 * in use and we can free it. Update the config rom pointers
1776 * to point to the current config rom and clear the
88393161 1777 * next_config_rom pointer so a new update can take place.
c781c06d 1778 */
ed568912
KH		 1779
1780 if (ohci->next_config_rom != NULL) {
0bd243c4
KH		 1781 if (ohci->next_config_rom != ohci->config_rom) {
1782 free_rom = ohci->config_rom;
1783 free_rom_bus = ohci->config_rom_bus;
1784 }
ed568912
KH		 1785 ohci->config_rom = ohci->next_config_rom;
1786 ohci->config_rom_bus = ohci->next_config_rom_bus;
1787 ohci->next_config_rom = NULL;
1788
c781c06d
KH		 1789 /*
1790 * Restore config_rom image and manually update
ed568912
KH		 1791 * config_rom registers. Writing the header quadlet
1792 * will indicate that the config rom is ready, so we
c781c06d
KH		 1793 * do that last.
1794 */
ed568912
KH		 1795 reg_write(ohci, OHCI1394_BusOptions,
1796 be32_to_cpu(ohci->config_rom[2]));
8e85973e
SR		 1797 ohci->config_rom[0] = ohci->next_header;
1798 reg_write(ohci, OHCI1394_ConfigROMhdr,
1799 be32_to_cpu(ohci->next_header));
ed568912
KH		 1800 }
1801
080de8c2
SR		 1802#ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
1803 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0);
1804 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0);
1805#endif
1806
ed568912
KH		 1807 spin_unlock_irqrestore(&ohci->lock, flags);
1808
4eaff7d6
SR		 1809 if (free_rom)
1810 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1811 free_rom, free_rom_bus);
1812
08ddb2f4
SR		 1813 log_selfids(ohci->node_id, generation,
1814 self_id_count, ohci->self_id_buffer);
ad3c0fe8 1815
e636fe25 1816 fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation,
c8a94ded
SR		 1817 self_id_count, ohci->self_id_buffer,
1818 ohci->csr_state_setclear_abdicate);
1819 ohci->csr_state_setclear_abdicate = false;
ed568912
KH		 1820}
1821
1822static irqreturn_t irq_handler(int irq, void *data)
1823{
1824 struct fw_ohci *ohci = data;
168cf9af 1825 u32 event, iso_event;
ed568912
KH		 1826 int i;
1827
1828 event = reg_read(ohci, OHCI1394_IntEventClear);
1829
a515958d 1830 if (!event || !~event)
ed568912
KH		 1831 return IRQ_NONE;
1832
8327b37b
CL		 1833 /*
1834 * busReset and postedWriteErr must not be cleared yet
1835 * (OHCI 1.1 clauses 7.2.3.2 and 13.2.8.1)
1836 */
1837 reg_write(ohci, OHCI1394_IntEventClear,
1838 event & ~(OHCI1394_busReset | OHCI1394_postedWriteErr));
ad3c0fe8 1839 log_irqs(event);
ed568912
KH		 1840
1841 if (event & OHCI1394_selfIDComplete)
1842 tasklet_schedule(&ohci->bus_reset_tasklet);
1843
1844 if (event & OHCI1394_RQPkt)
1845 tasklet_schedule(&ohci->ar_request_ctx.tasklet);
1846
1847 if (event & OHCI1394_RSPkt)
1848 tasklet_schedule(&ohci->ar_response_ctx.tasklet);
1849
1850 if (event & OHCI1394_reqTxComplete)
1851 tasklet_schedule(&ohci->at_request_ctx.tasklet);
1852
1853 if (event & OHCI1394_respTxComplete)
1854 tasklet_schedule(&ohci->at_response_ctx.tasklet);
1855
2dd5bed5
CL		 1856 if (event & OHCI1394_isochRx) {
1857 iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear);
1858 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event);
1859
1860 while (iso_event) {
1861 i = ffs(iso_event) - 1;
1862 tasklet_schedule(
1863 &ohci->ir_context_list[i].context.tasklet);
1864 iso_event &= ~(1 << i);
1865 }
ed568912
KH		 1866 }
1867
2dd5bed5
CL		 1868 if (event & OHCI1394_isochTx) {
1869 iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear);
1870 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event);
ed568912 1871
2dd5bed5
CL		 1872 while (iso_event) {
1873 i = ffs(iso_event) - 1;
1874 tasklet_schedule(
1875 &ohci->it_context_list[i].context.tasklet);
1876 iso_event &= ~(1 << i);
1877 }
ed568912
KH		 1878 }
1879
75f7832e
JW		 1880 if (unlikely(event & OHCI1394_regAccessFail))
1881 fw_error("Register access failure - "
1882 "please notify linux1394-devel@lists.sf.net\n");
1883
8327b37b
CL		 1884 if (unlikely(event & OHCI1394_postedWriteErr)) {
1885 reg_read(ohci, OHCI1394_PostedWriteAddressHi);
1886 reg_read(ohci, OHCI1394_PostedWriteAddressLo);
1887 reg_write(ohci, OHCI1394_IntEventClear,
1888 OHCI1394_postedWriteErr);
e524f616 1889 fw_error("PCI posted write error\n");
8327b37b 1890 }
e524f616 1891
bb9f2206
SR		 1892 if (unlikely(event & OHCI1394_cycleTooLong)) {
1893 if (printk_ratelimit())
1894 fw_notify("isochronous cycle too long\n");
1895 reg_write(ohci, OHCI1394_LinkControlSet,
1896 OHCI1394_LinkControl_cycleMaster);
1897 }
1898
5ed1f321
JF		 1899 if (unlikely(event & OHCI1394_cycleInconsistent)) {
1900 /*
1901 * We need to clear this event bit in order to make
1902 * cycleMatch isochronous I/O work. In theory we should
1903 * stop active cycleMatch iso contexts now and restart
1904 * them at least two cycles later. (FIXME?)
1905 */
1906 if (printk_ratelimit())
1907 fw_notify("isochronous cycle inconsistent\n");
1908 }
1909
a48777e0
CL		 1910 if (event & OHCI1394_cycle64Seconds) {
1911 spin_lock(&ohci->lock);
1912 update_bus_time(ohci);
1913 spin_unlock(&ohci->lock);
e597e989
CL		 1914 } else
1915 flush_writes(ohci);
a48777e0 1916
ed568912
KH		 1917 return IRQ_HANDLED;
1918}
1919
2aef469a
KH		 1920static int software_reset(struct fw_ohci *ohci)
1921{
1922 int i;
1923
1924 reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
1925
1926 for (i = 0; i < OHCI_LOOP_COUNT; i++) {
1927 if ((reg_read(ohci, OHCI1394_HCControlSet) &
1928 OHCI1394_HCControl_softReset) == 0)
1929 return 0;
1930 msleep(1);
1931 }
1932
1933 return -EBUSY;
1934}
1935
8e85973e
SR		 1936static void copy_config_rom(__be32 *dest, const __be32 *src, size_t length)
1937{
1938 size_t size = length * 4;
1939
1940 memcpy(dest, src, size);
1941 if (size < CONFIG_ROM_SIZE)
1942 memset(&dest[length], 0, CONFIG_ROM_SIZE - size);
1943}
1944
925e7a65
CL		 1945static int configure_1394a_enhancements(struct fw_ohci *ohci)
1946{
1947 bool enable_1394a;
35d999b1 1948 int ret, clear, set, offset;
925e7a65
CL		 1949
1950 /* Check if the driver should configure link and PHY. */
1951 if (!(reg_read(ohci, OHCI1394_HCControlSet) &
1952 OHCI1394_HCControl_programPhyEnable))
1953 return 0;
1954
1955 /* Paranoia: check whether the PHY supports 1394a, too. */
1956 enable_1394a = false;
35d999b1
SR		 1957 ret = read_phy_reg(ohci, 2);
1958 if (ret < 0)
1959 return ret;
1960 if ((ret & PHY_EXTENDED_REGISTERS) == PHY_EXTENDED_REGISTERS) {
1961 ret = read_paged_phy_reg(ohci, 1, 8);
1962 if (ret < 0)
1963 return ret;
1964 if (ret >= 1)
925e7a65
CL		 1965 enable_1394a = true;
1966 }
1967
1968 if (ohci->quirks & QUIRK_NO_1394A)
1969 enable_1394a = false;
1970
1971 /* Configure PHY and link consistently. */
1972 if (enable_1394a) {
1973 clear = 0;
1974 set = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
1975 } else {
1976 clear = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
1977 set = 0;
1978 }
02d37bed 1979 ret = update_phy_reg(ohci, 5, clear, set);
35d999b1
SR		 1980 if (ret < 0)
1981 return ret;
925e7a65
CL		 1982
1983 if (enable_1394a)
1984 offset = OHCI1394_HCControlSet;
1985 else
1986 offset = OHCI1394_HCControlClear;
1987 reg_write(ohci, offset, OHCI1394_HCControl_aPhyEnhanceEnable);
1988
1989 /* Clean up: configuration has been taken care of. */
1990 reg_write(ohci, OHCI1394_HCControlClear,
1991 OHCI1394_HCControl_programPhyEnable);
1992
1993 return 0;
1994}
1995
8e85973e
SR		 1996static int ohci_enable(struct fw_card *card,
1997 const __be32 *config_rom, size_t length)
ed568912
KH		 1998{
1999 struct fw_ohci *ohci = fw_ohci(card);
2000 struct pci_dev *dev = to_pci_dev(card->device);
e91b2787 2001 u32 lps, seconds, version, irqs;
35d999b1 2002 int i, ret;
ed568912 2003
2aef469a
KH		 2004 if (software_reset(ohci)) {
2005 fw_error("Failed to reset ohci card.\n");
2006 return -EBUSY;
2007 }
2008
2009 /*
2010 * Now enable LPS, which we need in order to start accessing
2011 * most of the registers. In fact, on some cards (ALI M5251),
2012 * accessing registers in the SClk domain without LPS enabled
2013 * will lock up the machine. Wait 50msec to make sure we have
02214724
JW		 2014 * full link enabled. However, with some cards (well, at least
2015 * a JMicron PCIe card), we have to try again sometimes.
2aef469a
KH		 2016 */
2017 reg_write(ohci, OHCI1394_HCControlSet,
2018 OHCI1394_HCControl_LPS |
2019 OHCI1394_HCControl_postedWriteEnable);
2020 flush_writes(ohci);
02214724
JW		 2021
2022 for (lps = 0, i = 0; !lps && i < 3; i++) {
2023 msleep(50);
2024 lps = reg_read(ohci, OHCI1394_HCControlSet) &
2025 OHCI1394_HCControl_LPS;
2026 }
2027
2028 if (!lps) {
2029 fw_error("Failed to set Link Power Status\n");
2030 return -EIO;
2031 }
2aef469a
KH		 2032
2033 reg_write(ohci, OHCI1394_HCControlClear,
2034 OHCI1394_HCControl_noByteSwapData);
2035
affc9c24 2036 reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
2aef469a
KH		 2037 reg_write(ohci, OHCI1394_LinkControlSet,
2038 OHCI1394_LinkControl_rcvSelfID |
bf54e146 2039 OHCI1394_LinkControl_rcvPhyPkt |
2aef469a
KH		 2040 OHCI1394_LinkControl_cycleTimerEnable |
2041 OHCI1394_LinkControl_cycleMaster);
2042
2043 reg_write(ohci, OHCI1394_ATRetries,
2044 OHCI1394_MAX_AT_REQ_RETRIES |
2045 (OHCI1394_MAX_AT_RESP_RETRIES << 4) |
27a2329f
CL		 2046 (OHCI1394_MAX_PHYS_RESP_RETRIES << 8) |
2047 (200 << 16));
2aef469a 2048
a48777e0
CL		 2049 seconds = lower_32_bits(get_seconds());
2050 reg_write(ohci, OHCI1394_IsochronousCycleTimer, seconds << 25);
2051 ohci->bus_time = seconds & ~0x3f;
2052
e91b2787
CL		 2053 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
2054 if (version >= OHCI_VERSION_1_1) {
2055 reg_write(ohci, OHCI1394_InitialChannelsAvailableHi,
2056 0xfffffffe);
db3c9cc1 2057 card->broadcast_channel_auto_allocated = true;
e91b2787
CL		 2058 }
2059
a1a1132b
CL		 2060 /* Get implemented bits of the priority arbitration request counter. */
2061 reg_write(ohci, OHCI1394_FairnessControl, 0x3f);
2062 ohci->pri_req_max = reg_read(ohci, OHCI1394_FairnessControl) & 0x3f;
2063 reg_write(ohci, OHCI1394_FairnessControl, 0);
db3c9cc1 2064 card->priority_budget_implemented = ohci->pri_req_max != 0;
2aef469a
KH		 2065
2066 ar_context_run(&ohci->ar_request_ctx);
2067 ar_context_run(&ohci->ar_response_ctx);
2068
2aef469a
KH		 2069 reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000);
2070 reg_write(ohci, OHCI1394_IntEventClear, ~0);
2071 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
2aef469a 2072
35d999b1
SR		 2073 ret = configure_1394a_enhancements(ohci);
2074 if (ret < 0)
2075 return ret;
925e7a65 2076
2aef469a 2077 /* Activate link_on bit and contender bit in our self ID packets.*/
35d999b1
SR		 2078 ret = ohci_update_phy_reg(card, 4, 0, PHY_LINK_ACTIVE | PHY_CONTENDER);
2079 if (ret < 0)
2080 return ret;
2aef469a 2081
c781c06d
KH		 2082 /*
2083 * When the link is not yet enabled, the atomic config rom
ed568912
KH		 2084 * update mechanism described below in ohci_set_config_rom()
2085 * is not active. We have to update ConfigRomHeader and
2086 * BusOptions manually, and the write to ConfigROMmap takes
2087 * effect immediately. We tie this to the enabling of the
2088 * link, so we have a valid config rom before enabling - the
2089 * OHCI requires that ConfigROMhdr and BusOptions have valid
2090 * values before enabling.
2091 *
2092 * However, when the ConfigROMmap is written, some controllers
2093 * always read back quadlets 0 and 2 from the config rom to
2094 * the ConfigRomHeader and BusOptions registers on bus reset.
2095 * They shouldn't do that in this initial case where the link
2096 * isn't enabled. This means we have to use the same
2097 * workaround here, setting the bus header to 0 and then write
2098 * the right values in the bus reset tasklet.
2099 */
2100
0bd243c4
KH		 2101 if (config_rom) {
2102 ohci->next_config_rom =
2103 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2104 &ohci->next_config_rom_bus,
2105 GFP_KERNEL);
2106 if (ohci->next_config_rom == NULL)
2107 return -ENOMEM;
ed568912 2108
8e85973e 2109 copy_config_rom(ohci->next_config_rom, config_rom, length);
0bd243c4
KH		 2110 } else {
2111 /*
2112 * In the suspend case, config_rom is NULL, which
2113 * means that we just reuse the old config rom.
2114 */
2115 ohci->next_config_rom = ohci->config_rom;
2116 ohci->next_config_rom_bus = ohci->config_rom_bus;
2117 }
ed568912 2118
8e85973e 2119 ohci->next_header = ohci->next_config_rom[0];
ed568912
KH		 2120 ohci->next_config_rom[0] = 0;
2121 reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
0bd243c4
KH		 2122 reg_write(ohci, OHCI1394_BusOptions,
2123 be32_to_cpu(ohci->next_config_rom[2]));
ed568912
KH		 2124 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
2125
2126 reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
2127
262444ee
CL		 2128 if (!(ohci->quirks & QUIRK_NO_MSI))
2129 pci_enable_msi(dev);
ed568912 2130 if (request_irq(dev->irq, irq_handler,
262444ee
CL		 2131 pci_dev_msi_enabled(dev) ? 0 : IRQF_SHARED,
2132 ohci_driver_name, ohci)) {
2133 fw_error("Failed to allocate interrupt %d.\n", dev->irq);
2134 pci_disable_msi(dev);
ed568912
KH		 2135 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2136 ohci->config_rom, ohci->config_rom_bus);
2137 return -EIO;
2138 }
2139
148c7866
SR		 2140 irqs = OHCI1394_reqTxComplete | OHCI1394_respTxComplete |
2141 OHCI1394_RQPkt | OHCI1394_RSPkt |
2142 OHCI1394_isochTx | OHCI1394_isochRx |
2143 OHCI1394_postedWriteErr |
2144 OHCI1394_selfIDComplete |
2145 OHCI1394_regAccessFail |
a48777e0 2146 OHCI1394_cycle64Seconds |
148c7866
SR		 2147 OHCI1394_cycleInconsistent | OHCI1394_cycleTooLong |
2148 OHCI1394_masterIntEnable;
2149 if (param_debug & OHCI_PARAM_DEBUG_BUSRESETS)
2150 irqs |= OHCI1394_busReset;
2151 reg_write(ohci, OHCI1394_IntMaskSet, irqs);
2152
ed568912
KH		 2153 reg_write(ohci, OHCI1394_HCControlSet,
2154 OHCI1394_HCControl_linkEnable |
2155 OHCI1394_HCControl_BIBimageValid);
2156 flush_writes(ohci);
2157
02d37bed
SR		 2158 /* We are ready to go, reset bus to finish initialization. */
2159 fw_schedule_bus_reset(&ohci->card, false, true);
ed568912
KH		 2160
2161 return 0;
2162}
2163
53dca511 2164static int ohci_set_config_rom(struct fw_card *card,
8e85973e 2165 const __be32 *config_rom, size_t length)
ed568912
KH		 2166{
2167 struct fw_ohci *ohci;
2168 unsigned long flags;
2dbd7d7e 2169 int ret = -EBUSY;
ed568912 2170 __be32 *next_config_rom;
f5101d58 2171 dma_addr_t uninitialized_var(next_config_rom_bus);
ed568912
KH		 2172
2173 ohci = fw_ohci(card);
2174
c781c06d
KH		 2175 /*
2176 * When the OHCI controller is enabled, the config rom update
ed568912
KH		 2177 * mechanism is a bit tricky, but easy enough to use. See
2178 * section 5.5.6 in the OHCI specification.
2179 *
2180 * The OHCI controller caches the new config rom address in a
2181 * shadow register (ConfigROMmapNext) and needs a bus reset
2182 * for the changes to take place. When the bus reset is
2183 * detected, the controller loads the new values for the
2184 * ConfigRomHeader and BusOptions registers from the specified
2185 * config rom and loads ConfigROMmap from the ConfigROMmapNext
2186 * shadow register. All automatically and atomically.
2187 *
2188 * Now, there's a twist to this story. The automatic load of
2189 * ConfigRomHeader and BusOptions doesn't honor the
2190 * noByteSwapData bit, so with a be32 config rom, the
2191 * controller will load be32 values in to these registers
2192 * during the atomic update, even on litte endian
2193 * architectures. The workaround we use is to put a 0 in the
2194 * header quadlet; 0 is endian agnostic and means that the
2195 * config rom isn't ready yet. In the bus reset tasklet we
2196 * then set up the real values for the two registers.
2197 *
2198 * We use ohci->lock to avoid racing with the code that sets
2199 * ohci->next_config_rom to NULL (see bus_reset_tasklet).
2200 */
2201
2202 next_config_rom =
2203 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2204 &next_config_rom_bus, GFP_KERNEL);
2205 if (next_config_rom == NULL)
2206 return -ENOMEM;
2207
2208 spin_lock_irqsave(&ohci->lock, flags);
2209
2210 if (ohci->next_config_rom == NULL) {
2211 ohci->next_config_rom = next_config_rom;
2212 ohci->next_config_rom_bus = next_config_rom_bus;
2213
8e85973e 2214 copy_config_rom(ohci->next_config_rom, config_rom, length);
ed568912
KH		 2215
2216 ohci->next_header = config_rom[0];
2217 ohci->next_config_rom[0] = 0;
2218
2219 reg_write(ohci, OHCI1394_ConfigROMmap,
2220 ohci->next_config_rom_bus);
2dbd7d7e 2221 ret = 0;
ed568912
KH		 2222 }
2223
2224 spin_unlock_irqrestore(&ohci->lock, flags);
2225
c781c06d
KH		 2226 /*
2227 * Now initiate a bus reset to have the changes take
ed568912
KH		 2228 * effect. We clean up the old config rom memory and DMA
2229 * mappings in the bus reset tasklet, since the OHCI
2230 * controller could need to access it before the bus reset
c781c06d
KH		 2231 * takes effect.
2232 */
2dbd7d7e 2233 if (ret == 0)
02d37bed 2234 fw_schedule_bus_reset(&ohci->card, true, true);
4eaff7d6
SR		 2235 else
2236 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2237 next_config_rom, next_config_rom_bus);
ed568912 2238
2dbd7d7e 2239 return ret;
ed568912
KH		 2240}
2241
2242static void ohci_send_request(struct fw_card *card, struct fw_packet *packet)
2243{
2244 struct fw_ohci *ohci = fw_ohci(card);
2245
2246 at_context_transmit(&ohci->at_request_ctx, packet);
2247}
2248
2249static void ohci_send_response(struct fw_card *card, struct fw_packet *packet)
2250{
2251 struct fw_ohci *ohci = fw_ohci(card);
2252
2253 at_context_transmit(&ohci->at_response_ctx, packet);
2254}
2255
730c32f5
KH		 2256static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet)
2257{
2258 struct fw_ohci *ohci = fw_ohci(card);
f319b6a0
KH		 2259 struct context *ctx = &ohci->at_request_ctx;
2260 struct driver_data *driver_data = packet->driver_data;
2dbd7d7e 2261 int ret = -ENOENT;
730c32f5 2262
f319b6a0 2263 tasklet_disable(&ctx->tasklet);
730c32f5 2264
f319b6a0
KH		 2265 if (packet->ack != 0)
2266 goto out;
730c32f5 2267
19593ffd 2268 if (packet->payload_mapped)
1d1dc5e8
SR		 2269 dma_unmap_single(ohci->card.device, packet->payload_bus,
2270 packet->payload_length, DMA_TO_DEVICE);
2271
ad3c0fe8 2272 log_ar_at_event('T', packet->speed, packet->header, 0x20);
f319b6a0
KH		 2273 driver_data->packet = NULL;
2274 packet->ack = RCODE_CANCELLED;
2275 packet->callback(packet, &ohci->card, packet->ack);
2dbd7d7e 2276 ret = 0;
f319b6a0
KH		 2277 out:
2278 tasklet_enable(&ctx->tasklet);
730c32f5 2279
2dbd7d7e 2280 return ret;
730c32f5
KH		 2281}
2282
53dca511
SR		 2283static int ohci_enable_phys_dma(struct fw_card *card,
2284 int node_id, int generation)
ed568912 2285{
080de8c2
SR		 2286#ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
2287 return 0;
2288#else
ed568912
KH		 2289 struct fw_ohci *ohci = fw_ohci(card);
2290 unsigned long flags;
2dbd7d7e 2291 int n, ret = 0;
ed568912 2292
c781c06d
KH		 2293 /*
2294 * FIXME: Make sure this bitmask is cleared when we clear the busReset
2295 * interrupt bit. Clear physReqResourceAllBuses on bus reset.
2296 */
ed568912
KH		 2297
2298 spin_lock_irqsave(&ohci->lock, flags);
2299
2300 if (ohci->generation != generation) {
2dbd7d7e 2301 ret = -ESTALE;
ed568912
KH		 2302 goto out;
2303 }
2304
c781c06d
KH		 2305 /*
2306 * Note, if the node ID contains a non-local bus ID, physical DMA is
2307 * enabled for _all_ nodes on remote buses.
2308 */
907293d7
SR		 2309
2310 n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63;
2311 if (n < 32)
2312 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n);
2313 else
2314 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32));
2315
ed568912 2316 flush_writes(ohci);
ed568912 2317 out:
6cad95fe 2318 spin_unlock_irqrestore(&ohci->lock, flags);
2dbd7d7e
SR		 2319
2320 return ret;
080de8c2 2321#endif /* CONFIG_FIREWIRE_OHCI_REMOTE_DMA */
ed568912 2322}
373b2edd 2323
0fcff4e3 2324static u32 ohci_read_csr(struct fw_card *card, int csr_offset)
b677532b 2325{
60d32970 2326 struct fw_ohci *ohci = fw_ohci(card);
a48777e0
CL		 2327 unsigned long flags;
2328 u32 value;
60d32970
CL		 2329
2330 switch (csr_offset) {
4ffb7a6a
CL		 2331 case CSR_STATE_CLEAR:
2332 case CSR_STATE_SET:
4ffb7a6a
CL		 2333 if (ohci->is_root &&
2334 (reg_read(ohci, OHCI1394_LinkControlSet) &
2335 OHCI1394_LinkControl_cycleMaster))
c8a94ded 2336 value = CSR_STATE_BIT_CMSTR;
4ffb7a6a 2337 else
c8a94ded
SR		 2338 value = 0;
2339 if (ohci->csr_state_setclear_abdicate)
2340 value |= CSR_STATE_BIT_ABDICATE;
b677532b 2341
c8a94ded 2342 return value;
4a9bde9b 2343
506f1a31
CL		 2344 case CSR_NODE_IDS:
2345 return reg_read(ohci, OHCI1394_NodeID) << 16;
2346
60d32970
CL		 2347 case CSR_CYCLE_TIME:
2348 return get_cycle_time(ohci);
2349
a48777e0
CL		 2350 case CSR_BUS_TIME:
2351 /*
2352 * We might be called just after the cycle timer has wrapped
2353 * around but just before the cycle64Seconds handler, so we
2354 * better check here, too, if the bus time needs to be updated.
2355 */
2356 spin_lock_irqsave(&ohci->lock, flags);
2357 value = update_bus_time(ohci);
2358 spin_unlock_irqrestore(&ohci->lock, flags);
2359 return value;
2360
27a2329f
CL		 2361 case CSR_BUSY_TIMEOUT:
2362 value = reg_read(ohci, OHCI1394_ATRetries);
2363 return (value >> 4) & 0x0ffff00f;
2364
a1a1132b
CL		 2365 case CSR_PRIORITY_BUDGET:
2366 return (reg_read(ohci, OHCI1394_FairnessControl) & 0x3f) |
2367 (ohci->pri_req_max << 8);
2368
60d32970
CL		 2369 default:
2370 WARN_ON(1);
2371 return 0;
2372 }
b677532b
CL		 2373}
2374
0fcff4e3 2375static void ohci_write_csr(struct fw_card *card, int csr_offset, u32 value)
d60d7f1d
KH		 2376{
2377 struct fw_ohci *ohci = fw_ohci(card);
a48777e0 2378 unsigned long flags;
d60d7f1d 2379
506f1a31 2380 switch (csr_offset) {
4ffb7a6a 2381 case CSR_STATE_CLEAR:
4ffb7a6a
CL		 2382 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
2383 reg_write(ohci, OHCI1394_LinkControlClear,
2384 OHCI1394_LinkControl_cycleMaster);
2385 flush_writes(ohci);
2386 }
c8a94ded
SR		 2387 if (value & CSR_STATE_BIT_ABDICATE)
2388 ohci->csr_state_setclear_abdicate = false;
4ffb7a6a 2389 break;
4a9bde9b 2390
4ffb7a6a
CL		 2391 case CSR_STATE_SET:
2392 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
2393 reg_write(ohci, OHCI1394_LinkControlSet,
2394 OHCI1394_LinkControl_cycleMaster);
2395 flush_writes(ohci);
2396 }
c8a94ded
SR		 2397 if (value & CSR_STATE_BIT_ABDICATE)
2398 ohci->csr_state_setclear_abdicate = true;
4ffb7a6a 2399 break;
d60d7f1d 2400
506f1a31
CL		 2401 case CSR_NODE_IDS:
2402 reg_write(ohci, OHCI1394_NodeID, value >> 16);
2403 flush_writes(ohci);
2404 break;
2405
9ab5071c
CL		 2406 case CSR_CYCLE_TIME:
2407 reg_write(ohci, OHCI1394_IsochronousCycleTimer, value);
2408 reg_write(ohci, OHCI1394_IntEventSet,
2409 OHCI1394_cycleInconsistent);
2410 flush_writes(ohci);
2411 break;
2412
a48777e0
CL		 2413 case CSR_BUS_TIME:
2414 spin_lock_irqsave(&ohci->lock, flags);
2415 ohci->bus_time = (ohci->bus_time & 0x7f) | (value & ~0x7f);
2416 spin_unlock_irqrestore(&ohci->lock, flags);
2417 break;
2418
27a2329f
CL		 2419 case CSR_BUSY_TIMEOUT:
2420 value = (value & 0xf) | ((value & 0xf) << 4) |
2421 ((value & 0xf) << 8) | ((value & 0x0ffff000) << 4);
2422 reg_write(ohci, OHCI1394_ATRetries, value);
2423 flush_writes(ohci);
2424 break;
2425
a1a1132b
CL		 2426 case CSR_PRIORITY_BUDGET:
2427 reg_write(ohci, OHCI1394_FairnessControl, value & 0x3f);
2428 flush_writes(ohci);
2429 break;
2430
506f1a31
CL		 2431 default:
2432 WARN_ON(1);
2433 break;
2434 }
d60d7f1d
KH		 2435}
2436
1aa292bb
DM		 2437static void copy_iso_headers(struct iso_context *ctx, void *p)
2438{
2439 int i = ctx->header_length;
2440
2441 if (i + ctx->base.header_size > PAGE_SIZE)
2442 return;
2443
2444 /*
2445 * The iso header is byteswapped to little endian by
2446 * the controller, but the remaining header quadlets
2447 * are big endian. We want to present all the headers
2448 * as big endian, so we have to swap the first quadlet.
2449 */
2450 if (ctx->base.header_size > 0)
2451 *(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4));
2452 if (ctx->base.header_size > 4)
2453 *(u32 *) (ctx->header + i + 4) = __swab32(*(u32 *) p);
2454 if (ctx->base.header_size > 8)
2455 memcpy(ctx->header + i + 8, p + 8, ctx->base.header_size - 8);
2456 ctx->header_length += ctx->base.header_size;
2457}
2458
a186b4a6
JW		 2459static int handle_ir_packet_per_buffer(struct context *context,
2460 struct descriptor *d,
2461 struct descriptor *last)
2462{
2463 struct iso_context *ctx =
2464 container_of(context, struct iso_context, context);
bcee893c 2465 struct descriptor *pd;
a186b4a6 2466 __le32 *ir_header;
bcee893c 2467 void *p;
a186b4a6 2468
872e330e 2469 for (pd = d; pd <= last; pd++)
bcee893c
DM		 2470 if (pd->transfer_status)
2471 break;
bcee893c 2472 if (pd > last)
a186b4a6
JW		 2473 /* Descriptor(s) not done yet, stop iteration */
2474 return 0;
2475
1aa292bb
DM		 2476 p = last + 1;
2477 copy_iso_headers(ctx, p);
a186b4a6 2478
bcee893c
DM		 2479 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
2480 ir_header = (__le32 *) p;
872e330e
SR		 2481 ctx->base.callback.sc(&ctx->base,
2482 le32_to_cpu(ir_header[0]) & 0xffff,
2483 ctx->header_length, ctx->header,
2484 ctx->base.callback_data);
a186b4a6
JW		 2485 ctx->header_length = 0;
2486 }
2487
a186b4a6
JW		 2488 return 1;
2489}
2490
872e330e
SR		 2491/* d == last because each descriptor block is only a single descriptor. */
2492static int handle_ir_buffer_fill(struct context *context,
2493 struct descriptor *d,
2494 struct descriptor *last)
2495{
2496 struct iso_context *ctx =
2497 container_of(context, struct iso_context, context);
2498
2499 if (!last->transfer_status)
2500 /* Descriptor(s) not done yet, stop iteration */
2501 return 0;
2502
2503 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS)
2504 ctx->base.callback.mc(&ctx->base,
2505 le32_to_cpu(last->data_address) +
2506 le16_to_cpu(last->req_count) -
2507 le16_to_cpu(last->res_count),
2508 ctx->base.callback_data);
2509
2510 return 1;
2511}
2512
30200739
KH		 2513static int handle_it_packet(struct context *context,
2514 struct descriptor *d,
2515 struct descriptor *last)
ed568912 2516{
30200739
KH		 2517 struct iso_context *ctx =
2518 container_of(context, struct iso_context, context);
31769cef
JF		 2519 int i;
2520 struct descriptor *pd;
373b2edd 2521
31769cef
JF		 2522 for (pd = d; pd <= last; pd++)
2523 if (pd->transfer_status)
2524 break;
2525 if (pd > last)
2526 /* Descriptor(s) not done yet, stop iteration */
30200739
KH		 2527 return 0;
2528
31769cef
JF		 2529 i = ctx->header_length;
2530 if (i + 4 < PAGE_SIZE) {
2531 /* Present this value as big-endian to match the receive code */
2532 *(__be32 *)(ctx->header + i) = cpu_to_be32(
2533 ((u32)le16_to_cpu(pd->transfer_status) << 16) |
2534 le16_to_cpu(pd->res_count));
2535 ctx->header_length += 4;
2536 }
2537 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
872e330e
SR		 2538 ctx->base.callback.sc(&ctx->base, le16_to_cpu(last->res_count),
2539 ctx->header_length, ctx->header,
2540 ctx->base.callback_data);
31769cef
JF		 2541 ctx->header_length = 0;
2542 }
30200739 2543 return 1;
ed568912
KH		 2544}
2545
872e330e
SR		 2546static void set_multichannel_mask(struct fw_ohci *ohci, u64 channels)
2547{
2548 u32 hi = channels >> 32, lo = channels;
2549
2550 reg_write(ohci, OHCI1394_IRMultiChanMaskHiClear, ~hi);
2551 reg_write(ohci, OHCI1394_IRMultiChanMaskLoClear, ~lo);
2552 reg_write(ohci, OHCI1394_IRMultiChanMaskHiSet, hi);
2553 reg_write(ohci, OHCI1394_IRMultiChanMaskLoSet, lo);
2554 mmiowb();
2555 ohci->mc_channels = channels;
2556}
2557
53dca511 2558static struct fw_iso_context *ohci_allocate_iso_context(struct fw_card *card,
4817ed24 2559 int type, int channel, size_t header_size)
ed568912
KH		 2560{
2561 struct fw_ohci *ohci = fw_ohci(card);
872e330e
SR		 2562 struct iso_context *uninitialized_var(ctx);
2563 descriptor_callback_t uninitialized_var(callback);
2564 u64 *uninitialized_var(channels);
2565 u32 *uninitialized_var(mask), uninitialized_var(regs);
ed568912 2566 unsigned long flags;
872e330e 2567 int index, ret = -EBUSY;
ed568912 2568
872e330e 2569 spin_lock_irqsave(&ohci->lock, flags);
ed568912 2570
872e330e
SR		 2571 switch (type) {
2572 case FW_ISO_CONTEXT_TRANSMIT:
2573 mask = &ohci->it_context_mask;
30200739 2574 callback = handle_it_packet;
872e330e
SR		 2575 index = ffs(*mask) - 1;
2576 if (index >= 0) {
2577 *mask &= ~(1 << index);
2578 regs = OHCI1394_IsoXmitContextBase(index);
2579 ctx = &ohci->it_context_list[index];
2580 }
2581 break;
2582
2583 case FW_ISO_CONTEXT_RECEIVE:
4817ed24 2584 channels = &ohci->ir_context_channels;
872e330e 2585 mask = &ohci->ir_context_mask;
6498ba04 2586 callback = handle_ir_packet_per_buffer;
872e330e
SR		 2587 index = *channels & 1ULL << channel ? ffs(*mask) - 1 : -1;
2588 if (index >= 0) {
2589 *channels &= ~(1ULL << channel);
2590 *mask &= ~(1 << index);
2591 regs = OHCI1394_IsoRcvContextBase(index);
2592 ctx = &ohci->ir_context_list[index];
2593 }
2594 break;
ed568912 2595
872e330e
SR		 2596 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2597 mask = &ohci->ir_context_mask;
2598 callback = handle_ir_buffer_fill;
2599 index = !ohci->mc_allocated ? ffs(*mask) - 1 : -1;
2600 if (index >= 0) {
2601 ohci->mc_allocated = true;
2602 *mask &= ~(1 << index);
2603 regs = OHCI1394_IsoRcvContextBase(index);
2604 ctx = &ohci->ir_context_list[index];
2605 }
2606 break;
2607
2608 default:
2609 index = -1;
2610 ret = -ENOSYS;
4817ed24 2611 }
872e330e 2612
ed568912
KH		 2613 spin_unlock_irqrestore(&ohci->lock, flags);
2614
2615 if (index < 0)
872e330e 2616 return ERR_PTR(ret);
373b2edd 2617
2d826cc5 2618 memset(ctx, 0, sizeof(*ctx));
9b32d5f3
KH		 2619 ctx->header_length = 0;
2620 ctx->header = (void *) __get_free_page(GFP_KERNEL);
872e330e
SR		 2621 if (ctx->header == NULL) {
2622 ret = -ENOMEM;
9b32d5f3 2623 goto out;
872e330e 2624 }
2dbd7d7e
SR		 2625 ret = context_init(&ctx->context, ohci, regs, callback);
2626 if (ret < 0)
9b32d5f3 2627 goto out_with_header;
ed568912 2628
872e330e
SR		 2629 if (type == FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL)
2630 set_multichannel_mask(ohci, 0);
2631
ed568912 2632 return &ctx->base;
9b32d5f3
KH		 2633
2634 out_with_header:
2635 free_page((unsigned long)ctx->header);
2636 out:
2637 spin_lock_irqsave(&ohci->lock, flags);
872e330e
SR		 2638
2639 switch (type) {
2640 case FW_ISO_CONTEXT_RECEIVE:
2641 *channels |= 1ULL << channel;
2642 break;
2643
2644 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2645 ohci->mc_allocated = false;
2646 break;
2647 }
9b32d5f3 2648 *mask |= 1 << index;
872e330e 2649
9b32d5f3
KH		 2650 spin_unlock_irqrestore(&ohci->lock, flags);
2651
2dbd7d7e 2652 return ERR_PTR(ret);
ed568912
KH		 2653}
2654
eb0306ea
KH		 2655static int ohci_start_iso(struct fw_iso_context *base,
2656 s32 cycle, u32 sync, u32 tags)
ed568912 2657{
373b2edd 2658 struct iso_context *ctx = container_of(base, struct iso_context, base);
30200739 2659 struct fw_ohci *ohci = ctx->context.ohci;
872e330e 2660 u32 control = IR_CONTEXT_ISOCH_HEADER, match;
ed568912
KH		 2661 int index;
2662
872e330e
SR		 2663 switch (ctx->base.type) {
2664 case FW_ISO_CONTEXT_TRANSMIT:
295e3feb 2665 index = ctx - ohci->it_context_list;
8a2f7d93
KH		 2666 match = 0;
2667 if (cycle >= 0)
2668 match = IT_CONTEXT_CYCLE_MATCH_ENABLE |
295e3feb 2669 (cycle & 0x7fff) << 16;
21efb3cf 2670
295e3feb
KH		 2671 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index);
2672 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index);
8a2f7d93 2673 context_run(&ctx->context, match);
872e330e
SR		 2674 break;
2675
2676 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2677 control |= IR_CONTEXT_BUFFER_FILL|IR_CONTEXT_MULTI_CHANNEL_MODE;
2678 /* fall through */
2679 case FW_ISO_CONTEXT_RECEIVE:
295e3feb 2680 index = ctx - ohci->ir_context_list;
8a2f7d93
KH		 2681 match = (tags << 28) | (sync << 8) | ctx->base.channel;
2682 if (cycle >= 0) {
2683 match |= (cycle & 0x07fff) << 12;
2684 control |= IR_CONTEXT_CYCLE_MATCH_ENABLE;
2685 }
ed568912 2686
295e3feb
KH		 2687 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index);
2688 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index);
a77754a7 2689 reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match);
8a2f7d93 2690 context_run(&ctx->context, control);
dd23736e
ML		 2691
2692 ctx->sync = sync;
2693 ctx->tags = tags;
2694
872e330e 2695 break;
295e3feb 2696 }
ed568912
KH		 2697
2698 return 0;
2699}
2700
b8295668
KH		 2701static int ohci_stop_iso(struct fw_iso_context *base)
2702{
2703 struct fw_ohci *ohci = fw_ohci(base->card);
373b2edd 2704 struct iso_context *ctx = container_of(base, struct iso_context, base);
b8295668
KH		 2705 int index;
2706
872e330e
SR		 2707 switch (ctx->base.type) {
2708 case FW_ISO_CONTEXT_TRANSMIT:
b8295668
KH		 2709 index = ctx - ohci->it_context_list;
2710 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index);
872e330e
SR		 2711 break;
2712
2713 case FW_ISO_CONTEXT_RECEIVE:
2714 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
b8295668
KH		 2715 index = ctx - ohci->ir_context_list;
2716 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index);
872e330e 2717 break;
b8295668
KH		 2718 }
2719 flush_writes(ohci);
2720 context_stop(&ctx->context);
2721
2722 return 0;
2723}
2724
ed568912
KH		 2725static void ohci_free_iso_context(struct fw_iso_context *base)
2726{
2727 struct fw_ohci *ohci = fw_ohci(base->card);
373b2edd 2728 struct iso_context *ctx = container_of(base, struct iso_context, base);
ed568912
KH		 2729 unsigned long flags;
2730 int index;
2731
b8295668
KH		 2732 ohci_stop_iso(base);
2733 context_release(&ctx->context);
9b32d5f3 2734 free_page((unsigned long)ctx->header);
b8295668 2735
ed568912
KH		 2736 spin_lock_irqsave(&ohci->lock, flags);
2737
872e330e
SR		 2738 switch (base->type) {
2739 case FW_ISO_CONTEXT_TRANSMIT:
ed568912 2740 index = ctx - ohci->it_context_list;
ed568912 2741 ohci->it_context_mask |= 1 << index;
872e330e
SR		 2742 break;
2743
2744 case FW_ISO_CONTEXT_RECEIVE:
ed568912 2745 index = ctx - ohci->ir_context_list;
ed568912 2746 ohci->ir_context_mask |= 1 << index;
4817ed24 2747 ohci->ir_context_channels |= 1ULL << base->channel;
872e330e
SR		 2748 break;
2749
2750 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2751 index = ctx - ohci->ir_context_list;
2752 ohci->ir_context_mask |= 1 << index;
2753 ohci->ir_context_channels |= ohci->mc_channels;
2754 ohci->mc_channels = 0;
2755 ohci->mc_allocated = false;
2756 break;
ed568912 2757 }
ed568912
KH		 2758
2759 spin_unlock_irqrestore(&ohci->lock, flags);
2760}
2761
872e330e
SR		 2762static int ohci_set_iso_channels(struct fw_iso_context *base, u64 *channels)
2763{
2764 struct fw_ohci *ohci = fw_ohci(base->card);
2765 unsigned long flags;
2766 int ret;
2767
2768 switch (base->type) {
2769 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2770
2771 spin_lock_irqsave(&ohci->lock, flags);
2772
2773 /* Don't allow multichannel to grab other contexts' channels. */
2774 if (~ohci->ir_context_channels & ~ohci->mc_channels & *channels) {
2775 *channels = ohci->ir_context_channels;
2776 ret = -EBUSY;
2777 } else {
2778 set_multichannel_mask(ohci, *channels);
2779 ret = 0;
2780 }
2781
2782 spin_unlock_irqrestore(&ohci->lock, flags);
2783
2784 break;
2785 default:
2786 ret = -EINVAL;
2787 }
2788
2789 return ret;
2790}
2791
dd23736e
ML		 2792#ifdef CONFIG_PM
2793static void ohci_resume_iso_dma(struct fw_ohci *ohci)
2794{
2795 int i;
2796 struct iso_context *ctx;
2797
2798 for (i = 0 ; i < ohci->n_ir ; i++) {
2799 ctx = &ohci->ir_context_list[i];
2800 if (ctx->context.active)
2801 ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags);
2802 }
2803
2804 for (i = 0 ; i < ohci->n_it ; i++) {
2805 ctx = &ohci->it_context_list[i];
2806 if (ctx->context.active)
2807 ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags);
2808 }
2809}
2810#endif
2811
872e330e
SR		 2812static int queue_iso_transmit(struct iso_context *ctx,
2813 struct fw_iso_packet *packet,
2814 struct fw_iso_buffer *buffer,
2815 unsigned long payload)
ed568912 2816{
30200739 2817 struct descriptor *d, *last, *pd;
ed568912
KH		 2818 struct fw_iso_packet *p;
2819 __le32 *header;
9aad8125 2820 dma_addr_t d_bus, page_bus;
ed568912
KH		 2821 u32 z, header_z, payload_z, irq;
2822 u32 payload_index, payload_end_index, next_page_index;
30200739 2823 int page, end_page, i, length, offset;
ed568912 2824
ed568912 2825 p = packet;
9aad8125 2826 payload_index = payload;
ed568912
KH		 2827
2828 if (p->skip)
2829 z = 1;
2830 else
2831 z = 2;
2832 if (p->header_length > 0)
2833 z++;
2834
2835 /* Determine the first page the payload isn't contained in. */
2836 end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT;
2837 if (p->payload_length > 0)
2838 payload_z = end_page - (payload_index >> PAGE_SHIFT);
2839 else
2840 payload_z = 0;
2841
2842 z += payload_z;
2843
2844 /* Get header size in number of descriptors. */
2d826cc5 2845 header_z = DIV_ROUND_UP(p->header_length, sizeof(*d));
ed568912 2846
30200739
KH		 2847 d = context_get_descriptors(&ctx->context, z + header_z, &d_bus);
2848 if (d == NULL)
2849 return -ENOMEM;
ed568912
KH		 2850
2851 if (!p->skip) {
a77754a7 2852 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
ed568912 2853 d[0].req_count = cpu_to_le16(8);
7f51a100
CL		 2854 /*
2855 * Link the skip address to this descriptor itself. This causes
2856 * a context to skip a cycle whenever lost cycles or FIFO
2857 * overruns occur, without dropping the data. The application
2858 * should then decide whether this is an error condition or not.
2859 * FIXME: Make the context's cycle-lost behaviour configurable?
2860 */
2861 d[0].branch_address = cpu_to_le32(d_bus | z);
ed568912
KH		 2862
2863 header = (__le32 *) &d[1];
a77754a7
KH		 2864 header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) |
2865 IT_HEADER_TAG(p->tag) |
2866 IT_HEADER_TCODE(TCODE_STREAM_DATA) |
2867 IT_HEADER_CHANNEL(ctx->base.channel) |
2868 IT_HEADER_SPEED(ctx->base.speed));
ed568912 2869 header[1] =
a77754a7 2870 cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length +
ed568912
KH		 2871 p->payload_length));
2872 }
2873
2874 if (p->header_length > 0) {
2875 d[2].req_count = cpu_to_le16(p->header_length);
2d826cc5 2876 d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d));
ed568912
KH		 2877 memcpy(&d[z], p->header, p->header_length);
2878 }
2879
2880 pd = d + z - payload_z;
2881 payload_end_index = payload_index + p->payload_length;
2882 for (i = 0; i < payload_z; i++) {
2883 page = payload_index >> PAGE_SHIFT;
2884 offset = payload_index & ~PAGE_MASK;
2885 next_page_index = (page + 1) << PAGE_SHIFT;
2886 length =
2887 min(next_page_index, payload_end_index) - payload_index;
2888 pd[i].req_count = cpu_to_le16(length);
9aad8125
KH		 2889
2890 page_bus = page_private(buffer->pages[page]);
2891 pd[i].data_address = cpu_to_le32(page_bus + offset);
ed568912
KH		 2892
2893 payload_index += length;
2894 }
2895
ed568912 2896 if (p->interrupt)
a77754a7 2897 irq = DESCRIPTOR_IRQ_ALWAYS;
ed568912 2898 else
a77754a7 2899 irq = DESCRIPTOR_NO_IRQ;
ed568912 2900
30200739 2901 last = z == 2 ? d : d + z - 1;
a77754a7
KH		 2902 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
2903 DESCRIPTOR_STATUS |
2904 DESCRIPTOR_BRANCH_ALWAYS |
cbb59da7 2905 irq);
ed568912 2906
30200739 2907 context_append(&ctx->context, d, z, header_z);
ed568912
KH		 2908
2909 return 0;
2910}
373b2edd 2911
872e330e
SR		 2912static int queue_iso_packet_per_buffer(struct iso_context *ctx,
2913 struct fw_iso_packet *packet,
2914 struct fw_iso_buffer *buffer,
2915 unsigned long payload)
a186b4a6 2916{
8c0c0cc2 2917 struct descriptor *d, *pd;
a186b4a6
JW		 2918 dma_addr_t d_bus, page_bus;
2919 u32 z, header_z, rest;
bcee893c
DM		 2920 int i, j, length;
2921 int page, offset, packet_count, header_size, payload_per_buffer;
a186b4a6
JW		 2922
2923 /*
1aa292bb
DM		 2924 * The OHCI controller puts the isochronous header and trailer in the
2925 * buffer, so we need at least 8 bytes.
a186b4a6 2926 */
872e330e 2927 packet_count = packet->header_length / ctx->base.header_size;
1aa292bb 2928 header_size = max(ctx->base.header_size, (size_t)8);
a186b4a6
JW		 2929
2930 /* Get header size in number of descriptors. */
2931 header_z = DIV_ROUND_UP(header_size, sizeof(*d));
2932 page = payload >> PAGE_SHIFT;
2933 offset = payload & ~PAGE_MASK;
872e330e 2934 payload_per_buffer = packet->payload_length / packet_count;
a186b4a6
JW		 2935
2936 for (i = 0; i < packet_count; i++) {
2937 /* d points to the header descriptor */
bcee893c 2938 z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1;
a186b4a6 2939 d = context_get_descriptors(&ctx->context,
bcee893c 2940 z + header_z, &d_bus);
a186b4a6
JW		 2941 if (d == NULL)
2942 return -ENOMEM;
2943
bcee893c
DM		 2944 d->control = cpu_to_le16(DESCRIPTOR_STATUS |
2945 DESCRIPTOR_INPUT_MORE);
872e330e 2946 if (packet->skip && i == 0)
bcee893c 2947 d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
a186b4a6
JW		 2948 d->req_count = cpu_to_le16(header_size);
2949 d->res_count = d->req_count;
bcee893c 2950 d->transfer_status = 0;
a186b4a6
JW		 2951 d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d)));
2952
bcee893c 2953 rest = payload_per_buffer;
8c0c0cc2 2954 pd = d;
bcee893c 2955 for (j = 1; j < z; j++) {
8c0c0cc2 2956 pd++;
bcee893c
DM		 2957 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
2958 DESCRIPTOR_INPUT_MORE);
2959
2960 if (offset + rest < PAGE_SIZE)
2961 length = rest;
2962 else
2963 length = PAGE_SIZE - offset;
2964 pd->req_count = cpu_to_le16(length);
2965 pd->res_count = pd->req_count;
2966 pd->transfer_status = 0;
2967
2968 page_bus = page_private(buffer->pages[page]);
2969 pd->data_address = cpu_to_le32(page_bus + offset);
2970
2971 offset = (offset + length) & ~PAGE_MASK;
2972 rest -= length;
2973 if (offset == 0)
2974 page++;
2975 }
a186b4a6
JW		 2976 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
2977 DESCRIPTOR_INPUT_LAST |
2978 DESCRIPTOR_BRANCH_ALWAYS);
872e330e 2979 if (packet->interrupt && i == packet_count - 1)
a186b4a6
JW		 2980 pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
2981
a186b4a6
JW		 2982 context_append(&ctx->context, d, z, header_z);
2983 }
2984
2985 return 0;
2986}
2987
872e330e
SR		 2988static int queue_iso_buffer_fill(struct iso_context *ctx,
2989 struct fw_iso_packet *packet,
2990 struct fw_iso_buffer *buffer,
2991 unsigned long payload)
2992{
2993 struct descriptor *d;
2994 dma_addr_t d_bus, page_bus;
2995 int page, offset, rest, z, i, length;
2996
2997 page = payload >> PAGE_SHIFT;
2998 offset = payload & ~PAGE_MASK;
2999 rest = packet->payload_length;
3000
3001 /* We need one descriptor for each page in the buffer. */
3002 z = DIV_ROUND_UP(offset + rest, PAGE_SIZE);
3003
3004 if (WARN_ON(offset & 3 || rest & 3 || page + z > buffer->page_count))
3005 return -EFAULT;
3006
3007 for (i = 0; i < z; i++) {
3008 d = context_get_descriptors(&ctx->context, 1, &d_bus);
3009 if (d == NULL)
3010 return -ENOMEM;
3011
3012 d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
3013 DESCRIPTOR_BRANCH_ALWAYS);
3014 if (packet->skip && i == 0)
3015 d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
3016 if (packet->interrupt && i == z - 1)
3017 d->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
3018
3019 if (offset + rest < PAGE_SIZE)
3020 length = rest;
3021 else
3022 length = PAGE_SIZE - offset;
3023 d->req_count = cpu_to_le16(length);
3024 d->res_count = d->req_count;
3025 d->transfer_status = 0;
3026
3027 page_bus = page_private(buffer->pages[page]);
3028 d->data_address = cpu_to_le32(page_bus + offset);
3029
3030 rest -= length;
3031 offset = 0;
3032 page++;
3033
3034 context_append(&ctx->context, d, 1, 0);
3035 }
3036
3037 return 0;
3038}
3039
53dca511
SR		 3040static int ohci_queue_iso(struct fw_iso_context *base,
3041 struct fw_iso_packet *packet,
3042 struct fw_iso_buffer *buffer,
3043 unsigned long payload)
295e3feb 3044{
e364cf4e 3045 struct iso_context *ctx = container_of(base, struct iso_context, base);
fe5ca634 3046 unsigned long flags;
872e330e 3047 int ret = -ENOSYS;
e364cf4e 3048
fe5ca634 3049 spin_lock_irqsave(&ctx->context.ohci->lock, flags);
872e330e
SR		 3050 switch (base->type) {
3051 case FW_ISO_CONTEXT_TRANSMIT:
3052 ret = queue_iso_transmit(ctx, packet, buffer, payload);
3053 break;
3054 case FW_ISO_CONTEXT_RECEIVE:
3055 ret = queue_iso_packet_per_buffer(ctx, packet, buffer, payload);
3056 break;
3057 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3058 ret = queue_iso_buffer_fill(ctx, packet, buffer, payload);
3059 break;
3060 }
fe5ca634
DM		 3061 spin_unlock_irqrestore(&ctx->context.ohci->lock, flags);
3062
2dbd7d7e 3063 return ret;
295e3feb
KH		 3064}
3065
21ebcd12 3066static const struct fw_card_driver ohci_driver = {
ed568912 3067 .enable = ohci_enable,
02d37bed 3068 .read_phy_reg = ohci_read_phy_reg,
ed568912
KH		 3069 .update_phy_reg = ohci_update_phy_reg,
3070 .set_config_rom = ohci_set_config_rom,
3071 .send_request = ohci_send_request,
3072 .send_response = ohci_send_response,
730c32f5 3073 .cancel_packet = ohci_cancel_packet,
ed568912 3074 .enable_phys_dma = ohci_enable_phys_dma,
0fcff4e3
SR		 3075 .read_csr = ohci_read_csr,
3076 .write_csr = ohci_write_csr,
ed568912
KH		 3077
3078 .allocate_iso_context = ohci_allocate_iso_context,
3079 .free_iso_context = ohci_free_iso_context,
872e330e 3080 .set_iso_channels = ohci_set_iso_channels,
ed568912 3081 .queue_iso = ohci_queue_iso,
69cdb726 3082 .start_iso = ohci_start_iso,
b8295668 3083 .stop_iso = ohci_stop_iso,
ed568912
KH		 3084};
3085
ea8d006b 3086#ifdef CONFIG_PPC_PMAC
5da3dac8 3087static void pmac_ohci_on(struct pci_dev *dev)
2ed0f181 3088{
ea8d006b
SR		 3089 if (machine_is(powermac)) {
3090 struct device_node *ofn = pci_device_to_OF_node(dev);
3091
3092 if (ofn) {
3093 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1);
3094 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1);
3095 }
3096 }
2ed0f181
SR		 3097}
3098
5da3dac8 3099static void pmac_ohci_off(struct pci_dev *dev)
2ed0f181
SR		 3100{
3101 if (machine_is(powermac)) {
3102 struct device_node *ofn = pci_device_to_OF_node(dev);
3103
3104 if (ofn) {
3105 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0);
3106 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0);
3107 }
3108 }
3109}
3110#else
5da3dac8
SR		 3111static inline void pmac_ohci_on(struct pci_dev *dev) {}
3112static inline void pmac_ohci_off(struct pci_dev *dev) {}
ea8d006b
SR		 3113#endif /* CONFIG_PPC_PMAC */
3114
53dca511
SR		 3115static int __devinit pci_probe(struct pci_dev *dev,
3116 const struct pci_device_id *ent)
2ed0f181
SR		 3117{
3118 struct fw_ohci *ohci;
aa0170ff 3119 u32 bus_options, max_receive, link_speed, version;
2ed0f181 3120 u64 guid;
dd23736e 3121 int i, err;
2ed0f181
SR		 3122 size_t size;
3123
2d826cc5 3124 ohci = kzalloc(sizeof(*ohci), GFP_KERNEL);
ed568912 3125 if (ohci == NULL) {
7007a076
SR		 3126 err = -ENOMEM;
3127 goto fail;
ed568912
KH		 3128 }
3129
3130 fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev);
3131
5da3dac8 3132 pmac_ohci_on(dev);
130d5496 3133
d79406dd
KH		 3134 err = pci_enable_device(dev);
3135 if (err) {
7007a076 3136 fw_error("Failed to enable OHCI hardware\n");
bd7dee63 3137 goto fail_free;
ed568912
KH		 3138 }
3139
3140 pci_set_master(dev);
3141 pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0);
3142 pci_set_drvdata(dev, ohci);
3143
3144 spin_lock_init(&ohci->lock);
02d37bed 3145 mutex_init(&ohci->phy_reg_mutex);
ed568912
KH		 3146
3147 tasklet_init(&ohci->bus_reset_tasklet,
3148 bus_reset_tasklet, (unsigned long)ohci);
3149
d79406dd
KH		 3150 err = pci_request_region(dev, 0, ohci_driver_name);
3151 if (err) {
ed568912 3152 fw_error("MMIO resource unavailable\n");
d79406dd 3153 goto fail_disable;
ed568912
KH		 3154 }
3155
3156 ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE);
3157 if (ohci->registers == NULL) {
3158 fw_error("Failed to remap registers\n");
d79406dd
KH		 3159 err = -ENXIO;
3160 goto fail_iomem;
ed568912
KH		 3161 }
3162
4a635593 3163 for (i = 0; i < ARRAY_SIZE(ohci_quirks); i++)
9993e0fe
SR		 3164 if ((ohci_quirks[i].vendor == dev->vendor) &&
3165 (ohci_quirks[i].device == (unsigned short)PCI_ANY_ID ||
3166 ohci_quirks[i].device == dev->device) &&
3167 (ohci_quirks[i].revision == (unsigned short)PCI_ANY_ID ||
3168 ohci_quirks[i].revision >= dev->revision)) {
4a635593
SR		 3169 ohci->quirks = ohci_quirks[i].flags;
3170 break;
3171 }
3e9cc2f3
SR		 3172 if (param_quirks)
3173 ohci->quirks = param_quirks;
b677532b 3174
ec766a79
CL		 3175 /*
3176 * Because dma_alloc_coherent() allocates at least one page,
3177 * we save space by using a common buffer for the AR request/
3178 * response descriptors and the self IDs buffer.
3179 */
3180 BUILD_BUG_ON(AR_BUFFERS * sizeof(struct descriptor) > PAGE_SIZE/4);
3181 BUILD_BUG_ON(SELF_ID_BUF_SIZE > PAGE_SIZE/2);
3182 ohci->misc_buffer = dma_alloc_coherent(ohci->card.device,
3183 PAGE_SIZE,
3184 &ohci->misc_buffer_bus,
3185 GFP_KERNEL);
3186 if (!ohci->misc_buffer) {
3187 err = -ENOMEM;
3188 goto fail_iounmap;
3189 }
3190
3191 err = ar_context_init(&ohci->ar_request_ctx, ohci, 0,
7a39d8b8
CL		 3192 OHCI1394_AsReqRcvContextControlSet);
3193 if (err < 0)
ec766a79 3194 goto fail_misc_buf;
ed568912 3195
ec766a79 3196 err = ar_context_init(&ohci->ar_response_ctx, ohci, PAGE_SIZE/4,
7a39d8b8
CL		 3197 OHCI1394_AsRspRcvContextControlSet);
3198 if (err < 0)
3199 goto fail_arreq_ctx;
ed568912 3200
c088ab30
CL		 3201 err = context_init(&ohci->at_request_ctx, ohci,
3202 OHCI1394_AsReqTrContextControlSet, handle_at_packet);
3203 if (err < 0)
3204 goto fail_arrsp_ctx;
ed568912 3205
c088ab30
CL		 3206 err = context_init(&ohci->at_response_ctx, ohci,
3207 OHCI1394_AsRspTrContextControlSet, handle_at_packet);
3208 if (err < 0)
3209 goto fail_atreq_ctx;
ed568912 3210
ed568912 3211 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0);
4802f16d
SR		 3212 ohci->ir_context_channels = ~0ULL;
3213 ohci->ir_context_mask = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet);
ed568912 3214 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0);
dd23736e
ML		 3215 ohci->n_ir = hweight32(ohci->ir_context_mask);
3216 size = sizeof(struct iso_context) * ohci->n_ir;
4802f16d 3217 ohci->ir_context_list = kzalloc(size, GFP_KERNEL);
ed568912
KH		 3218
3219 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0);
4802f16d 3220 ohci->it_context_mask = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet);
ed568912 3221 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0);
dd23736e
ML		 3222 ohci->n_it = hweight32(ohci->it_context_mask);
3223 size = sizeof(struct iso_context) * ohci->n_it;
4802f16d 3224 ohci->it_context_list = kzalloc(size, GFP_KERNEL);
ed568912
KH		 3225
3226 if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) {
d79406dd 3227 err = -ENOMEM;
7007a076 3228 goto fail_contexts;
ed568912
KH		 3229 }
3230
ec766a79
CL		 3231 ohci->self_id_cpu = ohci->misc_buffer + PAGE_SIZE/2;
3232 ohci->self_id_bus = ohci->misc_buffer_bus + PAGE_SIZE/2;
ed568912 3233
ed568912
KH		 3234 bus_options = reg_read(ohci, OHCI1394_BusOptions);
3235 max_receive = (bus_options >> 12) & 0xf;
3236 link_speed = bus_options & 0x7;
3237 guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) |
3238 reg_read(ohci, OHCI1394_GUIDLo);
3239
d79406dd 3240 err = fw_card_add(&ohci->card, max_receive, link_speed, guid);
e1eff7a3 3241 if (err)
ec766a79 3242 goto fail_contexts;
ed568912 3243
6fdb2ee2
SR		 3244 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
3245 fw_notify("Added fw-ohci device %s, OHCI v%x.%x, "
3246 "%d IR + %d IT contexts, quirks 0x%x\n",
3247 dev_name(&dev->dev), version >> 16, version & 0xff,
dd23736e 3248 ohci->n_ir, ohci->n_it, ohci->quirks);
e1eff7a3 3249
ed568912 3250 return 0;
d79406dd 3251
7007a076 3252 fail_contexts:
d79406dd 3253 kfree(ohci->ir_context_list);
7007a076
SR		 3254 kfree(ohci->it_context_list);
3255 context_release(&ohci->at_response_ctx);
c088ab30 3256 fail_atreq_ctx:
7007a076 3257 context_release(&ohci->at_request_ctx);
c088ab30 3258 fail_arrsp_ctx:
7007a076 3259 ar_context_release(&ohci->ar_response_ctx);
7a39d8b8 3260 fail_arreq_ctx:
7007a076 3261 ar_context_release(&ohci->ar_request_ctx);
ec766a79
CL		 3262 fail_misc_buf:
3263 dma_free_coherent(ohci->card.device, PAGE_SIZE,
3264 ohci->misc_buffer, ohci->misc_buffer_bus);
7a39d8b8 3265 fail_iounmap:
d79406dd
KH		 3266 pci_iounmap(dev, ohci->registers);
3267 fail_iomem:
3268 pci_release_region(dev, 0);
3269 fail_disable:
3270 pci_disable_device(dev);
bd7dee63
SR		 3271 fail_free:
3272 kfree(&ohci->card);
5da3dac8 3273 pmac_ohci_off(dev);
7007a076
SR		 3274 fail:
3275 if (err == -ENOMEM)
3276 fw_error("Out of memory\n");
d79406dd
KH		 3277
3278 return err;
ed568912
KH		 3279}
3280
3281static void pci_remove(struct pci_dev *dev)
3282{
3283 struct fw_ohci *ohci;
3284
3285 ohci = pci_get_drvdata(dev);
e254a4b4
KH		 3286 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
3287 flush_writes(ohci);
ed568912
KH		 3288 fw_core_remove_card(&ohci->card);
3289
c781c06d
KH		 3290 /*
3291 * FIXME: Fail all pending packets here, now that the upper
3292 * layers can't queue any more.
3293 */
ed568912
KH		 3294
3295 software_reset(ohci);
3296 free_irq(dev->irq, ohci);
a55709ba
JF		 3297
3298 if (ohci->next_config_rom && ohci->next_config_rom != ohci->config_rom)
3299 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
3300 ohci->next_config_rom, ohci->next_config_rom_bus);
3301 if (ohci->config_rom)
3302 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
3303 ohci->config_rom, ohci->config_rom_bus);
a55709ba
JF		 3304 ar_context_release(&ohci->ar_request_ctx);
3305 ar_context_release(&ohci->ar_response_ctx);
ec766a79
CL		 3306 dma_free_coherent(ohci->card.device, PAGE_SIZE,
3307 ohci->misc_buffer, ohci->misc_buffer_bus);
a55709ba
JF		 3308 context_release(&ohci->at_request_ctx);
3309 context_release(&ohci->at_response_ctx);
d79406dd
KH		 3310 kfree(ohci->it_context_list);
3311 kfree(ohci->ir_context_list);
262444ee 3312 pci_disable_msi(dev);
d79406dd
KH		 3313 pci_iounmap(dev, ohci->registers);
3314 pci_release_region(dev, 0);
3315 pci_disable_device(dev);
bd7dee63 3316 kfree(&ohci->card);
5da3dac8 3317 pmac_ohci_off(dev);
ea8d006b 3318
ed568912
KH		 3319 fw_notify("Removed fw-ohci device.\n");
3320}
3321
2aef469a 3322#ifdef CONFIG_PM
2ed0f181 3323static int pci_suspend(struct pci_dev *dev, pm_message_t state)
2aef469a 3324{
2ed0f181 3325 struct fw_ohci *ohci = pci_get_drvdata(dev);
2aef469a
KH		 3326 int err;
3327
3328 software_reset(ohci);
2ed0f181 3329 free_irq(dev->irq, ohci);
262444ee 3330 pci_disable_msi(dev);
2ed0f181 3331 err = pci_save_state(dev);
2aef469a 3332 if (err) {
8a8cea27 3333 fw_error("pci_save_state failed\n");
2aef469a
KH		 3334 return err;
3335 }
2ed0f181 3336 err = pci_set_power_state(dev, pci_choose_state(dev, state));
55111428
SR		 3337 if (err)
3338 fw_error("pci_set_power_state failed with %d\n", err);
5da3dac8 3339 pmac_ohci_off(dev);
ea8d006b 3340
2aef469a
KH		 3341 return 0;
3342}
3343
2ed0f181 3344static int pci_resume(struct pci_dev *dev)
2aef469a 3345{
2ed0f181 3346 struct fw_ohci *ohci = pci_get_drvdata(dev);
2aef469a
KH		 3347 int err;
3348
5da3dac8 3349 pmac_ohci_on(dev);
2ed0f181
SR		 3350 pci_set_power_state(dev, PCI_D0);
3351 pci_restore_state(dev);
3352 err = pci_enable_device(dev);
2aef469a 3353 if (err) {
8a8cea27 3354 fw_error("pci_enable_device failed\n");
2aef469a
KH		 3355 return err;
3356 }
3357
8662b6b0
ML		 3358 /* Some systems don't setup GUID register on resume from ram */
3359 if (!reg_read(ohci, OHCI1394_GUIDLo) &&
3360 !reg_read(ohci, OHCI1394_GUIDHi)) {
3361 reg_write(ohci, OHCI1394_GUIDLo, (u32)ohci->card.guid);
3362 reg_write(ohci, OHCI1394_GUIDHi, (u32)(ohci->card.guid >> 32));
3363 }
3364
dd23736e
ML		 3365 err = ohci_enable(&ohci->card, NULL, 0);
3366
3367 if (err)
3368 return err;
3369
3370 ohci_resume_iso_dma(ohci);
3371 return 0;
2aef469a
KH		 3372}
3373#endif
3374
a67483d2 3375static const struct pci_device_id pci_table[] = {
ed568912
KH		 3376 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) },
3377 { }
3378};
3379
3380MODULE_DEVICE_TABLE(pci, pci_table);
3381
3382static struct pci_driver fw_ohci_pci_driver = {
3383 .name = ohci_driver_name,
3384 .id_table = pci_table,
3385 .probe = pci_probe,
3386 .remove = pci_remove,
2aef469a
KH		 3387#ifdef CONFIG_PM
3388 .resume = pci_resume,
3389 .suspend = pci_suspend,
3390#endif
ed568912
KH		 3391};
3392
3393MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
3394MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
3395MODULE_LICENSE("GPL");
3396
1e4c7b0d
OH		 3397/* Provide a module alias so root-on-sbp2 initrds don't break. */
3398#ifndef CONFIG_IEEE1394_OHCI1394_MODULE
3399MODULE_ALIAS("ohci1394");
3400#endif
3401
ed568912
KH		 3402static int __init fw_ohci_init(void)
3403{
3404 return pci_register_driver(&fw_ohci_pci_driver);
3405}
3406
3407static void __exit fw_ohci_cleanup(void)
3408{
3409 pci_unregister_driver(&fw_ohci_pci_driver);
3410}
3411
3412module_init(fw_ohci_init);
3413module_exit(fw_ohci_cleanup);
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