]>
Commit | Line | Data |
---|---|---|
c781c06d KH |
1 | /* |
2 | * Driver for OHCI 1394 controllers | |
ed568912 | 3 | * |
ed568912 KH |
4 | * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net> |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software Foundation, | |
18 | * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
19 | */ | |
20 | ||
e524f616 | 21 | #include <linux/compiler.h> |
ed568912 | 22 | #include <linux/delay.h> |
e8ca9702 | 23 | #include <linux/device.h> |
cf3e72fd | 24 | #include <linux/dma-mapping.h> |
77c9a5da | 25 | #include <linux/firewire.h> |
e8ca9702 | 26 | #include <linux/firewire-constants.h> |
c26f0234 | 27 | #include <linux/gfp.h> |
a7fb60db SR |
28 | #include <linux/init.h> |
29 | #include <linux/interrupt.h> | |
e8ca9702 | 30 | #include <linux/io.h> |
a7fb60db | 31 | #include <linux/kernel.h> |
e8ca9702 | 32 | #include <linux/list.h> |
faa2fb4e | 33 | #include <linux/mm.h> |
a7fb60db | 34 | #include <linux/module.h> |
ad3c0fe8 | 35 | #include <linux/moduleparam.h> |
a7fb60db | 36 | #include <linux/pci.h> |
fc383796 | 37 | #include <linux/pci_ids.h> |
c26f0234 | 38 | #include <linux/spinlock.h> |
e8ca9702 | 39 | #include <linux/string.h> |
cf3e72fd | 40 | |
3dcdc500 | 41 | #include <asm/atomic.h> |
e8ca9702 | 42 | #include <asm/byteorder.h> |
c26f0234 | 43 | #include <asm/page.h> |
ee71c2f9 | 44 | #include <asm/system.h> |
ed568912 | 45 | |
ea8d006b SR |
46 | #ifdef CONFIG_PPC_PMAC |
47 | #include <asm/pmac_feature.h> | |
48 | #endif | |
49 | ||
77c9a5da SR |
50 | #include "core.h" |
51 | #include "ohci.h" | |
ed568912 | 52 | |
a77754a7 KH |
53 | #define DESCRIPTOR_OUTPUT_MORE 0 |
54 | #define DESCRIPTOR_OUTPUT_LAST (1 << 12) | |
55 | #define DESCRIPTOR_INPUT_MORE (2 << 12) | |
56 | #define DESCRIPTOR_INPUT_LAST (3 << 12) | |
57 | #define DESCRIPTOR_STATUS (1 << 11) | |
58 | #define DESCRIPTOR_KEY_IMMEDIATE (2 << 8) | |
59 | #define DESCRIPTOR_PING (1 << 7) | |
60 | #define DESCRIPTOR_YY (1 << 6) | |
61 | #define DESCRIPTOR_NO_IRQ (0 << 4) | |
62 | #define DESCRIPTOR_IRQ_ERROR (1 << 4) | |
63 | #define DESCRIPTOR_IRQ_ALWAYS (3 << 4) | |
64 | #define DESCRIPTOR_BRANCH_ALWAYS (3 << 2) | |
65 | #define DESCRIPTOR_WAIT (3 << 0) | |
ed568912 KH |
66 | |
67 | struct descriptor { | |
68 | __le16 req_count; | |
69 | __le16 control; | |
70 | __le32 data_address; | |
71 | __le32 branch_address; | |
72 | __le16 res_count; | |
73 | __le16 transfer_status; | |
74 | } __attribute__((aligned(16))); | |
75 | ||
295e3feb KH |
76 | struct db_descriptor { |
77 | __le16 first_size; | |
78 | __le16 control; | |
79 | __le16 second_req_count; | |
80 | __le16 first_req_count; | |
81 | __le32 branch_address; | |
82 | __le16 second_res_count; | |
83 | __le16 first_res_count; | |
84 | __le32 reserved0; | |
85 | __le32 first_buffer; | |
86 | __le32 second_buffer; | |
87 | __le32 reserved1; | |
88 | } __attribute__((aligned(16))); | |
89 | ||
a77754a7 KH |
90 | #define CONTROL_SET(regs) (regs) |
91 | #define CONTROL_CLEAR(regs) ((regs) + 4) | |
92 | #define COMMAND_PTR(regs) ((regs) + 12) | |
93 | #define CONTEXT_MATCH(regs) ((regs) + 16) | |
72e318e0 | 94 | |
32b46093 | 95 | struct ar_buffer { |
ed568912 | 96 | struct descriptor descriptor; |
32b46093 KH |
97 | struct ar_buffer *next; |
98 | __le32 data[0]; | |
99 | }; | |
ed568912 | 100 | |
32b46093 KH |
101 | struct ar_context { |
102 | struct fw_ohci *ohci; | |
103 | struct ar_buffer *current_buffer; | |
104 | struct ar_buffer *last_buffer; | |
105 | void *pointer; | |
72e318e0 | 106 | u32 regs; |
ed568912 KH |
107 | struct tasklet_struct tasklet; |
108 | }; | |
109 | ||
30200739 KH |
110 | struct context; |
111 | ||
112 | typedef int (*descriptor_callback_t)(struct context *ctx, | |
113 | struct descriptor *d, | |
114 | struct descriptor *last); | |
fe5ca634 DM |
115 | |
116 | /* | |
117 | * A buffer that contains a block of DMA-able coherent memory used for | |
118 | * storing a portion of a DMA descriptor program. | |
119 | */ | |
120 | struct descriptor_buffer { | |
121 | struct list_head list; | |
122 | dma_addr_t buffer_bus; | |
123 | size_t buffer_size; | |
124 | size_t used; | |
125 | struct descriptor buffer[0]; | |
126 | }; | |
127 | ||
30200739 | 128 | struct context { |
373b2edd | 129 | struct fw_ohci *ohci; |
30200739 | 130 | u32 regs; |
fe5ca634 | 131 | int total_allocation; |
373b2edd | 132 | |
fe5ca634 DM |
133 | /* |
134 | * List of page-sized buffers for storing DMA descriptors. | |
135 | * Head of list contains buffers in use and tail of list contains | |
136 | * free buffers. | |
137 | */ | |
138 | struct list_head buffer_list; | |
139 | ||
140 | /* | |
141 | * Pointer to a buffer inside buffer_list that contains the tail | |
142 | * end of the current DMA program. | |
143 | */ | |
144 | struct descriptor_buffer *buffer_tail; | |
145 | ||
146 | /* | |
147 | * The descriptor containing the branch address of the first | |
148 | * descriptor that has not yet been filled by the device. | |
149 | */ | |
150 | struct descriptor *last; | |
151 | ||
152 | /* | |
153 | * The last descriptor in the DMA program. It contains the branch | |
154 | * address that must be updated upon appending a new descriptor. | |
155 | */ | |
156 | struct descriptor *prev; | |
30200739 KH |
157 | |
158 | descriptor_callback_t callback; | |
159 | ||
373b2edd | 160 | struct tasklet_struct tasklet; |
30200739 | 161 | }; |
30200739 | 162 | |
a77754a7 KH |
163 | #define IT_HEADER_SY(v) ((v) << 0) |
164 | #define IT_HEADER_TCODE(v) ((v) << 4) | |
165 | #define IT_HEADER_CHANNEL(v) ((v) << 8) | |
166 | #define IT_HEADER_TAG(v) ((v) << 14) | |
167 | #define IT_HEADER_SPEED(v) ((v) << 16) | |
168 | #define IT_HEADER_DATA_LENGTH(v) ((v) << 16) | |
ed568912 KH |
169 | |
170 | struct iso_context { | |
171 | struct fw_iso_context base; | |
30200739 | 172 | struct context context; |
0642b657 | 173 | int excess_bytes; |
9b32d5f3 KH |
174 | void *header; |
175 | size_t header_length; | |
ed568912 KH |
176 | }; |
177 | ||
178 | #define CONFIG_ROM_SIZE 1024 | |
179 | ||
180 | struct fw_ohci { | |
181 | struct fw_card card; | |
182 | ||
183 | __iomem char *registers; | |
184 | dma_addr_t self_id_bus; | |
185 | __le32 *self_id_cpu; | |
186 | struct tasklet_struct bus_reset_tasklet; | |
e636fe25 | 187 | int node_id; |
ed568912 | 188 | int generation; |
e09770db | 189 | int request_generation; /* for timestamping incoming requests */ |
3dcdc500 | 190 | atomic_t bus_seconds; |
95984f62 SR |
191 | |
192 | bool use_dualbuffer; | |
11bf20ad | 193 | bool old_uninorth; |
d34316a4 | 194 | bool bus_reset_packet_quirk; |
ed568912 | 195 | |
c781c06d KH |
196 | /* |
197 | * Spinlock for accessing fw_ohci data. Never call out of | |
198 | * this driver with this lock held. | |
199 | */ | |
ed568912 KH |
200 | spinlock_t lock; |
201 | u32 self_id_buffer[512]; | |
202 | ||
203 | /* Config rom buffers */ | |
204 | __be32 *config_rom; | |
205 | dma_addr_t config_rom_bus; | |
206 | __be32 *next_config_rom; | |
207 | dma_addr_t next_config_rom_bus; | |
208 | u32 next_header; | |
209 | ||
210 | struct ar_context ar_request_ctx; | |
211 | struct ar_context ar_response_ctx; | |
f319b6a0 KH |
212 | struct context at_request_ctx; |
213 | struct context at_response_ctx; | |
ed568912 KH |
214 | |
215 | u32 it_context_mask; | |
216 | struct iso_context *it_context_list; | |
4817ed24 | 217 | u64 ir_context_channels; |
ed568912 KH |
218 | u32 ir_context_mask; |
219 | struct iso_context *ir_context_list; | |
220 | }; | |
221 | ||
95688e97 | 222 | static inline struct fw_ohci *fw_ohci(struct fw_card *card) |
ed568912 KH |
223 | { |
224 | return container_of(card, struct fw_ohci, card); | |
225 | } | |
226 | ||
295e3feb KH |
227 | #define IT_CONTEXT_CYCLE_MATCH_ENABLE 0x80000000 |
228 | #define IR_CONTEXT_BUFFER_FILL 0x80000000 | |
229 | #define IR_CONTEXT_ISOCH_HEADER 0x40000000 | |
230 | #define IR_CONTEXT_CYCLE_MATCH_ENABLE 0x20000000 | |
231 | #define IR_CONTEXT_MULTI_CHANNEL_MODE 0x10000000 | |
232 | #define IR_CONTEXT_DUAL_BUFFER_MODE 0x08000000 | |
ed568912 KH |
233 | |
234 | #define CONTEXT_RUN 0x8000 | |
235 | #define CONTEXT_WAKE 0x1000 | |
236 | #define CONTEXT_DEAD 0x0800 | |
237 | #define CONTEXT_ACTIVE 0x0400 | |
238 | ||
8b7b6afa | 239 | #define OHCI1394_MAX_AT_REQ_RETRIES 0xf |
ed568912 KH |
240 | #define OHCI1394_MAX_AT_RESP_RETRIES 0x2 |
241 | #define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8 | |
242 | ||
ed568912 KH |
243 | #define OHCI1394_REGISTER_SIZE 0x800 |
244 | #define OHCI_LOOP_COUNT 500 | |
245 | #define OHCI1394_PCI_HCI_Control 0x40 | |
246 | #define SELF_ID_BUF_SIZE 0x800 | |
32b46093 | 247 | #define OHCI_TCODE_PHY_PACKET 0x0e |
e364cf4e | 248 | #define OHCI_VERSION_1_1 0x010010 |
0edeefd9 | 249 | |
ed568912 KH |
250 | static char ohci_driver_name[] = KBUILD_MODNAME; |
251 | ||
ad3c0fe8 SR |
252 | #ifdef CONFIG_FIREWIRE_OHCI_DEBUG |
253 | ||
a007bb85 | 254 | #define OHCI_PARAM_DEBUG_AT_AR 1 |
ad3c0fe8 | 255 | #define OHCI_PARAM_DEBUG_SELFIDS 2 |
a007bb85 SR |
256 | #define OHCI_PARAM_DEBUG_IRQS 4 |
257 | #define OHCI_PARAM_DEBUG_BUSRESETS 8 /* only effective before chip init */ | |
ad3c0fe8 SR |
258 | |
259 | static int param_debug; | |
260 | module_param_named(debug, param_debug, int, 0644); | |
261 | MODULE_PARM_DESC(debug, "Verbose logging (default = 0" | |
ad3c0fe8 | 262 | ", AT/AR events = " __stringify(OHCI_PARAM_DEBUG_AT_AR) |
a007bb85 SR |
263 | ", self-IDs = " __stringify(OHCI_PARAM_DEBUG_SELFIDS) |
264 | ", IRQs = " __stringify(OHCI_PARAM_DEBUG_IRQS) | |
265 | ", busReset events = " __stringify(OHCI_PARAM_DEBUG_BUSRESETS) | |
ad3c0fe8 SR |
266 | ", or a combination, or all = -1)"); |
267 | ||
268 | static void log_irqs(u32 evt) | |
269 | { | |
a007bb85 SR |
270 | if (likely(!(param_debug & |
271 | (OHCI_PARAM_DEBUG_IRQS | OHCI_PARAM_DEBUG_BUSRESETS)))) | |
272 | return; | |
273 | ||
274 | if (!(param_debug & OHCI_PARAM_DEBUG_IRQS) && | |
275 | !(evt & OHCI1394_busReset)) | |
ad3c0fe8 SR |
276 | return; |
277 | ||
5ed1f321 | 278 | fw_notify("IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt, |
161b96e7 SR |
279 | evt & OHCI1394_selfIDComplete ? " selfID" : "", |
280 | evt & OHCI1394_RQPkt ? " AR_req" : "", | |
281 | evt & OHCI1394_RSPkt ? " AR_resp" : "", | |
282 | evt & OHCI1394_reqTxComplete ? " AT_req" : "", | |
283 | evt & OHCI1394_respTxComplete ? " AT_resp" : "", | |
284 | evt & OHCI1394_isochRx ? " IR" : "", | |
285 | evt & OHCI1394_isochTx ? " IT" : "", | |
286 | evt & OHCI1394_postedWriteErr ? " postedWriteErr" : "", | |
287 | evt & OHCI1394_cycleTooLong ? " cycleTooLong" : "", | |
288 | evt & OHCI1394_cycle64Seconds ? " cycle64Seconds" : "", | |
5ed1f321 | 289 | evt & OHCI1394_cycleInconsistent ? " cycleInconsistent" : "", |
161b96e7 SR |
290 | evt & OHCI1394_regAccessFail ? " regAccessFail" : "", |
291 | evt & OHCI1394_busReset ? " busReset" : "", | |
292 | evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt | | |
293 | OHCI1394_RSPkt | OHCI1394_reqTxComplete | | |
294 | OHCI1394_respTxComplete | OHCI1394_isochRx | | |
295 | OHCI1394_isochTx | OHCI1394_postedWriteErr | | |
296 | OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds | | |
5ed1f321 | 297 | OHCI1394_cycleInconsistent | |
161b96e7 | 298 | OHCI1394_regAccessFail | OHCI1394_busReset) |
ad3c0fe8 SR |
299 | ? " ?" : ""); |
300 | } | |
301 | ||
302 | static const char *speed[] = { | |
303 | [0] = "S100", [1] = "S200", [2] = "S400", [3] = "beta", | |
304 | }; | |
305 | static const char *power[] = { | |
306 | [0] = "+0W", [1] = "+15W", [2] = "+30W", [3] = "+45W", | |
307 | [4] = "-3W", [5] = " ?W", [6] = "-3..-6W", [7] = "-3..-10W", | |
308 | }; | |
309 | static const char port[] = { '.', '-', 'p', 'c', }; | |
310 | ||
311 | static char _p(u32 *s, int shift) | |
312 | { | |
313 | return port[*s >> shift & 3]; | |
314 | } | |
315 | ||
08ddb2f4 | 316 | static void log_selfids(int node_id, int generation, int self_id_count, u32 *s) |
ad3c0fe8 SR |
317 | { |
318 | if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS))) | |
319 | return; | |
320 | ||
161b96e7 SR |
321 | fw_notify("%d selfIDs, generation %d, local node ID %04x\n", |
322 | self_id_count, generation, node_id); | |
ad3c0fe8 SR |
323 | |
324 | for (; self_id_count--; ++s) | |
325 | if ((*s & 1 << 23) == 0) | |
161b96e7 SR |
326 | fw_notify("selfID 0: %08x, phy %d [%c%c%c] " |
327 | "%s gc=%d %s %s%s%s\n", | |
328 | *s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2), | |
329 | speed[*s >> 14 & 3], *s >> 16 & 63, | |
330 | power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "", | |
331 | *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : ""); | |
ad3c0fe8 | 332 | else |
161b96e7 SR |
333 | fw_notify("selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n", |
334 | *s, *s >> 24 & 63, | |
335 | _p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10), | |
336 | _p(s, 8), _p(s, 6), _p(s, 4), _p(s, 2)); | |
ad3c0fe8 SR |
337 | } |
338 | ||
339 | static const char *evts[] = { | |
340 | [0x00] = "evt_no_status", [0x01] = "-reserved-", | |
341 | [0x02] = "evt_long_packet", [0x03] = "evt_missing_ack", | |
342 | [0x04] = "evt_underrun", [0x05] = "evt_overrun", | |
343 | [0x06] = "evt_descriptor_read", [0x07] = "evt_data_read", | |
344 | [0x08] = "evt_data_write", [0x09] = "evt_bus_reset", | |
345 | [0x0a] = "evt_timeout", [0x0b] = "evt_tcode_err", | |
346 | [0x0c] = "-reserved-", [0x0d] = "-reserved-", | |
347 | [0x0e] = "evt_unknown", [0x0f] = "evt_flushed", | |
348 | [0x10] = "-reserved-", [0x11] = "ack_complete", | |
349 | [0x12] = "ack_pending ", [0x13] = "-reserved-", | |
350 | [0x14] = "ack_busy_X", [0x15] = "ack_busy_A", | |
351 | [0x16] = "ack_busy_B", [0x17] = "-reserved-", | |
352 | [0x18] = "-reserved-", [0x19] = "-reserved-", | |
353 | [0x1a] = "-reserved-", [0x1b] = "ack_tardy", | |
354 | [0x1c] = "-reserved-", [0x1d] = "ack_data_error", | |
355 | [0x1e] = "ack_type_error", [0x1f] = "-reserved-", | |
356 | [0x20] = "pending/cancelled", | |
357 | }; | |
358 | static const char *tcodes[] = { | |
359 | [0x0] = "QW req", [0x1] = "BW req", | |
360 | [0x2] = "W resp", [0x3] = "-reserved-", | |
361 | [0x4] = "QR req", [0x5] = "BR req", | |
362 | [0x6] = "QR resp", [0x7] = "BR resp", | |
363 | [0x8] = "cycle start", [0x9] = "Lk req", | |
364 | [0xa] = "async stream packet", [0xb] = "Lk resp", | |
365 | [0xc] = "-reserved-", [0xd] = "-reserved-", | |
366 | [0xe] = "link internal", [0xf] = "-reserved-", | |
367 | }; | |
368 | static const char *phys[] = { | |
369 | [0x0] = "phy config packet", [0x1] = "link-on packet", | |
370 | [0x2] = "self-id packet", [0x3] = "-reserved-", | |
371 | }; | |
372 | ||
373 | static void log_ar_at_event(char dir, int speed, u32 *header, int evt) | |
374 | { | |
375 | int tcode = header[0] >> 4 & 0xf; | |
376 | char specific[12]; | |
377 | ||
378 | if (likely(!(param_debug & OHCI_PARAM_DEBUG_AT_AR))) | |
379 | return; | |
380 | ||
381 | if (unlikely(evt >= ARRAY_SIZE(evts))) | |
382 | evt = 0x1f; | |
383 | ||
08ddb2f4 | 384 | if (evt == OHCI1394_evt_bus_reset) { |
161b96e7 SR |
385 | fw_notify("A%c evt_bus_reset, generation %d\n", |
386 | dir, (header[2] >> 16) & 0xff); | |
08ddb2f4 SR |
387 | return; |
388 | } | |
389 | ||
ad3c0fe8 | 390 | if (header[0] == ~header[1]) { |
161b96e7 SR |
391 | fw_notify("A%c %s, %s, %08x\n", |
392 | dir, evts[evt], phys[header[0] >> 30 & 0x3], header[0]); | |
ad3c0fe8 SR |
393 | return; |
394 | } | |
395 | ||
396 | switch (tcode) { | |
397 | case 0x0: case 0x6: case 0x8: | |
398 | snprintf(specific, sizeof(specific), " = %08x", | |
399 | be32_to_cpu((__force __be32)header[3])); | |
400 | break; | |
401 | case 0x1: case 0x5: case 0x7: case 0x9: case 0xb: | |
402 | snprintf(specific, sizeof(specific), " %x,%x", | |
403 | header[3] >> 16, header[3] & 0xffff); | |
404 | break; | |
405 | default: | |
406 | specific[0] = '\0'; | |
407 | } | |
408 | ||
409 | switch (tcode) { | |
410 | case 0xe: case 0xa: | |
161b96e7 | 411 | fw_notify("A%c %s, %s\n", dir, evts[evt], tcodes[tcode]); |
ad3c0fe8 SR |
412 | break; |
413 | case 0x0: case 0x1: case 0x4: case 0x5: case 0x9: | |
161b96e7 SR |
414 | fw_notify("A%c spd %x tl %02x, " |
415 | "%04x -> %04x, %s, " | |
416 | "%s, %04x%08x%s\n", | |
417 | dir, speed, header[0] >> 10 & 0x3f, | |
418 | header[1] >> 16, header[0] >> 16, evts[evt], | |
419 | tcodes[tcode], header[1] & 0xffff, header[2], specific); | |
ad3c0fe8 SR |
420 | break; |
421 | default: | |
161b96e7 SR |
422 | fw_notify("A%c spd %x tl %02x, " |
423 | "%04x -> %04x, %s, " | |
424 | "%s%s\n", | |
425 | dir, speed, header[0] >> 10 & 0x3f, | |
426 | header[1] >> 16, header[0] >> 16, evts[evt], | |
427 | tcodes[tcode], specific); | |
ad3c0fe8 SR |
428 | } |
429 | } | |
430 | ||
431 | #else | |
432 | ||
433 | #define log_irqs(evt) | |
08ddb2f4 | 434 | #define log_selfids(node_id, generation, self_id_count, sid) |
ad3c0fe8 SR |
435 | #define log_ar_at_event(dir, speed, header, evt) |
436 | ||
437 | #endif /* CONFIG_FIREWIRE_OHCI_DEBUG */ | |
438 | ||
95688e97 | 439 | static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data) |
ed568912 KH |
440 | { |
441 | writel(data, ohci->registers + offset); | |
442 | } | |
443 | ||
95688e97 | 444 | static inline u32 reg_read(const struct fw_ohci *ohci, int offset) |
ed568912 KH |
445 | { |
446 | return readl(ohci->registers + offset); | |
447 | } | |
448 | ||
95688e97 | 449 | static inline void flush_writes(const struct fw_ohci *ohci) |
ed568912 KH |
450 | { |
451 | /* Do a dummy read to flush writes. */ | |
452 | reg_read(ohci, OHCI1394_Version); | |
453 | } | |
454 | ||
53dca511 SR |
455 | static int ohci_update_phy_reg(struct fw_card *card, int addr, |
456 | int clear_bits, int set_bits) | |
ed568912 KH |
457 | { |
458 | struct fw_ohci *ohci = fw_ohci(card); | |
459 | u32 val, old; | |
460 | ||
461 | reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr)); | |
362e901c | 462 | flush_writes(ohci); |
ed568912 KH |
463 | msleep(2); |
464 | val = reg_read(ohci, OHCI1394_PhyControl); | |
465 | if ((val & OHCI1394_PhyControl_ReadDone) == 0) { | |
466 | fw_error("failed to set phy reg bits.\n"); | |
467 | return -EBUSY; | |
468 | } | |
469 | ||
470 | old = OHCI1394_PhyControl_ReadData(val); | |
471 | old = (old & ~clear_bits) | set_bits; | |
472 | reg_write(ohci, OHCI1394_PhyControl, | |
473 | OHCI1394_PhyControl_Write(addr, old)); | |
474 | ||
475 | return 0; | |
476 | } | |
477 | ||
32b46093 | 478 | static int ar_context_add_page(struct ar_context *ctx) |
ed568912 | 479 | { |
32b46093 KH |
480 | struct device *dev = ctx->ohci->card.device; |
481 | struct ar_buffer *ab; | |
f5101d58 | 482 | dma_addr_t uninitialized_var(ab_bus); |
32b46093 KH |
483 | size_t offset; |
484 | ||
bde1709a | 485 | ab = dma_alloc_coherent(dev, PAGE_SIZE, &ab_bus, GFP_ATOMIC); |
32b46093 KH |
486 | if (ab == NULL) |
487 | return -ENOMEM; | |
488 | ||
a55709ba | 489 | ab->next = NULL; |
2d826cc5 | 490 | memset(&ab->descriptor, 0, sizeof(ab->descriptor)); |
a77754a7 KH |
491 | ab->descriptor.control = cpu_to_le16(DESCRIPTOR_INPUT_MORE | |
492 | DESCRIPTOR_STATUS | | |
493 | DESCRIPTOR_BRANCH_ALWAYS); | |
32b46093 KH |
494 | offset = offsetof(struct ar_buffer, data); |
495 | ab->descriptor.req_count = cpu_to_le16(PAGE_SIZE - offset); | |
496 | ab->descriptor.data_address = cpu_to_le32(ab_bus + offset); | |
497 | ab->descriptor.res_count = cpu_to_le16(PAGE_SIZE - offset); | |
498 | ab->descriptor.branch_address = 0; | |
499 | ||
ec839e43 | 500 | ctx->last_buffer->descriptor.branch_address = cpu_to_le32(ab_bus | 1); |
32b46093 KH |
501 | ctx->last_buffer->next = ab; |
502 | ctx->last_buffer = ab; | |
503 | ||
a77754a7 | 504 | reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE); |
ed568912 | 505 | flush_writes(ctx->ohci); |
32b46093 KH |
506 | |
507 | return 0; | |
ed568912 KH |
508 | } |
509 | ||
a55709ba JF |
510 | static void ar_context_release(struct ar_context *ctx) |
511 | { | |
512 | struct ar_buffer *ab, *ab_next; | |
513 | size_t offset; | |
514 | dma_addr_t ab_bus; | |
515 | ||
516 | for (ab = ctx->current_buffer; ab; ab = ab_next) { | |
517 | ab_next = ab->next; | |
518 | offset = offsetof(struct ar_buffer, data); | |
519 | ab_bus = le32_to_cpu(ab->descriptor.data_address) - offset; | |
520 | dma_free_coherent(ctx->ohci->card.device, PAGE_SIZE, | |
521 | ab, ab_bus); | |
522 | } | |
523 | } | |
524 | ||
11bf20ad SR |
525 | #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32) |
526 | #define cond_le32_to_cpu(v) \ | |
527 | (ohci->old_uninorth ? (__force __u32)(v) : le32_to_cpu(v)) | |
528 | #else | |
529 | #define cond_le32_to_cpu(v) le32_to_cpu(v) | |
530 | #endif | |
531 | ||
32b46093 | 532 | static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer) |
ed568912 | 533 | { |
ed568912 | 534 | struct fw_ohci *ohci = ctx->ohci; |
2639a6fb KH |
535 | struct fw_packet p; |
536 | u32 status, length, tcode; | |
43286568 | 537 | int evt; |
2639a6fb | 538 | |
11bf20ad SR |
539 | p.header[0] = cond_le32_to_cpu(buffer[0]); |
540 | p.header[1] = cond_le32_to_cpu(buffer[1]); | |
541 | p.header[2] = cond_le32_to_cpu(buffer[2]); | |
2639a6fb KH |
542 | |
543 | tcode = (p.header[0] >> 4) & 0x0f; | |
544 | switch (tcode) { | |
545 | case TCODE_WRITE_QUADLET_REQUEST: | |
546 | case TCODE_READ_QUADLET_RESPONSE: | |
32b46093 | 547 | p.header[3] = (__force __u32) buffer[3]; |
2639a6fb | 548 | p.header_length = 16; |
32b46093 | 549 | p.payload_length = 0; |
2639a6fb KH |
550 | break; |
551 | ||
2639a6fb | 552 | case TCODE_READ_BLOCK_REQUEST : |
11bf20ad | 553 | p.header[3] = cond_le32_to_cpu(buffer[3]); |
32b46093 KH |
554 | p.header_length = 16; |
555 | p.payload_length = 0; | |
556 | break; | |
557 | ||
558 | case TCODE_WRITE_BLOCK_REQUEST: | |
2639a6fb KH |
559 | case TCODE_READ_BLOCK_RESPONSE: |
560 | case TCODE_LOCK_REQUEST: | |
561 | case TCODE_LOCK_RESPONSE: | |
11bf20ad | 562 | p.header[3] = cond_le32_to_cpu(buffer[3]); |
2639a6fb | 563 | p.header_length = 16; |
32b46093 | 564 | p.payload_length = p.header[3] >> 16; |
2639a6fb KH |
565 | break; |
566 | ||
567 | case TCODE_WRITE_RESPONSE: | |
568 | case TCODE_READ_QUADLET_REQUEST: | |
32b46093 | 569 | case OHCI_TCODE_PHY_PACKET: |
2639a6fb | 570 | p.header_length = 12; |
32b46093 | 571 | p.payload_length = 0; |
2639a6fb | 572 | break; |
ccff9629 SR |
573 | |
574 | default: | |
575 | /* FIXME: Stop context, discard everything, and restart? */ | |
576 | p.header_length = 0; | |
577 | p.payload_length = 0; | |
2639a6fb | 578 | } |
ed568912 | 579 | |
32b46093 KH |
580 | p.payload = (void *) buffer + p.header_length; |
581 | ||
582 | /* FIXME: What to do about evt_* errors? */ | |
583 | length = (p.header_length + p.payload_length + 3) / 4; | |
11bf20ad | 584 | status = cond_le32_to_cpu(buffer[length]); |
43286568 | 585 | evt = (status >> 16) & 0x1f; |
32b46093 | 586 | |
43286568 | 587 | p.ack = evt - 16; |
32b46093 KH |
588 | p.speed = (status >> 21) & 0x7; |
589 | p.timestamp = status & 0xffff; | |
590 | p.generation = ohci->request_generation; | |
ed568912 | 591 | |
43286568 | 592 | log_ar_at_event('R', p.speed, p.header, evt); |
ad3c0fe8 | 593 | |
c781c06d KH |
594 | /* |
595 | * The OHCI bus reset handler synthesizes a phy packet with | |
ed568912 KH |
596 | * the new generation number when a bus reset happens (see |
597 | * section 8.4.2.3). This helps us determine when a request | |
598 | * was received and make sure we send the response in the same | |
599 | * generation. We only need this for requests; for responses | |
600 | * we use the unique tlabel for finding the matching | |
c781c06d | 601 | * request. |
d34316a4 SR |
602 | * |
603 | * Alas some chips sometimes emit bus reset packets with a | |
604 | * wrong generation. We set the correct generation for these | |
605 | * at a slightly incorrect time (in bus_reset_tasklet). | |
c781c06d | 606 | */ |
d34316a4 SR |
607 | if (evt == OHCI1394_evt_bus_reset) { |
608 | if (!ohci->bus_reset_packet_quirk) | |
609 | ohci->request_generation = (p.header[2] >> 16) & 0xff; | |
610 | } else if (ctx == &ohci->ar_request_ctx) { | |
2639a6fb | 611 | fw_core_handle_request(&ohci->card, &p); |
d34316a4 | 612 | } else { |
2639a6fb | 613 | fw_core_handle_response(&ohci->card, &p); |
d34316a4 | 614 | } |
ed568912 | 615 | |
32b46093 KH |
616 | return buffer + length + 1; |
617 | } | |
ed568912 | 618 | |
32b46093 KH |
619 | static void ar_context_tasklet(unsigned long data) |
620 | { | |
621 | struct ar_context *ctx = (struct ar_context *)data; | |
622 | struct fw_ohci *ohci = ctx->ohci; | |
623 | struct ar_buffer *ab; | |
624 | struct descriptor *d; | |
625 | void *buffer, *end; | |
626 | ||
627 | ab = ctx->current_buffer; | |
628 | d = &ab->descriptor; | |
629 | ||
630 | if (d->res_count == 0) { | |
631 | size_t size, rest, offset; | |
6b84236d JW |
632 | dma_addr_t start_bus; |
633 | void *start; | |
32b46093 | 634 | |
c781c06d KH |
635 | /* |
636 | * This descriptor is finished and we may have a | |
32b46093 | 637 | * packet split across this and the next buffer. We |
c781c06d KH |
638 | * reuse the page for reassembling the split packet. |
639 | */ | |
32b46093 KH |
640 | |
641 | offset = offsetof(struct ar_buffer, data); | |
6b84236d JW |
642 | start = buffer = ab; |
643 | start_bus = le32_to_cpu(ab->descriptor.data_address) - offset; | |
32b46093 | 644 | |
32b46093 KH |
645 | ab = ab->next; |
646 | d = &ab->descriptor; | |
647 | size = buffer + PAGE_SIZE - ctx->pointer; | |
648 | rest = le16_to_cpu(d->req_count) - le16_to_cpu(d->res_count); | |
649 | memmove(buffer, ctx->pointer, size); | |
650 | memcpy(buffer + size, ab->data, rest); | |
651 | ctx->current_buffer = ab; | |
652 | ctx->pointer = (void *) ab->data + rest; | |
653 | end = buffer + size + rest; | |
654 | ||
655 | while (buffer < end) | |
656 | buffer = handle_ar_packet(ctx, buffer); | |
657 | ||
bde1709a | 658 | dma_free_coherent(ohci->card.device, PAGE_SIZE, |
6b84236d | 659 | start, start_bus); |
32b46093 KH |
660 | ar_context_add_page(ctx); |
661 | } else { | |
662 | buffer = ctx->pointer; | |
663 | ctx->pointer = end = | |
664 | (void *) ab + PAGE_SIZE - le16_to_cpu(d->res_count); | |
665 | ||
666 | while (buffer < end) | |
667 | buffer = handle_ar_packet(ctx, buffer); | |
668 | } | |
ed568912 KH |
669 | } |
670 | ||
53dca511 SR |
671 | static int ar_context_init(struct ar_context *ctx, |
672 | struct fw_ohci *ohci, u32 regs) | |
ed568912 | 673 | { |
32b46093 | 674 | struct ar_buffer ab; |
ed568912 | 675 | |
72e318e0 KH |
676 | ctx->regs = regs; |
677 | ctx->ohci = ohci; | |
678 | ctx->last_buffer = &ab; | |
ed568912 KH |
679 | tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx); |
680 | ||
32b46093 KH |
681 | ar_context_add_page(ctx); |
682 | ar_context_add_page(ctx); | |
683 | ctx->current_buffer = ab.next; | |
684 | ctx->pointer = ctx->current_buffer->data; | |
685 | ||
2aef469a KH |
686 | return 0; |
687 | } | |
688 | ||
689 | static void ar_context_run(struct ar_context *ctx) | |
690 | { | |
691 | struct ar_buffer *ab = ctx->current_buffer; | |
692 | dma_addr_t ab_bus; | |
693 | size_t offset; | |
694 | ||
695 | offset = offsetof(struct ar_buffer, data); | |
0a9972ba | 696 | ab_bus = le32_to_cpu(ab->descriptor.data_address) - offset; |
2aef469a KH |
697 | |
698 | reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ab_bus | 1); | |
a77754a7 | 699 | reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN); |
32b46093 | 700 | flush_writes(ctx->ohci); |
ed568912 | 701 | } |
373b2edd | 702 | |
53dca511 | 703 | static struct descriptor *find_branch_descriptor(struct descriptor *d, int z) |
a186b4a6 JW |
704 | { |
705 | int b, key; | |
706 | ||
707 | b = (le16_to_cpu(d->control) & DESCRIPTOR_BRANCH_ALWAYS) >> 2; | |
708 | key = (le16_to_cpu(d->control) & DESCRIPTOR_KEY_IMMEDIATE) >> 8; | |
709 | ||
710 | /* figure out which descriptor the branch address goes in */ | |
711 | if (z == 2 && (b == 3 || key == 2)) | |
712 | return d; | |
713 | else | |
714 | return d + z - 1; | |
715 | } | |
716 | ||
30200739 KH |
717 | static void context_tasklet(unsigned long data) |
718 | { | |
719 | struct context *ctx = (struct context *) data; | |
30200739 KH |
720 | struct descriptor *d, *last; |
721 | u32 address; | |
722 | int z; | |
fe5ca634 | 723 | struct descriptor_buffer *desc; |
30200739 | 724 | |
fe5ca634 DM |
725 | desc = list_entry(ctx->buffer_list.next, |
726 | struct descriptor_buffer, list); | |
727 | last = ctx->last; | |
30200739 | 728 | while (last->branch_address != 0) { |
fe5ca634 | 729 | struct descriptor_buffer *old_desc = desc; |
30200739 KH |
730 | address = le32_to_cpu(last->branch_address); |
731 | z = address & 0xf; | |
fe5ca634 DM |
732 | address &= ~0xf; |
733 | ||
734 | /* If the branch address points to a buffer outside of the | |
735 | * current buffer, advance to the next buffer. */ | |
736 | if (address < desc->buffer_bus || | |
737 | address >= desc->buffer_bus + desc->used) | |
738 | desc = list_entry(desc->list.next, | |
739 | struct descriptor_buffer, list); | |
740 | d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d); | |
a186b4a6 | 741 | last = find_branch_descriptor(d, z); |
30200739 KH |
742 | |
743 | if (!ctx->callback(ctx, d, last)) | |
744 | break; | |
745 | ||
fe5ca634 DM |
746 | if (old_desc != desc) { |
747 | /* If we've advanced to the next buffer, move the | |
748 | * previous buffer to the free list. */ | |
749 | unsigned long flags; | |
750 | old_desc->used = 0; | |
751 | spin_lock_irqsave(&ctx->ohci->lock, flags); | |
752 | list_move_tail(&old_desc->list, &ctx->buffer_list); | |
753 | spin_unlock_irqrestore(&ctx->ohci->lock, flags); | |
754 | } | |
755 | ctx->last = last; | |
30200739 KH |
756 | } |
757 | } | |
758 | ||
fe5ca634 DM |
759 | /* |
760 | * Allocate a new buffer and add it to the list of free buffers for this | |
761 | * context. Must be called with ohci->lock held. | |
762 | */ | |
53dca511 | 763 | static int context_add_buffer(struct context *ctx) |
fe5ca634 DM |
764 | { |
765 | struct descriptor_buffer *desc; | |
f5101d58 | 766 | dma_addr_t uninitialized_var(bus_addr); |
fe5ca634 DM |
767 | int offset; |
768 | ||
769 | /* | |
770 | * 16MB of descriptors should be far more than enough for any DMA | |
771 | * program. This will catch run-away userspace or DoS attacks. | |
772 | */ | |
773 | if (ctx->total_allocation >= 16*1024*1024) | |
774 | return -ENOMEM; | |
775 | ||
776 | desc = dma_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE, | |
777 | &bus_addr, GFP_ATOMIC); | |
778 | if (!desc) | |
779 | return -ENOMEM; | |
780 | ||
781 | offset = (void *)&desc->buffer - (void *)desc; | |
782 | desc->buffer_size = PAGE_SIZE - offset; | |
783 | desc->buffer_bus = bus_addr + offset; | |
784 | desc->used = 0; | |
785 | ||
786 | list_add_tail(&desc->list, &ctx->buffer_list); | |
787 | ctx->total_allocation += PAGE_SIZE; | |
788 | ||
789 | return 0; | |
790 | } | |
791 | ||
53dca511 SR |
792 | static int context_init(struct context *ctx, struct fw_ohci *ohci, |
793 | u32 regs, descriptor_callback_t callback) | |
30200739 KH |
794 | { |
795 | ctx->ohci = ohci; | |
796 | ctx->regs = regs; | |
fe5ca634 DM |
797 | ctx->total_allocation = 0; |
798 | ||
799 | INIT_LIST_HEAD(&ctx->buffer_list); | |
800 | if (context_add_buffer(ctx) < 0) | |
30200739 KH |
801 | return -ENOMEM; |
802 | ||
fe5ca634 DM |
803 | ctx->buffer_tail = list_entry(ctx->buffer_list.next, |
804 | struct descriptor_buffer, list); | |
805 | ||
30200739 KH |
806 | tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx); |
807 | ctx->callback = callback; | |
808 | ||
c781c06d KH |
809 | /* |
810 | * We put a dummy descriptor in the buffer that has a NULL | |
30200739 | 811 | * branch address and looks like it's been sent. That way we |
fe5ca634 | 812 | * have a descriptor to append DMA programs to. |
c781c06d | 813 | */ |
fe5ca634 DM |
814 | memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer)); |
815 | ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST); | |
816 | ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011); | |
817 | ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer); | |
818 | ctx->last = ctx->buffer_tail->buffer; | |
819 | ctx->prev = ctx->buffer_tail->buffer; | |
30200739 KH |
820 | |
821 | return 0; | |
822 | } | |
823 | ||
53dca511 | 824 | static void context_release(struct context *ctx) |
30200739 KH |
825 | { |
826 | struct fw_card *card = &ctx->ohci->card; | |
fe5ca634 | 827 | struct descriptor_buffer *desc, *tmp; |
30200739 | 828 | |
fe5ca634 DM |
829 | list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list) |
830 | dma_free_coherent(card->device, PAGE_SIZE, desc, | |
831 | desc->buffer_bus - | |
832 | ((void *)&desc->buffer - (void *)desc)); | |
30200739 KH |
833 | } |
834 | ||
fe5ca634 | 835 | /* Must be called with ohci->lock held */ |
53dca511 SR |
836 | static struct descriptor *context_get_descriptors(struct context *ctx, |
837 | int z, dma_addr_t *d_bus) | |
30200739 | 838 | { |
fe5ca634 DM |
839 | struct descriptor *d = NULL; |
840 | struct descriptor_buffer *desc = ctx->buffer_tail; | |
841 | ||
842 | if (z * sizeof(*d) > desc->buffer_size) | |
843 | return NULL; | |
844 | ||
845 | if (z * sizeof(*d) > desc->buffer_size - desc->used) { | |
846 | /* No room for the descriptor in this buffer, so advance to the | |
847 | * next one. */ | |
30200739 | 848 | |
fe5ca634 DM |
849 | if (desc->list.next == &ctx->buffer_list) { |
850 | /* If there is no free buffer next in the list, | |
851 | * allocate one. */ | |
852 | if (context_add_buffer(ctx) < 0) | |
853 | return NULL; | |
854 | } | |
855 | desc = list_entry(desc->list.next, | |
856 | struct descriptor_buffer, list); | |
857 | ctx->buffer_tail = desc; | |
858 | } | |
30200739 | 859 | |
fe5ca634 | 860 | d = desc->buffer + desc->used / sizeof(*d); |
2d826cc5 | 861 | memset(d, 0, z * sizeof(*d)); |
fe5ca634 | 862 | *d_bus = desc->buffer_bus + desc->used; |
30200739 KH |
863 | |
864 | return d; | |
865 | } | |
866 | ||
295e3feb | 867 | static void context_run(struct context *ctx, u32 extra) |
30200739 KH |
868 | { |
869 | struct fw_ohci *ohci = ctx->ohci; | |
870 | ||
a77754a7 | 871 | reg_write(ohci, COMMAND_PTR(ctx->regs), |
fe5ca634 | 872 | le32_to_cpu(ctx->last->branch_address)); |
a77754a7 KH |
873 | reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0); |
874 | reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra); | |
30200739 KH |
875 | flush_writes(ohci); |
876 | } | |
877 | ||
878 | static void context_append(struct context *ctx, | |
879 | struct descriptor *d, int z, int extra) | |
880 | { | |
881 | dma_addr_t d_bus; | |
fe5ca634 | 882 | struct descriptor_buffer *desc = ctx->buffer_tail; |
30200739 | 883 | |
fe5ca634 | 884 | d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d); |
30200739 | 885 | |
fe5ca634 DM |
886 | desc->used += (z + extra) * sizeof(*d); |
887 | ctx->prev->branch_address = cpu_to_le32(d_bus | z); | |
888 | ctx->prev = find_branch_descriptor(d, z); | |
30200739 | 889 | |
a77754a7 | 890 | reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE); |
30200739 KH |
891 | flush_writes(ctx->ohci); |
892 | } | |
893 | ||
894 | static void context_stop(struct context *ctx) | |
895 | { | |
896 | u32 reg; | |
b8295668 | 897 | int i; |
30200739 | 898 | |
a77754a7 | 899 | reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN); |
b8295668 | 900 | flush_writes(ctx->ohci); |
30200739 | 901 | |
b8295668 | 902 | for (i = 0; i < 10; i++) { |
a77754a7 | 903 | reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs)); |
b8295668 | 904 | if ((reg & CONTEXT_ACTIVE) == 0) |
b0068549 | 905 | return; |
b8295668 | 906 | |
b980f5a2 | 907 | mdelay(1); |
b8295668 | 908 | } |
b0068549 | 909 | fw_error("Error: DMA context still active (0x%08x)\n", reg); |
30200739 | 910 | } |
ed568912 | 911 | |
f319b6a0 KH |
912 | struct driver_data { |
913 | struct fw_packet *packet; | |
914 | }; | |
ed568912 | 915 | |
c781c06d KH |
916 | /* |
917 | * This function apppends a packet to the DMA queue for transmission. | |
f319b6a0 | 918 | * Must always be called with the ochi->lock held to ensure proper |
c781c06d KH |
919 | * generation handling and locking around packet queue manipulation. |
920 | */ | |
53dca511 SR |
921 | static int at_context_queue_packet(struct context *ctx, |
922 | struct fw_packet *packet) | |
ed568912 | 923 | { |
ed568912 | 924 | struct fw_ohci *ohci = ctx->ohci; |
4b6d51ec | 925 | dma_addr_t d_bus, uninitialized_var(payload_bus); |
f319b6a0 KH |
926 | struct driver_data *driver_data; |
927 | struct descriptor *d, *last; | |
928 | __le32 *header; | |
ed568912 | 929 | int z, tcode; |
f319b6a0 | 930 | u32 reg; |
ed568912 | 931 | |
f319b6a0 KH |
932 | d = context_get_descriptors(ctx, 4, &d_bus); |
933 | if (d == NULL) { | |
934 | packet->ack = RCODE_SEND_ERROR; | |
935 | return -1; | |
ed568912 KH |
936 | } |
937 | ||
a77754a7 | 938 | d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE); |
f319b6a0 KH |
939 | d[0].res_count = cpu_to_le16(packet->timestamp); |
940 | ||
c781c06d KH |
941 | /* |
942 | * The DMA format for asyncronous link packets is different | |
ed568912 KH |
943 | * from the IEEE1394 layout, so shift the fields around |
944 | * accordingly. If header_length is 8, it's a PHY packet, to | |
c781c06d KH |
945 | * which we need to prepend an extra quadlet. |
946 | */ | |
f319b6a0 KH |
947 | |
948 | header = (__le32 *) &d[1]; | |
f8c2287c JF |
949 | switch (packet->header_length) { |
950 | case 16: | |
951 | case 12: | |
f319b6a0 KH |
952 | header[0] = cpu_to_le32((packet->header[0] & 0xffff) | |
953 | (packet->speed << 16)); | |
954 | header[1] = cpu_to_le32((packet->header[1] & 0xffff) | | |
955 | (packet->header[0] & 0xffff0000)); | |
956 | header[2] = cpu_to_le32(packet->header[2]); | |
ed568912 KH |
957 | |
958 | tcode = (packet->header[0] >> 4) & 0x0f; | |
959 | if (TCODE_IS_BLOCK_PACKET(tcode)) | |
f319b6a0 | 960 | header[3] = cpu_to_le32(packet->header[3]); |
ed568912 | 961 | else |
f319b6a0 KH |
962 | header[3] = (__force __le32) packet->header[3]; |
963 | ||
964 | d[0].req_count = cpu_to_le16(packet->header_length); | |
f8c2287c JF |
965 | break; |
966 | ||
967 | case 8: | |
f319b6a0 KH |
968 | header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) | |
969 | (packet->speed << 16)); | |
970 | header[1] = cpu_to_le32(packet->header[0]); | |
971 | header[2] = cpu_to_le32(packet->header[1]); | |
972 | d[0].req_count = cpu_to_le16(12); | |
f8c2287c JF |
973 | break; |
974 | ||
975 | case 4: | |
976 | header[0] = cpu_to_le32((packet->header[0] & 0xffff) | | |
977 | (packet->speed << 16)); | |
978 | header[1] = cpu_to_le32(packet->header[0] & 0xffff0000); | |
979 | d[0].req_count = cpu_to_le16(8); | |
980 | break; | |
981 | ||
982 | default: | |
983 | /* BUG(); */ | |
984 | packet->ack = RCODE_SEND_ERROR; | |
985 | return -1; | |
ed568912 KH |
986 | } |
987 | ||
f319b6a0 KH |
988 | driver_data = (struct driver_data *) &d[3]; |
989 | driver_data->packet = packet; | |
20d11673 | 990 | packet->driver_data = driver_data; |
a186b4a6 | 991 | |
f319b6a0 KH |
992 | if (packet->payload_length > 0) { |
993 | payload_bus = | |
994 | dma_map_single(ohci->card.device, packet->payload, | |
995 | packet->payload_length, DMA_TO_DEVICE); | |
8d8bb39b | 996 | if (dma_mapping_error(ohci->card.device, payload_bus)) { |
f319b6a0 KH |
997 | packet->ack = RCODE_SEND_ERROR; |
998 | return -1; | |
999 | } | |
1d1dc5e8 | 1000 | packet->payload_bus = payload_bus; |
f319b6a0 KH |
1001 | |
1002 | d[2].req_count = cpu_to_le16(packet->payload_length); | |
1003 | d[2].data_address = cpu_to_le32(payload_bus); | |
1004 | last = &d[2]; | |
1005 | z = 3; | |
ed568912 | 1006 | } else { |
f319b6a0 KH |
1007 | last = &d[0]; |
1008 | z = 2; | |
ed568912 | 1009 | } |
ed568912 | 1010 | |
a77754a7 KH |
1011 | last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST | |
1012 | DESCRIPTOR_IRQ_ALWAYS | | |
1013 | DESCRIPTOR_BRANCH_ALWAYS); | |
ed568912 | 1014 | |
76f73ca1 JW |
1015 | /* |
1016 | * If the controller and packet generations don't match, we need to | |
1017 | * bail out and try again. If IntEvent.busReset is set, the AT context | |
1018 | * is halted, so appending to the context and trying to run it is | |
1019 | * futile. Most controllers do the right thing and just flush the AT | |
1020 | * queue (per section 7.2.3.2 of the OHCI 1.1 specification), but | |
1021 | * some controllers (like a JMicron JMB381 PCI-e) misbehave and wind | |
1022 | * up stalling out. So we just bail out in software and try again | |
1023 | * later, and everyone is happy. | |
1024 | * FIXME: Document how the locking works. | |
1025 | */ | |
1026 | if (ohci->generation != packet->generation || | |
1027 | reg_read(ohci, OHCI1394_IntEventSet) & OHCI1394_busReset) { | |
ab88ca48 SR |
1028 | if (packet->payload_length > 0) |
1029 | dma_unmap_single(ohci->card.device, payload_bus, | |
1030 | packet->payload_length, DMA_TO_DEVICE); | |
f319b6a0 KH |
1031 | packet->ack = RCODE_GENERATION; |
1032 | return -1; | |
1033 | } | |
1034 | ||
1035 | context_append(ctx, d, z, 4 - z); | |
ed568912 | 1036 | |
f319b6a0 | 1037 | /* If the context isn't already running, start it up. */ |
a77754a7 | 1038 | reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs)); |
053b3080 | 1039 | if ((reg & CONTEXT_RUN) == 0) |
f319b6a0 KH |
1040 | context_run(ctx, 0); |
1041 | ||
1042 | return 0; | |
ed568912 KH |
1043 | } |
1044 | ||
f319b6a0 KH |
1045 | static int handle_at_packet(struct context *context, |
1046 | struct descriptor *d, | |
1047 | struct descriptor *last) | |
ed568912 | 1048 | { |
f319b6a0 | 1049 | struct driver_data *driver_data; |
ed568912 | 1050 | struct fw_packet *packet; |
f319b6a0 | 1051 | struct fw_ohci *ohci = context->ohci; |
ed568912 KH |
1052 | int evt; |
1053 | ||
f319b6a0 KH |
1054 | if (last->transfer_status == 0) |
1055 | /* This descriptor isn't done yet, stop iteration. */ | |
1056 | return 0; | |
ed568912 | 1057 | |
f319b6a0 KH |
1058 | driver_data = (struct driver_data *) &d[3]; |
1059 | packet = driver_data->packet; | |
1060 | if (packet == NULL) | |
1061 | /* This packet was cancelled, just continue. */ | |
1062 | return 1; | |
730c32f5 | 1063 | |
1d1dc5e8 SR |
1064 | if (packet->payload_bus) |
1065 | dma_unmap_single(ohci->card.device, packet->payload_bus, | |
ed568912 | 1066 | packet->payload_length, DMA_TO_DEVICE); |
ed568912 | 1067 | |
f319b6a0 KH |
1068 | evt = le16_to_cpu(last->transfer_status) & 0x1f; |
1069 | packet->timestamp = le16_to_cpu(last->res_count); | |
ed568912 | 1070 | |
ad3c0fe8 SR |
1071 | log_ar_at_event('T', packet->speed, packet->header, evt); |
1072 | ||
f319b6a0 KH |
1073 | switch (evt) { |
1074 | case OHCI1394_evt_timeout: | |
1075 | /* Async response transmit timed out. */ | |
1076 | packet->ack = RCODE_CANCELLED; | |
1077 | break; | |
ed568912 | 1078 | |
f319b6a0 | 1079 | case OHCI1394_evt_flushed: |
c781c06d KH |
1080 | /* |
1081 | * The packet was flushed should give same error as | |
1082 | * when we try to use a stale generation count. | |
1083 | */ | |
f319b6a0 KH |
1084 | packet->ack = RCODE_GENERATION; |
1085 | break; | |
ed568912 | 1086 | |
f319b6a0 | 1087 | case OHCI1394_evt_missing_ack: |
c781c06d KH |
1088 | /* |
1089 | * Using a valid (current) generation count, but the | |
1090 | * node is not on the bus or not sending acks. | |
1091 | */ | |
f319b6a0 KH |
1092 | packet->ack = RCODE_NO_ACK; |
1093 | break; | |
ed568912 | 1094 | |
f319b6a0 KH |
1095 | case ACK_COMPLETE + 0x10: |
1096 | case ACK_PENDING + 0x10: | |
1097 | case ACK_BUSY_X + 0x10: | |
1098 | case ACK_BUSY_A + 0x10: | |
1099 | case ACK_BUSY_B + 0x10: | |
1100 | case ACK_DATA_ERROR + 0x10: | |
1101 | case ACK_TYPE_ERROR + 0x10: | |
1102 | packet->ack = evt - 0x10; | |
1103 | break; | |
ed568912 | 1104 | |
f319b6a0 KH |
1105 | default: |
1106 | packet->ack = RCODE_SEND_ERROR; | |
1107 | break; | |
1108 | } | |
ed568912 | 1109 | |
f319b6a0 | 1110 | packet->callback(packet, &ohci->card, packet->ack); |
ed568912 | 1111 | |
f319b6a0 | 1112 | return 1; |
ed568912 KH |
1113 | } |
1114 | ||
a77754a7 KH |
1115 | #define HEADER_GET_DESTINATION(q) (((q) >> 16) & 0xffff) |
1116 | #define HEADER_GET_TCODE(q) (((q) >> 4) & 0x0f) | |
1117 | #define HEADER_GET_OFFSET_HIGH(q) (((q) >> 0) & 0xffff) | |
1118 | #define HEADER_GET_DATA_LENGTH(q) (((q) >> 16) & 0xffff) | |
1119 | #define HEADER_GET_EXTENDED_TCODE(q) (((q) >> 0) & 0xffff) | |
93c4cceb | 1120 | |
53dca511 SR |
1121 | static void handle_local_rom(struct fw_ohci *ohci, |
1122 | struct fw_packet *packet, u32 csr) | |
93c4cceb KH |
1123 | { |
1124 | struct fw_packet response; | |
1125 | int tcode, length, i; | |
1126 | ||
a77754a7 | 1127 | tcode = HEADER_GET_TCODE(packet->header[0]); |
93c4cceb | 1128 | if (TCODE_IS_BLOCK_PACKET(tcode)) |
a77754a7 | 1129 | length = HEADER_GET_DATA_LENGTH(packet->header[3]); |
93c4cceb KH |
1130 | else |
1131 | length = 4; | |
1132 | ||
1133 | i = csr - CSR_CONFIG_ROM; | |
1134 | if (i + length > CONFIG_ROM_SIZE) { | |
1135 | fw_fill_response(&response, packet->header, | |
1136 | RCODE_ADDRESS_ERROR, NULL, 0); | |
1137 | } else if (!TCODE_IS_READ_REQUEST(tcode)) { | |
1138 | fw_fill_response(&response, packet->header, | |
1139 | RCODE_TYPE_ERROR, NULL, 0); | |
1140 | } else { | |
1141 | fw_fill_response(&response, packet->header, RCODE_COMPLETE, | |
1142 | (void *) ohci->config_rom + i, length); | |
1143 | } | |
1144 | ||
1145 | fw_core_handle_response(&ohci->card, &response); | |
1146 | } | |
1147 | ||
53dca511 SR |
1148 | static void handle_local_lock(struct fw_ohci *ohci, |
1149 | struct fw_packet *packet, u32 csr) | |
93c4cceb KH |
1150 | { |
1151 | struct fw_packet response; | |
1152 | int tcode, length, ext_tcode, sel; | |
1153 | __be32 *payload, lock_old; | |
1154 | u32 lock_arg, lock_data; | |
1155 | ||
a77754a7 KH |
1156 | tcode = HEADER_GET_TCODE(packet->header[0]); |
1157 | length = HEADER_GET_DATA_LENGTH(packet->header[3]); | |
93c4cceb | 1158 | payload = packet->payload; |
a77754a7 | 1159 | ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]); |
93c4cceb KH |
1160 | |
1161 | if (tcode == TCODE_LOCK_REQUEST && | |
1162 | ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) { | |
1163 | lock_arg = be32_to_cpu(payload[0]); | |
1164 | lock_data = be32_to_cpu(payload[1]); | |
1165 | } else if (tcode == TCODE_READ_QUADLET_REQUEST) { | |
1166 | lock_arg = 0; | |
1167 | lock_data = 0; | |
1168 | } else { | |
1169 | fw_fill_response(&response, packet->header, | |
1170 | RCODE_TYPE_ERROR, NULL, 0); | |
1171 | goto out; | |
1172 | } | |
1173 | ||
1174 | sel = (csr - CSR_BUS_MANAGER_ID) / 4; | |
1175 | reg_write(ohci, OHCI1394_CSRData, lock_data); | |
1176 | reg_write(ohci, OHCI1394_CSRCompareData, lock_arg); | |
1177 | reg_write(ohci, OHCI1394_CSRControl, sel); | |
1178 | ||
1179 | if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000) | |
1180 | lock_old = cpu_to_be32(reg_read(ohci, OHCI1394_CSRData)); | |
1181 | else | |
1182 | fw_notify("swap not done yet\n"); | |
1183 | ||
1184 | fw_fill_response(&response, packet->header, | |
2d826cc5 | 1185 | RCODE_COMPLETE, &lock_old, sizeof(lock_old)); |
93c4cceb KH |
1186 | out: |
1187 | fw_core_handle_response(&ohci->card, &response); | |
1188 | } | |
1189 | ||
53dca511 | 1190 | static void handle_local_request(struct context *ctx, struct fw_packet *packet) |
93c4cceb KH |
1191 | { |
1192 | u64 offset; | |
1193 | u32 csr; | |
1194 | ||
473d28c7 KH |
1195 | if (ctx == &ctx->ohci->at_request_ctx) { |
1196 | packet->ack = ACK_PENDING; | |
1197 | packet->callback(packet, &ctx->ohci->card, packet->ack); | |
1198 | } | |
93c4cceb KH |
1199 | |
1200 | offset = | |
1201 | ((unsigned long long) | |
a77754a7 | 1202 | HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) | |
93c4cceb KH |
1203 | packet->header[2]; |
1204 | csr = offset - CSR_REGISTER_BASE; | |
1205 | ||
1206 | /* Handle config rom reads. */ | |
1207 | if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END) | |
1208 | handle_local_rom(ctx->ohci, packet, csr); | |
1209 | else switch (csr) { | |
1210 | case CSR_BUS_MANAGER_ID: | |
1211 | case CSR_BANDWIDTH_AVAILABLE: | |
1212 | case CSR_CHANNELS_AVAILABLE_HI: | |
1213 | case CSR_CHANNELS_AVAILABLE_LO: | |
1214 | handle_local_lock(ctx->ohci, packet, csr); | |
1215 | break; | |
1216 | default: | |
1217 | if (ctx == &ctx->ohci->at_request_ctx) | |
1218 | fw_core_handle_request(&ctx->ohci->card, packet); | |
1219 | else | |
1220 | fw_core_handle_response(&ctx->ohci->card, packet); | |
1221 | break; | |
1222 | } | |
473d28c7 KH |
1223 | |
1224 | if (ctx == &ctx->ohci->at_response_ctx) { | |
1225 | packet->ack = ACK_COMPLETE; | |
1226 | packet->callback(packet, &ctx->ohci->card, packet->ack); | |
1227 | } | |
93c4cceb | 1228 | } |
e636fe25 | 1229 | |
53dca511 | 1230 | static void at_context_transmit(struct context *ctx, struct fw_packet *packet) |
ed568912 | 1231 | { |
ed568912 | 1232 | unsigned long flags; |
2dbd7d7e | 1233 | int ret; |
ed568912 KH |
1234 | |
1235 | spin_lock_irqsave(&ctx->ohci->lock, flags); | |
1236 | ||
a77754a7 | 1237 | if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id && |
e636fe25 | 1238 | ctx->ohci->generation == packet->generation) { |
93c4cceb KH |
1239 | spin_unlock_irqrestore(&ctx->ohci->lock, flags); |
1240 | handle_local_request(ctx, packet); | |
1241 | return; | |
e636fe25 | 1242 | } |
ed568912 | 1243 | |
2dbd7d7e | 1244 | ret = at_context_queue_packet(ctx, packet); |
ed568912 KH |
1245 | spin_unlock_irqrestore(&ctx->ohci->lock, flags); |
1246 | ||
2dbd7d7e | 1247 | if (ret < 0) |
f319b6a0 | 1248 | packet->callback(packet, &ctx->ohci->card, packet->ack); |
a186b4a6 | 1249 | |
ed568912 KH |
1250 | } |
1251 | ||
1252 | static void bus_reset_tasklet(unsigned long data) | |
1253 | { | |
1254 | struct fw_ohci *ohci = (struct fw_ohci *)data; | |
e636fe25 | 1255 | int self_id_count, i, j, reg; |
ed568912 KH |
1256 | int generation, new_generation; |
1257 | unsigned long flags; | |
4eaff7d6 SR |
1258 | void *free_rom = NULL; |
1259 | dma_addr_t free_rom_bus = 0; | |
ed568912 KH |
1260 | |
1261 | reg = reg_read(ohci, OHCI1394_NodeID); | |
1262 | if (!(reg & OHCI1394_NodeID_idValid)) { | |
02ff8f8e | 1263 | fw_notify("node ID not valid, new bus reset in progress\n"); |
ed568912 KH |
1264 | return; |
1265 | } | |
02ff8f8e SR |
1266 | if ((reg & OHCI1394_NodeID_nodeNumber) == 63) { |
1267 | fw_notify("malconfigured bus\n"); | |
1268 | return; | |
1269 | } | |
1270 | ohci->node_id = reg & (OHCI1394_NodeID_busNumber | | |
1271 | OHCI1394_NodeID_nodeNumber); | |
ed568912 | 1272 | |
c8a9a498 SR |
1273 | reg = reg_read(ohci, OHCI1394_SelfIDCount); |
1274 | if (reg & OHCI1394_SelfIDCount_selfIDError) { | |
1275 | fw_notify("inconsistent self IDs\n"); | |
1276 | return; | |
1277 | } | |
c781c06d KH |
1278 | /* |
1279 | * The count in the SelfIDCount register is the number of | |
ed568912 KH |
1280 | * bytes in the self ID receive buffer. Since we also receive |
1281 | * the inverted quadlets and a header quadlet, we shift one | |
c781c06d KH |
1282 | * bit extra to get the actual number of self IDs. |
1283 | */ | |
928ec5f1 SR |
1284 | self_id_count = (reg >> 3) & 0xff; |
1285 | if (self_id_count == 0 || self_id_count > 252) { | |
016bf3df SR |
1286 | fw_notify("inconsistent self IDs\n"); |
1287 | return; | |
1288 | } | |
11bf20ad | 1289 | generation = (cond_le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff; |
ee71c2f9 | 1290 | rmb(); |
ed568912 KH |
1291 | |
1292 | for (i = 1, j = 0; j < self_id_count; i += 2, j++) { | |
c8a9a498 SR |
1293 | if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1]) { |
1294 | fw_notify("inconsistent self IDs\n"); | |
1295 | return; | |
1296 | } | |
11bf20ad SR |
1297 | ohci->self_id_buffer[j] = |
1298 | cond_le32_to_cpu(ohci->self_id_cpu[i]); | |
ed568912 | 1299 | } |
ee71c2f9 | 1300 | rmb(); |
ed568912 | 1301 | |
c781c06d KH |
1302 | /* |
1303 | * Check the consistency of the self IDs we just read. The | |
ed568912 KH |
1304 | * problem we face is that a new bus reset can start while we |
1305 | * read out the self IDs from the DMA buffer. If this happens, | |
1306 | * the DMA buffer will be overwritten with new self IDs and we | |
1307 | * will read out inconsistent data. The OHCI specification | |
1308 | * (section 11.2) recommends a technique similar to | |
1309 | * linux/seqlock.h, where we remember the generation of the | |
1310 | * self IDs in the buffer before reading them out and compare | |
1311 | * it to the current generation after reading them out. If | |
1312 | * the two generations match we know we have a consistent set | |
c781c06d KH |
1313 | * of self IDs. |
1314 | */ | |
ed568912 KH |
1315 | |
1316 | new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff; | |
1317 | if (new_generation != generation) { | |
1318 | fw_notify("recursive bus reset detected, " | |
1319 | "discarding self ids\n"); | |
1320 | return; | |
1321 | } | |
1322 | ||
1323 | /* FIXME: Document how the locking works. */ | |
1324 | spin_lock_irqsave(&ohci->lock, flags); | |
1325 | ||
1326 | ohci->generation = generation; | |
f319b6a0 KH |
1327 | context_stop(&ohci->at_request_ctx); |
1328 | context_stop(&ohci->at_response_ctx); | |
ed568912 KH |
1329 | reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset); |
1330 | ||
d34316a4 SR |
1331 | if (ohci->bus_reset_packet_quirk) |
1332 | ohci->request_generation = generation; | |
1333 | ||
c781c06d KH |
1334 | /* |
1335 | * This next bit is unrelated to the AT context stuff but we | |
ed568912 KH |
1336 | * have to do it under the spinlock also. If a new config rom |
1337 | * was set up before this reset, the old one is now no longer | |
1338 | * in use and we can free it. Update the config rom pointers | |
1339 | * to point to the current config rom and clear the | |
c781c06d KH |
1340 | * next_config_rom pointer so a new udpate can take place. |
1341 | */ | |
ed568912 KH |
1342 | |
1343 | if (ohci->next_config_rom != NULL) { | |
0bd243c4 KH |
1344 | if (ohci->next_config_rom != ohci->config_rom) { |
1345 | free_rom = ohci->config_rom; | |
1346 | free_rom_bus = ohci->config_rom_bus; | |
1347 | } | |
ed568912 KH |
1348 | ohci->config_rom = ohci->next_config_rom; |
1349 | ohci->config_rom_bus = ohci->next_config_rom_bus; | |
1350 | ohci->next_config_rom = NULL; | |
1351 | ||
c781c06d KH |
1352 | /* |
1353 | * Restore config_rom image and manually update | |
ed568912 KH |
1354 | * config_rom registers. Writing the header quadlet |
1355 | * will indicate that the config rom is ready, so we | |
c781c06d KH |
1356 | * do that last. |
1357 | */ | |
ed568912 KH |
1358 | reg_write(ohci, OHCI1394_BusOptions, |
1359 | be32_to_cpu(ohci->config_rom[2])); | |
1360 | ohci->config_rom[0] = cpu_to_be32(ohci->next_header); | |
1361 | reg_write(ohci, OHCI1394_ConfigROMhdr, ohci->next_header); | |
1362 | } | |
1363 | ||
080de8c2 SR |
1364 | #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA |
1365 | reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0); | |
1366 | reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0); | |
1367 | #endif | |
1368 | ||
ed568912 KH |
1369 | spin_unlock_irqrestore(&ohci->lock, flags); |
1370 | ||
4eaff7d6 SR |
1371 | if (free_rom) |
1372 | dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, | |
1373 | free_rom, free_rom_bus); | |
1374 | ||
08ddb2f4 SR |
1375 | log_selfids(ohci->node_id, generation, |
1376 | self_id_count, ohci->self_id_buffer); | |
ad3c0fe8 | 1377 | |
e636fe25 | 1378 | fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation, |
ed568912 KH |
1379 | self_id_count, ohci->self_id_buffer); |
1380 | } | |
1381 | ||
1382 | static irqreturn_t irq_handler(int irq, void *data) | |
1383 | { | |
1384 | struct fw_ohci *ohci = data; | |
d60d7f1d | 1385 | u32 event, iso_event, cycle_time; |
ed568912 KH |
1386 | int i; |
1387 | ||
1388 | event = reg_read(ohci, OHCI1394_IntEventClear); | |
1389 | ||
a515958d | 1390 | if (!event || !~event) |
ed568912 KH |
1391 | return IRQ_NONE; |
1392 | ||
a007bb85 SR |
1393 | /* busReset must not be cleared yet, see OHCI 1.1 clause 7.2.3.2 */ |
1394 | reg_write(ohci, OHCI1394_IntEventClear, event & ~OHCI1394_busReset); | |
ad3c0fe8 | 1395 | log_irqs(event); |
ed568912 KH |
1396 | |
1397 | if (event & OHCI1394_selfIDComplete) | |
1398 | tasklet_schedule(&ohci->bus_reset_tasklet); | |
1399 | ||
1400 | if (event & OHCI1394_RQPkt) | |
1401 | tasklet_schedule(&ohci->ar_request_ctx.tasklet); | |
1402 | ||
1403 | if (event & OHCI1394_RSPkt) | |
1404 | tasklet_schedule(&ohci->ar_response_ctx.tasklet); | |
1405 | ||
1406 | if (event & OHCI1394_reqTxComplete) | |
1407 | tasklet_schedule(&ohci->at_request_ctx.tasklet); | |
1408 | ||
1409 | if (event & OHCI1394_respTxComplete) | |
1410 | tasklet_schedule(&ohci->at_response_ctx.tasklet); | |
1411 | ||
c889475f | 1412 | iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear); |
ed568912 KH |
1413 | reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event); |
1414 | ||
1415 | while (iso_event) { | |
1416 | i = ffs(iso_event) - 1; | |
30200739 | 1417 | tasklet_schedule(&ohci->ir_context_list[i].context.tasklet); |
ed568912 KH |
1418 | iso_event &= ~(1 << i); |
1419 | } | |
1420 | ||
c889475f | 1421 | iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear); |
ed568912 KH |
1422 | reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event); |
1423 | ||
1424 | while (iso_event) { | |
1425 | i = ffs(iso_event) - 1; | |
30200739 | 1426 | tasklet_schedule(&ohci->it_context_list[i].context.tasklet); |
ed568912 KH |
1427 | iso_event &= ~(1 << i); |
1428 | } | |
1429 | ||
75f7832e JW |
1430 | if (unlikely(event & OHCI1394_regAccessFail)) |
1431 | fw_error("Register access failure - " | |
1432 | "please notify linux1394-devel@lists.sf.net\n"); | |
1433 | ||
e524f616 SR |
1434 | if (unlikely(event & OHCI1394_postedWriteErr)) |
1435 | fw_error("PCI posted write error\n"); | |
1436 | ||
bb9f2206 SR |
1437 | if (unlikely(event & OHCI1394_cycleTooLong)) { |
1438 | if (printk_ratelimit()) | |
1439 | fw_notify("isochronous cycle too long\n"); | |
1440 | reg_write(ohci, OHCI1394_LinkControlSet, | |
1441 | OHCI1394_LinkControl_cycleMaster); | |
1442 | } | |
1443 | ||
5ed1f321 JF |
1444 | if (unlikely(event & OHCI1394_cycleInconsistent)) { |
1445 | /* | |
1446 | * We need to clear this event bit in order to make | |
1447 | * cycleMatch isochronous I/O work. In theory we should | |
1448 | * stop active cycleMatch iso contexts now and restart | |
1449 | * them at least two cycles later. (FIXME?) | |
1450 | */ | |
1451 | if (printk_ratelimit()) | |
1452 | fw_notify("isochronous cycle inconsistent\n"); | |
1453 | } | |
1454 | ||
d60d7f1d KH |
1455 | if (event & OHCI1394_cycle64Seconds) { |
1456 | cycle_time = reg_read(ohci, OHCI1394_IsochronousCycleTimer); | |
1457 | if ((cycle_time & 0x80000000) == 0) | |
3dcdc500 | 1458 | atomic_inc(&ohci->bus_seconds); |
d60d7f1d KH |
1459 | } |
1460 | ||
ed568912 KH |
1461 | return IRQ_HANDLED; |
1462 | } | |
1463 | ||
2aef469a KH |
1464 | static int software_reset(struct fw_ohci *ohci) |
1465 | { | |
1466 | int i; | |
1467 | ||
1468 | reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset); | |
1469 | ||
1470 | for (i = 0; i < OHCI_LOOP_COUNT; i++) { | |
1471 | if ((reg_read(ohci, OHCI1394_HCControlSet) & | |
1472 | OHCI1394_HCControl_softReset) == 0) | |
1473 | return 0; | |
1474 | msleep(1); | |
1475 | } | |
1476 | ||
1477 | return -EBUSY; | |
1478 | } | |
1479 | ||
ed568912 KH |
1480 | static int ohci_enable(struct fw_card *card, u32 *config_rom, size_t length) |
1481 | { | |
1482 | struct fw_ohci *ohci = fw_ohci(card); | |
1483 | struct pci_dev *dev = to_pci_dev(card->device); | |
02214724 JW |
1484 | u32 lps; |
1485 | int i; | |
ed568912 | 1486 | |
2aef469a KH |
1487 | if (software_reset(ohci)) { |
1488 | fw_error("Failed to reset ohci card.\n"); | |
1489 | return -EBUSY; | |
1490 | } | |
1491 | ||
1492 | /* | |
1493 | * Now enable LPS, which we need in order to start accessing | |
1494 | * most of the registers. In fact, on some cards (ALI M5251), | |
1495 | * accessing registers in the SClk domain without LPS enabled | |
1496 | * will lock up the machine. Wait 50msec to make sure we have | |
02214724 JW |
1497 | * full link enabled. However, with some cards (well, at least |
1498 | * a JMicron PCIe card), we have to try again sometimes. | |
2aef469a KH |
1499 | */ |
1500 | reg_write(ohci, OHCI1394_HCControlSet, | |
1501 | OHCI1394_HCControl_LPS | | |
1502 | OHCI1394_HCControl_postedWriteEnable); | |
1503 | flush_writes(ohci); | |
02214724 JW |
1504 | |
1505 | for (lps = 0, i = 0; !lps && i < 3; i++) { | |
1506 | msleep(50); | |
1507 | lps = reg_read(ohci, OHCI1394_HCControlSet) & | |
1508 | OHCI1394_HCControl_LPS; | |
1509 | } | |
1510 | ||
1511 | if (!lps) { | |
1512 | fw_error("Failed to set Link Power Status\n"); | |
1513 | return -EIO; | |
1514 | } | |
2aef469a KH |
1515 | |
1516 | reg_write(ohci, OHCI1394_HCControlClear, | |
1517 | OHCI1394_HCControl_noByteSwapData); | |
1518 | ||
affc9c24 | 1519 | reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus); |
e896ec43 SR |
1520 | reg_write(ohci, OHCI1394_LinkControlClear, |
1521 | OHCI1394_LinkControl_rcvPhyPkt); | |
2aef469a KH |
1522 | reg_write(ohci, OHCI1394_LinkControlSet, |
1523 | OHCI1394_LinkControl_rcvSelfID | | |
1524 | OHCI1394_LinkControl_cycleTimerEnable | | |
1525 | OHCI1394_LinkControl_cycleMaster); | |
1526 | ||
1527 | reg_write(ohci, OHCI1394_ATRetries, | |
1528 | OHCI1394_MAX_AT_REQ_RETRIES | | |
1529 | (OHCI1394_MAX_AT_RESP_RETRIES << 4) | | |
1530 | (OHCI1394_MAX_PHYS_RESP_RETRIES << 8)); | |
1531 | ||
1532 | ar_context_run(&ohci->ar_request_ctx); | |
1533 | ar_context_run(&ohci->ar_response_ctx); | |
1534 | ||
2aef469a KH |
1535 | reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000); |
1536 | reg_write(ohci, OHCI1394_IntEventClear, ~0); | |
1537 | reg_write(ohci, OHCI1394_IntMaskClear, ~0); | |
1538 | reg_write(ohci, OHCI1394_IntMaskSet, | |
1539 | OHCI1394_selfIDComplete | | |
1540 | OHCI1394_RQPkt | OHCI1394_RSPkt | | |
1541 | OHCI1394_reqTxComplete | OHCI1394_respTxComplete | | |
1542 | OHCI1394_isochRx | OHCI1394_isochTx | | |
bb9f2206 | 1543 | OHCI1394_postedWriteErr | OHCI1394_cycleTooLong | |
5ed1f321 | 1544 | OHCI1394_cycleInconsistent | |
75f7832e JW |
1545 | OHCI1394_cycle64Seconds | OHCI1394_regAccessFail | |
1546 | OHCI1394_masterIntEnable); | |
a007bb85 SR |
1547 | if (param_debug & OHCI_PARAM_DEBUG_BUSRESETS) |
1548 | reg_write(ohci, OHCI1394_IntMaskSet, OHCI1394_busReset); | |
2aef469a KH |
1549 | |
1550 | /* Activate link_on bit and contender bit in our self ID packets.*/ | |
1551 | if (ohci_update_phy_reg(card, 4, 0, | |
1552 | PHY_LINK_ACTIVE | PHY_CONTENDER) < 0) | |
1553 | return -EIO; | |
1554 | ||
c781c06d KH |
1555 | /* |
1556 | * When the link is not yet enabled, the atomic config rom | |
ed568912 KH |
1557 | * update mechanism described below in ohci_set_config_rom() |
1558 | * is not active. We have to update ConfigRomHeader and | |
1559 | * BusOptions manually, and the write to ConfigROMmap takes | |
1560 | * effect immediately. We tie this to the enabling of the | |
1561 | * link, so we have a valid config rom before enabling - the | |
1562 | * OHCI requires that ConfigROMhdr and BusOptions have valid | |
1563 | * values before enabling. | |
1564 | * | |
1565 | * However, when the ConfigROMmap is written, some controllers | |
1566 | * always read back quadlets 0 and 2 from the config rom to | |
1567 | * the ConfigRomHeader and BusOptions registers on bus reset. | |
1568 | * They shouldn't do that in this initial case where the link | |
1569 | * isn't enabled. This means we have to use the same | |
1570 | * workaround here, setting the bus header to 0 and then write | |
1571 | * the right values in the bus reset tasklet. | |
1572 | */ | |
1573 | ||
0bd243c4 KH |
1574 | if (config_rom) { |
1575 | ohci->next_config_rom = | |
1576 | dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE, | |
1577 | &ohci->next_config_rom_bus, | |
1578 | GFP_KERNEL); | |
1579 | if (ohci->next_config_rom == NULL) | |
1580 | return -ENOMEM; | |
ed568912 | 1581 | |
0bd243c4 KH |
1582 | memset(ohci->next_config_rom, 0, CONFIG_ROM_SIZE); |
1583 | fw_memcpy_to_be32(ohci->next_config_rom, config_rom, length * 4); | |
1584 | } else { | |
1585 | /* | |
1586 | * In the suspend case, config_rom is NULL, which | |
1587 | * means that we just reuse the old config rom. | |
1588 | */ | |
1589 | ohci->next_config_rom = ohci->config_rom; | |
1590 | ohci->next_config_rom_bus = ohci->config_rom_bus; | |
1591 | } | |
ed568912 | 1592 | |
0bd243c4 | 1593 | ohci->next_header = be32_to_cpu(ohci->next_config_rom[0]); |
ed568912 KH |
1594 | ohci->next_config_rom[0] = 0; |
1595 | reg_write(ohci, OHCI1394_ConfigROMhdr, 0); | |
0bd243c4 KH |
1596 | reg_write(ohci, OHCI1394_BusOptions, |
1597 | be32_to_cpu(ohci->next_config_rom[2])); | |
ed568912 KH |
1598 | reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus); |
1599 | ||
1600 | reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000); | |
1601 | ||
1602 | if (request_irq(dev->irq, irq_handler, | |
65efffa8 | 1603 | IRQF_SHARED, ohci_driver_name, ohci)) { |
ed568912 KH |
1604 | fw_error("Failed to allocate shared interrupt %d.\n", |
1605 | dev->irq); | |
1606 | dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, | |
1607 | ohci->config_rom, ohci->config_rom_bus); | |
1608 | return -EIO; | |
1609 | } | |
1610 | ||
1611 | reg_write(ohci, OHCI1394_HCControlSet, | |
1612 | OHCI1394_HCControl_linkEnable | | |
1613 | OHCI1394_HCControl_BIBimageValid); | |
1614 | flush_writes(ohci); | |
1615 | ||
c781c06d KH |
1616 | /* |
1617 | * We are ready to go, initiate bus reset to finish the | |
1618 | * initialization. | |
1619 | */ | |
ed568912 KH |
1620 | |
1621 | fw_core_initiate_bus_reset(&ohci->card, 1); | |
1622 | ||
1623 | return 0; | |
1624 | } | |
1625 | ||
53dca511 SR |
1626 | static int ohci_set_config_rom(struct fw_card *card, |
1627 | u32 *config_rom, size_t length) | |
ed568912 KH |
1628 | { |
1629 | struct fw_ohci *ohci; | |
1630 | unsigned long flags; | |
2dbd7d7e | 1631 | int ret = -EBUSY; |
ed568912 | 1632 | __be32 *next_config_rom; |
f5101d58 | 1633 | dma_addr_t uninitialized_var(next_config_rom_bus); |
ed568912 KH |
1634 | |
1635 | ohci = fw_ohci(card); | |
1636 | ||
c781c06d KH |
1637 | /* |
1638 | * When the OHCI controller is enabled, the config rom update | |
ed568912 KH |
1639 | * mechanism is a bit tricky, but easy enough to use. See |
1640 | * section 5.5.6 in the OHCI specification. | |
1641 | * | |
1642 | * The OHCI controller caches the new config rom address in a | |
1643 | * shadow register (ConfigROMmapNext) and needs a bus reset | |
1644 | * for the changes to take place. When the bus reset is | |
1645 | * detected, the controller loads the new values for the | |
1646 | * ConfigRomHeader and BusOptions registers from the specified | |
1647 | * config rom and loads ConfigROMmap from the ConfigROMmapNext | |
1648 | * shadow register. All automatically and atomically. | |
1649 | * | |
1650 | * Now, there's a twist to this story. The automatic load of | |
1651 | * ConfigRomHeader and BusOptions doesn't honor the | |
1652 | * noByteSwapData bit, so with a be32 config rom, the | |
1653 | * controller will load be32 values in to these registers | |
1654 | * during the atomic update, even on litte endian | |
1655 | * architectures. The workaround we use is to put a 0 in the | |
1656 | * header quadlet; 0 is endian agnostic and means that the | |
1657 | * config rom isn't ready yet. In the bus reset tasklet we | |
1658 | * then set up the real values for the two registers. | |
1659 | * | |
1660 | * We use ohci->lock to avoid racing with the code that sets | |
1661 | * ohci->next_config_rom to NULL (see bus_reset_tasklet). | |
1662 | */ | |
1663 | ||
1664 | next_config_rom = | |
1665 | dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE, | |
1666 | &next_config_rom_bus, GFP_KERNEL); | |
1667 | if (next_config_rom == NULL) | |
1668 | return -ENOMEM; | |
1669 | ||
1670 | spin_lock_irqsave(&ohci->lock, flags); | |
1671 | ||
1672 | if (ohci->next_config_rom == NULL) { | |
1673 | ohci->next_config_rom = next_config_rom; | |
1674 | ohci->next_config_rom_bus = next_config_rom_bus; | |
1675 | ||
1676 | memset(ohci->next_config_rom, 0, CONFIG_ROM_SIZE); | |
1677 | fw_memcpy_to_be32(ohci->next_config_rom, config_rom, | |
1678 | length * 4); | |
1679 | ||
1680 | ohci->next_header = config_rom[0]; | |
1681 | ohci->next_config_rom[0] = 0; | |
1682 | ||
1683 | reg_write(ohci, OHCI1394_ConfigROMmap, | |
1684 | ohci->next_config_rom_bus); | |
2dbd7d7e | 1685 | ret = 0; |
ed568912 KH |
1686 | } |
1687 | ||
1688 | spin_unlock_irqrestore(&ohci->lock, flags); | |
1689 | ||
c781c06d KH |
1690 | /* |
1691 | * Now initiate a bus reset to have the changes take | |
ed568912 KH |
1692 | * effect. We clean up the old config rom memory and DMA |
1693 | * mappings in the bus reset tasklet, since the OHCI | |
1694 | * controller could need to access it before the bus reset | |
c781c06d KH |
1695 | * takes effect. |
1696 | */ | |
2dbd7d7e | 1697 | if (ret == 0) |
ed568912 | 1698 | fw_core_initiate_bus_reset(&ohci->card, 1); |
4eaff7d6 SR |
1699 | else |
1700 | dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, | |
1701 | next_config_rom, next_config_rom_bus); | |
ed568912 | 1702 | |
2dbd7d7e | 1703 | return ret; |
ed568912 KH |
1704 | } |
1705 | ||
1706 | static void ohci_send_request(struct fw_card *card, struct fw_packet *packet) | |
1707 | { | |
1708 | struct fw_ohci *ohci = fw_ohci(card); | |
1709 | ||
1710 | at_context_transmit(&ohci->at_request_ctx, packet); | |
1711 | } | |
1712 | ||
1713 | static void ohci_send_response(struct fw_card *card, struct fw_packet *packet) | |
1714 | { | |
1715 | struct fw_ohci *ohci = fw_ohci(card); | |
1716 | ||
1717 | at_context_transmit(&ohci->at_response_ctx, packet); | |
1718 | } | |
1719 | ||
730c32f5 KH |
1720 | static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet) |
1721 | { | |
1722 | struct fw_ohci *ohci = fw_ohci(card); | |
f319b6a0 KH |
1723 | struct context *ctx = &ohci->at_request_ctx; |
1724 | struct driver_data *driver_data = packet->driver_data; | |
2dbd7d7e | 1725 | int ret = -ENOENT; |
730c32f5 | 1726 | |
f319b6a0 | 1727 | tasklet_disable(&ctx->tasklet); |
730c32f5 | 1728 | |
f319b6a0 KH |
1729 | if (packet->ack != 0) |
1730 | goto out; | |
730c32f5 | 1731 | |
1d1dc5e8 SR |
1732 | if (packet->payload_bus) |
1733 | dma_unmap_single(ohci->card.device, packet->payload_bus, | |
1734 | packet->payload_length, DMA_TO_DEVICE); | |
1735 | ||
ad3c0fe8 | 1736 | log_ar_at_event('T', packet->speed, packet->header, 0x20); |
f319b6a0 KH |
1737 | driver_data->packet = NULL; |
1738 | packet->ack = RCODE_CANCELLED; | |
1739 | packet->callback(packet, &ohci->card, packet->ack); | |
2dbd7d7e | 1740 | ret = 0; |
f319b6a0 KH |
1741 | out: |
1742 | tasklet_enable(&ctx->tasklet); | |
730c32f5 | 1743 | |
2dbd7d7e | 1744 | return ret; |
730c32f5 KH |
1745 | } |
1746 | ||
53dca511 SR |
1747 | static int ohci_enable_phys_dma(struct fw_card *card, |
1748 | int node_id, int generation) | |
ed568912 | 1749 | { |
080de8c2 SR |
1750 | #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA |
1751 | return 0; | |
1752 | #else | |
ed568912 KH |
1753 | struct fw_ohci *ohci = fw_ohci(card); |
1754 | unsigned long flags; | |
2dbd7d7e | 1755 | int n, ret = 0; |
ed568912 | 1756 | |
c781c06d KH |
1757 | /* |
1758 | * FIXME: Make sure this bitmask is cleared when we clear the busReset | |
1759 | * interrupt bit. Clear physReqResourceAllBuses on bus reset. | |
1760 | */ | |
ed568912 KH |
1761 | |
1762 | spin_lock_irqsave(&ohci->lock, flags); | |
1763 | ||
1764 | if (ohci->generation != generation) { | |
2dbd7d7e | 1765 | ret = -ESTALE; |
ed568912 KH |
1766 | goto out; |
1767 | } | |
1768 | ||
c781c06d KH |
1769 | /* |
1770 | * Note, if the node ID contains a non-local bus ID, physical DMA is | |
1771 | * enabled for _all_ nodes on remote buses. | |
1772 | */ | |
907293d7 SR |
1773 | |
1774 | n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63; | |
1775 | if (n < 32) | |
1776 | reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n); | |
1777 | else | |
1778 | reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32)); | |
1779 | ||
ed568912 | 1780 | flush_writes(ohci); |
ed568912 | 1781 | out: |
6cad95fe | 1782 | spin_unlock_irqrestore(&ohci->lock, flags); |
2dbd7d7e SR |
1783 | |
1784 | return ret; | |
080de8c2 | 1785 | #endif /* CONFIG_FIREWIRE_OHCI_REMOTE_DMA */ |
ed568912 | 1786 | } |
373b2edd | 1787 | |
53dca511 | 1788 | static u64 ohci_get_bus_time(struct fw_card *card) |
d60d7f1d KH |
1789 | { |
1790 | struct fw_ohci *ohci = fw_ohci(card); | |
1791 | u32 cycle_time; | |
1792 | u64 bus_time; | |
1793 | ||
1794 | cycle_time = reg_read(ohci, OHCI1394_IsochronousCycleTimer); | |
3dcdc500 | 1795 | bus_time = ((u64)atomic_read(&ohci->bus_seconds) << 32) | cycle_time; |
d60d7f1d KH |
1796 | |
1797 | return bus_time; | |
1798 | } | |
1799 | ||
1aa292bb DM |
1800 | static void copy_iso_headers(struct iso_context *ctx, void *p) |
1801 | { | |
1802 | int i = ctx->header_length; | |
1803 | ||
1804 | if (i + ctx->base.header_size > PAGE_SIZE) | |
1805 | return; | |
1806 | ||
1807 | /* | |
1808 | * The iso header is byteswapped to little endian by | |
1809 | * the controller, but the remaining header quadlets | |
1810 | * are big endian. We want to present all the headers | |
1811 | * as big endian, so we have to swap the first quadlet. | |
1812 | */ | |
1813 | if (ctx->base.header_size > 0) | |
1814 | *(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4)); | |
1815 | if (ctx->base.header_size > 4) | |
1816 | *(u32 *) (ctx->header + i + 4) = __swab32(*(u32 *) p); | |
1817 | if (ctx->base.header_size > 8) | |
1818 | memcpy(ctx->header + i + 8, p + 8, ctx->base.header_size - 8); | |
1819 | ctx->header_length += ctx->base.header_size; | |
1820 | } | |
1821 | ||
d2746dc1 KH |
1822 | static int handle_ir_dualbuffer_packet(struct context *context, |
1823 | struct descriptor *d, | |
1824 | struct descriptor *last) | |
ed568912 | 1825 | { |
295e3feb KH |
1826 | struct iso_context *ctx = |
1827 | container_of(context, struct iso_context, context); | |
1828 | struct db_descriptor *db = (struct db_descriptor *) d; | |
c70dc788 | 1829 | __le32 *ir_header; |
9b32d5f3 | 1830 | size_t header_length; |
c70dc788 | 1831 | void *p, *end; |
d2746dc1 | 1832 | |
efbf390a | 1833 | if (db->first_res_count != 0 && db->second_res_count != 0) { |
0642b657 DM |
1834 | if (ctx->excess_bytes <= le16_to_cpu(db->second_req_count)) { |
1835 | /* This descriptor isn't done yet, stop iteration. */ | |
1836 | return 0; | |
1837 | } | |
1838 | ctx->excess_bytes -= le16_to_cpu(db->second_req_count); | |
1839 | } | |
295e3feb | 1840 | |
c70dc788 KH |
1841 | header_length = le16_to_cpu(db->first_req_count) - |
1842 | le16_to_cpu(db->first_res_count); | |
1843 | ||
c70dc788 KH |
1844 | p = db + 1; |
1845 | end = p + header_length; | |
1aa292bb DM |
1846 | while (p < end) { |
1847 | copy_iso_headers(ctx, p); | |
0642b657 | 1848 | ctx->excess_bytes += |
efbf390a | 1849 | (le32_to_cpu(*(__le32 *)(p + 4)) >> 16) & 0xffff; |
1aa292bb | 1850 | p += max(ctx->base.header_size, (size_t)8); |
c70dc788 | 1851 | } |
9b32d5f3 | 1852 | |
0642b657 DM |
1853 | ctx->excess_bytes -= le16_to_cpu(db->second_req_count) - |
1854 | le16_to_cpu(db->second_res_count); | |
1855 | ||
a77754a7 | 1856 | if (le16_to_cpu(db->control) & DESCRIPTOR_IRQ_ALWAYS) { |
c70dc788 KH |
1857 | ir_header = (__le32 *) (db + 1); |
1858 | ctx->base.callback(&ctx->base, | |
1859 | le32_to_cpu(ir_header[0]) & 0xffff, | |
9b32d5f3 | 1860 | ctx->header_length, ctx->header, |
295e3feb | 1861 | ctx->base.callback_data); |
9b32d5f3 KH |
1862 | ctx->header_length = 0; |
1863 | } | |
ed568912 | 1864 | |
295e3feb | 1865 | return 1; |
ed568912 KH |
1866 | } |
1867 | ||
a186b4a6 JW |
1868 | static int handle_ir_packet_per_buffer(struct context *context, |
1869 | struct descriptor *d, | |
1870 | struct descriptor *last) | |
1871 | { | |
1872 | struct iso_context *ctx = | |
1873 | container_of(context, struct iso_context, context); | |
bcee893c | 1874 | struct descriptor *pd; |
a186b4a6 | 1875 | __le32 *ir_header; |
bcee893c | 1876 | void *p; |
a186b4a6 | 1877 | |
bcee893c DM |
1878 | for (pd = d; pd <= last; pd++) { |
1879 | if (pd->transfer_status) | |
1880 | break; | |
1881 | } | |
1882 | if (pd > last) | |
a186b4a6 JW |
1883 | /* Descriptor(s) not done yet, stop iteration */ |
1884 | return 0; | |
1885 | ||
1aa292bb DM |
1886 | p = last + 1; |
1887 | copy_iso_headers(ctx, p); | |
a186b4a6 | 1888 | |
bcee893c DM |
1889 | if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) { |
1890 | ir_header = (__le32 *) p; | |
a186b4a6 JW |
1891 | ctx->base.callback(&ctx->base, |
1892 | le32_to_cpu(ir_header[0]) & 0xffff, | |
1893 | ctx->header_length, ctx->header, | |
1894 | ctx->base.callback_data); | |
1895 | ctx->header_length = 0; | |
1896 | } | |
1897 | ||
a186b4a6 JW |
1898 | return 1; |
1899 | } | |
1900 | ||
30200739 KH |
1901 | static int handle_it_packet(struct context *context, |
1902 | struct descriptor *d, | |
1903 | struct descriptor *last) | |
ed568912 | 1904 | { |
30200739 KH |
1905 | struct iso_context *ctx = |
1906 | container_of(context, struct iso_context, context); | |
373b2edd | 1907 | |
30200739 KH |
1908 | if (last->transfer_status == 0) |
1909 | /* This descriptor isn't done yet, stop iteration. */ | |
1910 | return 0; | |
1911 | ||
a77754a7 | 1912 | if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) |
9b32d5f3 KH |
1913 | ctx->base.callback(&ctx->base, le16_to_cpu(last->res_count), |
1914 | 0, NULL, ctx->base.callback_data); | |
30200739 KH |
1915 | |
1916 | return 1; | |
ed568912 KH |
1917 | } |
1918 | ||
53dca511 | 1919 | static struct fw_iso_context *ohci_allocate_iso_context(struct fw_card *card, |
4817ed24 | 1920 | int type, int channel, size_t header_size) |
ed568912 KH |
1921 | { |
1922 | struct fw_ohci *ohci = fw_ohci(card); | |
1923 | struct iso_context *ctx, *list; | |
30200739 | 1924 | descriptor_callback_t callback; |
4817ed24 | 1925 | u64 *channels, dont_care = ~0ULL; |
295e3feb | 1926 | u32 *mask, regs; |
ed568912 | 1927 | unsigned long flags; |
2dbd7d7e | 1928 | int index, ret = -ENOMEM; |
ed568912 KH |
1929 | |
1930 | if (type == FW_ISO_CONTEXT_TRANSMIT) { | |
4817ed24 | 1931 | channels = &dont_care; |
ed568912 KH |
1932 | mask = &ohci->it_context_mask; |
1933 | list = ohci->it_context_list; | |
30200739 | 1934 | callback = handle_it_packet; |
ed568912 | 1935 | } else { |
4817ed24 | 1936 | channels = &ohci->ir_context_channels; |
373b2edd SR |
1937 | mask = &ohci->ir_context_mask; |
1938 | list = ohci->ir_context_list; | |
95984f62 | 1939 | if (ohci->use_dualbuffer) |
a186b4a6 JW |
1940 | callback = handle_ir_dualbuffer_packet; |
1941 | else | |
1942 | callback = handle_ir_packet_per_buffer; | |
ed568912 KH |
1943 | } |
1944 | ||
1945 | spin_lock_irqsave(&ohci->lock, flags); | |
4817ed24 SR |
1946 | index = *channels & 1ULL << channel ? ffs(*mask) - 1 : -1; |
1947 | if (index >= 0) { | |
1948 | *channels &= ~(1ULL << channel); | |
ed568912 | 1949 | *mask &= ~(1 << index); |
4817ed24 | 1950 | } |
ed568912 KH |
1951 | spin_unlock_irqrestore(&ohci->lock, flags); |
1952 | ||
1953 | if (index < 0) | |
1954 | return ERR_PTR(-EBUSY); | |
1955 | ||
373b2edd SR |
1956 | if (type == FW_ISO_CONTEXT_TRANSMIT) |
1957 | regs = OHCI1394_IsoXmitContextBase(index); | |
1958 | else | |
1959 | regs = OHCI1394_IsoRcvContextBase(index); | |
1960 | ||
ed568912 | 1961 | ctx = &list[index]; |
2d826cc5 | 1962 | memset(ctx, 0, sizeof(*ctx)); |
9b32d5f3 KH |
1963 | ctx->header_length = 0; |
1964 | ctx->header = (void *) __get_free_page(GFP_KERNEL); | |
1965 | if (ctx->header == NULL) | |
1966 | goto out; | |
1967 | ||
2dbd7d7e SR |
1968 | ret = context_init(&ctx->context, ohci, regs, callback); |
1969 | if (ret < 0) | |
9b32d5f3 | 1970 | goto out_with_header; |
ed568912 KH |
1971 | |
1972 | return &ctx->base; | |
9b32d5f3 KH |
1973 | |
1974 | out_with_header: | |
1975 | free_page((unsigned long)ctx->header); | |
1976 | out: | |
1977 | spin_lock_irqsave(&ohci->lock, flags); | |
1978 | *mask |= 1 << index; | |
1979 | spin_unlock_irqrestore(&ohci->lock, flags); | |
1980 | ||
2dbd7d7e | 1981 | return ERR_PTR(ret); |
ed568912 KH |
1982 | } |
1983 | ||
eb0306ea KH |
1984 | static int ohci_start_iso(struct fw_iso_context *base, |
1985 | s32 cycle, u32 sync, u32 tags) | |
ed568912 | 1986 | { |
373b2edd | 1987 | struct iso_context *ctx = container_of(base, struct iso_context, base); |
30200739 | 1988 | struct fw_ohci *ohci = ctx->context.ohci; |
8a2f7d93 | 1989 | u32 control, match; |
ed568912 KH |
1990 | int index; |
1991 | ||
295e3feb KH |
1992 | if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) { |
1993 | index = ctx - ohci->it_context_list; | |
8a2f7d93 KH |
1994 | match = 0; |
1995 | if (cycle >= 0) | |
1996 | match = IT_CONTEXT_CYCLE_MATCH_ENABLE | | |
295e3feb | 1997 | (cycle & 0x7fff) << 16; |
21efb3cf | 1998 | |
295e3feb KH |
1999 | reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index); |
2000 | reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index); | |
8a2f7d93 | 2001 | context_run(&ctx->context, match); |
295e3feb KH |
2002 | } else { |
2003 | index = ctx - ohci->ir_context_list; | |
a186b4a6 | 2004 | control = IR_CONTEXT_ISOCH_HEADER; |
95984f62 | 2005 | if (ohci->use_dualbuffer) |
a186b4a6 | 2006 | control |= IR_CONTEXT_DUAL_BUFFER_MODE; |
8a2f7d93 KH |
2007 | match = (tags << 28) | (sync << 8) | ctx->base.channel; |
2008 | if (cycle >= 0) { | |
2009 | match |= (cycle & 0x07fff) << 12; | |
2010 | control |= IR_CONTEXT_CYCLE_MATCH_ENABLE; | |
2011 | } | |
ed568912 | 2012 | |
295e3feb KH |
2013 | reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index); |
2014 | reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index); | |
a77754a7 | 2015 | reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match); |
8a2f7d93 | 2016 | context_run(&ctx->context, control); |
295e3feb | 2017 | } |
ed568912 KH |
2018 | |
2019 | return 0; | |
2020 | } | |
2021 | ||
b8295668 KH |
2022 | static int ohci_stop_iso(struct fw_iso_context *base) |
2023 | { | |
2024 | struct fw_ohci *ohci = fw_ohci(base->card); | |
373b2edd | 2025 | struct iso_context *ctx = container_of(base, struct iso_context, base); |
b8295668 KH |
2026 | int index; |
2027 | ||
2028 | if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) { | |
2029 | index = ctx - ohci->it_context_list; | |
2030 | reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index); | |
2031 | } else { | |
2032 | index = ctx - ohci->ir_context_list; | |
2033 | reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index); | |
2034 | } | |
2035 | flush_writes(ohci); | |
2036 | context_stop(&ctx->context); | |
2037 | ||
2038 | return 0; | |
2039 | } | |
2040 | ||
ed568912 KH |
2041 | static void ohci_free_iso_context(struct fw_iso_context *base) |
2042 | { | |
2043 | struct fw_ohci *ohci = fw_ohci(base->card); | |
373b2edd | 2044 | struct iso_context *ctx = container_of(base, struct iso_context, base); |
ed568912 KH |
2045 | unsigned long flags; |
2046 | int index; | |
2047 | ||
b8295668 KH |
2048 | ohci_stop_iso(base); |
2049 | context_release(&ctx->context); | |
9b32d5f3 | 2050 | free_page((unsigned long)ctx->header); |
b8295668 | 2051 | |
ed568912 KH |
2052 | spin_lock_irqsave(&ohci->lock, flags); |
2053 | ||
2054 | if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) { | |
2055 | index = ctx - ohci->it_context_list; | |
ed568912 KH |
2056 | ohci->it_context_mask |= 1 << index; |
2057 | } else { | |
2058 | index = ctx - ohci->ir_context_list; | |
ed568912 | 2059 | ohci->ir_context_mask |= 1 << index; |
4817ed24 | 2060 | ohci->ir_context_channels |= 1ULL << base->channel; |
ed568912 | 2061 | } |
ed568912 KH |
2062 | |
2063 | spin_unlock_irqrestore(&ohci->lock, flags); | |
2064 | } | |
2065 | ||
53dca511 SR |
2066 | static int ohci_queue_iso_transmit(struct fw_iso_context *base, |
2067 | struct fw_iso_packet *packet, | |
2068 | struct fw_iso_buffer *buffer, | |
2069 | unsigned long payload) | |
ed568912 | 2070 | { |
373b2edd | 2071 | struct iso_context *ctx = container_of(base, struct iso_context, base); |
30200739 | 2072 | struct descriptor *d, *last, *pd; |
ed568912 KH |
2073 | struct fw_iso_packet *p; |
2074 | __le32 *header; | |
9aad8125 | 2075 | dma_addr_t d_bus, page_bus; |
ed568912 KH |
2076 | u32 z, header_z, payload_z, irq; |
2077 | u32 payload_index, payload_end_index, next_page_index; | |
30200739 | 2078 | int page, end_page, i, length, offset; |
ed568912 | 2079 | |
c781c06d KH |
2080 | /* |
2081 | * FIXME: Cycle lost behavior should be configurable: lose | |
2082 | * packet, retransmit or terminate.. | |
2083 | */ | |
ed568912 KH |
2084 | |
2085 | p = packet; | |
9aad8125 | 2086 | payload_index = payload; |
ed568912 KH |
2087 | |
2088 | if (p->skip) | |
2089 | z = 1; | |
2090 | else | |
2091 | z = 2; | |
2092 | if (p->header_length > 0) | |
2093 | z++; | |
2094 | ||
2095 | /* Determine the first page the payload isn't contained in. */ | |
2096 | end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT; | |
2097 | if (p->payload_length > 0) | |
2098 | payload_z = end_page - (payload_index >> PAGE_SHIFT); | |
2099 | else | |
2100 | payload_z = 0; | |
2101 | ||
2102 | z += payload_z; | |
2103 | ||
2104 | /* Get header size in number of descriptors. */ | |
2d826cc5 | 2105 | header_z = DIV_ROUND_UP(p->header_length, sizeof(*d)); |
ed568912 | 2106 | |
30200739 KH |
2107 | d = context_get_descriptors(&ctx->context, z + header_z, &d_bus); |
2108 | if (d == NULL) | |
2109 | return -ENOMEM; | |
ed568912 KH |
2110 | |
2111 | if (!p->skip) { | |
a77754a7 | 2112 | d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE); |
ed568912 KH |
2113 | d[0].req_count = cpu_to_le16(8); |
2114 | ||
2115 | header = (__le32 *) &d[1]; | |
a77754a7 KH |
2116 | header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) | |
2117 | IT_HEADER_TAG(p->tag) | | |
2118 | IT_HEADER_TCODE(TCODE_STREAM_DATA) | | |
2119 | IT_HEADER_CHANNEL(ctx->base.channel) | | |
2120 | IT_HEADER_SPEED(ctx->base.speed)); | |
ed568912 | 2121 | header[1] = |
a77754a7 | 2122 | cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length + |
ed568912 KH |
2123 | p->payload_length)); |
2124 | } | |
2125 | ||
2126 | if (p->header_length > 0) { | |
2127 | d[2].req_count = cpu_to_le16(p->header_length); | |
2d826cc5 | 2128 | d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d)); |
ed568912 KH |
2129 | memcpy(&d[z], p->header, p->header_length); |
2130 | } | |
2131 | ||
2132 | pd = d + z - payload_z; | |
2133 | payload_end_index = payload_index + p->payload_length; | |
2134 | for (i = 0; i < payload_z; i++) { | |
2135 | page = payload_index >> PAGE_SHIFT; | |
2136 | offset = payload_index & ~PAGE_MASK; | |
2137 | next_page_index = (page + 1) << PAGE_SHIFT; | |
2138 | length = | |
2139 | min(next_page_index, payload_end_index) - payload_index; | |
2140 | pd[i].req_count = cpu_to_le16(length); | |
9aad8125 KH |
2141 | |
2142 | page_bus = page_private(buffer->pages[page]); | |
2143 | pd[i].data_address = cpu_to_le32(page_bus + offset); | |
ed568912 KH |
2144 | |
2145 | payload_index += length; | |
2146 | } | |
2147 | ||
ed568912 | 2148 | if (p->interrupt) |
a77754a7 | 2149 | irq = DESCRIPTOR_IRQ_ALWAYS; |
ed568912 | 2150 | else |
a77754a7 | 2151 | irq = DESCRIPTOR_NO_IRQ; |
ed568912 | 2152 | |
30200739 | 2153 | last = z == 2 ? d : d + z - 1; |
a77754a7 KH |
2154 | last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST | |
2155 | DESCRIPTOR_STATUS | | |
2156 | DESCRIPTOR_BRANCH_ALWAYS | | |
cbb59da7 | 2157 | irq); |
ed568912 | 2158 | |
30200739 | 2159 | context_append(&ctx->context, d, z, header_z); |
ed568912 KH |
2160 | |
2161 | return 0; | |
2162 | } | |
373b2edd | 2163 | |
53dca511 SR |
2164 | static int ohci_queue_iso_receive_dualbuffer(struct fw_iso_context *base, |
2165 | struct fw_iso_packet *packet, | |
2166 | struct fw_iso_buffer *buffer, | |
2167 | unsigned long payload) | |
295e3feb KH |
2168 | { |
2169 | struct iso_context *ctx = container_of(base, struct iso_context, base); | |
2170 | struct db_descriptor *db = NULL; | |
2171 | struct descriptor *d; | |
2172 | struct fw_iso_packet *p; | |
2173 | dma_addr_t d_bus, page_bus; | |
2174 | u32 z, header_z, length, rest; | |
c70dc788 | 2175 | int page, offset, packet_count, header_size; |
373b2edd | 2176 | |
c781c06d KH |
2177 | /* |
2178 | * FIXME: Cycle lost behavior should be configurable: lose | |
2179 | * packet, retransmit or terminate.. | |
2180 | */ | |
295e3feb KH |
2181 | |
2182 | p = packet; | |
2183 | z = 2; | |
2184 | ||
c781c06d | 2185 | /* |
1aa292bb DM |
2186 | * The OHCI controller puts the isochronous header and trailer in the |
2187 | * buffer, so we need at least 8 bytes. | |
c781c06d | 2188 | */ |
c70dc788 | 2189 | packet_count = p->header_length / ctx->base.header_size; |
1aa292bb | 2190 | header_size = packet_count * max(ctx->base.header_size, (size_t)8); |
c70dc788 | 2191 | |
295e3feb | 2192 | /* Get header size in number of descriptors. */ |
2d826cc5 | 2193 | header_z = DIV_ROUND_UP(header_size, sizeof(*d)); |
295e3feb KH |
2194 | page = payload >> PAGE_SHIFT; |
2195 | offset = payload & ~PAGE_MASK; | |
2196 | rest = p->payload_length; | |
2197 | ||
295e3feb KH |
2198 | /* FIXME: make packet-per-buffer/dual-buffer a context option */ |
2199 | while (rest > 0) { | |
2200 | d = context_get_descriptors(&ctx->context, | |
2201 | z + header_z, &d_bus); | |
2202 | if (d == NULL) | |
2203 | return -ENOMEM; | |
2204 | ||
2205 | db = (struct db_descriptor *) d; | |
a77754a7 KH |
2206 | db->control = cpu_to_le16(DESCRIPTOR_STATUS | |
2207 | DESCRIPTOR_BRANCH_ALWAYS); | |
1aa292bb DM |
2208 | db->first_size = |
2209 | cpu_to_le16(max(ctx->base.header_size, (size_t)8)); | |
0642b657 DM |
2210 | if (p->skip && rest == p->payload_length) { |
2211 | db->control |= cpu_to_le16(DESCRIPTOR_WAIT); | |
2212 | db->first_req_count = db->first_size; | |
2213 | } else { | |
2214 | db->first_req_count = cpu_to_le16(header_size); | |
2215 | } | |
1e1d196b | 2216 | db->first_res_count = db->first_req_count; |
2d826cc5 | 2217 | db->first_buffer = cpu_to_le32(d_bus + sizeof(*db)); |
373b2edd | 2218 | |
0642b657 DM |
2219 | if (p->skip && rest == p->payload_length) |
2220 | length = 4; | |
2221 | else if (offset + rest < PAGE_SIZE) | |
295e3feb KH |
2222 | length = rest; |
2223 | else | |
2224 | length = PAGE_SIZE - offset; | |
2225 | ||
1e1d196b KH |
2226 | db->second_req_count = cpu_to_le16(length); |
2227 | db->second_res_count = db->second_req_count; | |
295e3feb KH |
2228 | page_bus = page_private(buffer->pages[page]); |
2229 | db->second_buffer = cpu_to_le32(page_bus + offset); | |
2230 | ||
cb2d2cdb | 2231 | if (p->interrupt && length == rest) |
a77754a7 | 2232 | db->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS); |
cb2d2cdb | 2233 | |
295e3feb KH |
2234 | context_append(&ctx->context, d, z, header_z); |
2235 | offset = (offset + length) & ~PAGE_MASK; | |
2236 | rest -= length; | |
0642b657 DM |
2237 | if (offset == 0) |
2238 | page++; | |
295e3feb KH |
2239 | } |
2240 | ||
d2746dc1 KH |
2241 | return 0; |
2242 | } | |
21efb3cf | 2243 | |
53dca511 SR |
2244 | static int ohci_queue_iso_receive_packet_per_buffer(struct fw_iso_context *base, |
2245 | struct fw_iso_packet *packet, | |
2246 | struct fw_iso_buffer *buffer, | |
2247 | unsigned long payload) | |
a186b4a6 JW |
2248 | { |
2249 | struct iso_context *ctx = container_of(base, struct iso_context, base); | |
2250 | struct descriptor *d = NULL, *pd = NULL; | |
bcee893c | 2251 | struct fw_iso_packet *p = packet; |
a186b4a6 JW |
2252 | dma_addr_t d_bus, page_bus; |
2253 | u32 z, header_z, rest; | |
bcee893c DM |
2254 | int i, j, length; |
2255 | int page, offset, packet_count, header_size, payload_per_buffer; | |
a186b4a6 JW |
2256 | |
2257 | /* | |
1aa292bb DM |
2258 | * The OHCI controller puts the isochronous header and trailer in the |
2259 | * buffer, so we need at least 8 bytes. | |
a186b4a6 JW |
2260 | */ |
2261 | packet_count = p->header_length / ctx->base.header_size; | |
1aa292bb | 2262 | header_size = max(ctx->base.header_size, (size_t)8); |
a186b4a6 JW |
2263 | |
2264 | /* Get header size in number of descriptors. */ | |
2265 | header_z = DIV_ROUND_UP(header_size, sizeof(*d)); | |
2266 | page = payload >> PAGE_SHIFT; | |
2267 | offset = payload & ~PAGE_MASK; | |
bcee893c | 2268 | payload_per_buffer = p->payload_length / packet_count; |
a186b4a6 JW |
2269 | |
2270 | for (i = 0; i < packet_count; i++) { | |
2271 | /* d points to the header descriptor */ | |
bcee893c | 2272 | z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1; |
a186b4a6 | 2273 | d = context_get_descriptors(&ctx->context, |
bcee893c | 2274 | z + header_z, &d_bus); |
a186b4a6 JW |
2275 | if (d == NULL) |
2276 | return -ENOMEM; | |
2277 | ||
bcee893c DM |
2278 | d->control = cpu_to_le16(DESCRIPTOR_STATUS | |
2279 | DESCRIPTOR_INPUT_MORE); | |
2280 | if (p->skip && i == 0) | |
2281 | d->control |= cpu_to_le16(DESCRIPTOR_WAIT); | |
a186b4a6 JW |
2282 | d->req_count = cpu_to_le16(header_size); |
2283 | d->res_count = d->req_count; | |
bcee893c | 2284 | d->transfer_status = 0; |
a186b4a6 JW |
2285 | d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d))); |
2286 | ||
bcee893c DM |
2287 | rest = payload_per_buffer; |
2288 | for (j = 1; j < z; j++) { | |
2289 | pd = d + j; | |
2290 | pd->control = cpu_to_le16(DESCRIPTOR_STATUS | | |
2291 | DESCRIPTOR_INPUT_MORE); | |
2292 | ||
2293 | if (offset + rest < PAGE_SIZE) | |
2294 | length = rest; | |
2295 | else | |
2296 | length = PAGE_SIZE - offset; | |
2297 | pd->req_count = cpu_to_le16(length); | |
2298 | pd->res_count = pd->req_count; | |
2299 | pd->transfer_status = 0; | |
2300 | ||
2301 | page_bus = page_private(buffer->pages[page]); | |
2302 | pd->data_address = cpu_to_le32(page_bus + offset); | |
2303 | ||
2304 | offset = (offset + length) & ~PAGE_MASK; | |
2305 | rest -= length; | |
2306 | if (offset == 0) | |
2307 | page++; | |
2308 | } | |
a186b4a6 JW |
2309 | pd->control = cpu_to_le16(DESCRIPTOR_STATUS | |
2310 | DESCRIPTOR_INPUT_LAST | | |
2311 | DESCRIPTOR_BRANCH_ALWAYS); | |
bcee893c | 2312 | if (p->interrupt && i == packet_count - 1) |
a186b4a6 JW |
2313 | pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS); |
2314 | ||
a186b4a6 JW |
2315 | context_append(&ctx->context, d, z, header_z); |
2316 | } | |
2317 | ||
2318 | return 0; | |
2319 | } | |
2320 | ||
53dca511 SR |
2321 | static int ohci_queue_iso(struct fw_iso_context *base, |
2322 | struct fw_iso_packet *packet, | |
2323 | struct fw_iso_buffer *buffer, | |
2324 | unsigned long payload) | |
295e3feb | 2325 | { |
e364cf4e | 2326 | struct iso_context *ctx = container_of(base, struct iso_context, base); |
fe5ca634 | 2327 | unsigned long flags; |
2dbd7d7e | 2328 | int ret; |
e364cf4e | 2329 | |
fe5ca634 | 2330 | spin_lock_irqsave(&ctx->context.ohci->lock, flags); |
295e3feb | 2331 | if (base->type == FW_ISO_CONTEXT_TRANSMIT) |
2dbd7d7e | 2332 | ret = ohci_queue_iso_transmit(base, packet, buffer, payload); |
95984f62 | 2333 | else if (ctx->context.ohci->use_dualbuffer) |
2dbd7d7e SR |
2334 | ret = ohci_queue_iso_receive_dualbuffer(base, packet, |
2335 | buffer, payload); | |
e364cf4e | 2336 | else |
2dbd7d7e SR |
2337 | ret = ohci_queue_iso_receive_packet_per_buffer(base, packet, |
2338 | buffer, payload); | |
fe5ca634 DM |
2339 | spin_unlock_irqrestore(&ctx->context.ohci->lock, flags); |
2340 | ||
2dbd7d7e | 2341 | return ret; |
295e3feb KH |
2342 | } |
2343 | ||
21ebcd12 | 2344 | static const struct fw_card_driver ohci_driver = { |
ed568912 KH |
2345 | .enable = ohci_enable, |
2346 | .update_phy_reg = ohci_update_phy_reg, | |
2347 | .set_config_rom = ohci_set_config_rom, | |
2348 | .send_request = ohci_send_request, | |
2349 | .send_response = ohci_send_response, | |
730c32f5 | 2350 | .cancel_packet = ohci_cancel_packet, |
ed568912 | 2351 | .enable_phys_dma = ohci_enable_phys_dma, |
d60d7f1d | 2352 | .get_bus_time = ohci_get_bus_time, |
ed568912 KH |
2353 | |
2354 | .allocate_iso_context = ohci_allocate_iso_context, | |
2355 | .free_iso_context = ohci_free_iso_context, | |
2356 | .queue_iso = ohci_queue_iso, | |
69cdb726 | 2357 | .start_iso = ohci_start_iso, |
b8295668 | 2358 | .stop_iso = ohci_stop_iso, |
ed568912 KH |
2359 | }; |
2360 | ||
ea8d006b | 2361 | #ifdef CONFIG_PPC_PMAC |
2ed0f181 SR |
2362 | static void ohci_pmac_on(struct pci_dev *dev) |
2363 | { | |
ea8d006b SR |
2364 | if (machine_is(powermac)) { |
2365 | struct device_node *ofn = pci_device_to_OF_node(dev); | |
2366 | ||
2367 | if (ofn) { | |
2368 | pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1); | |
2369 | pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1); | |
2370 | } | |
2371 | } | |
2ed0f181 SR |
2372 | } |
2373 | ||
2374 | static void ohci_pmac_off(struct pci_dev *dev) | |
2375 | { | |
2376 | if (machine_is(powermac)) { | |
2377 | struct device_node *ofn = pci_device_to_OF_node(dev); | |
2378 | ||
2379 | if (ofn) { | |
2380 | pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0); | |
2381 | pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0); | |
2382 | } | |
2383 | } | |
2384 | } | |
2385 | #else | |
2386 | #define ohci_pmac_on(dev) | |
2387 | #define ohci_pmac_off(dev) | |
ea8d006b SR |
2388 | #endif /* CONFIG_PPC_PMAC */ |
2389 | ||
fc383796 SR |
2390 | #define PCI_VENDOR_ID_AGERE PCI_VENDOR_ID_ATT |
2391 | #define PCI_DEVICE_ID_AGERE_FW643 0x5901 | |
2392 | ||
53dca511 SR |
2393 | static int __devinit pci_probe(struct pci_dev *dev, |
2394 | const struct pci_device_id *ent) | |
2ed0f181 SR |
2395 | { |
2396 | struct fw_ohci *ohci; | |
95984f62 | 2397 | u32 bus_options, max_receive, link_speed, version; |
2ed0f181 SR |
2398 | u64 guid; |
2399 | int err; | |
2400 | size_t size; | |
2401 | ||
2d826cc5 | 2402 | ohci = kzalloc(sizeof(*ohci), GFP_KERNEL); |
ed568912 | 2403 | if (ohci == NULL) { |
7007a076 SR |
2404 | err = -ENOMEM; |
2405 | goto fail; | |
ed568912 KH |
2406 | } |
2407 | ||
2408 | fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev); | |
2409 | ||
130d5496 SR |
2410 | ohci_pmac_on(dev); |
2411 | ||
d79406dd KH |
2412 | err = pci_enable_device(dev); |
2413 | if (err) { | |
7007a076 | 2414 | fw_error("Failed to enable OHCI hardware\n"); |
bd7dee63 | 2415 | goto fail_free; |
ed568912 KH |
2416 | } |
2417 | ||
2418 | pci_set_master(dev); | |
2419 | pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0); | |
2420 | pci_set_drvdata(dev, ohci); | |
2421 | ||
2422 | spin_lock_init(&ohci->lock); | |
2423 | ||
2424 | tasklet_init(&ohci->bus_reset_tasklet, | |
2425 | bus_reset_tasklet, (unsigned long)ohci); | |
2426 | ||
d79406dd KH |
2427 | err = pci_request_region(dev, 0, ohci_driver_name); |
2428 | if (err) { | |
ed568912 | 2429 | fw_error("MMIO resource unavailable\n"); |
d79406dd | 2430 | goto fail_disable; |
ed568912 KH |
2431 | } |
2432 | ||
2433 | ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE); | |
2434 | if (ohci->registers == NULL) { | |
2435 | fw_error("Failed to remap registers\n"); | |
d79406dd KH |
2436 | err = -ENXIO; |
2437 | goto fail_iomem; | |
ed568912 KH |
2438 | } |
2439 | ||
95984f62 SR |
2440 | version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff; |
2441 | ohci->use_dualbuffer = version >= OHCI_VERSION_1_1; | |
2442 | ||
fc383796 SR |
2443 | /* dual-buffer mode is broken if more than one IR context is active */ |
2444 | if (dev->vendor == PCI_VENDOR_ID_AGERE && | |
2445 | dev->device == PCI_DEVICE_ID_AGERE_FW643) | |
2446 | ohci->use_dualbuffer = false; | |
2447 | ||
4fe0badd SR |
2448 | /* dual-buffer mode is broken */ |
2449 | if (dev->vendor == PCI_VENDOR_ID_RICOH && | |
2450 | dev->device == PCI_DEVICE_ID_RICOH_R5C832) | |
2451 | ohci->use_dualbuffer = false; | |
2452 | ||
95984f62 SR |
2453 | /* x86-32 currently doesn't use highmem for dma_alloc_coherent */ |
2454 | #if !defined(CONFIG_X86_32) | |
2455 | /* dual-buffer mode is broken with descriptor addresses above 2G */ | |
2456 | if (dev->vendor == PCI_VENDOR_ID_TI && | |
2457 | dev->device == PCI_DEVICE_ID_TI_TSB43AB22) | |
2458 | ohci->use_dualbuffer = false; | |
2459 | #endif | |
2460 | ||
2461 | #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32) | |
2462 | ohci->old_uninorth = dev->vendor == PCI_VENDOR_ID_APPLE && | |
2463 | dev->device == PCI_DEVICE_ID_APPLE_UNI_N_FW; | |
2464 | #endif | |
2465 | ohci->bus_reset_packet_quirk = dev->vendor == PCI_VENDOR_ID_TI; | |
2466 | ||
ed568912 KH |
2467 | ar_context_init(&ohci->ar_request_ctx, ohci, |
2468 | OHCI1394_AsReqRcvContextControlSet); | |
2469 | ||
2470 | ar_context_init(&ohci->ar_response_ctx, ohci, | |
2471 | OHCI1394_AsRspRcvContextControlSet); | |
2472 | ||
fe5ca634 | 2473 | context_init(&ohci->at_request_ctx, ohci, |
f319b6a0 | 2474 | OHCI1394_AsReqTrContextControlSet, handle_at_packet); |
ed568912 | 2475 | |
fe5ca634 | 2476 | context_init(&ohci->at_response_ctx, ohci, |
f319b6a0 | 2477 | OHCI1394_AsRspTrContextControlSet, handle_at_packet); |
ed568912 | 2478 | |
ed568912 KH |
2479 | reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0); |
2480 | ohci->it_context_mask = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet); | |
2481 | reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0); | |
2482 | size = sizeof(struct iso_context) * hweight32(ohci->it_context_mask); | |
2483 | ohci->it_context_list = kzalloc(size, GFP_KERNEL); | |
2484 | ||
2485 | reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0); | |
4817ed24 | 2486 | ohci->ir_context_channels = ~0ULL; |
ed568912 KH |
2487 | ohci->ir_context_mask = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet); |
2488 | reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0); | |
2489 | size = sizeof(struct iso_context) * hweight32(ohci->ir_context_mask); | |
2490 | ohci->ir_context_list = kzalloc(size, GFP_KERNEL); | |
2491 | ||
2492 | if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) { | |
d79406dd | 2493 | err = -ENOMEM; |
7007a076 | 2494 | goto fail_contexts; |
ed568912 KH |
2495 | } |
2496 | ||
2497 | /* self-id dma buffer allocation */ | |
2498 | ohci->self_id_cpu = dma_alloc_coherent(ohci->card.device, | |
2499 | SELF_ID_BUF_SIZE, | |
2500 | &ohci->self_id_bus, | |
2501 | GFP_KERNEL); | |
2502 | if (ohci->self_id_cpu == NULL) { | |
d79406dd | 2503 | err = -ENOMEM; |
7007a076 | 2504 | goto fail_contexts; |
ed568912 KH |
2505 | } |
2506 | ||
ed568912 KH |
2507 | bus_options = reg_read(ohci, OHCI1394_BusOptions); |
2508 | max_receive = (bus_options >> 12) & 0xf; | |
2509 | link_speed = bus_options & 0x7; | |
2510 | guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) | | |
2511 | reg_read(ohci, OHCI1394_GUIDLo); | |
2512 | ||
d79406dd | 2513 | err = fw_card_add(&ohci->card, max_receive, link_speed, guid); |
e1eff7a3 | 2514 | if (err) |
d79406dd | 2515 | goto fail_self_id; |
ed568912 | 2516 | |
500be725 | 2517 | fw_notify("Added fw-ohci device %s, OHCI version %x.%x\n", |
a1f64819 | 2518 | dev_name(&dev->dev), version >> 16, version & 0xff); |
e1eff7a3 | 2519 | |
ed568912 | 2520 | return 0; |
d79406dd KH |
2521 | |
2522 | fail_self_id: | |
2523 | dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE, | |
2524 | ohci->self_id_cpu, ohci->self_id_bus); | |
7007a076 | 2525 | fail_contexts: |
d79406dd | 2526 | kfree(ohci->ir_context_list); |
7007a076 SR |
2527 | kfree(ohci->it_context_list); |
2528 | context_release(&ohci->at_response_ctx); | |
2529 | context_release(&ohci->at_request_ctx); | |
2530 | ar_context_release(&ohci->ar_response_ctx); | |
2531 | ar_context_release(&ohci->ar_request_ctx); | |
d79406dd KH |
2532 | pci_iounmap(dev, ohci->registers); |
2533 | fail_iomem: | |
2534 | pci_release_region(dev, 0); | |
2535 | fail_disable: | |
2536 | pci_disable_device(dev); | |
bd7dee63 SR |
2537 | fail_free: |
2538 | kfree(&ohci->card); | |
130d5496 | 2539 | ohci_pmac_off(dev); |
7007a076 SR |
2540 | fail: |
2541 | if (err == -ENOMEM) | |
2542 | fw_error("Out of memory\n"); | |
d79406dd KH |
2543 | |
2544 | return err; | |
ed568912 KH |
2545 | } |
2546 | ||
2547 | static void pci_remove(struct pci_dev *dev) | |
2548 | { | |
2549 | struct fw_ohci *ohci; | |
2550 | ||
2551 | ohci = pci_get_drvdata(dev); | |
e254a4b4 KH |
2552 | reg_write(ohci, OHCI1394_IntMaskClear, ~0); |
2553 | flush_writes(ohci); | |
ed568912 KH |
2554 | fw_core_remove_card(&ohci->card); |
2555 | ||
c781c06d KH |
2556 | /* |
2557 | * FIXME: Fail all pending packets here, now that the upper | |
2558 | * layers can't queue any more. | |
2559 | */ | |
ed568912 KH |
2560 | |
2561 | software_reset(ohci); | |
2562 | free_irq(dev->irq, ohci); | |
a55709ba JF |
2563 | |
2564 | if (ohci->next_config_rom && ohci->next_config_rom != ohci->config_rom) | |
2565 | dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, | |
2566 | ohci->next_config_rom, ohci->next_config_rom_bus); | |
2567 | if (ohci->config_rom) | |
2568 | dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, | |
2569 | ohci->config_rom, ohci->config_rom_bus); | |
d79406dd KH |
2570 | dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE, |
2571 | ohci->self_id_cpu, ohci->self_id_bus); | |
a55709ba JF |
2572 | ar_context_release(&ohci->ar_request_ctx); |
2573 | ar_context_release(&ohci->ar_response_ctx); | |
2574 | context_release(&ohci->at_request_ctx); | |
2575 | context_release(&ohci->at_response_ctx); | |
d79406dd KH |
2576 | kfree(ohci->it_context_list); |
2577 | kfree(ohci->ir_context_list); | |
2578 | pci_iounmap(dev, ohci->registers); | |
2579 | pci_release_region(dev, 0); | |
2580 | pci_disable_device(dev); | |
bd7dee63 | 2581 | kfree(&ohci->card); |
2ed0f181 | 2582 | ohci_pmac_off(dev); |
ea8d006b | 2583 | |
ed568912 KH |
2584 | fw_notify("Removed fw-ohci device.\n"); |
2585 | } | |
2586 | ||
2aef469a | 2587 | #ifdef CONFIG_PM |
2ed0f181 | 2588 | static int pci_suspend(struct pci_dev *dev, pm_message_t state) |
2aef469a | 2589 | { |
2ed0f181 | 2590 | struct fw_ohci *ohci = pci_get_drvdata(dev); |
2aef469a KH |
2591 | int err; |
2592 | ||
2593 | software_reset(ohci); | |
2ed0f181 SR |
2594 | free_irq(dev->irq, ohci); |
2595 | err = pci_save_state(dev); | |
2aef469a | 2596 | if (err) { |
8a8cea27 | 2597 | fw_error("pci_save_state failed\n"); |
2aef469a KH |
2598 | return err; |
2599 | } | |
2ed0f181 | 2600 | err = pci_set_power_state(dev, pci_choose_state(dev, state)); |
55111428 SR |
2601 | if (err) |
2602 | fw_error("pci_set_power_state failed with %d\n", err); | |
2ed0f181 | 2603 | ohci_pmac_off(dev); |
ea8d006b | 2604 | |
2aef469a KH |
2605 | return 0; |
2606 | } | |
2607 | ||
2ed0f181 | 2608 | static int pci_resume(struct pci_dev *dev) |
2aef469a | 2609 | { |
2ed0f181 | 2610 | struct fw_ohci *ohci = pci_get_drvdata(dev); |
2aef469a KH |
2611 | int err; |
2612 | ||
2ed0f181 SR |
2613 | ohci_pmac_on(dev); |
2614 | pci_set_power_state(dev, PCI_D0); | |
2615 | pci_restore_state(dev); | |
2616 | err = pci_enable_device(dev); | |
2aef469a | 2617 | if (err) { |
8a8cea27 | 2618 | fw_error("pci_enable_device failed\n"); |
2aef469a KH |
2619 | return err; |
2620 | } | |
2621 | ||
0bd243c4 | 2622 | return ohci_enable(&ohci->card, NULL, 0); |
2aef469a KH |
2623 | } |
2624 | #endif | |
2625 | ||
ed568912 KH |
2626 | static struct pci_device_id pci_table[] = { |
2627 | { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) }, | |
2628 | { } | |
2629 | }; | |
2630 | ||
2631 | MODULE_DEVICE_TABLE(pci, pci_table); | |
2632 | ||
2633 | static struct pci_driver fw_ohci_pci_driver = { | |
2634 | .name = ohci_driver_name, | |
2635 | .id_table = pci_table, | |
2636 | .probe = pci_probe, | |
2637 | .remove = pci_remove, | |
2aef469a KH |
2638 | #ifdef CONFIG_PM |
2639 | .resume = pci_resume, | |
2640 | .suspend = pci_suspend, | |
2641 | #endif | |
ed568912 KH |
2642 | }; |
2643 | ||
2644 | MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>"); | |
2645 | MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers"); | |
2646 | MODULE_LICENSE("GPL"); | |
2647 | ||
1e4c7b0d OH |
2648 | /* Provide a module alias so root-on-sbp2 initrds don't break. */ |
2649 | #ifndef CONFIG_IEEE1394_OHCI1394_MODULE | |
2650 | MODULE_ALIAS("ohci1394"); | |
2651 | #endif | |
2652 | ||
ed568912 KH |
2653 | static int __init fw_ohci_init(void) |
2654 | { | |
2655 | return pci_register_driver(&fw_ohci_pci_driver); | |
2656 | } | |
2657 | ||
2658 | static void __exit fw_ohci_cleanup(void) | |
2659 | { | |
2660 | pci_unregister_driver(&fw_ohci_pci_driver); | |
2661 | } | |
2662 | ||
2663 | module_init(fw_ohci_init); | |
2664 | module_exit(fw_ohci_cleanup); |