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Merge branches 'for-4.4/upstream-fixes', 'for-4.5/async-suspend', 'for-4.5/container...
[mirror_ubuntu-artful-kernel.git] / drivers / firewire / ohci.c
CommitLineData
c781c06d
KH		 1/*
2 * Driver for OHCI 1394 controllers
ed568912 3 *
ed568912
KH		 4 * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software Foundation,
18 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
dd23736e 21#include <linux/bitops.h>
65b2742a 22#include <linux/bug.h>
e524f616 23#include <linux/compiler.h>
ed568912 24#include <linux/delay.h>
e8ca9702 25#include <linux/device.h>
cf3e72fd 26#include <linux/dma-mapping.h>
77c9a5da 27#include <linux/firewire.h>
e8ca9702 28#include <linux/firewire-constants.h>
a7fb60db
SR		 29#include <linux/init.h>
30#include <linux/interrupt.h>
e8ca9702 31#include <linux/io.h>
a7fb60db 32#include <linux/kernel.h>
e8ca9702 33#include <linux/list.h>
faa2fb4e 34#include <linux/mm.h>
a7fb60db 35#include <linux/module.h>
ad3c0fe8 36#include <linux/moduleparam.h>
02d37bed 37#include <linux/mutex.h>
a7fb60db 38#include <linux/pci.h>
fc383796 39#include <linux/pci_ids.h>
5a0e3ad6 40#include <linux/slab.h>
c26f0234 41#include <linux/spinlock.h>
e8ca9702 42#include <linux/string.h>
e78483c5 43#include <linux/time.h>
7a39d8b8 44#include <linux/vmalloc.h>
2d7a36e2 45#include <linux/workqueue.h>
cf3e72fd 46
e8ca9702 47#include <asm/byteorder.h>
c26f0234 48#include <asm/page.h>
ed568912 49
ea8d006b
SR		 50#ifdef CONFIG_PPC_PMAC
51#include <asm/pmac_feature.h>
52#endif
53
77c9a5da
SR		 54#include "core.h"
55#include "ohci.h"
ed568912 56
de97cb64
PH		 57#define ohci_info(ohci, f, args...) dev_info(ohci->card.device, f, ##args)
58#define ohci_notice(ohci, f, args...) dev_notice(ohci->card.device, f, ##args)
59#define ohci_err(ohci, f, args...) dev_err(ohci->card.device, f, ##args)
60
a77754a7
KH		 61#define DESCRIPTOR_OUTPUT_MORE 0
62#define DESCRIPTOR_OUTPUT_LAST (1 << 12)
63#define DESCRIPTOR_INPUT_MORE (2 << 12)
64#define DESCRIPTOR_INPUT_LAST (3 << 12)
65#define DESCRIPTOR_STATUS (1 << 11)
66#define DESCRIPTOR_KEY_IMMEDIATE (2 << 8)
67#define DESCRIPTOR_PING (1 << 7)
68#define DESCRIPTOR_YY (1 << 6)
69#define DESCRIPTOR_NO_IRQ (0 << 4)
70#define DESCRIPTOR_IRQ_ERROR (1 << 4)
71#define DESCRIPTOR_IRQ_ALWAYS (3 << 4)
72#define DESCRIPTOR_BRANCH_ALWAYS (3 << 2)
73#define DESCRIPTOR_WAIT (3 << 0)
ed568912 74
be8dcab9
AL		 75#define DESCRIPTOR_CMD (0xf << 12)
76
ed568912
KH		 77struct descriptor {
78 __le16 req_count;
79 __le16 control;
80 __le32 data_address;
81 __le32 branch_address;
82 __le16 res_count;
83 __le16 transfer_status;
84} __attribute__((aligned(16)));
85
a77754a7
KH		 86#define CONTROL_SET(regs) (regs)
87#define CONTROL_CLEAR(regs) ((regs) + 4)
88#define COMMAND_PTR(regs) ((regs) + 12)
89#define CONTEXT_MATCH(regs) ((regs) + 16)
72e318e0 90
7a39d8b8
CL		 91#define AR_BUFFER_SIZE (32*1024)
92#define AR_BUFFERS_MIN DIV_ROUND_UP(AR_BUFFER_SIZE, PAGE_SIZE)
93/* we need at least two pages for proper list management */
94#define AR_BUFFERS (AR_BUFFERS_MIN >= 2 ? AR_BUFFERS_MIN : 2)
95
96#define MAX_ASYNC_PAYLOAD 4096
97#define MAX_AR_PACKET_SIZE (16 + MAX_ASYNC_PAYLOAD + 4)
98#define AR_WRAPAROUND_PAGES DIV_ROUND_UP(MAX_AR_PACKET_SIZE, PAGE_SIZE)
ed568912 99
32b46093
KH		 100struct ar_context {
101 struct fw_ohci *ohci;
7a39d8b8
CL		 102 struct page *pages[AR_BUFFERS];
103 void *buffer;
104 struct descriptor *descriptors;
105 dma_addr_t descriptors_bus;
32b46093 106 void *pointer;
7a39d8b8 107 unsigned int last_buffer_index;
72e318e0 108 u32 regs;
ed568912
KH		 109 struct tasklet_struct tasklet;
110};
111
30200739
KH		 112struct context;
113
114typedef int (*descriptor_callback_t)(struct context *ctx,
115 struct descriptor *d,
116 struct descriptor *last);
fe5ca634
DM		 117
118/*
119 * A buffer that contains a block of DMA-able coherent memory used for
120 * storing a portion of a DMA descriptor program.
121 */
122struct descriptor_buffer {
123 struct list_head list;
124 dma_addr_t buffer_bus;
125 size_t buffer_size;
126 size_t used;
127 struct descriptor buffer[0];
128};
129
30200739 130struct context {
373b2edd 131 struct fw_ohci *ohci;
30200739 132 u32 regs;
fe5ca634 133 int total_allocation;
a572e688 134 u32 current_bus;
386a4153 135 bool running;
82b662dc 136 bool flushing;
373b2edd 137
fe5ca634
DM		 138 /*
139 * List of page-sized buffers for storing DMA descriptors.
140 * Head of list contains buffers in use and tail of list contains
141 * free buffers.
142 */
143 struct list_head buffer_list;
144
145 /*
146 * Pointer to a buffer inside buffer_list that contains the tail
147 * end of the current DMA program.
148 */
149 struct descriptor_buffer *buffer_tail;
150
151 /*
152 * The descriptor containing the branch address of the first
153 * descriptor that has not yet been filled by the device.
154 */
155 struct descriptor *last;
156
157 /*
be8dcab9 158 * The last descriptor block in the DMA program. It contains the branch
fe5ca634
DM		 159 * address that must be updated upon appending a new descriptor.
160 */
161 struct descriptor *prev;
be8dcab9 162 int prev_z;
30200739
KH		 163
164 descriptor_callback_t callback;
165
373b2edd 166 struct tasklet_struct tasklet;
30200739 167};
30200739 168
a77754a7
KH		 169#define IT_HEADER_SY(v) ((v) << 0)
170#define IT_HEADER_TCODE(v) ((v) << 4)
171#define IT_HEADER_CHANNEL(v) ((v) << 8)
172#define IT_HEADER_TAG(v) ((v) << 14)
173#define IT_HEADER_SPEED(v) ((v) << 16)
174#define IT_HEADER_DATA_LENGTH(v) ((v) << 16)
ed568912
KH		 175
176struct iso_context {
177 struct fw_iso_context base;
30200739 178 struct context context;
9b32d5f3
KH		 179 void *header;
180 size_t header_length;
d1bbd209
CL		 181 unsigned long flushing_completions;
182 u32 mc_buffer_bus;
183 u16 mc_completed;
910e76c6 184 u16 last_timestamp;
dd23736e
ML		 185 u8 sync;
186 u8 tags;
ed568912
KH		 187};
188
189#define CONFIG_ROM_SIZE 1024
190
191struct fw_ohci {
192 struct fw_card card;
193
194 __iomem char *registers;
e636fe25 195 int node_id;
ed568912 196 int generation;
e09770db 197 int request_generation; /* for timestamping incoming requests */
4a635593 198 unsigned quirks;
a1a1132b 199 unsigned int pri_req_max;
a48777e0 200 u32 bus_time;
9d60ef2b 201 bool bus_time_running;
4ffb7a6a 202 bool is_root;
c8a94ded 203 bool csr_state_setclear_abdicate;
dd23736e
ML		 204 int n_ir;
205 int n_it;
c781c06d
KH		 206 /*
207 * Spinlock for accessing fw_ohci data. Never call out of
208 * this driver with this lock held.
209 */
ed568912 210 spinlock_t lock;
ed568912 211
02d37bed
SR		 212 struct mutex phy_reg_mutex;
213
ec766a79
CL		 214 void *misc_buffer;
215 dma_addr_t misc_buffer_bus;
216
ed568912
KH		 217 struct ar_context ar_request_ctx;
218 struct ar_context ar_response_ctx;
f319b6a0
KH		 219 struct context at_request_ctx;
220 struct context at_response_ctx;
ed568912 221
f117a3e3 222 u32 it_context_support;
872e330e 223 u32 it_context_mask; /* unoccupied IT contexts */
ed568912 224 struct iso_context *it_context_list;
872e330e 225 u64 ir_context_channels; /* unoccupied channels */
f117a3e3 226 u32 ir_context_support;
872e330e 227 u32 ir_context_mask; /* unoccupied IR contexts */
ed568912 228 struct iso_context *ir_context_list;
872e330e
SR		 229 u64 mc_channels; /* channels in use by the multichannel IR context */
230 bool mc_allocated;
ecb1cf9c
SR		 231
232 __be32 *config_rom;
233 dma_addr_t config_rom_bus;
234 __be32 *next_config_rom;
235 dma_addr_t next_config_rom_bus;
236 __be32 next_header;
237
af53122a 238 __le32 *self_id;
ecb1cf9c 239 dma_addr_t self_id_bus;
2d7a36e2 240 struct work_struct bus_reset_work;
ecb1cf9c
SR		 241
242 u32 self_id_buffer[512];
ed568912
KH		 243};
244
db9ae8fe
SG		 245static struct workqueue_struct *selfid_workqueue;
246
95688e97 247static inline struct fw_ohci *fw_ohci(struct fw_card *card)
ed568912
KH		 248{
249 return container_of(card, struct fw_ohci, card);
250}
251
295e3feb
KH		 252#define IT_CONTEXT_CYCLE_MATCH_ENABLE 0x80000000
253#define IR_CONTEXT_BUFFER_FILL 0x80000000
254#define IR_CONTEXT_ISOCH_HEADER 0x40000000
255#define IR_CONTEXT_CYCLE_MATCH_ENABLE 0x20000000
256#define IR_CONTEXT_MULTI_CHANNEL_MODE 0x10000000
257#define IR_CONTEXT_DUAL_BUFFER_MODE 0x08000000
ed568912
KH		 258
259#define CONTEXT_RUN 0x8000
260#define CONTEXT_WAKE 0x1000
261#define CONTEXT_DEAD 0x0800
262#define CONTEXT_ACTIVE 0x0400
263
8b7b6afa 264#define OHCI1394_MAX_AT_REQ_RETRIES 0xf
ed568912
KH		 265#define OHCI1394_MAX_AT_RESP_RETRIES 0x2
266#define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8
267
ed568912 268#define OHCI1394_REGISTER_SIZE 0x800
ed568912
KH		 269#define OHCI1394_PCI_HCI_Control 0x40
270#define SELF_ID_BUF_SIZE 0x800
32b46093 271#define OHCI_TCODE_PHY_PACKET 0x0e
e364cf4e 272#define OHCI_VERSION_1_1 0x010010
0edeefd9 273
ed568912
KH		 274static char ohci_driver_name[] = KBUILD_MODNAME;
275
0dbe15f8 276#define PCI_VENDOR_ID_PINNACLE_SYSTEMS 0x11bd
9993e0fe 277#define PCI_DEVICE_ID_AGERE_FW643 0x5901
d1bb399a 278#define PCI_DEVICE_ID_CREATIVE_SB1394 0x4001
262444ee 279#define PCI_DEVICE_ID_JMICRON_JMB38X_FW 0x2380
8301b91b 280#define PCI_DEVICE_ID_TI_TSB12LV22 0x8009
25935ebe
SG		 281#define PCI_DEVICE_ID_TI_TSB12LV26 0x8020
282#define PCI_DEVICE_ID_TI_TSB82AA2 0x8025
be8dcab9 283#define PCI_DEVICE_ID_VIA_VT630X 0x3044
be8dcab9 284#define PCI_REV_ID_VIA_VT6306 0x46
d151f985 285#define PCI_DEVICE_ID_VIA_VT6315 0x3403
8301b91b 286
0dbe15f8
SR		 287#define QUIRK_CYCLE_TIMER 0x1
288#define QUIRK_RESET_PACKET 0x2
289#define QUIRK_BE_HEADERS 0x4
290#define QUIRK_NO_1394A 0x8
291#define QUIRK_NO_MSI 0x10
292#define QUIRK_TI_SLLZ059 0x20
293#define QUIRK_IR_WAKE 0x40
4a635593
SR		 294
295/* In case of multiple matches in ohci_quirks[], only the first one is used. */
296static const struct {
9993e0fe 297 unsigned short vendor, device, revision, flags;
4a635593 298} ohci_quirks[] = {
9993e0fe
SR		 299 {PCI_VENDOR_ID_AL, PCI_ANY_ID, PCI_ANY_ID,
300 QUIRK_CYCLE_TIMER},
301
302 {PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_FW, PCI_ANY_ID,
303 QUIRK_BE_HEADERS},
304
305 {PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_AGERE_FW643, 6,
0ca49345 306 QUIRK_NO_MSI},
9993e0fe 307
d1bb399a
CL		 308 {PCI_VENDOR_ID_CREATIVE, PCI_DEVICE_ID_CREATIVE_SB1394, PCI_ANY_ID,
309 QUIRK_RESET_PACKET},
310
9993e0fe
SR		 311 {PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB38X_FW, PCI_ANY_ID,
312 QUIRK_NO_MSI},
313
314 {PCI_VENDOR_ID_NEC, PCI_ANY_ID, PCI_ANY_ID,
315 QUIRK_CYCLE_TIMER},
316
f39aa30d
ML		 317 {PCI_VENDOR_ID_O2, PCI_ANY_ID, PCI_ANY_ID,
318 QUIRK_NO_MSI},
319
9993e0fe 320 {PCI_VENDOR_ID_RICOH, PCI_ANY_ID, PCI_ANY_ID,
320cfa6c 321 QUIRK_CYCLE_TIMER | QUIRK_NO_MSI},
9993e0fe
SR		 322
323 {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV22, PCI_ANY_ID,
324 QUIRK_CYCLE_TIMER | QUIRK_RESET_PACKET | QUIRK_NO_1394A},
325
25935ebe
SG		 326 {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV26, PCI_ANY_ID,
327 QUIRK_RESET_PACKET | QUIRK_TI_SLLZ059},
328
329 {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB82AA2, PCI_ANY_ID,
330 QUIRK_RESET_PACKET | QUIRK_TI_SLLZ059},
331
9993e0fe
SR		 332 {PCI_VENDOR_ID_TI, PCI_ANY_ID, PCI_ANY_ID,
333 QUIRK_RESET_PACKET},
334
be8dcab9
AL		 335 {PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT630X, PCI_REV_ID_VIA_VT6306,
336 QUIRK_CYCLE_TIMER | QUIRK_IR_WAKE},
337
d151f985 338 {PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT6315, 0,
d584a662 339 QUIRK_CYCLE_TIMER /* FIXME: necessary? */ | QUIRK_NO_MSI},
d151f985
SR		 340
341 {PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT6315, PCI_ANY_ID,
d584a662 342 QUIRK_NO_MSI},
d151f985 343
9993e0fe
SR		 344 {PCI_VENDOR_ID_VIA, PCI_ANY_ID, PCI_ANY_ID,
345 QUIRK_CYCLE_TIMER | QUIRK_NO_MSI},
4a635593
SR		 346};
347
3e9cc2f3
SR		 348/* This overrides anything that was found in ohci_quirks[]. */
349static int param_quirks;
350module_param_named(quirks, param_quirks, int, 0644);
351MODULE_PARM_DESC(quirks, "Chip quirks (default = 0"
352 ", nonatomic cycle timer = " __stringify(QUIRK_CYCLE_TIMER)
353 ", reset packet generation = " __stringify(QUIRK_RESET_PACKET)
8a168ca7 354 ", AR/selfID endianness = " __stringify(QUIRK_BE_HEADERS)
925e7a65 355 ", no 1394a enhancements = " __stringify(QUIRK_NO_1394A)
262444ee 356 ", disable MSI = " __stringify(QUIRK_NO_MSI)
28897fb7 357 ", TI SLLZ059 erratum = " __stringify(QUIRK_TI_SLLZ059)
be8dcab9 358 ", IR wake unreliable = " __stringify(QUIRK_IR_WAKE)
3e9cc2f3
SR		 359 ")");
360
a007bb85 361#define OHCI_PARAM_DEBUG_AT_AR 1
ad3c0fe8 362#define OHCI_PARAM_DEBUG_SELFIDS 2
a007bb85
SR		 363#define OHCI_PARAM_DEBUG_IRQS 4
364#define OHCI_PARAM_DEBUG_BUSRESETS 8 /* only effective before chip init */
ad3c0fe8
SR		 365
366static int param_debug;
367module_param_named(debug, param_debug, int, 0644);
368MODULE_PARM_DESC(debug, "Verbose logging (default = 0"
ad3c0fe8 369 ", AT/AR events = " __stringify(OHCI_PARAM_DEBUG_AT_AR)
a007bb85
SR		 370 ", self-IDs = " __stringify(OHCI_PARAM_DEBUG_SELFIDS)
371 ", IRQs = " __stringify(OHCI_PARAM_DEBUG_IRQS)
372 ", busReset events = " __stringify(OHCI_PARAM_DEBUG_BUSRESETS)
ad3c0fe8
SR		 373 ", or a combination, or all = -1)");
374
8bc588e0
LR		 375static bool param_remote_dma;
376module_param_named(remote_dma, param_remote_dma, bool, 0444);
377MODULE_PARM_DESC(remote_dma, "Enable unfiltered remote DMA (default = N)");
378
64d21720 379static void log_irqs(struct fw_ohci *ohci, u32 evt)
ad3c0fe8 380{
a007bb85
SR		 381 if (likely(!(param_debug &
382 (OHCI_PARAM_DEBUG_IRQS | OHCI_PARAM_DEBUG_BUSRESETS))))
383 return;
384
385 if (!(param_debug & OHCI_PARAM_DEBUG_IRQS) &&
386 !(evt & OHCI1394_busReset))
ad3c0fe8
SR		 387 return;
388
de97cb64 389 ohci_notice(ohci, "IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt,
161b96e7
SR		 390 evt & OHCI1394_selfIDComplete ? " selfID" : "",
391 evt & OHCI1394_RQPkt ? " AR_req" : "",
392 evt & OHCI1394_RSPkt ? " AR_resp" : "",
393 evt & OHCI1394_reqTxComplete ? " AT_req" : "",
394 evt & OHCI1394_respTxComplete ? " AT_resp" : "",
395 evt & OHCI1394_isochRx ? " IR" : "",
396 evt & OHCI1394_isochTx ? " IT" : "",
397 evt & OHCI1394_postedWriteErr ? " postedWriteErr" : "",
398 evt & OHCI1394_cycleTooLong ? " cycleTooLong" : "",
a48777e0 399 evt & OHCI1394_cycle64Seconds ? " cycle64Seconds" : "",
5ed1f321 400 evt & OHCI1394_cycleInconsistent ? " cycleInconsistent" : "",
161b96e7 401 evt & OHCI1394_regAccessFail ? " regAccessFail" : "",
f117a3e3 402 evt & OHCI1394_unrecoverableError ? " unrecoverableError" : "",
161b96e7
SR		 403 evt & OHCI1394_busReset ? " busReset" : "",
404 evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt |
405 OHCI1394_RSPkt | OHCI1394_reqTxComplete |
406 OHCI1394_respTxComplete | OHCI1394_isochRx |
407 OHCI1394_isochTx | OHCI1394_postedWriteErr |
a48777e0
CL		 408 OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds |
409 OHCI1394_cycleInconsistent |
161b96e7 410 OHCI1394_regAccessFail | OHCI1394_busReset)
ad3c0fe8
SR		 411 ? " ?" : "");
412}
413
414static const char *speed[] = {
415 [0] = "S100", [1] = "S200", [2] = "S400", [3] = "beta",
416};
417static const char *power[] = {
418 [0] = "+0W", [1] = "+15W", [2] = "+30W", [3] = "+45W",
419 [4] = "-3W", [5] = " ?W", [6] = "-3..-6W", [7] = "-3..-10W",
420};
421static const char port[] = { '.', '-', 'p', 'c', };
422
423static char _p(u32 *s, int shift)
424{
425 return port[*s >> shift & 3];
426}
427
64d21720 428static void log_selfids(struct fw_ohci *ohci, int generation, int self_id_count)
ad3c0fe8 429{
64d21720
SR		 430 u32 *s;
431
ad3c0fe8
SR		 432 if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS)))
433 return;
434
de97cb64
PH		 435 ohci_notice(ohci, "%d selfIDs, generation %d, local node ID %04x\n",
436 self_id_count, generation, ohci->node_id);
ad3c0fe8 437
64d21720 438 for (s = ohci->self_id_buffer; self_id_count--; ++s)
ad3c0fe8 439 if ((*s & 1 << 23) == 0)
de97cb64
PH		 440 ohci_notice(ohci,
441 "selfID 0: %08x, phy %d [%c%c%c] %s gc=%d %s %s%s%s\n",
161b96e7
SR		 442 *s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2),
443 speed[*s >> 14 & 3], *s >> 16 & 63,
444 power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "",
445 *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : "");
ad3c0fe8 446 else
de97cb64 447 ohci_notice(ohci,
64d21720 448 "selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n",
161b96e7
SR		 449 *s, *s >> 24 & 63,
450 _p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10),
451 _p(s, 8), _p(s, 6), _p(s, 4), _p(s, 2));
ad3c0fe8
SR		 452}
453
454static const char *evts[] = {
455 [0x00] = "evt_no_status", [0x01] = "-reserved-",
456 [0x02] = "evt_long_packet", [0x03] = "evt_missing_ack",
457 [0x04] = "evt_underrun", [0x05] = "evt_overrun",
458 [0x06] = "evt_descriptor_read", [0x07] = "evt_data_read",
459 [0x08] = "evt_data_write", [0x09] = "evt_bus_reset",
460 [0x0a] = "evt_timeout", [0x0b] = "evt_tcode_err",
461 [0x0c] = "-reserved-", [0x0d] = "-reserved-",
462 [0x0e] = "evt_unknown", [0x0f] = "evt_flushed",
463 [0x10] = "-reserved-", [0x11] = "ack_complete",
464 [0x12] = "ack_pending ", [0x13] = "-reserved-",
465 [0x14] = "ack_busy_X", [0x15] = "ack_busy_A",
466 [0x16] = "ack_busy_B", [0x17] = "-reserved-",
467 [0x18] = "-reserved-", [0x19] = "-reserved-",
468 [0x1a] = "-reserved-", [0x1b] = "ack_tardy",
469 [0x1c] = "-reserved-", [0x1d] = "ack_data_error",
470 [0x1e] = "ack_type_error", [0x1f] = "-reserved-",
471 [0x20] = "pending/cancelled",
472};
473static const char *tcodes[] = {
474 [0x0] = "QW req", [0x1] = "BW req",
475 [0x2] = "W resp", [0x3] = "-reserved-",
476 [0x4] = "QR req", [0x5] = "BR req",
477 [0x6] = "QR resp", [0x7] = "BR resp",
478 [0x8] = "cycle start", [0x9] = "Lk req",
479 [0xa] = "async stream packet", [0xb] = "Lk resp",
480 [0xc] = "-reserved-", [0xd] = "-reserved-",
481 [0xe] = "link internal", [0xf] = "-reserved-",
482};
ad3c0fe8 483
64d21720
SR		 484static void log_ar_at_event(struct fw_ohci *ohci,
485 char dir, int speed, u32 *header, int evt)
ad3c0fe8
SR		 486{
487 int tcode = header[0] >> 4 & 0xf;
488 char specific[12];
489
490 if (likely(!(param_debug & OHCI_PARAM_DEBUG_AT_AR)))
491 return;
492
493 if (unlikely(evt >= ARRAY_SIZE(evts)))
494 evt = 0x1f;
495
08ddb2f4 496 if (evt == OHCI1394_evt_bus_reset) {
de97cb64
PH		 497 ohci_notice(ohci, "A%c evt_bus_reset, generation %d\n",
498 dir, (header[2] >> 16) & 0xff);
08ddb2f4
SR		 499 return;
500 }
501
ad3c0fe8
SR		 502 switch (tcode) {
503 case 0x0: case 0x6: case 0x8:
504 snprintf(specific, sizeof(specific), " = %08x",
505 be32_to_cpu((__force __be32)header[3]));
506 break;
507 case 0x1: case 0x5: case 0x7: case 0x9: case 0xb:
508 snprintf(specific, sizeof(specific), " %x,%x",
509 header[3] >> 16, header[3] & 0xffff);
510 break;
511 default:
512 specific[0] = '\0';
513 }
514
515 switch (tcode) {
5b06db16 516 case 0xa:
de97cb64
PH		 517 ohci_notice(ohci, "A%c %s, %s\n",
518 dir, evts[evt], tcodes[tcode]);
ad3c0fe8 519 break;
5b06db16 520 case 0xe:
de97cb64
PH		 521 ohci_notice(ohci, "A%c %s, PHY %08x %08x\n",
522 dir, evts[evt], header[1], header[2]);
5b06db16 523 break;
ad3c0fe8 524 case 0x0: case 0x1: case 0x4: case 0x5: case 0x9:
de97cb64
PH		 525 ohci_notice(ohci,
526 "A%c spd %x tl %02x, %04x -> %04x, %s, %s, %04x%08x%s\n",
527 dir, speed, header[0] >> 10 & 0x3f,
528 header[1] >> 16, header[0] >> 16, evts[evt],
529 tcodes[tcode], header[1] & 0xffff, header[2], specific);
ad3c0fe8
SR		 530 break;
531 default:
de97cb64
PH		 532 ohci_notice(ohci,
533 "A%c spd %x tl %02x, %04x -> %04x, %s, %s%s\n",
534 dir, speed, header[0] >> 10 & 0x3f,
535 header[1] >> 16, header[0] >> 16, evts[evt],
536 tcodes[tcode], specific);
ad3c0fe8
SR		 537 }
538}
539
95688e97 540static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data)
ed568912
KH		 541{
542 writel(data, ohci->registers + offset);
543}
544
95688e97 545static inline u32 reg_read(const struct fw_ohci *ohci, int offset)
ed568912
KH		 546{
547 return readl(ohci->registers + offset);
548}
549
95688e97 550static inline void flush_writes(const struct fw_ohci *ohci)
ed568912
KH		 551{
552 /* Do a dummy read to flush writes. */
553 reg_read(ohci, OHCI1394_Version);
554}
555
b14c369d
SR		 556/*
557 * Beware! read_phy_reg(), write_phy_reg(), update_phy_reg(), and
558 * read_paged_phy_reg() require the caller to hold ohci->phy_reg_mutex.
559 * In other words, only use ohci_read_phy_reg() and ohci_update_phy_reg()
560 * directly. Exceptions are intrinsically serialized contexts like pci_probe.
561 */
35d999b1 562static int read_phy_reg(struct fw_ohci *ohci, int addr)
ed568912 563{
4a96b4fc 564 u32 val;
35d999b1 565 int i;
ed568912
KH		 566
567 reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr));
153e3979 568 for (i = 0; i < 3 + 100; i++) {
35d999b1 569 val = reg_read(ohci, OHCI1394_PhyControl);
215fa444
SR		 570 if (!~val)
571 return -ENODEV; /* Card was ejected. */
572
35d999b1
SR		 573 if (val & OHCI1394_PhyControl_ReadDone)
574 return OHCI1394_PhyControl_ReadData(val);
575
153e3979
CL		 576 /*
577 * Try a few times without waiting. Sleeping is necessary
578 * only when the link/PHY interface is busy.
579 */
580 if (i >= 3)
581 msleep(1);
ed568912 582 }
6fe9efb9
PH		 583 ohci_err(ohci, "failed to read phy reg %d\n", addr);
584 dump_stack();
ed568912 585
35d999b1
SR		 586 return -EBUSY;
587}
4a96b4fc 588
35d999b1
SR		 589static int write_phy_reg(const struct fw_ohci *ohci, int addr, u32 val)
590{
591 int i;
ed568912 592
ed568912 593 reg_write(ohci, OHCI1394_PhyControl,
35d999b1 594 OHCI1394_PhyControl_Write(addr, val));
153e3979 595 for (i = 0; i < 3 + 100; i++) {
35d999b1 596 val = reg_read(ohci, OHCI1394_PhyControl);
215fa444
SR		 597 if (!~val)
598 return -ENODEV; /* Card was ejected. */
599
35d999b1
SR		 600 if (!(val & OHCI1394_PhyControl_WritePending))
601 return 0;
ed568912 602
153e3979
CL		 603 if (i >= 3)
604 msleep(1);
35d999b1 605 }
6fe9efb9
PH		 606 ohci_err(ohci, "failed to write phy reg %d, val %u\n", addr, val);
607 dump_stack();
35d999b1
SR		 608
609 return -EBUSY;
4a96b4fc
CL		 610}
611
02d37bed
SR		 612static int update_phy_reg(struct fw_ohci *ohci, int addr,
613 int clear_bits, int set_bits)
4a96b4fc 614{
02d37bed 615 int ret = read_phy_reg(ohci, addr);
35d999b1
SR		 616 if (ret < 0)
617 return ret;
4a96b4fc 618
e7014dad
CL		 619 /*
620 * The interrupt status bits are cleared by writing a one bit.
621 * Avoid clearing them unless explicitly requested in set_bits.
622 */
623 if (addr == 5)
624 clear_bits |= PHY_INT_STATUS_BITS;
625
35d999b1 626 return write_phy_reg(ohci, addr, (ret & ~clear_bits) | set_bits);
ed568912
KH		 627}
628
35d999b1 629static int read_paged_phy_reg(struct fw_ohci *ohci, int page, int addr)
925e7a65 630{
35d999b1 631 int ret;
925e7a65 632
02d37bed 633 ret = update_phy_reg(ohci, 7, PHY_PAGE_SELECT, page << 5);
35d999b1
SR		 634 if (ret < 0)
635 return ret;
925e7a65 636
35d999b1 637 return read_phy_reg(ohci, addr);
ed568912
KH		 638}
639
02d37bed
SR		 640static int ohci_read_phy_reg(struct fw_card *card, int addr)
641{
642 struct fw_ohci *ohci = fw_ohci(card);
643 int ret;
644
645 mutex_lock(&ohci->phy_reg_mutex);
646 ret = read_phy_reg(ohci, addr);
647 mutex_unlock(&ohci->phy_reg_mutex);
648
649 return ret;
650}
651
652static int ohci_update_phy_reg(struct fw_card *card, int addr,
653 int clear_bits, int set_bits)
654{
655 struct fw_ohci *ohci = fw_ohci(card);
656 int ret;
657
658 mutex_lock(&ohci->phy_reg_mutex);
659 ret = update_phy_reg(ohci, addr, clear_bits, set_bits);
660 mutex_unlock(&ohci->phy_reg_mutex);
661
662 return ret;
ed568912
KH		 663}
664
7a39d8b8
CL		 665static inline dma_addr_t ar_buffer_bus(struct ar_context *ctx, unsigned int i)
666{
667 return page_private(ctx->pages[i]);
668}
669
670static void ar_context_link_page(struct ar_context *ctx, unsigned int index)
ed568912 671{
7a39d8b8 672 struct descriptor *d;
32b46093 673
7a39d8b8
CL		 674 d = &ctx->descriptors[index];
675 d->branch_address &= cpu_to_le32(~0xf);
676 d->res_count = cpu_to_le16(PAGE_SIZE);
677 d->transfer_status = 0;
32b46093 678
071595eb 679 wmb(); /* finish init of new descriptors before branch_address update */
7a39d8b8
CL		 680 d = &ctx->descriptors[ctx->last_buffer_index];
681 d->branch_address |= cpu_to_le32(1);
682
683 ctx->last_buffer_index = index;
32b46093 684
a77754a7 685 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
837596a6
CL		 686}
687
7a39d8b8 688static void ar_context_release(struct ar_context *ctx)
837596a6 689{
7a39d8b8 690 unsigned int i;
837596a6 691
51b04d59 692 vunmap(ctx->buffer);
32b46093 693
7a39d8b8
CL		 694 for (i = 0; i < AR_BUFFERS; i++)
695 if (ctx->pages[i]) {
696 dma_unmap_page(ctx->ohci->card.device,
697 ar_buffer_bus(ctx, i),
698 PAGE_SIZE, DMA_FROM_DEVICE);
699 __free_page(ctx->pages[i]);
700 }
ed568912
KH		 701}
702
7a39d8b8 703static void ar_context_abort(struct ar_context *ctx, const char *error_msg)
a55709ba 704{
64d21720 705 struct fw_ohci *ohci = ctx->ohci;
a55709ba 706
64d21720
SR		 707 if (reg_read(ohci, CONTROL_CLEAR(ctx->regs)) & CONTEXT_RUN) {
708 reg_write(ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
709 flush_writes(ohci);
a55709ba 710
de97cb64 711 ohci_err(ohci, "AR error: %s; DMA stopped\n", error_msg);
a55709ba 712 }
7a39d8b8
CL		 713 /* FIXME: restart? */
714}
715
716static inline unsigned int ar_next_buffer_index(unsigned int index)
717{
718 return (index + 1) % AR_BUFFERS;
719}
720
7a39d8b8
CL		 721static inline unsigned int ar_first_buffer_index(struct ar_context *ctx)
722{
723 return ar_next_buffer_index(ctx->last_buffer_index);
724}
725
726/*
727 * We search for the buffer that contains the last AR packet DMA data written
728 * by the controller.
729 */
730static unsigned int ar_search_last_active_buffer(struct ar_context *ctx,
731 unsigned int *buffer_offset)
732{
733 unsigned int i, next_i, last = ctx->last_buffer_index;
734 __le16 res_count, next_res_count;
735
736 i = ar_first_buffer_index(ctx);
737 res_count = ACCESS_ONCE(ctx->descriptors[i].res_count);
738
739 /* A buffer that is not yet completely filled must be the last one. */
740 while (i != last && res_count == 0) {
741
742 /* Peek at the next descriptor. */
743 next_i = ar_next_buffer_index(i);
744 rmb(); /* read descriptors in order */
745 next_res_count = ACCESS_ONCE(
746 ctx->descriptors[next_i].res_count);
747 /*
748 * If the next descriptor is still empty, we must stop at this
749 * descriptor.
750 */
751 if (next_res_count == cpu_to_le16(PAGE_SIZE)) {
752 /*
753 * The exception is when the DMA data for one packet is
754 * split over three buffers; in this case, the middle
755 * buffer's descriptor might be never updated by the
756 * controller and look still empty, and we have to peek
757 * at the third one.
758 */
759 if (MAX_AR_PACKET_SIZE > PAGE_SIZE && i != last) {
760 next_i = ar_next_buffer_index(next_i);
761 rmb();
762 next_res_count = ACCESS_ONCE(
763 ctx->descriptors[next_i].res_count);
764 if (next_res_count != cpu_to_le16(PAGE_SIZE))
765 goto next_buffer_is_active;
766 }
767
768 break;
769 }
770
771next_buffer_is_active:
772 i = next_i;
773 res_count = next_res_count;
774 }
775
776 rmb(); /* read res_count before the DMA data */
777
778 *buffer_offset = PAGE_SIZE - le16_to_cpu(res_count);
779 if (*buffer_offset > PAGE_SIZE) {
780 *buffer_offset = 0;
781 ar_context_abort(ctx, "corrupted descriptor");
782 }
783
784 return i;
785}
786
787static void ar_sync_buffers_for_cpu(struct ar_context *ctx,
788 unsigned int end_buffer_index,
789 unsigned int end_buffer_offset)
790{
791 unsigned int i;
792
793 i = ar_first_buffer_index(ctx);
794 while (i != end_buffer_index) {
795 dma_sync_single_for_cpu(ctx->ohci->card.device,
796 ar_buffer_bus(ctx, i),
797 PAGE_SIZE, DMA_FROM_DEVICE);
798 i = ar_next_buffer_index(i);
799 }
800 if (end_buffer_offset > 0)
801 dma_sync_single_for_cpu(ctx->ohci->card.device,
802 ar_buffer_bus(ctx, i),
803 end_buffer_offset, DMA_FROM_DEVICE);
a55709ba
JF		 804}
805
11bf20ad
SR		 806#if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
807#define cond_le32_to_cpu(v) \
4a635593 808 (ohci->quirks & QUIRK_BE_HEADERS ? (__force __u32)(v) : le32_to_cpu(v))
11bf20ad
SR		 809#else
810#define cond_le32_to_cpu(v) le32_to_cpu(v)
811#endif
812
32b46093 813static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer)
ed568912 814{
ed568912 815 struct fw_ohci *ohci = ctx->ohci;
2639a6fb
KH		 816 struct fw_packet p;
817 u32 status, length, tcode;
43286568 818 int evt;
2639a6fb 819
11bf20ad
SR		 820 p.header[0] = cond_le32_to_cpu(buffer[0]);
821 p.header[1] = cond_le32_to_cpu(buffer[1]);
822 p.header[2] = cond_le32_to_cpu(buffer[2]);
2639a6fb
KH		 823
824 tcode = (p.header[0] >> 4) & 0x0f;
825 switch (tcode) {
826 case TCODE_WRITE_QUADLET_REQUEST:
827 case TCODE_READ_QUADLET_RESPONSE:
32b46093 828 p.header[3] = (__force __u32) buffer[3];
2639a6fb 829 p.header_length = 16;
32b46093 830 p.payload_length = 0;
2639a6fb
KH		 831 break;
832
2639a6fb 833 case TCODE_READ_BLOCK_REQUEST :
11bf20ad 834 p.header[3] = cond_le32_to_cpu(buffer[3]);
32b46093
KH		 835 p.header_length = 16;
836 p.payload_length = 0;
837 break;
838
839 case TCODE_WRITE_BLOCK_REQUEST:
2639a6fb
KH		 840 case TCODE_READ_BLOCK_RESPONSE:
841 case TCODE_LOCK_REQUEST:
842 case TCODE_LOCK_RESPONSE:
11bf20ad 843 p.header[3] = cond_le32_to_cpu(buffer[3]);
2639a6fb 844 p.header_length = 16;
32b46093 845 p.payload_length = p.header[3] >> 16;
7a39d8b8
CL		 846 if (p.payload_length > MAX_ASYNC_PAYLOAD) {
847 ar_context_abort(ctx, "invalid packet length");
848 return NULL;
849 }
2639a6fb
KH		 850 break;
851
852 case TCODE_WRITE_RESPONSE:
853 case TCODE_READ_QUADLET_REQUEST:
32b46093 854 case OHCI_TCODE_PHY_PACKET:
2639a6fb 855 p.header_length = 12;
32b46093 856 p.payload_length = 0;
2639a6fb 857 break;
ccff9629
SR		 858
859 default:
7a39d8b8
CL		 860 ar_context_abort(ctx, "invalid tcode");
861 return NULL;
2639a6fb 862 }
ed568912 863
32b46093
KH		 864 p.payload = (void *) buffer + p.header_length;
865
866 /* FIXME: What to do about evt_* errors? */
867 length = (p.header_length + p.payload_length + 3) / 4;
11bf20ad 868 status = cond_le32_to_cpu(buffer[length]);
43286568 869 evt = (status >> 16) & 0x1f;
32b46093 870
43286568 871 p.ack = evt - 16;
32b46093
KH		 872 p.speed = (status >> 21) & 0x7;
873 p.timestamp = status & 0xffff;
874 p.generation = ohci->request_generation;
ed568912 875
64d21720 876 log_ar_at_event(ohci, 'R', p.speed, p.header, evt);
ad3c0fe8 877
c781c06d 878 /*
a4dc090b
SR		 879 * Several controllers, notably from NEC and VIA, forget to
880 * write ack_complete status at PHY packet reception.
881 */
882 if (evt == OHCI1394_evt_no_status &&
883 (p.header[0] & 0xff) == (OHCI1394_phy_tcode << 4))
884 p.ack = ACK_COMPLETE;
885
886 /*
887 * The OHCI bus reset handler synthesizes a PHY packet with
ed568912
KH		 888 * the new generation number when a bus reset happens (see
889 * section 8.4.2.3). This helps us determine when a request
890 * was received and make sure we send the response in the same
891 * generation. We only need this for requests; for responses
892 * we use the unique tlabel for finding the matching
c781c06d 893 * request.
d34316a4
SR		 894 *
895 * Alas some chips sometimes emit bus reset packets with a
896 * wrong generation. We set the correct generation for these
2d7a36e2 897 * at a slightly incorrect time (in bus_reset_work).
c781c06d 898 */
d34316a4 899 if (evt == OHCI1394_evt_bus_reset) {
4a635593 900 if (!(ohci->quirks & QUIRK_RESET_PACKET))
d34316a4
SR		 901 ohci->request_generation = (p.header[2] >> 16) & 0xff;
902 } else if (ctx == &ohci->ar_request_ctx) {
2639a6fb 903 fw_core_handle_request(&ohci->card, &p);
d34316a4 904 } else {
2639a6fb 905 fw_core_handle_response(&ohci->card, &p);
d34316a4 906 }
ed568912 907
32b46093
KH		 908 return buffer + length + 1;
909}
ed568912 910
7a39d8b8
CL		 911static void *handle_ar_packets(struct ar_context *ctx, void *p, void *end)
912{
913 void *next;
914
915 while (p < end) {
916 next = handle_ar_packet(ctx, p);
917 if (!next)
918 return p;
919 p = next;
920 }
921
922 return p;
923}
924
925static void ar_recycle_buffers(struct ar_context *ctx, unsigned int end_buffer)
926{
927 unsigned int i;
928
929 i = ar_first_buffer_index(ctx);
930 while (i != end_buffer) {
931 dma_sync_single_for_device(ctx->ohci->card.device,
932 ar_buffer_bus(ctx, i),
933 PAGE_SIZE, DMA_FROM_DEVICE);
934 ar_context_link_page(ctx, i);
935 i = ar_next_buffer_index(i);
936 }
937}
938
32b46093
KH		 939static void ar_context_tasklet(unsigned long data)
940{
941 struct ar_context *ctx = (struct ar_context *)data;
7a39d8b8
CL		 942 unsigned int end_buffer_index, end_buffer_offset;
943 void *p, *end;
32b46093 944
7a39d8b8
CL		 945 p = ctx->pointer;
946 if (!p)
947 return;
32b46093 948
7a39d8b8
CL		 949 end_buffer_index = ar_search_last_active_buffer(ctx,
950 &end_buffer_offset);
951 ar_sync_buffers_for_cpu(ctx, end_buffer_index, end_buffer_offset);
952 end = ctx->buffer + end_buffer_index * PAGE_SIZE + end_buffer_offset;
32b46093 953
7a39d8b8 954 if (end_buffer_index < ar_first_buffer_index(ctx)) {
c781c06d 955 /*
7a39d8b8
CL		 956 * The filled part of the overall buffer wraps around; handle
957 * all packets up to the buffer end here. If the last packet
958 * wraps around, its tail will be visible after the buffer end
959 * because the buffer start pages are mapped there again.
c781c06d 960 */
7a39d8b8
CL		 961 void *buffer_end = ctx->buffer + AR_BUFFERS * PAGE_SIZE;
962 p = handle_ar_packets(ctx, p, buffer_end);
963 if (p < buffer_end)
964 goto error;
965 /* adjust p to point back into the actual buffer */
966 p -= AR_BUFFERS * PAGE_SIZE;
967 }
32b46093 968
7a39d8b8
CL		 969 p = handle_ar_packets(ctx, p, end);
970 if (p != end) {
971 if (p > end)
972 ar_context_abort(ctx, "inconsistent descriptor");
973 goto error;
974 }
32b46093 975
7a39d8b8
CL		 976 ctx->pointer = p;
977 ar_recycle_buffers(ctx, end_buffer_index);
32b46093 978
7a39d8b8 979 return;
a1f805e5 980
7a39d8b8
CL		 981error:
982 ctx->pointer = NULL;
ed568912
KH		 983}
984
ec766a79
CL		 985static int ar_context_init(struct ar_context *ctx, struct fw_ohci *ohci,
986 unsigned int descriptors_offset, u32 regs)
ed568912 987{
7a39d8b8
CL		 988 unsigned int i;
989 dma_addr_t dma_addr;
990 struct page *pages[AR_BUFFERS + AR_WRAPAROUND_PAGES];
991 struct descriptor *d;
ed568912 992
72e318e0
KH		 993 ctx->regs = regs;
994 ctx->ohci = ohci;
ed568912
KH		 995 tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx);
996
7a39d8b8
CL		 997 for (i = 0; i < AR_BUFFERS; i++) {
998 ctx->pages[i] = alloc_page(GFP_KERNEL | GFP_DMA32);
999 if (!ctx->pages[i])
1000 goto out_of_memory;
1001 dma_addr = dma_map_page(ohci->card.device, ctx->pages[i],
1002 0, PAGE_SIZE, DMA_FROM_DEVICE);
1003 if (dma_mapping_error(ohci->card.device, dma_addr)) {
1004 __free_page(ctx->pages[i]);
1005 ctx->pages[i] = NULL;
1006 goto out_of_memory;
1007 }
1008 set_page_private(ctx->pages[i], dma_addr);
1009 }
1010
1011 for (i = 0; i < AR_BUFFERS; i++)
1012 pages[i] = ctx->pages[i];
1013 for (i = 0; i < AR_WRAPAROUND_PAGES; i++)
1014 pages[AR_BUFFERS + i] = ctx->pages[i];
51b04d59 1015 ctx->buffer = vmap(pages, ARRAY_SIZE(pages), VM_MAP, PAGE_KERNEL);
7a39d8b8
CL		 1016 if (!ctx->buffer)
1017 goto out_of_memory;
1018
ec766a79
CL		 1019 ctx->descriptors = ohci->misc_buffer + descriptors_offset;
1020 ctx->descriptors_bus = ohci->misc_buffer_bus + descriptors_offset;
7a39d8b8
CL		 1021
1022 for (i = 0; i < AR_BUFFERS; i++) {
1023 d = &ctx->descriptors[i];
1024 d->req_count = cpu_to_le16(PAGE_SIZE);
1025 d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
1026 DESCRIPTOR_STATUS |
1027 DESCRIPTOR_BRANCH_ALWAYS);
1028 d->data_address = cpu_to_le32(ar_buffer_bus(ctx, i));
1029 d->branch_address = cpu_to_le32(ctx->descriptors_bus +
1030 ar_next_buffer_index(i) * sizeof(struct descriptor));
1031 }
32b46093 1032
2aef469a 1033 return 0;
7a39d8b8
CL		 1034
1035out_of_memory:
1036 ar_context_release(ctx);
1037
1038 return -ENOMEM;
2aef469a
KH		 1039}
1040
1041static void ar_context_run(struct ar_context *ctx)
1042{
7a39d8b8
CL		 1043 unsigned int i;
1044
1045 for (i = 0; i < AR_BUFFERS; i++)
1046 ar_context_link_page(ctx, i);
2aef469a 1047
7a39d8b8 1048 ctx->pointer = ctx->buffer;
2aef469a 1049
7a39d8b8 1050 reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ctx->descriptors_bus | 1);
a77754a7 1051 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN);
ed568912 1052}
373b2edd 1053
53dca511 1054static struct descriptor *find_branch_descriptor(struct descriptor *d, int z)
a186b4a6 1055{
0ff8fbc6 1056 __le16 branch;
a186b4a6 1057
0ff8fbc6 1058 branch = d->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS);
a186b4a6
JW		 1059
1060 /* figure out which descriptor the branch address goes in */
0ff8fbc6 1061 if (z == 2 && branch == cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))
a186b4a6
JW		 1062 return d;
1063 else
1064 return d + z - 1;
1065}
1066
30200739
KH		 1067static void context_tasklet(unsigned long data)
1068{
1069 struct context *ctx = (struct context *) data;
30200739
KH		 1070 struct descriptor *d, *last;
1071 u32 address;
1072 int z;
fe5ca634 1073 struct descriptor_buffer *desc;
30200739 1074
fe5ca634
DM		 1075 desc = list_entry(ctx->buffer_list.next,
1076 struct descriptor_buffer, list);
1077 last = ctx->last;
30200739 1078 while (last->branch_address != 0) {
fe5ca634 1079 struct descriptor_buffer *old_desc = desc;
30200739
KH		 1080 address = le32_to_cpu(last->branch_address);
1081 z = address & 0xf;
fe5ca634 1082 address &= ~0xf;
a572e688 1083 ctx->current_bus = address;
fe5ca634
DM		 1084
1085 /* If the branch address points to a buffer outside of the
1086 * current buffer, advance to the next buffer. */
1087 if (address < desc->buffer_bus ||
1088 address >= desc->buffer_bus + desc->used)
1089 desc = list_entry(desc->list.next,
1090 struct descriptor_buffer, list);
1091 d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d);
a186b4a6 1092 last = find_branch_descriptor(d, z);
30200739
KH		 1093
1094 if (!ctx->callback(ctx, d, last))
1095 break;
1096
fe5ca634
DM		 1097 if (old_desc != desc) {
1098 /* If we've advanced to the next buffer, move the
1099 * previous buffer to the free list. */
1100 unsigned long flags;
1101 old_desc->used = 0;
1102 spin_lock_irqsave(&ctx->ohci->lock, flags);
1103 list_move_tail(&old_desc->list, &ctx->buffer_list);
1104 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1105 }
1106 ctx->last = last;
30200739
KH		 1107 }
1108}
1109
fe5ca634
DM		 1110/*
1111 * Allocate a new buffer and add it to the list of free buffers for this
1112 * context. Must be called with ohci->lock held.
1113 */
53dca511 1114static int context_add_buffer(struct context *ctx)
fe5ca634
DM		 1115{
1116 struct descriptor_buffer *desc;
f5101d58 1117 dma_addr_t uninitialized_var(bus_addr);
fe5ca634
DM		 1118 int offset;
1119
1120 /*
1121 * 16MB of descriptors should be far more than enough for any DMA
1122 * program. This will catch run-away userspace or DoS attacks.
1123 */
1124 if (ctx->total_allocation >= 16*1024*1024)
1125 return -ENOMEM;
1126
1127 desc = dma_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE,
1128 &bus_addr, GFP_ATOMIC);
1129 if (!desc)
1130 return -ENOMEM;
1131
1132 offset = (void *)&desc->buffer - (void *)desc;
1133 desc->buffer_size = PAGE_SIZE - offset;
1134 desc->buffer_bus = bus_addr + offset;
1135 desc->used = 0;
1136
1137 list_add_tail(&desc->list, &ctx->buffer_list);
1138 ctx->total_allocation += PAGE_SIZE;
1139
1140 return 0;
1141}
1142
53dca511
SR		 1143static int context_init(struct context *ctx, struct fw_ohci *ohci,
1144 u32 regs, descriptor_callback_t callback)
30200739
KH		 1145{
1146 ctx->ohci = ohci;
1147 ctx->regs = regs;
fe5ca634
DM		 1148 ctx->total_allocation = 0;
1149
1150 INIT_LIST_HEAD(&ctx->buffer_list);
1151 if (context_add_buffer(ctx) < 0)
30200739
KH		 1152 return -ENOMEM;
1153
fe5ca634
DM		 1154 ctx->buffer_tail = list_entry(ctx->buffer_list.next,
1155 struct descriptor_buffer, list);
1156
30200739
KH		 1157 tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx);
1158 ctx->callback = callback;
1159
c781c06d
KH		 1160 /*
1161 * We put a dummy descriptor in the buffer that has a NULL
30200739 1162 * branch address and looks like it's been sent. That way we
fe5ca634 1163 * have a descriptor to append DMA programs to.
c781c06d 1164 */
fe5ca634
DM		 1165 memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer));
1166 ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST);
1167 ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011);
1168 ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer);
1169 ctx->last = ctx->buffer_tail->buffer;
1170 ctx->prev = ctx->buffer_tail->buffer;
be8dcab9 1171 ctx->prev_z = 1;
30200739
KH		 1172
1173 return 0;
1174}
1175
53dca511 1176static void context_release(struct context *ctx)
30200739
KH		 1177{
1178 struct fw_card *card = &ctx->ohci->card;
fe5ca634 1179 struct descriptor_buffer *desc, *tmp;
30200739 1180
fe5ca634
DM		 1181 list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list)
1182 dma_free_coherent(card->device, PAGE_SIZE, desc,
1183 desc->buffer_bus -
1184 ((void *)&desc->buffer - (void *)desc));
30200739
KH		 1185}
1186
fe5ca634 1187/* Must be called with ohci->lock held */
53dca511
SR		 1188static struct descriptor *context_get_descriptors(struct context *ctx,
1189 int z, dma_addr_t *d_bus)
30200739 1190{
fe5ca634
DM		 1191 struct descriptor *d = NULL;
1192 struct descriptor_buffer *desc = ctx->buffer_tail;
1193
1194 if (z * sizeof(*d) > desc->buffer_size)
1195 return NULL;
1196
1197 if (z * sizeof(*d) > desc->buffer_size - desc->used) {
1198 /* No room for the descriptor in this buffer, so advance to the
1199 * next one. */
30200739 1200
fe5ca634
DM		 1201 if (desc->list.next == &ctx->buffer_list) {
1202 /* If there is no free buffer next in the list,
1203 * allocate one. */
1204 if (context_add_buffer(ctx) < 0)
1205 return NULL;
1206 }
1207 desc = list_entry(desc->list.next,
1208 struct descriptor_buffer, list);
1209 ctx->buffer_tail = desc;
1210 }
30200739 1211
fe5ca634 1212 d = desc->buffer + desc->used / sizeof(*d);
2d826cc5 1213 memset(d, 0, z * sizeof(*d));
fe5ca634 1214 *d_bus = desc->buffer_bus + desc->used;
30200739
KH		 1215
1216 return d;
1217}
1218
295e3feb 1219static void context_run(struct context *ctx, u32 extra)
30200739
KH		 1220{
1221 struct fw_ohci *ohci = ctx->ohci;
1222
a77754a7 1223 reg_write(ohci, COMMAND_PTR(ctx->regs),
fe5ca634 1224 le32_to_cpu(ctx->last->branch_address));
a77754a7
KH		 1225 reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0);
1226 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra);
386a4153 1227 ctx->running = true;
30200739
KH		 1228 flush_writes(ohci);
1229}
1230
1231static void context_append(struct context *ctx,
1232 struct descriptor *d, int z, int extra)
1233{
1234 dma_addr_t d_bus;
fe5ca634 1235 struct descriptor_buffer *desc = ctx->buffer_tail;
be8dcab9 1236 struct descriptor *d_branch;
30200739 1237
fe5ca634 1238 d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d);
30200739 1239
fe5ca634 1240 desc->used += (z + extra) * sizeof(*d);
071595eb
SR		 1241
1242 wmb(); /* finish init of new descriptors before branch_address update */
be8dcab9
AL		 1243
1244 d_branch = find_branch_descriptor(ctx->prev, ctx->prev_z);
1245 d_branch->branch_address = cpu_to_le32(d_bus | z);
1246
1247 /*
1248 * VT6306 incorrectly checks only the single descriptor at the
1249 * CommandPtr when the wake bit is written, so if it's a
1250 * multi-descriptor block starting with an INPUT_MORE, put a copy of
1251 * the branch address in the first descriptor.
1252 *
1253 * Not doing this for transmit contexts since not sure how it interacts
1254 * with skip addresses.
1255 */
1256 if (unlikely(ctx->ohci->quirks & QUIRK_IR_WAKE) &&
1257 d_branch != ctx->prev &&
1258 (ctx->prev->control & cpu_to_le16(DESCRIPTOR_CMD)) ==
1259 cpu_to_le16(DESCRIPTOR_INPUT_MORE)) {
1260 ctx->prev->branch_address = cpu_to_le32(d_bus | z);
1261 }
1262
1263 ctx->prev = d;
1264 ctx->prev_z = z;
30200739
KH		 1265}
1266
1267static void context_stop(struct context *ctx)
1268{
64d21720 1269 struct fw_ohci *ohci = ctx->ohci;
30200739 1270 u32 reg;
b8295668 1271 int i;
30200739 1272
64d21720 1273 reg_write(ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
386a4153 1274 ctx->running = false;
30200739 1275
9ef28ccd 1276 for (i = 0; i < 1000; i++) {
64d21720 1277 reg = reg_read(ohci, CONTROL_SET(ctx->regs));
b8295668 1278 if ((reg & CONTEXT_ACTIVE) == 0)
b0068549 1279 return;
b8295668 1280
9ef28ccd
SR		 1281 if (i)
1282 udelay(10);
b8295668 1283 }
de97cb64 1284 ohci_err(ohci, "DMA context still active (0x%08x)\n", reg);
30200739 1285}
ed568912 1286
f319b6a0 1287struct driver_data {
da28947e 1288 u8 inline_data[8];
f319b6a0
KH		 1289 struct fw_packet *packet;
1290};
ed568912 1291
c781c06d
KH		 1292/*
1293 * This function apppends a packet to the DMA queue for transmission.
f319b6a0 1294 * Must always be called with the ochi->lock held to ensure proper
c781c06d
KH		 1295 * generation handling and locking around packet queue manipulation.
1296 */
53dca511
SR		 1297static int at_context_queue_packet(struct context *ctx,
1298 struct fw_packet *packet)
ed568912 1299{
ed568912 1300 struct fw_ohci *ohci = ctx->ohci;
4b6d51ec 1301 dma_addr_t d_bus, uninitialized_var(payload_bus);
f319b6a0
KH		 1302 struct driver_data *driver_data;
1303 struct descriptor *d, *last;
1304 __le32 *header;
ed568912
KH		 1305 int z, tcode;
1306
f319b6a0
KH		 1307 d = context_get_descriptors(ctx, 4, &d_bus);
1308 if (d == NULL) {
1309 packet->ack = RCODE_SEND_ERROR;
1310 return -1;
ed568912
KH		 1311 }
1312
a77754a7 1313 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
f319b6a0
KH		 1314 d[0].res_count = cpu_to_le16(packet->timestamp);
1315
c781c06d 1316 /*
b3834be5 1317 * The DMA format for asynchronous link packets is different
ed568912 1318 * from the IEEE1394 layout, so shift the fields around
5b06db16 1319 * accordingly.
c781c06d 1320 */
f319b6a0 1321
5b06db16 1322 tcode = (packet->header[0] >> 4) & 0x0f;
f319b6a0 1323 header = (__le32 *) &d[1];
5b06db16
CL		 1324 switch (tcode) {
1325 case TCODE_WRITE_QUADLET_REQUEST:
1326 case TCODE_WRITE_BLOCK_REQUEST:
1327 case TCODE_WRITE_RESPONSE:
1328 case TCODE_READ_QUADLET_REQUEST:
1329 case TCODE_READ_BLOCK_REQUEST:
1330 case TCODE_READ_QUADLET_RESPONSE:
1331 case TCODE_READ_BLOCK_RESPONSE:
1332 case TCODE_LOCK_REQUEST:
1333 case TCODE_LOCK_RESPONSE:
f319b6a0
KH		 1334 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1335 (packet->speed << 16));
1336 header[1] = cpu_to_le32((packet->header[1] & 0xffff) |
1337 (packet->header[0] & 0xffff0000));
1338 header[2] = cpu_to_le32(packet->header[2]);
ed568912 1339
ed568912 1340 if (TCODE_IS_BLOCK_PACKET(tcode))
f319b6a0 1341 header[3] = cpu_to_le32(packet->header[3]);
ed568912 1342 else
f319b6a0
KH		 1343 header[3] = (__force __le32) packet->header[3];
1344
1345 d[0].req_count = cpu_to_le16(packet->header_length);
f8c2287c
JF		 1346 break;
1347
5b06db16 1348 case TCODE_LINK_INTERNAL:
f319b6a0
KH		 1349 header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) |
1350 (packet->speed << 16));
5b06db16
CL		 1351 header[1] = cpu_to_le32(packet->header[1]);
1352 header[2] = cpu_to_le32(packet->header[2]);
f319b6a0 1353 d[0].req_count = cpu_to_le16(12);
cc550216 1354
5b06db16 1355 if (is_ping_packet(&packet->header[1]))
cc550216 1356 d[0].control |= cpu_to_le16(DESCRIPTOR_PING);
f8c2287c
JF		 1357 break;
1358
5b06db16 1359 case TCODE_STREAM_DATA:
f8c2287c
JF		 1360 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1361 (packet->speed << 16));
1362 header[1] = cpu_to_le32(packet->header[0] & 0xffff0000);
1363 d[0].req_count = cpu_to_le16(8);
1364 break;
1365
1366 default:
1367 /* BUG(); */
1368 packet->ack = RCODE_SEND_ERROR;
1369 return -1;
ed568912
KH		 1370 }
1371
da28947e 1372 BUILD_BUG_ON(sizeof(struct driver_data) > sizeof(struct descriptor));
f319b6a0
KH		 1373 driver_data = (struct driver_data *) &d[3];
1374 driver_data->packet = packet;
20d11673 1375 packet->driver_data = driver_data;
a186b4a6 1376
f319b6a0 1377 if (packet->payload_length > 0) {
da28947e
CL		 1378 if (packet->payload_length > sizeof(driver_data->inline_data)) {
1379 payload_bus = dma_map_single(ohci->card.device,
1380 packet->payload,
1381 packet->payload_length,
1382 DMA_TO_DEVICE);
1383 if (dma_mapping_error(ohci->card.device, payload_bus)) {
1384 packet->ack = RCODE_SEND_ERROR;
1385 return -1;
1386 }
1387 packet->payload_bus = payload_bus;
1388 packet->payload_mapped = true;
1389 } else {
1390 memcpy(driver_data->inline_data, packet->payload,
1391 packet->payload_length);
1392 payload_bus = d_bus + 3 * sizeof(*d);
f319b6a0
KH		 1393 }
1394
1395 d[2].req_count = cpu_to_le16(packet->payload_length);
1396 d[2].data_address = cpu_to_le32(payload_bus);
1397 last = &d[2];
1398 z = 3;
ed568912 1399 } else {
f319b6a0
KH		 1400 last = &d[0];
1401 z = 2;
ed568912 1402 }
ed568912 1403
a77754a7
KH		 1404 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
1405 DESCRIPTOR_IRQ_ALWAYS |
1406 DESCRIPTOR_BRANCH_ALWAYS);
ed568912 1407
b6258fc1
SR		 1408 /* FIXME: Document how the locking works. */
1409 if (ohci->generation != packet->generation) {
19593ffd 1410 if (packet->payload_mapped)
ab88ca48
SR		 1411 dma_unmap_single(ohci->card.device, payload_bus,
1412 packet->payload_length, DMA_TO_DEVICE);
f319b6a0
KH		 1413 packet->ack = RCODE_GENERATION;
1414 return -1;
1415 }
1416
1417 context_append(ctx, d, z, 4 - z);
ed568912 1418
dd6254e5 1419 if (ctx->running)
13882a82 1420 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
dd6254e5 1421 else
f319b6a0
KH		 1422 context_run(ctx, 0);
1423
1424 return 0;
ed568912
KH		 1425}
1426
82b662dc
CL		 1427static void at_context_flush(struct context *ctx)
1428{
1429 tasklet_disable(&ctx->tasklet);
1430
1431 ctx->flushing = true;
1432 context_tasklet((unsigned long)ctx);
1433 ctx->flushing = false;
1434
1435 tasklet_enable(&ctx->tasklet);
1436}
1437
f319b6a0
KH		 1438static int handle_at_packet(struct context *context,
1439 struct descriptor *d,
1440 struct descriptor *last)
ed568912 1441{
f319b6a0 1442 struct driver_data *driver_data;
ed568912 1443 struct fw_packet *packet;
f319b6a0 1444 struct fw_ohci *ohci = context->ohci;
ed568912
KH		 1445 int evt;
1446
82b662dc 1447 if (last->transfer_status == 0 && !context->flushing)
f319b6a0
KH		 1448 /* This descriptor isn't done yet, stop iteration. */
1449 return 0;
ed568912 1450
f319b6a0
KH		 1451 driver_data = (struct driver_data *) &d[3];
1452 packet = driver_data->packet;
1453 if (packet == NULL)
1454 /* This packet was cancelled, just continue. */
1455 return 1;
730c32f5 1456
19593ffd 1457 if (packet->payload_mapped)
1d1dc5e8 1458 dma_unmap_single(ohci->card.device, packet->payload_bus,
ed568912 1459 packet->payload_length, DMA_TO_DEVICE);
ed568912 1460
f319b6a0
KH		 1461 evt = le16_to_cpu(last->transfer_status) & 0x1f;
1462 packet->timestamp = le16_to_cpu(last->res_count);
ed568912 1463
64d21720 1464 log_ar_at_event(ohci, 'T', packet->speed, packet->header, evt);
ad3c0fe8 1465
f319b6a0
KH		 1466 switch (evt) {
1467 case OHCI1394_evt_timeout:
1468 /* Async response transmit timed out. */
1469 packet->ack = RCODE_CANCELLED;
1470 break;
ed568912 1471
f319b6a0 1472 case OHCI1394_evt_flushed:
c781c06d
KH		 1473 /*
1474 * The packet was flushed should give same error as
1475 * when we try to use a stale generation count.
1476 */
f319b6a0
KH		 1477 packet->ack = RCODE_GENERATION;
1478 break;
ed568912 1479
f319b6a0 1480 case OHCI1394_evt_missing_ack:
82b662dc
CL		 1481 if (context->flushing)
1482 packet->ack = RCODE_GENERATION;
1483 else {
1484 /*
1485 * Using a valid (current) generation count, but the
1486 * node is not on the bus or not sending acks.
1487 */
1488 packet->ack = RCODE_NO_ACK;
1489 }
f319b6a0 1490 break;
ed568912 1491
f319b6a0
KH		 1492 case ACK_COMPLETE + 0x10:
1493 case ACK_PENDING + 0x10:
1494 case ACK_BUSY_X + 0x10:
1495 case ACK_BUSY_A + 0x10:
1496 case ACK_BUSY_B + 0x10:
1497 case ACK_DATA_ERROR + 0x10:
1498 case ACK_TYPE_ERROR + 0x10:
1499 packet->ack = evt - 0x10;
1500 break;
ed568912 1501
82b662dc
CL		 1502 case OHCI1394_evt_no_status:
1503 if (context->flushing) {
1504 packet->ack = RCODE_GENERATION;
1505 break;
1506 }
1507 /* fall through */
1508
f319b6a0
KH		 1509 default:
1510 packet->ack = RCODE_SEND_ERROR;
1511 break;
1512 }
ed568912 1513
f319b6a0 1514 packet->callback(packet, &ohci->card, packet->ack);
ed568912 1515
f319b6a0 1516 return 1;
ed568912
KH		 1517}
1518
a77754a7
KH		 1519#define HEADER_GET_DESTINATION(q) (((q) >> 16) & 0xffff)
1520#define HEADER_GET_TCODE(q) (((q) >> 4) & 0x0f)
1521#define HEADER_GET_OFFSET_HIGH(q) (((q) >> 0) & 0xffff)
1522#define HEADER_GET_DATA_LENGTH(q) (((q) >> 16) & 0xffff)
1523#define HEADER_GET_EXTENDED_TCODE(q) (((q) >> 0) & 0xffff)
93c4cceb 1524
53dca511
SR		 1525static void handle_local_rom(struct fw_ohci *ohci,
1526 struct fw_packet *packet, u32 csr)
93c4cceb
KH		 1527{
1528 struct fw_packet response;
1529 int tcode, length, i;
1530
a77754a7 1531 tcode = HEADER_GET_TCODE(packet->header[0]);
93c4cceb 1532 if (TCODE_IS_BLOCK_PACKET(tcode))
a77754a7 1533 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
93c4cceb
KH		 1534 else
1535 length = 4;
1536
1537 i = csr - CSR_CONFIG_ROM;
1538 if (i + length > CONFIG_ROM_SIZE) {
1539 fw_fill_response(&response, packet->header,
1540 RCODE_ADDRESS_ERROR, NULL, 0);
1541 } else if (!TCODE_IS_READ_REQUEST(tcode)) {
1542 fw_fill_response(&response, packet->header,
1543 RCODE_TYPE_ERROR, NULL, 0);
1544 } else {
1545 fw_fill_response(&response, packet->header, RCODE_COMPLETE,
1546 (void *) ohci->config_rom + i, length);
1547 }
1548
1549 fw_core_handle_response(&ohci->card, &response);
1550}
1551
53dca511
SR		 1552static void handle_local_lock(struct fw_ohci *ohci,
1553 struct fw_packet *packet, u32 csr)
93c4cceb
KH		 1554{
1555 struct fw_packet response;
e1393667 1556 int tcode, length, ext_tcode, sel, try;
93c4cceb
KH		 1557 __be32 *payload, lock_old;
1558 u32 lock_arg, lock_data;
1559
a77754a7
KH		 1560 tcode = HEADER_GET_TCODE(packet->header[0]);
1561 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
93c4cceb 1562 payload = packet->payload;
a77754a7 1563 ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]);
93c4cceb
KH		 1564
1565 if (tcode == TCODE_LOCK_REQUEST &&
1566 ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) {
1567 lock_arg = be32_to_cpu(payload[0]);
1568 lock_data = be32_to_cpu(payload[1]);
1569 } else if (tcode == TCODE_READ_QUADLET_REQUEST) {
1570 lock_arg = 0;
1571 lock_data = 0;
1572 } else {
1573 fw_fill_response(&response, packet->header,
1574 RCODE_TYPE_ERROR, NULL, 0);
1575 goto out;
1576 }
1577
1578 sel = (csr - CSR_BUS_MANAGER_ID) / 4;
1579 reg_write(ohci, OHCI1394_CSRData, lock_data);
1580 reg_write(ohci, OHCI1394_CSRCompareData, lock_arg);
1581 reg_write(ohci, OHCI1394_CSRControl, sel);
1582
e1393667
CL		 1583 for (try = 0; try < 20; try++)
1584 if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000) {
1585 lock_old = cpu_to_be32(reg_read(ohci,
1586 OHCI1394_CSRData));
1587 fw_fill_response(&response, packet->header,
1588 RCODE_COMPLETE,
1589 &lock_old, sizeof(lock_old));
1590 goto out;
1591 }
1592
de97cb64 1593 ohci_err(ohci, "swap not done (CSR lock timeout)\n");
e1393667 1594 fw_fill_response(&response, packet->header, RCODE_BUSY, NULL, 0);
93c4cceb 1595
93c4cceb
KH		 1596 out:
1597 fw_core_handle_response(&ohci->card, &response);
1598}
1599
53dca511 1600static void handle_local_request(struct context *ctx, struct fw_packet *packet)
93c4cceb 1601{
2608203d 1602 u64 offset, csr;
93c4cceb 1603
473d28c7
KH		 1604 if (ctx == &ctx->ohci->at_request_ctx) {
1605 packet->ack = ACK_PENDING;
1606 packet->callback(packet, &ctx->ohci->card, packet->ack);
1607 }
93c4cceb
KH		 1608
1609 offset =
1610 ((unsigned long long)
a77754a7 1611 HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) |
93c4cceb
KH		 1612 packet->header[2];
1613 csr = offset - CSR_REGISTER_BASE;
1614
1615 /* Handle config rom reads. */
1616 if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END)
1617 handle_local_rom(ctx->ohci, packet, csr);
1618 else switch (csr) {
1619 case CSR_BUS_MANAGER_ID:
1620 case CSR_BANDWIDTH_AVAILABLE:
1621 case CSR_CHANNELS_AVAILABLE_HI:
1622 case CSR_CHANNELS_AVAILABLE_LO:
1623 handle_local_lock(ctx->ohci, packet, csr);
1624 break;
1625 default:
1626 if (ctx == &ctx->ohci->at_request_ctx)
1627 fw_core_handle_request(&ctx->ohci->card, packet);
1628 else
1629 fw_core_handle_response(&ctx->ohci->card, packet);
1630 break;
1631 }
473d28c7
KH		 1632
1633 if (ctx == &ctx->ohci->at_response_ctx) {
1634 packet->ack = ACK_COMPLETE;
1635 packet->callback(packet, &ctx->ohci->card, packet->ack);
1636 }
93c4cceb 1637}
e636fe25 1638
53dca511 1639static void at_context_transmit(struct context *ctx, struct fw_packet *packet)
ed568912 1640{
ed568912 1641 unsigned long flags;
2dbd7d7e 1642 int ret;
ed568912
KH		 1643
1644 spin_lock_irqsave(&ctx->ohci->lock, flags);
1645
a77754a7 1646 if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id &&
e636fe25 1647 ctx->ohci->generation == packet->generation) {
93c4cceb
KH		 1648 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1649 handle_local_request(ctx, packet);
1650 return;
e636fe25 1651 }
ed568912 1652
2dbd7d7e 1653 ret = at_context_queue_packet(ctx, packet);
ed568912
KH		 1654 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1655
2dbd7d7e 1656 if (ret < 0)
f319b6a0 1657 packet->callback(packet, &ctx->ohci->card, packet->ack);
a186b4a6 1658
ed568912
KH		 1659}
1660
f117a3e3
CL		 1661static void detect_dead_context(struct fw_ohci *ohci,
1662 const char *name, unsigned int regs)
1663{
1664 u32 ctl;
1665
1666 ctl = reg_read(ohci, CONTROL_SET(regs));
cfda62ba 1667 if (ctl & CONTEXT_DEAD)
de97cb64 1668 ohci_err(ohci, "DMA context %s has stopped, error code: %s\n",
64d21720 1669 name, evts[ctl & 0x1f]);
f117a3e3
CL		 1670}
1671
1672static void handle_dead_contexts(struct fw_ohci *ohci)
1673{
1674 unsigned int i;
1675 char name[8];
1676
1677 detect_dead_context(ohci, "ATReq", OHCI1394_AsReqTrContextBase);
1678 detect_dead_context(ohci, "ATRsp", OHCI1394_AsRspTrContextBase);
1679 detect_dead_context(ohci, "ARReq", OHCI1394_AsReqRcvContextBase);
1680 detect_dead_context(ohci, "ARRsp", OHCI1394_AsRspRcvContextBase);
1681 for (i = 0; i < 32; ++i) {
1682 if (!(ohci->it_context_support & (1 << i)))
1683 continue;
1684 sprintf(name, "IT%u", i);
1685 detect_dead_context(ohci, name, OHCI1394_IsoXmitContextBase(i));
1686 }
1687 for (i = 0; i < 32; ++i) {
1688 if (!(ohci->ir_context_support & (1 << i)))
1689 continue;
1690 sprintf(name, "IR%u", i);
1691 detect_dead_context(ohci, name, OHCI1394_IsoRcvContextBase(i));
1692 }
1693 /* TODO: maybe try to flush and restart the dead contexts */
1694}
1695
a48777e0
CL		 1696static u32 cycle_timer_ticks(u32 cycle_timer)
1697{
1698 u32 ticks;
1699
1700 ticks = cycle_timer & 0xfff;
1701 ticks += 3072 * ((cycle_timer >> 12) & 0x1fff);
1702 ticks += (3072 * 8000) * (cycle_timer >> 25);
1703
1704 return ticks;
1705}
1706
1707/*
1708 * Some controllers exhibit one or more of the following bugs when updating the
1709 * iso cycle timer register:
1710 * - When the lowest six bits are wrapping around to zero, a read that happens
1711 * at the same time will return garbage in the lowest ten bits.
1712 * - When the cycleOffset field wraps around to zero, the cycleCount field is
1713 * not incremented for about 60 ns.
1714 * - Occasionally, the entire register reads zero.
1715 *
1716 * To catch these, we read the register three times and ensure that the
1717 * difference between each two consecutive reads is approximately the same, i.e.
1718 * less than twice the other. Furthermore, any negative difference indicates an
1719 * error. (A PCI read should take at least 20 ticks of the 24.576 MHz timer to
1720 * execute, so we have enough precision to compute the ratio of the differences.)
1721 */
1722static u32 get_cycle_time(struct fw_ohci *ohci)
1723{
1724 u32 c0, c1, c2;
1725 u32 t0, t1, t2;
1726 s32 diff01, diff12;
1727 int i;
1728
1729 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1730
1731 if (ohci->quirks & QUIRK_CYCLE_TIMER) {
1732 i = 0;
1733 c1 = c2;
1734 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1735 do {
1736 c0 = c1;
1737 c1 = c2;
1738 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1739 t0 = cycle_timer_ticks(c0);
1740 t1 = cycle_timer_ticks(c1);
1741 t2 = cycle_timer_ticks(c2);
1742 diff01 = t1 - t0;
1743 diff12 = t2 - t1;
1744 } while ((diff01 <= 0 || diff12 <= 0 ||
1745 diff01 / diff12 >= 2 || diff12 / diff01 >= 2)
1746 && i++ < 20);
1747 }
1748
1749 return c2;
1750}
1751
1752/*
1753 * This function has to be called at least every 64 seconds. The bus_time
1754 * field stores not only the upper 25 bits of the BUS_TIME register but also
1755 * the most significant bit of the cycle timer in bit 6 so that we can detect
1756 * changes in this bit.
1757 */
1758static u32 update_bus_time(struct fw_ohci *ohci)
1759{
1760 u32 cycle_time_seconds = get_cycle_time(ohci) >> 25;
1761
9d60ef2b
CL		 1762 if (unlikely(!ohci->bus_time_running)) {
1763 reg_write(ohci, OHCI1394_IntMaskSet, OHCI1394_cycle64Seconds);
1764 ohci->bus_time = (lower_32_bits(get_seconds()) & ~0x7f) |
1765 (cycle_time_seconds & 0x40);
1766 ohci->bus_time_running = true;
1767 }
1768
a48777e0
CL		 1769 if ((ohci->bus_time & 0x40) != (cycle_time_seconds & 0x40))
1770 ohci->bus_time += 0x40;
1771
1772 return ohci->bus_time | cycle_time_seconds;
1773}
1774
25935ebe
SG		 1775static int get_status_for_port(struct fw_ohci *ohci, int port_index)
1776{
1777 int reg;
1778
1779 mutex_lock(&ohci->phy_reg_mutex);
1780 reg = write_phy_reg(ohci, 7, port_index);
28897fb7
SR		 1781 if (reg >= 0)
1782 reg = read_phy_reg(ohci, 8);
25935ebe
SG		 1783 mutex_unlock(&ohci->phy_reg_mutex);
1784 if (reg < 0)
1785 return reg;
1786
1787 switch (reg & 0x0f) {
1788 case 0x06:
1789 return 2; /* is child node (connected to parent node) */
1790 case 0x0e:
1791 return 3; /* is parent node (connected to child node) */
1792 }
1793 return 1; /* not connected */
1794}
1795
1796static int get_self_id_pos(struct fw_ohci *ohci, u32 self_id,
1797 int self_id_count)
1798{
1799 int i;
1800 u32 entry;
28897fb7 1801
25935ebe
SG		 1802 for (i = 0; i < self_id_count; i++) {
1803 entry = ohci->self_id_buffer[i];
1804 if ((self_id & 0xff000000) == (entry & 0xff000000))
1805 return -1;
1806 if ((self_id & 0xff000000) < (entry & 0xff000000))
1807 return i;
1808 }
1809 return i;
1810}
1811
52439d60
SG		 1812static int initiated_reset(struct fw_ohci *ohci)
1813{
1814 int reg;
1815 int ret = 0;
1816
1817 mutex_lock(&ohci->phy_reg_mutex);
1818 reg = write_phy_reg(ohci, 7, 0xe0); /* Select page 7 */
1819 if (reg >= 0) {
1820 reg = read_phy_reg(ohci, 8);
1821 reg |= 0x40;
1822 reg = write_phy_reg(ohci, 8, reg); /* set PMODE bit */
1823 if (reg >= 0) {
1824 reg = read_phy_reg(ohci, 12); /* read register 12 */
1825 if (reg >= 0) {
1826 if ((reg & 0x08) == 0x08) {
1827 /* bit 3 indicates "initiated reset" */
1828 ret = 0x2;
1829 }
1830 }
1831 }
1832 }
1833 mutex_unlock(&ohci->phy_reg_mutex);
1834 return ret;
1835}
1836
25935ebe 1837/*
28897fb7
SR		 1838 * TI TSB82AA2B and TSB12LV26 do not receive the selfID of a locally
1839 * attached TSB41BA3D phy; see http://www.ti.com/litv/pdf/sllz059.
1840 * Construct the selfID from phy register contents.
25935ebe 1841 */
25935ebe
SG		 1842static int find_and_insert_self_id(struct fw_ohci *ohci, int self_id_count)
1843{
28897fb7
SR		 1844 int reg, i, pos, status;
1845 /* link active 1, speed 3, bridge 0, contender 1, more packets 0 */
1846 u32 self_id = 0x8040c800;
25935ebe
SG		 1847
1848 reg = reg_read(ohci, OHCI1394_NodeID);
1849 if (!(reg & OHCI1394_NodeID_idValid)) {
de97cb64
PH		 1850 ohci_notice(ohci,
1851 "node ID not valid, new bus reset in progress\n");
25935ebe
SG		 1852 return -EBUSY;
1853 }
1854 self_id |= ((reg & 0x3f) << 24); /* phy ID */
1855
28897fb7 1856 reg = ohci_read_phy_reg(&ohci->card, 4);
25935ebe
SG		 1857 if (reg < 0)
1858 return reg;
1859 self_id |= ((reg & 0x07) << 8); /* power class */
1860
28897fb7 1861 reg = ohci_read_phy_reg(&ohci->card, 1);
25935ebe
SG		 1862 if (reg < 0)
1863 return reg;
1864 self_id |= ((reg & 0x3f) << 16); /* gap count */
1865
1866 for (i = 0; i < 3; i++) {
1867 status = get_status_for_port(ohci, i);
1868 if (status < 0)
1869 return status;
1870 self_id |= ((status & 0x3) << (6 - (i * 2)));
1871 }
1872
52439d60
SG		 1873 self_id |= initiated_reset(ohci);
1874
25935ebe
SG		 1875 pos = get_self_id_pos(ohci, self_id, self_id_count);
1876 if (pos >= 0) {
1877 memmove(&(ohci->self_id_buffer[pos+1]),
1878 &(ohci->self_id_buffer[pos]),
1879 (self_id_count - pos) * sizeof(*ohci->self_id_buffer));
1880 ohci->self_id_buffer[pos] = self_id;
1881 self_id_count++;
1882 }
1883 return self_id_count;
1884}
1885
2d7a36e2 1886static void bus_reset_work(struct work_struct *work)
ed568912 1887{
2d7a36e2
SG		 1888 struct fw_ohci *ohci =
1889 container_of(work, struct fw_ohci, bus_reset_work);
d713dfa7
SR		 1890 int self_id_count, generation, new_generation, i, j;
1891 u32 reg;
4eaff7d6
SR		 1892 void *free_rom = NULL;
1893 dma_addr_t free_rom_bus = 0;
4ffb7a6a 1894 bool is_new_root;
ed568912
KH		 1895
1896 reg = reg_read(ohci, OHCI1394_NodeID);
1897 if (!(reg & OHCI1394_NodeID_idValid)) {
de97cb64
PH		 1898 ohci_notice(ohci,
1899 "node ID not valid, new bus reset in progress\n");
ed568912
KH		 1900 return;
1901 }
02ff8f8e 1902 if ((reg & OHCI1394_NodeID_nodeNumber) == 63) {
de97cb64 1903 ohci_notice(ohci, "malconfigured bus\n");
02ff8f8e
SR		 1904 return;
1905 }
1906 ohci->node_id = reg & (OHCI1394_NodeID_busNumber |
1907 OHCI1394_NodeID_nodeNumber);
ed568912 1908
4ffb7a6a
CL		 1909 is_new_root = (reg & OHCI1394_NodeID_root) != 0;
1910 if (!(ohci->is_root && is_new_root))
1911 reg_write(ohci, OHCI1394_LinkControlSet,
1912 OHCI1394_LinkControl_cycleMaster);
1913 ohci->is_root = is_new_root;
1914
c8a9a498
SR		 1915 reg = reg_read(ohci, OHCI1394_SelfIDCount);
1916 if (reg & OHCI1394_SelfIDCount_selfIDError) {
67672134 1917 ohci_notice(ohci, "self ID receive error\n");
c8a9a498
SR		 1918 return;
1919 }
c781c06d
KH		 1920 /*
1921 * The count in the SelfIDCount register is the number of
ed568912
KH		 1922 * bytes in the self ID receive buffer. Since we also receive
1923 * the inverted quadlets and a header quadlet, we shift one
c781c06d
KH		 1924 * bit extra to get the actual number of self IDs.
1925 */
928ec5f1 1926 self_id_count = (reg >> 3) & 0xff;
25935ebe
SG		 1927
1928 if (self_id_count > 252) {
67672134 1929 ohci_notice(ohci, "bad selfIDSize (%08x)\n", reg);
016bf3df
SR		 1930 return;
1931 }
25935ebe 1932
af53122a 1933 generation = (cond_le32_to_cpu(ohci->self_id[0]) >> 16) & 0xff;
ee71c2f9 1934 rmb();
ed568912
KH		 1935
1936 for (i = 1, j = 0; j < self_id_count; i += 2, j++) {
af53122a
SR		 1937 u32 id = cond_le32_to_cpu(ohci->self_id[i]);
1938 u32 id2 = cond_le32_to_cpu(ohci->self_id[i + 1]);
67672134
PH		 1939
1940 if (id != ~id2) {
32eaeae1
CL		 1941 /*
1942 * If the invalid data looks like a cycle start packet,
1943 * it's likely to be the result of the cycle master
1944 * having a wrong gap count. In this case, the self IDs
1945 * so far are valid and should be processed so that the
1946 * bus manager can then correct the gap count.
1947 */
67672134
PH		 1948 if (id == 0xffff008f) {
1949 ohci_notice(ohci, "ignoring spurious self IDs\n");
32eaeae1
CL		 1950 self_id_count = j;
1951 break;
32eaeae1 1952 }
67672134
PH		 1953
1954 ohci_notice(ohci, "bad self ID %d/%d (%08x != ~%08x)\n",
1955 j, self_id_count, id, id2);
1956 return;
c8a9a498 1957 }
67672134 1958 ohci->self_id_buffer[j] = id;
ed568912 1959 }
25935ebe
SG		 1960
1961 if (ohci->quirks & QUIRK_TI_SLLZ059) {
1962 self_id_count = find_and_insert_self_id(ohci, self_id_count);
1963 if (self_id_count < 0) {
de97cb64
PH		 1964 ohci_notice(ohci,
1965 "could not construct local self ID\n");
25935ebe
SG		 1966 return;
1967 }
1968 }
1969
1970 if (self_id_count == 0) {
67672134 1971 ohci_notice(ohci, "no self IDs\n");
25935ebe
SG		 1972 return;
1973 }
ee71c2f9 1974 rmb();
ed568912 1975
c781c06d
KH		 1976 /*
1977 * Check the consistency of the self IDs we just read. The
ed568912
KH		 1978 * problem we face is that a new bus reset can start while we
1979 * read out the self IDs from the DMA buffer. If this happens,
1980 * the DMA buffer will be overwritten with new self IDs and we
1981 * will read out inconsistent data. The OHCI specification
1982 * (section 11.2) recommends a technique similar to
1983 * linux/seqlock.h, where we remember the generation of the
1984 * self IDs in the buffer before reading them out and compare
1985 * it to the current generation after reading them out. If
1986 * the two generations match we know we have a consistent set
c781c06d
KH		 1987 * of self IDs.
1988 */
ed568912
KH		 1989
1990 new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff;
1991 if (new_generation != generation) {
de97cb64 1992 ohci_notice(ohci, "new bus reset, discarding self ids\n");
ed568912
KH		 1993 return;
1994 }
1995
1996 /* FIXME: Document how the locking works. */
8a8c4736 1997 spin_lock_irq(&ohci->lock);
ed568912 1998
82b662dc 1999 ohci->generation = -1; /* prevent AT packet queueing */
f319b6a0
KH		 2000 context_stop(&ohci->at_request_ctx);
2001 context_stop(&ohci->at_response_ctx);
82b662dc 2002
8a8c4736 2003 spin_unlock_irq(&ohci->lock);
82b662dc 2004
78dec56d
SR		 2005 /*
2006 * Per OHCI 1.2 draft, clause 7.2.3.3, hardware may leave unsent
2007 * packets in the AT queues and software needs to drain them.
2008 * Some OHCI 1.1 controllers (JMicron) apparently require this too.
2009 */
82b662dc
CL		 2010 at_context_flush(&ohci->at_request_ctx);
2011 at_context_flush(&ohci->at_response_ctx);
2012
8a8c4736 2013 spin_lock_irq(&ohci->lock);
82b662dc
CL		 2014
2015 ohci->generation = generation;
ed568912
KH		 2016 reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
2017
4a635593 2018 if (ohci->quirks & QUIRK_RESET_PACKET)
d34316a4
SR		 2019 ohci->request_generation = generation;
2020
c781c06d
KH		 2021 /*
2022 * This next bit is unrelated to the AT context stuff but we
ed568912
KH		 2023 * have to do it under the spinlock also. If a new config rom
2024 * was set up before this reset, the old one is now no longer
2025 * in use and we can free it. Update the config rom pointers
2026 * to point to the current config rom and clear the
88393161 2027 * next_config_rom pointer so a new update can take place.
c781c06d 2028 */
ed568912
KH		 2029
2030 if (ohci->next_config_rom != NULL) {
0bd243c4
KH		 2031 if (ohci->next_config_rom != ohci->config_rom) {
2032 free_rom = ohci->config_rom;
2033 free_rom_bus = ohci->config_rom_bus;
2034 }
ed568912
KH		 2035 ohci->config_rom = ohci->next_config_rom;
2036 ohci->config_rom_bus = ohci->next_config_rom_bus;
2037 ohci->next_config_rom = NULL;
2038
c781c06d
KH		 2039 /*
2040 * Restore config_rom image and manually update
ed568912
KH		 2041 * config_rom registers. Writing the header quadlet
2042 * will indicate that the config rom is ready, so we
c781c06d
KH		 2043 * do that last.
2044 */
ed568912
KH		 2045 reg_write(ohci, OHCI1394_BusOptions,
2046 be32_to_cpu(ohci->config_rom[2]));
8e85973e
SR		 2047 ohci->config_rom[0] = ohci->next_header;
2048 reg_write(ohci, OHCI1394_ConfigROMhdr,
2049 be32_to_cpu(ohci->next_header));
ed568912
KH		 2050 }
2051
8bc588e0
LR		 2052 if (param_remote_dma) {
2053 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0);
2054 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0);
2055 }
080de8c2 2056
8a8c4736 2057 spin_unlock_irq(&ohci->lock);
ed568912 2058
4eaff7d6
SR		 2059 if (free_rom)
2060 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2061 free_rom, free_rom_bus);
2062
64d21720 2063 log_selfids(ohci, generation, self_id_count);
ad3c0fe8 2064
e636fe25 2065 fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation,
c8a94ded
SR		 2066 self_id_count, ohci->self_id_buffer,
2067 ohci->csr_state_setclear_abdicate);
2068 ohci->csr_state_setclear_abdicate = false;
ed568912
KH		 2069}
2070
2071static irqreturn_t irq_handler(int irq, void *data)
2072{
2073 struct fw_ohci *ohci = data;
168cf9af 2074 u32 event, iso_event;
ed568912
KH		 2075 int i;
2076
2077 event = reg_read(ohci, OHCI1394_IntEventClear);
2078
a515958d 2079 if (!event || !~event)
ed568912
KH		 2080 return IRQ_NONE;
2081
8327b37b
CL		 2082 /*
2083 * busReset and postedWriteErr must not be cleared yet
2084 * (OHCI 1.1 clauses 7.2.3.2 and 13.2.8.1)
2085 */
2086 reg_write(ohci, OHCI1394_IntEventClear,
2087 event & ~(OHCI1394_busReset | OHCI1394_postedWriteErr));
64d21720 2088 log_irqs(ohci, event);
ed568912
KH		 2089
2090 if (event & OHCI1394_selfIDComplete)
db9ae8fe 2091 queue_work(selfid_workqueue, &ohci->bus_reset_work);
ed568912
KH		 2092
2093 if (event & OHCI1394_RQPkt)
2094 tasklet_schedule(&ohci->ar_request_ctx.tasklet);
2095
2096 if (event & OHCI1394_RSPkt)
2097 tasklet_schedule(&ohci->ar_response_ctx.tasklet);
2098
2099 if (event & OHCI1394_reqTxComplete)
2100 tasklet_schedule(&ohci->at_request_ctx.tasklet);
2101
2102 if (event & OHCI1394_respTxComplete)
2103 tasklet_schedule(&ohci->at_response_ctx.tasklet);
2104
2dd5bed5
CL		 2105 if (event & OHCI1394_isochRx) {
2106 iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear);
2107 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event);
2108
2109 while (iso_event) {
2110 i = ffs(iso_event) - 1;
2111 tasklet_schedule(
2112 &ohci->ir_context_list[i].context.tasklet);
2113 iso_event &= ~(1 << i);
2114 }
ed568912
KH		 2115 }
2116
2dd5bed5
CL		 2117 if (event & OHCI1394_isochTx) {
2118 iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear);
2119 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event);
ed568912 2120
2dd5bed5
CL		 2121 while (iso_event) {
2122 i = ffs(iso_event) - 1;
2123 tasklet_schedule(
2124 &ohci->it_context_list[i].context.tasklet);
2125 iso_event &= ~(1 << i);
2126 }
ed568912
KH		 2127 }
2128
75f7832e 2129 if (unlikely(event & OHCI1394_regAccessFail))
de97cb64 2130 ohci_err(ohci, "register access failure\n");
75f7832e 2131
8327b37b
CL		 2132 if (unlikely(event & OHCI1394_postedWriteErr)) {
2133 reg_read(ohci, OHCI1394_PostedWriteAddressHi);
2134 reg_read(ohci, OHCI1394_PostedWriteAddressLo);
2135 reg_write(ohci, OHCI1394_IntEventClear,
2136 OHCI1394_postedWriteErr);
a74477db 2137 if (printk_ratelimit())
de97cb64 2138 ohci_err(ohci, "PCI posted write error\n");
8327b37b 2139 }
e524f616 2140
bb9f2206
SR		 2141 if (unlikely(event & OHCI1394_cycleTooLong)) {
2142 if (printk_ratelimit())
de97cb64 2143 ohci_notice(ohci, "isochronous cycle too long\n");
bb9f2206
SR		 2144 reg_write(ohci, OHCI1394_LinkControlSet,
2145 OHCI1394_LinkControl_cycleMaster);
2146 }
2147
5ed1f321
JF		 2148 if (unlikely(event & OHCI1394_cycleInconsistent)) {
2149 /*
2150 * We need to clear this event bit in order to make
2151 * cycleMatch isochronous I/O work. In theory we should
2152 * stop active cycleMatch iso contexts now and restart
2153 * them at least two cycles later. (FIXME?)
2154 */
2155 if (printk_ratelimit())
de97cb64 2156 ohci_notice(ohci, "isochronous cycle inconsistent\n");
5ed1f321
JF		 2157 }
2158
f117a3e3
CL		 2159 if (unlikely(event & OHCI1394_unrecoverableError))
2160 handle_dead_contexts(ohci);
2161
a48777e0
CL		 2162 if (event & OHCI1394_cycle64Seconds) {
2163 spin_lock(&ohci->lock);
2164 update_bus_time(ohci);
2165 spin_unlock(&ohci->lock);
e597e989
CL		 2166 } else
2167 flush_writes(ohci);
a48777e0 2168
ed568912
KH		 2169 return IRQ_HANDLED;
2170}
2171
2aef469a
KH		 2172static int software_reset(struct fw_ohci *ohci)
2173{
9f426173 2174 u32 val;
2aef469a
KH		 2175 int i;
2176
2177 reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
9f426173
SR		 2178 for (i = 0; i < 500; i++) {
2179 val = reg_read(ohci, OHCI1394_HCControlSet);
2180 if (!~val)
2181 return -ENODEV; /* Card was ejected. */
2aef469a 2182
9f426173 2183 if (!(val & OHCI1394_HCControl_softReset))
2aef469a 2184 return 0;
9f426173 2185
2aef469a
KH		 2186 msleep(1);
2187 }
2188
2189 return -EBUSY;
2190}
2191
8e85973e
SR		 2192static void copy_config_rom(__be32 *dest, const __be32 *src, size_t length)
2193{
2194 size_t size = length * 4;
2195
2196 memcpy(dest, src, size);
2197 if (size < CONFIG_ROM_SIZE)
2198 memset(&dest[length], 0, CONFIG_ROM_SIZE - size);
2199}
2200
925e7a65
CL		 2201static int configure_1394a_enhancements(struct fw_ohci *ohci)
2202{
2203 bool enable_1394a;
35d999b1 2204 int ret, clear, set, offset;
925e7a65
CL		 2205
2206 /* Check if the driver should configure link and PHY. */
2207 if (!(reg_read(ohci, OHCI1394_HCControlSet) &
2208 OHCI1394_HCControl_programPhyEnable))
2209 return 0;
2210
2211 /* Paranoia: check whether the PHY supports 1394a, too. */
2212 enable_1394a = false;
35d999b1
SR		 2213 ret = read_phy_reg(ohci, 2);
2214 if (ret < 0)
2215 return ret;
2216 if ((ret & PHY_EXTENDED_REGISTERS) == PHY_EXTENDED_REGISTERS) {
2217 ret = read_paged_phy_reg(ohci, 1, 8);
2218 if (ret < 0)
2219 return ret;
2220 if (ret >= 1)
925e7a65
CL		 2221 enable_1394a = true;
2222 }
2223
2224 if (ohci->quirks & QUIRK_NO_1394A)
2225 enable_1394a = false;
2226
2227 /* Configure PHY and link consistently. */
2228 if (enable_1394a) {
2229 clear = 0;
2230 set = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
2231 } else {
2232 clear = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
2233 set = 0;
2234 }
02d37bed 2235 ret = update_phy_reg(ohci, 5, clear, set);
35d999b1
SR		 2236 if (ret < 0)
2237 return ret;
925e7a65
CL		 2238
2239 if (enable_1394a)
2240 offset = OHCI1394_HCControlSet;
2241 else
2242 offset = OHCI1394_HCControlClear;
2243 reg_write(ohci, offset, OHCI1394_HCControl_aPhyEnhanceEnable);
2244
2245 /* Clean up: configuration has been taken care of. */
2246 reg_write(ohci, OHCI1394_HCControlClear,
2247 OHCI1394_HCControl_programPhyEnable);
2248
2249 return 0;
2250}
2251
25935ebe
SG		 2252static int probe_tsb41ba3d(struct fw_ohci *ohci)
2253{
b810e4ae
SR		 2254 /* TI vendor ID = 0x080028, TSB41BA3D product ID = 0x833005 (sic) */
2255 static const u8 id[] = { 0x08, 0x00, 0x28, 0x83, 0x30, 0x05, };
2256 int reg, i;
25935ebe
SG		 2257
2258 reg = read_phy_reg(ohci, 2);
2259 if (reg < 0)
2260 return reg;
b810e4ae
SR		 2261 if ((reg & PHY_EXTENDED_REGISTERS) != PHY_EXTENDED_REGISTERS)
2262 return 0;
25935ebe 2263
b810e4ae
SR		 2264 for (i = ARRAY_SIZE(id) - 1; i >= 0; i--) {
2265 reg = read_paged_phy_reg(ohci, 1, i + 10);
2266 if (reg < 0)
2267 return reg;
2268 if (reg != id[i])
2269 return 0;
25935ebe 2270 }
b810e4ae 2271 return 1;
25935ebe
SG		 2272}
2273
8e85973e
SR		 2274static int ohci_enable(struct fw_card *card,
2275 const __be32 *config_rom, size_t length)
ed568912
KH		 2276{
2277 struct fw_ohci *ohci = fw_ohci(card);
9d60ef2b 2278 u32 lps, version, irqs;
28897fb7 2279 int i, ret;
ed568912 2280
2aef469a 2281 if (software_reset(ohci)) {
de97cb64 2282 ohci_err(ohci, "failed to reset ohci card\n");
2aef469a
KH		 2283 return -EBUSY;
2284 }
2285
2286 /*
2287 * Now enable LPS, which we need in order to start accessing
2288 * most of the registers. In fact, on some cards (ALI M5251),
2289 * accessing registers in the SClk domain without LPS enabled
2290 * will lock up the machine. Wait 50msec to make sure we have
02214724
JW		 2291 * full link enabled. However, with some cards (well, at least
2292 * a JMicron PCIe card), we have to try again sometimes.
bd972688
PH		 2293 *
2294 * TI TSB82AA2 + TSB81BA3(A) cards signal LPS enabled early but
2295 * cannot actually use the phy at that time. These need tens of
2296 * millisecods pause between LPS write and first phy access too.
2aef469a 2297 */
bd972688 2298
2aef469a
KH		 2299 reg_write(ohci, OHCI1394_HCControlSet,
2300 OHCI1394_HCControl_LPS |
2301 OHCI1394_HCControl_postedWriteEnable);
2302 flush_writes(ohci);
02214724 2303
0ca49345 2304 for (lps = 0, i = 0; !lps && i < 3; i++) {
02214724
JW		 2305 msleep(50);
2306 lps = reg_read(ohci, OHCI1394_HCControlSet) &
2307 OHCI1394_HCControl_LPS;
2308 }
2309
2310 if (!lps) {
de97cb64 2311 ohci_err(ohci, "failed to set Link Power Status\n");
02214724
JW		 2312 return -EIO;
2313 }
2aef469a 2314
25935ebe 2315 if (ohci->quirks & QUIRK_TI_SLLZ059) {
28897fb7
SR		 2316 ret = probe_tsb41ba3d(ohci);
2317 if (ret < 0)
2318 return ret;
2319 if (ret)
de97cb64 2320 ohci_notice(ohci, "local TSB41BA3D phy\n");
28897fb7 2321 else
25935ebe 2322 ohci->quirks &= ~QUIRK_TI_SLLZ059;
25935ebe
SG		 2323 }
2324
2aef469a
KH		 2325 reg_write(ohci, OHCI1394_HCControlClear,
2326 OHCI1394_HCControl_noByteSwapData);
2327
affc9c24 2328 reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
2aef469a 2329 reg_write(ohci, OHCI1394_LinkControlSet,
2aef469a
KH		 2330 OHCI1394_LinkControl_cycleTimerEnable |
2331 OHCI1394_LinkControl_cycleMaster);
2332
2333 reg_write(ohci, OHCI1394_ATRetries,
2334 OHCI1394_MAX_AT_REQ_RETRIES |
2335 (OHCI1394_MAX_AT_RESP_RETRIES << 4) |
27a2329f
CL		 2336 (OHCI1394_MAX_PHYS_RESP_RETRIES << 8) |
2337 (200 << 16));
2aef469a 2338
9d60ef2b 2339 ohci->bus_time_running = false;
a48777e0 2340
e18907cc
CL		 2341 for (i = 0; i < 32; i++)
2342 if (ohci->ir_context_support & (1 << i))
2343 reg_write(ohci, OHCI1394_IsoRcvContextControlClear(i),
2344 IR_CONTEXT_MULTI_CHANNEL_MODE);
2345
e91b2787
CL		 2346 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
2347 if (version >= OHCI_VERSION_1_1) {
2348 reg_write(ohci, OHCI1394_InitialChannelsAvailableHi,
2349 0xfffffffe);
db3c9cc1 2350 card->broadcast_channel_auto_allocated = true;
e91b2787
CL		 2351 }
2352
a1a1132b
CL		 2353 /* Get implemented bits of the priority arbitration request counter. */
2354 reg_write(ohci, OHCI1394_FairnessControl, 0x3f);
2355 ohci->pri_req_max = reg_read(ohci, OHCI1394_FairnessControl) & 0x3f;
2356 reg_write(ohci, OHCI1394_FairnessControl, 0);
db3c9cc1 2357 card->priority_budget_implemented = ohci->pri_req_max != 0;
2aef469a 2358
fcd46b34 2359 reg_write(ohci, OHCI1394_PhyUpperBound, FW_MAX_PHYSICAL_RANGE >> 16);
2aef469a
KH		 2360 reg_write(ohci, OHCI1394_IntEventClear, ~0);
2361 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
2aef469a 2362
35d999b1
SR		 2363 ret = configure_1394a_enhancements(ohci);
2364 if (ret < 0)
2365 return ret;
925e7a65 2366
2aef469a 2367 /* Activate link_on bit and contender bit in our self ID packets.*/
35d999b1
SR		 2368 ret = ohci_update_phy_reg(card, 4, 0, PHY_LINK_ACTIVE | PHY_CONTENDER);
2369 if (ret < 0)
2370 return ret;
2aef469a 2371
c781c06d
KH		 2372 /*
2373 * When the link is not yet enabled, the atomic config rom
ed568912
KH		 2374 * update mechanism described below in ohci_set_config_rom()
2375 * is not active. We have to update ConfigRomHeader and
2376 * BusOptions manually, and the write to ConfigROMmap takes
2377 * effect immediately. We tie this to the enabling of the
2378 * link, so we have a valid config rom before enabling - the
2379 * OHCI requires that ConfigROMhdr and BusOptions have valid
2380 * values before enabling.
2381 *
2382 * However, when the ConfigROMmap is written, some controllers
2383 * always read back quadlets 0 and 2 from the config rom to
2384 * the ConfigRomHeader and BusOptions registers on bus reset.
2385 * They shouldn't do that in this initial case where the link
2386 * isn't enabled. This means we have to use the same
2387 * workaround here, setting the bus header to 0 and then write
2388 * the right values in the bus reset tasklet.
2389 */
2390
0bd243c4
KH		 2391 if (config_rom) {
2392 ohci->next_config_rom =
2393 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2394 &ohci->next_config_rom_bus,
2395 GFP_KERNEL);
2396 if (ohci->next_config_rom == NULL)
2397 return -ENOMEM;
ed568912 2398
8e85973e 2399 copy_config_rom(ohci->next_config_rom, config_rom, length);
0bd243c4
KH		 2400 } else {
2401 /*
2402 * In the suspend case, config_rom is NULL, which
2403 * means that we just reuse the old config rom.
2404 */
2405 ohci->next_config_rom = ohci->config_rom;
2406 ohci->next_config_rom_bus = ohci->config_rom_bus;
2407 }
ed568912 2408
8e85973e 2409 ohci->next_header = ohci->next_config_rom[0];
ed568912
KH		 2410 ohci->next_config_rom[0] = 0;
2411 reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
0bd243c4
KH		 2412 reg_write(ohci, OHCI1394_BusOptions,
2413 be32_to_cpu(ohci->next_config_rom[2]));
ed568912
KH		 2414 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
2415
2416 reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
2417
148c7866
SR		 2418 irqs = OHCI1394_reqTxComplete | OHCI1394_respTxComplete |
2419 OHCI1394_RQPkt | OHCI1394_RSPkt |
2420 OHCI1394_isochTx | OHCI1394_isochRx |
2421 OHCI1394_postedWriteErr |
2422 OHCI1394_selfIDComplete |
2423 OHCI1394_regAccessFail |
f117a3e3
CL		 2424 OHCI1394_cycleInconsistent |
2425 OHCI1394_unrecoverableError |
2426 OHCI1394_cycleTooLong |
148c7866
SR		 2427 OHCI1394_masterIntEnable;
2428 if (param_debug & OHCI_PARAM_DEBUG_BUSRESETS)
2429 irqs |= OHCI1394_busReset;
2430 reg_write(ohci, OHCI1394_IntMaskSet, irqs);
2431
ed568912
KH		 2432 reg_write(ohci, OHCI1394_HCControlSet,
2433 OHCI1394_HCControl_linkEnable |
2434 OHCI1394_HCControl_BIBimageValid);
ecf8328e
CL		 2435
2436 reg_write(ohci, OHCI1394_LinkControlSet,
2437 OHCI1394_LinkControl_rcvSelfID |
2438 OHCI1394_LinkControl_rcvPhyPkt);
2439
2440 ar_context_run(&ohci->ar_request_ctx);
dd6254e5
CL		 2441 ar_context_run(&ohci->ar_response_ctx);
2442
2443 flush_writes(ohci);
ed568912 2444
02d37bed
SR		 2445 /* We are ready to go, reset bus to finish initialization. */
2446 fw_schedule_bus_reset(&ohci->card, false, true);
ed568912
KH		 2447
2448 return 0;
2449}
2450
53dca511 2451static int ohci_set_config_rom(struct fw_card *card,
8e85973e 2452 const __be32 *config_rom, size_t length)
ed568912
KH		 2453{
2454 struct fw_ohci *ohci;
ed568912 2455 __be32 *next_config_rom;
f5101d58 2456 dma_addr_t uninitialized_var(next_config_rom_bus);
ed568912
KH		 2457
2458 ohci = fw_ohci(card);
2459
c781c06d
KH		 2460 /*
2461 * When the OHCI controller is enabled, the config rom update
ed568912
KH		 2462 * mechanism is a bit tricky, but easy enough to use. See
2463 * section 5.5.6 in the OHCI specification.
2464 *
2465 * The OHCI controller caches the new config rom address in a
2466 * shadow register (ConfigROMmapNext) and needs a bus reset
2467 * for the changes to take place. When the bus reset is
2468 * detected, the controller loads the new values for the
2469 * ConfigRomHeader and BusOptions registers from the specified
2470 * config rom and loads ConfigROMmap from the ConfigROMmapNext
2471 * shadow register. All automatically and atomically.
2472 *
2473 * Now, there's a twist to this story. The automatic load of
2474 * ConfigRomHeader and BusOptions doesn't honor the
2475 * noByteSwapData bit, so with a be32 config rom, the
2476 * controller will load be32 values in to these registers
2477 * during the atomic update, even on litte endian
2478 * architectures. The workaround we use is to put a 0 in the
2479 * header quadlet; 0 is endian agnostic and means that the
2480 * config rom isn't ready yet. In the bus reset tasklet we
2481 * then set up the real values for the two registers.
2482 *
2483 * We use ohci->lock to avoid racing with the code that sets
2d7a36e2 2484 * ohci->next_config_rom to NULL (see bus_reset_work).
ed568912
KH		 2485 */
2486
2487 next_config_rom =
2488 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2489 &next_config_rom_bus, GFP_KERNEL);
2490 if (next_config_rom == NULL)
2491 return -ENOMEM;
2492
8a8c4736 2493 spin_lock_irq(&ohci->lock);
ed568912 2494
2e053a27
B		 2495 /*
2496 * If there is not an already pending config_rom update,
2497 * push our new allocation into the ohci->next_config_rom
2498 * and then mark the local variable as null so that we
2499 * won't deallocate the new buffer.
2500 *
2501 * OTOH, if there is a pending config_rom update, just
2502 * use that buffer with the new config_rom data, and
2503 * let this routine free the unused DMA allocation.
2504 */
2505
ed568912
KH		 2506 if (ohci->next_config_rom == NULL) {
2507 ohci->next_config_rom = next_config_rom;
2508 ohci->next_config_rom_bus = next_config_rom_bus;
2e053a27
B		 2509 next_config_rom = NULL;
2510 }
ed568912 2511
2e053a27 2512 copy_config_rom(ohci->next_config_rom, config_rom, length);
ed568912 2513
2e053a27
B		 2514 ohci->next_header = config_rom[0];
2515 ohci->next_config_rom[0] = 0;
ed568912 2516
2e053a27 2517 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
ed568912 2518
8a8c4736 2519 spin_unlock_irq(&ohci->lock);
ed568912 2520
2e053a27
B		 2521 /* If we didn't use the DMA allocation, delete it. */
2522 if (next_config_rom != NULL)
2523 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2524 next_config_rom, next_config_rom_bus);
2525
c781c06d
KH		 2526 /*
2527 * Now initiate a bus reset to have the changes take
ed568912
KH		 2528 * effect. We clean up the old config rom memory and DMA
2529 * mappings in the bus reset tasklet, since the OHCI
2530 * controller could need to access it before the bus reset
c781c06d
KH		 2531 * takes effect.
2532 */
ed568912 2533
2e053a27
B		 2534 fw_schedule_bus_reset(&ohci->card, true, true);
2535
2536 return 0;
ed568912
KH		 2537}
2538
2539static void ohci_send_request(struct fw_card *card, struct fw_packet *packet)
2540{
2541 struct fw_ohci *ohci = fw_ohci(card);
2542
2543 at_context_transmit(&ohci->at_request_ctx, packet);
2544}
2545
2546static void ohci_send_response(struct fw_card *card, struct fw_packet *packet)
2547{
2548 struct fw_ohci *ohci = fw_ohci(card);
2549
2550 at_context_transmit(&ohci->at_response_ctx, packet);
2551}
2552
730c32f5
KH		 2553static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet)
2554{
2555 struct fw_ohci *ohci = fw_ohci(card);
f319b6a0
KH		 2556 struct context *ctx = &ohci->at_request_ctx;
2557 struct driver_data *driver_data = packet->driver_data;
2dbd7d7e 2558 int ret = -ENOENT;
730c32f5 2559
f319b6a0 2560 tasklet_disable(&ctx->tasklet);
730c32f5 2561
f319b6a0
KH		 2562 if (packet->ack != 0)
2563 goto out;
730c32f5 2564
19593ffd 2565 if (packet->payload_mapped)
1d1dc5e8
SR		 2566 dma_unmap_single(ohci->card.device, packet->payload_bus,
2567 packet->payload_length, DMA_TO_DEVICE);
2568
64d21720 2569 log_ar_at_event(ohci, 'T', packet->speed, packet->header, 0x20);
f319b6a0
KH		 2570 driver_data->packet = NULL;
2571 packet->ack = RCODE_CANCELLED;
2572 packet->callback(packet, &ohci->card, packet->ack);
2dbd7d7e 2573 ret = 0;
f319b6a0
KH		 2574 out:
2575 tasklet_enable(&ctx->tasklet);
730c32f5 2576
2dbd7d7e 2577 return ret;
730c32f5
KH		 2578}
2579
53dca511
SR		 2580static int ohci_enable_phys_dma(struct fw_card *card,
2581 int node_id, int generation)
ed568912
KH		 2582{
2583 struct fw_ohci *ohci = fw_ohci(card);
2584 unsigned long flags;
2dbd7d7e 2585 int n, ret = 0;
ed568912 2586
8bc588e0
LR		 2587 if (param_remote_dma)
2588 return 0;
2589
c781c06d
KH		 2590 /*
2591 * FIXME: Make sure this bitmask is cleared when we clear the busReset
2592 * interrupt bit. Clear physReqResourceAllBuses on bus reset.
2593 */
ed568912
KH		 2594
2595 spin_lock_irqsave(&ohci->lock, flags);
2596
2597 if (ohci->generation != generation) {
2dbd7d7e 2598 ret = -ESTALE;
ed568912
KH		 2599 goto out;
2600 }
2601
c781c06d
KH		 2602 /*
2603 * Note, if the node ID contains a non-local bus ID, physical DMA is
2604 * enabled for _all_ nodes on remote buses.
2605 */
907293d7
SR		 2606
2607 n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63;
2608 if (n < 32)
2609 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n);
2610 else
2611 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32));
2612
ed568912 2613 flush_writes(ohci);
ed568912 2614 out:
6cad95fe 2615 spin_unlock_irqrestore(&ohci->lock, flags);
2dbd7d7e
SR		 2616
2617 return ret;
ed568912 2618}
373b2edd 2619
0fcff4e3 2620static u32 ohci_read_csr(struct fw_card *card, int csr_offset)
b677532b 2621{
60d32970 2622 struct fw_ohci *ohci = fw_ohci(card);
a48777e0
CL		 2623 unsigned long flags;
2624 u32 value;
60d32970
CL		 2625
2626 switch (csr_offset) {
4ffb7a6a
CL		 2627 case CSR_STATE_CLEAR:
2628 case CSR_STATE_SET:
4ffb7a6a
CL		 2629 if (ohci->is_root &&
2630 (reg_read(ohci, OHCI1394_LinkControlSet) &
2631 OHCI1394_LinkControl_cycleMaster))
c8a94ded 2632 value = CSR_STATE_BIT_CMSTR;
4ffb7a6a 2633 else
c8a94ded
SR		 2634 value = 0;
2635 if (ohci->csr_state_setclear_abdicate)
2636 value |= CSR_STATE_BIT_ABDICATE;
b677532b 2637
c8a94ded 2638 return value;
4a9bde9b 2639
506f1a31
CL		 2640 case CSR_NODE_IDS:
2641 return reg_read(ohci, OHCI1394_NodeID) << 16;
2642
60d32970
CL		 2643 case CSR_CYCLE_TIME:
2644 return get_cycle_time(ohci);
2645
a48777e0
CL		 2646 case CSR_BUS_TIME:
2647 /*
2648 * We might be called just after the cycle timer has wrapped
2649 * around but just before the cycle64Seconds handler, so we
2650 * better check here, too, if the bus time needs to be updated.
2651 */
2652 spin_lock_irqsave(&ohci->lock, flags);
2653 value = update_bus_time(ohci);
2654 spin_unlock_irqrestore(&ohci->lock, flags);
2655 return value;
2656
27a2329f
CL		 2657 case CSR_BUSY_TIMEOUT:
2658 value = reg_read(ohci, OHCI1394_ATRetries);
2659 return (value >> 4) & 0x0ffff00f;
2660
a1a1132b
CL		 2661 case CSR_PRIORITY_BUDGET:
2662 return (reg_read(ohci, OHCI1394_FairnessControl) & 0x3f) |
2663 (ohci->pri_req_max << 8);
2664
60d32970
CL		 2665 default:
2666 WARN_ON(1);
2667 return 0;
2668 }
b677532b
CL		 2669}
2670
0fcff4e3 2671static void ohci_write_csr(struct fw_card *card, int csr_offset, u32 value)
d60d7f1d
KH		 2672{
2673 struct fw_ohci *ohci = fw_ohci(card);
a48777e0 2674 unsigned long flags;
d60d7f1d 2675
506f1a31 2676 switch (csr_offset) {
4ffb7a6a 2677 case CSR_STATE_CLEAR:
4ffb7a6a
CL		 2678 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
2679 reg_write(ohci, OHCI1394_LinkControlClear,
2680 OHCI1394_LinkControl_cycleMaster);
2681 flush_writes(ohci);
2682 }
c8a94ded
SR		 2683 if (value & CSR_STATE_BIT_ABDICATE)
2684 ohci->csr_state_setclear_abdicate = false;
4ffb7a6a 2685 break;
4a9bde9b 2686
4ffb7a6a
CL		 2687 case CSR_STATE_SET:
2688 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
2689 reg_write(ohci, OHCI1394_LinkControlSet,
2690 OHCI1394_LinkControl_cycleMaster);
2691 flush_writes(ohci);
2692 }
c8a94ded
SR		 2693 if (value & CSR_STATE_BIT_ABDICATE)
2694 ohci->csr_state_setclear_abdicate = true;
4ffb7a6a 2695 break;
d60d7f1d 2696
506f1a31
CL		 2697 case CSR_NODE_IDS:
2698 reg_write(ohci, OHCI1394_NodeID, value >> 16);
2699 flush_writes(ohci);
2700 break;
2701
9ab5071c
CL		 2702 case CSR_CYCLE_TIME:
2703 reg_write(ohci, OHCI1394_IsochronousCycleTimer, value);
2704 reg_write(ohci, OHCI1394_IntEventSet,
2705 OHCI1394_cycleInconsistent);
2706 flush_writes(ohci);
2707 break;
2708
a48777e0
CL		 2709 case CSR_BUS_TIME:
2710 spin_lock_irqsave(&ohci->lock, flags);
9d60ef2b
CL		 2711 ohci->bus_time = (update_bus_time(ohci) & 0x40) |
2712 (value & ~0x7f);
a48777e0
CL		 2713 spin_unlock_irqrestore(&ohci->lock, flags);
2714 break;
2715
27a2329f
CL		 2716 case CSR_BUSY_TIMEOUT:
2717 value = (value & 0xf) | ((value & 0xf) << 4) |
2718 ((value & 0xf) << 8) | ((value & 0x0ffff000) << 4);
2719 reg_write(ohci, OHCI1394_ATRetries, value);
2720 flush_writes(ohci);
2721 break;
2722
a1a1132b
CL		 2723 case CSR_PRIORITY_BUDGET:
2724 reg_write(ohci, OHCI1394_FairnessControl, value & 0x3f);
2725 flush_writes(ohci);
2726 break;
2727
506f1a31
CL		 2728 default:
2729 WARN_ON(1);
2730 break;
2731 }
d60d7f1d
KH		 2732}
2733
910e76c6 2734static void flush_iso_completions(struct iso_context *ctx)
1aa292bb 2735{
910e76c6
CL		 2736 ctx->base.callback.sc(&ctx->base, ctx->last_timestamp,
2737 ctx->header_length, ctx->header,
2738 ctx->base.callback_data);
2739 ctx->header_length = 0;
2740}
1aa292bb 2741
73864012 2742static void copy_iso_headers(struct iso_context *ctx, const u32 *dma_hdr)
1aa292bb 2743{
73864012 2744 u32 *ctx_hdr;
1aa292bb 2745
0699a73a
CL		 2746 if (ctx->header_length + ctx->base.header_size > PAGE_SIZE) {
2747 if (ctx->base.drop_overflow_headers)
2748 return;
18d62711 2749 flush_iso_completions(ctx);
0699a73a 2750 }
1aa292bb 2751
73864012 2752 ctx_hdr = ctx->header + ctx->header_length;
910e76c6 2753 ctx->last_timestamp = (u16)le32_to_cpu((__force __le32)dma_hdr[0]);
1aa292bb
DM		 2754
2755 /*
32c507f7
CL		 2756 * The two iso header quadlets are byteswapped to little
2757 * endian by the controller, but we want to present them
2758 * as big endian for consistency with the bus endianness.
1aa292bb
DM		 2759 */
2760 if (ctx->base.header_size > 0)
73864012 2761 ctx_hdr[0] = swab32(dma_hdr[1]); /* iso packet header */
1aa292bb 2762 if (ctx->base.header_size > 4)
73864012 2763 ctx_hdr[1] = swab32(dma_hdr[0]); /* timestamp */
1aa292bb 2764 if (ctx->base.header_size > 8)
73864012 2765 memcpy(&ctx_hdr[2], &dma_hdr[2], ctx->base.header_size - 8);
1aa292bb
DM		 2766 ctx->header_length += ctx->base.header_size;
2767}
2768
a186b4a6
JW		 2769static int handle_ir_packet_per_buffer(struct context *context,
2770 struct descriptor *d,
2771 struct descriptor *last)
2772{
2773 struct iso_context *ctx =
2774 container_of(context, struct iso_context, context);
bcee893c 2775 struct descriptor *pd;
a572e688 2776 u32 buffer_dma;
a186b4a6 2777
872e330e 2778 for (pd = d; pd <= last; pd++)
bcee893c
DM		 2779 if (pd->transfer_status)
2780 break;
bcee893c 2781 if (pd > last)
a186b4a6
JW		 2782 /* Descriptor(s) not done yet, stop iteration */
2783 return 0;
2784
a572e688
CL		 2785 while (!(d->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))) {
2786 d++;
2787 buffer_dma = le32_to_cpu(d->data_address);
2788 dma_sync_single_range_for_cpu(context->ohci->card.device,
2789 buffer_dma & PAGE_MASK,
2790 buffer_dma & ~PAGE_MASK,
2791 le16_to_cpu(d->req_count),
2792 DMA_FROM_DEVICE);
2793 }
2794
910e76c6 2795 copy_iso_headers(ctx, (u32 *) (last + 1));
a186b4a6 2796
910e76c6
CL		 2797 if (last->control & cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS))
2798 flush_iso_completions(ctx);
a186b4a6 2799
a186b4a6
JW		 2800 return 1;
2801}
2802
872e330e
SR		 2803/* d == last because each descriptor block is only a single descriptor. */
2804static int handle_ir_buffer_fill(struct context *context,
2805 struct descriptor *d,
2806 struct descriptor *last)
2807{
2808 struct iso_context *ctx =
2809 container_of(context, struct iso_context, context);
d1bbd209 2810 unsigned int req_count, res_count, completed;
a572e688 2811 u32 buffer_dma;
872e330e 2812
d1bbd209
CL		 2813 req_count = le16_to_cpu(last->req_count);
2814 res_count = le16_to_cpu(ACCESS_ONCE(last->res_count));
2815 completed = req_count - res_count;
2816 buffer_dma = le32_to_cpu(last->data_address);
2817
2818 if (completed > 0) {
2819 ctx->mc_buffer_bus = buffer_dma;
2820 ctx->mc_completed = completed;
2821 }
2822
2823 if (res_count != 0)
872e330e
SR		 2824 /* Descriptor(s) not done yet, stop iteration */
2825 return 0;
2826
a572e688
CL		 2827 dma_sync_single_range_for_cpu(context->ohci->card.device,
2828 buffer_dma & PAGE_MASK,
2829 buffer_dma & ~PAGE_MASK,
d1bbd209 2830 completed, DMA_FROM_DEVICE);
a572e688 2831
d1bbd209 2832 if (last->control & cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS)) {
872e330e 2833 ctx->base.callback.mc(&ctx->base,
d1bbd209 2834 buffer_dma + completed,
872e330e 2835 ctx->base.callback_data);
d1bbd209
CL		 2836 ctx->mc_completed = 0;
2837 }
872e330e
SR		 2838
2839 return 1;
2840}
2841
d1bbd209
CL		 2842static void flush_ir_buffer_fill(struct iso_context *ctx)
2843{
2844 dma_sync_single_range_for_cpu(ctx->context.ohci->card.device,
2845 ctx->mc_buffer_bus & PAGE_MASK,
2846 ctx->mc_buffer_bus & ~PAGE_MASK,
2847 ctx->mc_completed, DMA_FROM_DEVICE);
2848
2849 ctx->base.callback.mc(&ctx->base,
2850 ctx->mc_buffer_bus + ctx->mc_completed,
2851 ctx->base.callback_data);
2852 ctx->mc_completed = 0;
2853}
2854
a572e688
CL		 2855static inline void sync_it_packet_for_cpu(struct context *context,
2856 struct descriptor *pd)
2857{
2858 __le16 control;
2859 u32 buffer_dma;
2860
2861 /* only packets beginning with OUTPUT_MORE* have data buffers */
2862 if (pd->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))
2863 return;
2864
2865 /* skip over the OUTPUT_MORE_IMMEDIATE descriptor */
2866 pd += 2;
2867
2868 /*
2869 * If the packet has a header, the first OUTPUT_MORE/LAST descriptor's
2870 * data buffer is in the context program's coherent page and must not
2871 * be synced.
2872 */
2873 if ((le32_to_cpu(pd->data_address) & PAGE_MASK) ==
2874 (context->current_bus & PAGE_MASK)) {
2875 if (pd->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))
2876 return;
2877 pd++;
2878 }
2879
2880 do {
2881 buffer_dma = le32_to_cpu(pd->data_address);
2882 dma_sync_single_range_for_cpu(context->ohci->card.device,
2883 buffer_dma & PAGE_MASK,
2884 buffer_dma & ~PAGE_MASK,
2885 le16_to_cpu(pd->req_count),
2886 DMA_TO_DEVICE);
2887 control = pd->control;
2888 pd++;
2889 } while (!(control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS)));
2890}
2891
30200739
KH		 2892static int handle_it_packet(struct context *context,
2893 struct descriptor *d,
2894 struct descriptor *last)
ed568912 2895{
30200739
KH		 2896 struct iso_context *ctx =
2897 container_of(context, struct iso_context, context);
31769cef 2898 struct descriptor *pd;
73864012 2899 __be32 *ctx_hdr;
373b2edd 2900
31769cef
JF		 2901 for (pd = d; pd <= last; pd++)
2902 if (pd->transfer_status)
2903 break;
2904 if (pd > last)
2905 /* Descriptor(s) not done yet, stop iteration */
30200739
KH		 2906 return 0;
2907
a572e688
CL		 2908 sync_it_packet_for_cpu(context, d);
2909
0699a73a
CL		 2910 if (ctx->header_length + 4 > PAGE_SIZE) {
2911 if (ctx->base.drop_overflow_headers)
2912 return 1;
18d62711 2913 flush_iso_completions(ctx);
0699a73a 2914 }
910e76c6 2915
18d62711 2916 ctx_hdr = ctx->header + ctx->header_length;
910e76c6 2917 ctx->last_timestamp = le16_to_cpu(last->res_count);
18d62711
CL		 2918 /* Present this value as big-endian to match the receive code */
2919 *ctx_hdr = cpu_to_be32((le16_to_cpu(pd->transfer_status) << 16) |
2920 le16_to_cpu(pd->res_count));
2921 ctx->header_length += 4;
2922
910e76c6
CL		 2923 if (last->control & cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS))
2924 flush_iso_completions(ctx);
2925
30200739 2926 return 1;
ed568912
KH		 2927}
2928
872e330e
SR		 2929static void set_multichannel_mask(struct fw_ohci *ohci, u64 channels)
2930{
2931 u32 hi = channels >> 32, lo = channels;
2932
2933 reg_write(ohci, OHCI1394_IRMultiChanMaskHiClear, ~hi);
2934 reg_write(ohci, OHCI1394_IRMultiChanMaskLoClear, ~lo);
2935 reg_write(ohci, OHCI1394_IRMultiChanMaskHiSet, hi);
2936 reg_write(ohci, OHCI1394_IRMultiChanMaskLoSet, lo);
2937 mmiowb();
2938 ohci->mc_channels = channels;
2939}
2940
53dca511 2941static struct fw_iso_context *ohci_allocate_iso_context(struct fw_card *card,
4817ed24 2942 int type, int channel, size_t header_size)
ed568912
KH		 2943{
2944 struct fw_ohci *ohci = fw_ohci(card);
872e330e
SR		 2945 struct iso_context *uninitialized_var(ctx);
2946 descriptor_callback_t uninitialized_var(callback);
2947 u64 *uninitialized_var(channels);
2948 u32 *uninitialized_var(mask), uninitialized_var(regs);
872e330e 2949 int index, ret = -EBUSY;
ed568912 2950
8a8c4736 2951 spin_lock_irq(&ohci->lock);
ed568912 2952
872e330e
SR		 2953 switch (type) {
2954 case FW_ISO_CONTEXT_TRANSMIT:
2955 mask = &ohci->it_context_mask;
30200739 2956 callback = handle_it_packet;
872e330e
SR		 2957 index = ffs(*mask) - 1;
2958 if (index >= 0) {
2959 *mask &= ~(1 << index);
2960 regs = OHCI1394_IsoXmitContextBase(index);
2961 ctx = &ohci->it_context_list[index];
2962 }
2963 break;
2964
2965 case FW_ISO_CONTEXT_RECEIVE:
4817ed24 2966 channels = &ohci->ir_context_channels;
872e330e 2967 mask = &ohci->ir_context_mask;
6498ba04 2968 callback = handle_ir_packet_per_buffer;
872e330e
SR		 2969 index = *channels & 1ULL << channel ? ffs(*mask) - 1 : -1;
2970 if (index >= 0) {
2971 *channels &= ~(1ULL << channel);
2972 *mask &= ~(1 << index);
2973 regs = OHCI1394_IsoRcvContextBase(index);
2974 ctx = &ohci->ir_context_list[index];
2975 }
2976 break;
ed568912 2977
872e330e
SR		 2978 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2979 mask = &ohci->ir_context_mask;
2980 callback = handle_ir_buffer_fill;
2981 index = !ohci->mc_allocated ? ffs(*mask) - 1 : -1;
2982 if (index >= 0) {
2983 ohci->mc_allocated = true;
2984 *mask &= ~(1 << index);
2985 regs = OHCI1394_IsoRcvContextBase(index);
2986 ctx = &ohci->ir_context_list[index];
2987 }
2988 break;
2989
2990 default:
2991 index = -1;
2992 ret = -ENOSYS;
4817ed24 2993 }
872e330e 2994
8a8c4736 2995 spin_unlock_irq(&ohci->lock);
ed568912
KH		 2996
2997 if (index < 0)
872e330e 2998 return ERR_PTR(ret);
373b2edd 2999
2d826cc5 3000 memset(ctx, 0, sizeof(*ctx));
9b32d5f3
KH		 3001 ctx->header_length = 0;
3002 ctx->header = (void *) __get_free_page(GFP_KERNEL);
872e330e
SR		 3003 if (ctx->header == NULL) {
3004 ret = -ENOMEM;
9b32d5f3 3005 goto out;
872e330e 3006 }
2dbd7d7e
SR		 3007 ret = context_init(&ctx->context, ohci, regs, callback);
3008 if (ret < 0)
9b32d5f3 3009 goto out_with_header;
ed568912 3010
d1bbd209 3011 if (type == FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL) {
872e330e 3012 set_multichannel_mask(ohci, 0);
d1bbd209
CL		 3013 ctx->mc_completed = 0;
3014 }
872e330e 3015
ed568912 3016 return &ctx->base;
9b32d5f3
KH		 3017
3018 out_with_header:
3019 free_page((unsigned long)ctx->header);
3020 out:
8a8c4736 3021 spin_lock_irq(&ohci->lock);
872e330e
SR		 3022
3023 switch (type) {
3024 case FW_ISO_CONTEXT_RECEIVE:
3025 *channels |= 1ULL << channel;
3026 break;
3027
3028 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3029 ohci->mc_allocated = false;
3030 break;
3031 }
9b32d5f3 3032 *mask |= 1 << index;
872e330e 3033
8a8c4736 3034 spin_unlock_irq(&ohci->lock);
9b32d5f3 3035
2dbd7d7e 3036 return ERR_PTR(ret);
ed568912
KH		 3037}
3038
eb0306ea
KH		 3039static int ohci_start_iso(struct fw_iso_context *base,
3040 s32 cycle, u32 sync, u32 tags)
ed568912 3041{
373b2edd 3042 struct iso_context *ctx = container_of(base, struct iso_context, base);
30200739 3043 struct fw_ohci *ohci = ctx->context.ohci;
872e330e 3044 u32 control = IR_CONTEXT_ISOCH_HEADER, match;
ed568912
KH		 3045 int index;
3046
44b74d90
CL		 3047 /* the controller cannot start without any queued packets */
3048 if (ctx->context.last->branch_address == 0)
3049 return -ENODATA;
3050
872e330e
SR		 3051 switch (ctx->base.type) {
3052 case FW_ISO_CONTEXT_TRANSMIT:
295e3feb 3053 index = ctx - ohci->it_context_list;
8a2f7d93
KH		 3054 match = 0;
3055 if (cycle >= 0)
3056 match = IT_CONTEXT_CYCLE_MATCH_ENABLE |
295e3feb 3057 (cycle & 0x7fff) << 16;
21efb3cf 3058
295e3feb
KH		 3059 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index);
3060 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index);
8a2f7d93 3061 context_run(&ctx->context, match);
872e330e
SR		 3062 break;
3063
3064 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3065 control |= IR_CONTEXT_BUFFER_FILL|IR_CONTEXT_MULTI_CHANNEL_MODE;
3066 /* fall through */
3067 case FW_ISO_CONTEXT_RECEIVE:
295e3feb 3068 index = ctx - ohci->ir_context_list;
8a2f7d93
KH		 3069 match = (tags << 28) | (sync << 8) | ctx->base.channel;
3070 if (cycle >= 0) {
3071 match |= (cycle & 0x07fff) << 12;
3072 control |= IR_CONTEXT_CYCLE_MATCH_ENABLE;
3073 }
ed568912 3074
295e3feb
KH		 3075 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index);
3076 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index);
a77754a7 3077 reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match);
8a2f7d93 3078 context_run(&ctx->context, control);
dd23736e
ML		 3079
3080 ctx->sync = sync;
3081 ctx->tags = tags;
3082
872e330e 3083 break;
295e3feb 3084 }
ed568912
KH		 3085
3086 return 0;
3087}
3088
b8295668
KH		 3089static int ohci_stop_iso(struct fw_iso_context *base)
3090{
3091 struct fw_ohci *ohci = fw_ohci(base->card);
373b2edd 3092 struct iso_context *ctx = container_of(base, struct iso_context, base);
b8295668
KH		 3093 int index;
3094
872e330e
SR		 3095 switch (ctx->base.type) {
3096 case FW_ISO_CONTEXT_TRANSMIT:
b8295668
KH		 3097 index = ctx - ohci->it_context_list;
3098 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index);
872e330e
SR		 3099 break;
3100
3101 case FW_ISO_CONTEXT_RECEIVE:
3102 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
b8295668
KH		 3103 index = ctx - ohci->ir_context_list;
3104 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index);
872e330e 3105 break;
b8295668
KH		 3106 }
3107 flush_writes(ohci);
3108 context_stop(&ctx->context);
e81cbebd 3109 tasklet_kill(&ctx->context.tasklet);
b8295668
KH		 3110
3111 return 0;
3112}
3113
ed568912
KH		 3114static void ohci_free_iso_context(struct fw_iso_context *base)
3115{
3116 struct fw_ohci *ohci = fw_ohci(base->card);
373b2edd 3117 struct iso_context *ctx = container_of(base, struct iso_context, base);
ed568912
KH		 3118 unsigned long flags;
3119 int index;
3120
b8295668
KH		 3121 ohci_stop_iso(base);
3122 context_release(&ctx->context);
9b32d5f3 3123 free_page((unsigned long)ctx->header);
b8295668 3124
ed568912
KH		 3125 spin_lock_irqsave(&ohci->lock, flags);
3126
872e330e
SR		 3127 switch (base->type) {
3128 case FW_ISO_CONTEXT_TRANSMIT:
ed568912 3129 index = ctx - ohci->it_context_list;
ed568912 3130 ohci->it_context_mask |= 1 << index;
872e330e
SR		 3131 break;
3132
3133 case FW_ISO_CONTEXT_RECEIVE:
ed568912 3134 index = ctx - ohci->ir_context_list;
ed568912 3135 ohci->ir_context_mask |= 1 << index;
4817ed24 3136 ohci->ir_context_channels |= 1ULL << base->channel;
872e330e
SR		 3137 break;
3138
3139 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3140 index = ctx - ohci->ir_context_list;
3141 ohci->ir_context_mask |= 1 << index;
3142 ohci->ir_context_channels |= ohci->mc_channels;
3143 ohci->mc_channels = 0;
3144 ohci->mc_allocated = false;
3145 break;
ed568912 3146 }
ed568912
KH		 3147
3148 spin_unlock_irqrestore(&ohci->lock, flags);
3149}
3150
872e330e
SR		 3151static int ohci_set_iso_channels(struct fw_iso_context *base, u64 *channels)
3152{
3153 struct fw_ohci *ohci = fw_ohci(base->card);
3154 unsigned long flags;
3155 int ret;
3156
3157 switch (base->type) {
3158 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3159
3160 spin_lock_irqsave(&ohci->lock, flags);
3161
3162 /* Don't allow multichannel to grab other contexts' channels. */
3163 if (~ohci->ir_context_channels & ~ohci->mc_channels & *channels) {
3164 *channels = ohci->ir_context_channels;
3165 ret = -EBUSY;
3166 } else {
3167 set_multichannel_mask(ohci, *channels);
3168 ret = 0;
3169 }
3170
3171 spin_unlock_irqrestore(&ohci->lock, flags);
3172
3173 break;
3174 default:
3175 ret = -EINVAL;
3176 }
3177
3178 return ret;
3179}
3180
dd23736e
ML		 3181#ifdef CONFIG_PM
3182static void ohci_resume_iso_dma(struct fw_ohci *ohci)
3183{
3184 int i;
3185 struct iso_context *ctx;
3186
3187 for (i = 0 ; i < ohci->n_ir ; i++) {
3188 ctx = &ohci->ir_context_list[i];
693a50b5 3189 if (ctx->context.running)
dd23736e
ML		 3190 ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags);
3191 }
3192
3193 for (i = 0 ; i < ohci->n_it ; i++) {
3194 ctx = &ohci->it_context_list[i];
693a50b5 3195 if (ctx->context.running)
dd23736e
ML		 3196 ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags);
3197 }
3198}
3199#endif
3200
872e330e
SR		 3201static int queue_iso_transmit(struct iso_context *ctx,
3202 struct fw_iso_packet *packet,
3203 struct fw_iso_buffer *buffer,
3204 unsigned long payload)
ed568912 3205{
30200739 3206 struct descriptor *d, *last, *pd;
ed568912
KH		 3207 struct fw_iso_packet *p;
3208 __le32 *header;
9aad8125 3209 dma_addr_t d_bus, page_bus;
ed568912
KH		 3210 u32 z, header_z, payload_z, irq;
3211 u32 payload_index, payload_end_index, next_page_index;
30200739 3212 int page, end_page, i, length, offset;
ed568912 3213
ed568912 3214 p = packet;
9aad8125 3215 payload_index = payload;
ed568912
KH		 3216
3217 if (p->skip)
3218 z = 1;
3219 else
3220 z = 2;
3221 if (p->header_length > 0)
3222 z++;
3223
3224 /* Determine the first page the payload isn't contained in. */
3225 end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT;
3226 if (p->payload_length > 0)
3227 payload_z = end_page - (payload_index >> PAGE_SHIFT);
3228 else
3229 payload_z = 0;
3230
3231 z += payload_z;
3232
3233 /* Get header size in number of descriptors. */
2d826cc5 3234 header_z = DIV_ROUND_UP(p->header_length, sizeof(*d));
ed568912 3235
30200739
KH		 3236 d = context_get_descriptors(&ctx->context, z + header_z, &d_bus);
3237 if (d == NULL)
3238 return -ENOMEM;
ed568912
KH		 3239
3240 if (!p->skip) {
a77754a7 3241 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
ed568912 3242 d[0].req_count = cpu_to_le16(8);
7f51a100
CL		 3243 /*
3244 * Link the skip address to this descriptor itself. This causes
3245 * a context to skip a cycle whenever lost cycles or FIFO
3246 * overruns occur, without dropping the data. The application
3247 * should then decide whether this is an error condition or not.
3248 * FIXME: Make the context's cycle-lost behaviour configurable?
3249 */
3250 d[0].branch_address = cpu_to_le32(d_bus | z);
ed568912
KH		 3251
3252 header = (__le32 *) &d[1];
a77754a7
KH		 3253 header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) |
3254 IT_HEADER_TAG(p->tag) |
3255 IT_HEADER_TCODE(TCODE_STREAM_DATA) |
3256 IT_HEADER_CHANNEL(ctx->base.channel) |
3257 IT_HEADER_SPEED(ctx->base.speed));
ed568912 3258 header[1] =
a77754a7 3259 cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length +
ed568912
KH		 3260 p->payload_length));
3261 }
3262
3263 if (p->header_length > 0) {
3264 d[2].req_count = cpu_to_le16(p->header_length);
2d826cc5 3265 d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d));
ed568912
KH		 3266 memcpy(&d[z], p->header, p->header_length);
3267 }
3268
3269 pd = d + z - payload_z;
3270 payload_end_index = payload_index + p->payload_length;
3271 for (i = 0; i < payload_z; i++) {
3272 page = payload_index >> PAGE_SHIFT;
3273 offset = payload_index & ~PAGE_MASK;
3274 next_page_index = (page + 1) << PAGE_SHIFT;
3275 length =
3276 min(next_page_index, payload_end_index) - payload_index;
3277 pd[i].req_count = cpu_to_le16(length);
9aad8125
KH		 3278
3279 page_bus = page_private(buffer->pages[page]);
3280 pd[i].data_address = cpu_to_le32(page_bus + offset);
ed568912 3281
a572e688
CL		 3282 dma_sync_single_range_for_device(ctx->context.ohci->card.device,
3283 page_bus, offset, length,
3284 DMA_TO_DEVICE);
3285
ed568912
KH		 3286 payload_index += length;
3287 }
3288
ed568912 3289 if (p->interrupt)
a77754a7 3290 irq = DESCRIPTOR_IRQ_ALWAYS;
ed568912 3291 else
a77754a7 3292 irq = DESCRIPTOR_NO_IRQ;
ed568912 3293
30200739 3294 last = z == 2 ? d : d + z - 1;
a77754a7
KH		 3295 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
3296 DESCRIPTOR_STATUS |
3297 DESCRIPTOR_BRANCH_ALWAYS |
cbb59da7 3298 irq);
ed568912 3299
30200739 3300 context_append(&ctx->context, d, z, header_z);
ed568912
KH		 3301
3302 return 0;
3303}
373b2edd 3304
872e330e
SR		 3305static int queue_iso_packet_per_buffer(struct iso_context *ctx,
3306 struct fw_iso_packet *packet,
3307 struct fw_iso_buffer *buffer,
3308 unsigned long payload)
a186b4a6 3309{
a572e688 3310 struct device *device = ctx->context.ohci->card.device;
8c0c0cc2 3311 struct descriptor *d, *pd;
a186b4a6
JW		 3312 dma_addr_t d_bus, page_bus;
3313 u32 z, header_z, rest;
bcee893c
DM		 3314 int i, j, length;
3315 int page, offset, packet_count, header_size, payload_per_buffer;
a186b4a6
JW		 3316
3317 /*
1aa292bb
DM		 3318 * The OHCI controller puts the isochronous header and trailer in the
3319 * buffer, so we need at least 8 bytes.
a186b4a6 3320 */
872e330e 3321 packet_count = packet->header_length / ctx->base.header_size;
1aa292bb 3322 header_size = max(ctx->base.header_size, (size_t)8);
a186b4a6
JW		 3323
3324 /* Get header size in number of descriptors. */
3325 header_z = DIV_ROUND_UP(header_size, sizeof(*d));
3326 page = payload >> PAGE_SHIFT;
3327 offset = payload & ~PAGE_MASK;
872e330e 3328 payload_per_buffer = packet->payload_length / packet_count;
a186b4a6
JW		 3329
3330 for (i = 0; i < packet_count; i++) {
3331 /* d points to the header descriptor */
bcee893c 3332 z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1;
a186b4a6 3333 d = context_get_descriptors(&ctx->context,
bcee893c 3334 z + header_z, &d_bus);
a186b4a6
JW		 3335 if (d == NULL)
3336 return -ENOMEM;
3337
bcee893c
DM		 3338 d->control = cpu_to_le16(DESCRIPTOR_STATUS |
3339 DESCRIPTOR_INPUT_MORE);
872e330e 3340 if (packet->skip && i == 0)
bcee893c 3341 d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
a186b4a6
JW		 3342 d->req_count = cpu_to_le16(header_size);
3343 d->res_count = d->req_count;
bcee893c 3344 d->transfer_status = 0;
a186b4a6
JW		 3345 d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d)));
3346
bcee893c 3347 rest = payload_per_buffer;
8c0c0cc2 3348 pd = d;
bcee893c 3349 for (j = 1; j < z; j++) {
8c0c0cc2 3350 pd++;
bcee893c
DM		 3351 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
3352 DESCRIPTOR_INPUT_MORE);
3353
3354 if (offset + rest < PAGE_SIZE)
3355 length = rest;
3356 else
3357 length = PAGE_SIZE - offset;
3358 pd->req_count = cpu_to_le16(length);
3359 pd->res_count = pd->req_count;
3360 pd->transfer_status = 0;
3361
3362 page_bus = page_private(buffer->pages[page]);
3363 pd->data_address = cpu_to_le32(page_bus + offset);
3364
a572e688
CL		 3365 dma_sync_single_range_for_device(device, page_bus,
3366 offset, length,
3367 DMA_FROM_DEVICE);
3368
bcee893c
DM		 3369 offset = (offset + length) & ~PAGE_MASK;
3370 rest -= length;
3371 if (offset == 0)
3372 page++;
3373 }
a186b4a6
JW		 3374 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
3375 DESCRIPTOR_INPUT_LAST |
3376 DESCRIPTOR_BRANCH_ALWAYS);
872e330e 3377 if (packet->interrupt && i == packet_count - 1)
a186b4a6
JW		 3378 pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
3379
a186b4a6
JW		 3380 context_append(&ctx->context, d, z, header_z);
3381 }
3382
3383 return 0;
3384}
3385
872e330e
SR		 3386static int queue_iso_buffer_fill(struct iso_context *ctx,
3387 struct fw_iso_packet *packet,
3388 struct fw_iso_buffer *buffer,
3389 unsigned long payload)
3390{
3391 struct descriptor *d;
3392 dma_addr_t d_bus, page_bus;
3393 int page, offset, rest, z, i, length;
3394
3395 page = payload >> PAGE_SHIFT;
3396 offset = payload & ~PAGE_MASK;
3397 rest = packet->payload_length;
3398
3399 /* We need one descriptor for each page in the buffer. */
3400 z = DIV_ROUND_UP(offset + rest, PAGE_SIZE);
3401
3402 if (WARN_ON(offset & 3 || rest & 3 || page + z > buffer->page_count))
3403 return -EFAULT;
3404
3405 for (i = 0; i < z; i++) {
3406 d = context_get_descriptors(&ctx->context, 1, &d_bus);
3407 if (d == NULL)
3408 return -ENOMEM;
3409
3410 d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
3411 DESCRIPTOR_BRANCH_ALWAYS);
3412 if (packet->skip && i == 0)
3413 d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
3414 if (packet->interrupt && i == z - 1)
3415 d->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
3416
3417 if (offset + rest < PAGE_SIZE)
3418 length = rest;
3419 else
3420 length = PAGE_SIZE - offset;
3421 d->req_count = cpu_to_le16(length);
3422 d->res_count = d->req_count;
3423 d->transfer_status = 0;
3424
3425 page_bus = page_private(buffer->pages[page]);
3426 d->data_address = cpu_to_le32(page_bus + offset);
3427
a572e688
CL		 3428 dma_sync_single_range_for_device(ctx->context.ohci->card.device,
3429 page_bus, offset, length,
3430 DMA_FROM_DEVICE);
3431
872e330e
SR		 3432 rest -= length;
3433 offset = 0;
3434 page++;
3435
3436 context_append(&ctx->context, d, 1, 0);
3437 }
3438
3439 return 0;
3440}
3441
53dca511
SR		 3442static int ohci_queue_iso(struct fw_iso_context *base,
3443 struct fw_iso_packet *packet,
3444 struct fw_iso_buffer *buffer,
3445 unsigned long payload)
295e3feb 3446{
e364cf4e 3447 struct iso_context *ctx = container_of(base, struct iso_context, base);
fe5ca634 3448 unsigned long flags;
872e330e 3449 int ret = -ENOSYS;
e364cf4e 3450
fe5ca634 3451 spin_lock_irqsave(&ctx->context.ohci->lock, flags);
872e330e
SR		 3452 switch (base->type) {
3453 case FW_ISO_CONTEXT_TRANSMIT:
3454 ret = queue_iso_transmit(ctx, packet, buffer, payload);
3455 break;
3456 case FW_ISO_CONTEXT_RECEIVE:
3457 ret = queue_iso_packet_per_buffer(ctx, packet, buffer, payload);
3458 break;
3459 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3460 ret = queue_iso_buffer_fill(ctx, packet, buffer, payload);
3461 break;
3462 }
fe5ca634
DM		 3463 spin_unlock_irqrestore(&ctx->context.ohci->lock, flags);
3464
2dbd7d7e 3465 return ret;
295e3feb
KH		 3466}
3467
13882a82
CL		 3468static void ohci_flush_queue_iso(struct fw_iso_context *base)
3469{
3470 struct context *ctx =
3471 &container_of(base, struct iso_context, base)->context;
3472
3473 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
13882a82
CL		 3474}
3475
d1bbd209
CL		 3476static int ohci_flush_iso_completions(struct fw_iso_context *base)
3477{
3478 struct iso_context *ctx = container_of(base, struct iso_context, base);
3479 int ret = 0;
3480
3481 tasklet_disable(&ctx->context.tasklet);
3482
3483 if (!test_and_set_bit_lock(0, &ctx->flushing_completions)) {
3484 context_tasklet((unsigned long)&ctx->context);
3485
3486 switch (base->type) {
3487 case FW_ISO_CONTEXT_TRANSMIT:
3488 case FW_ISO_CONTEXT_RECEIVE:
3489 if (ctx->header_length != 0)
3490 flush_iso_completions(ctx);
3491 break;
3492 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3493 if (ctx->mc_completed != 0)
3494 flush_ir_buffer_fill(ctx);
3495 break;
3496 default:
3497 ret = -ENOSYS;
3498 }
3499
3500 clear_bit_unlock(0, &ctx->flushing_completions);
4e857c58 3501 smp_mb__after_atomic();
d1bbd209
CL		 3502 }
3503
3504 tasklet_enable(&ctx->context.tasklet);
3505
3506 return ret;
3507}
3508
21ebcd12 3509static const struct fw_card_driver ohci_driver = {
ed568912 3510 .enable = ohci_enable,
02d37bed 3511 .read_phy_reg = ohci_read_phy_reg,
ed568912
KH		 3512 .update_phy_reg = ohci_update_phy_reg,
3513 .set_config_rom = ohci_set_config_rom,
3514 .send_request = ohci_send_request,
3515 .send_response = ohci_send_response,
730c32f5 3516 .cancel_packet = ohci_cancel_packet,
ed568912 3517 .enable_phys_dma = ohci_enable_phys_dma,
0fcff4e3
SR		 3518 .read_csr = ohci_read_csr,
3519 .write_csr = ohci_write_csr,
ed568912
KH		 3520
3521 .allocate_iso_context = ohci_allocate_iso_context,
3522 .free_iso_context = ohci_free_iso_context,
872e330e 3523 .set_iso_channels = ohci_set_iso_channels,
ed568912 3524 .queue_iso = ohci_queue_iso,
13882a82 3525 .flush_queue_iso = ohci_flush_queue_iso,
d1bbd209 3526 .flush_iso_completions = ohci_flush_iso_completions,
69cdb726 3527 .start_iso = ohci_start_iso,
b8295668 3528 .stop_iso = ohci_stop_iso,
ed568912
KH		 3529};
3530
ea8d006b 3531#ifdef CONFIG_PPC_PMAC
5da3dac8 3532static void pmac_ohci_on(struct pci_dev *dev)
2ed0f181 3533{
ea8d006b
SR		 3534 if (machine_is(powermac)) {
3535 struct device_node *ofn = pci_device_to_OF_node(dev);
3536
3537 if (ofn) {
3538 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1);
3539 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1);
3540 }
3541 }
2ed0f181
SR		 3542}
3543
5da3dac8 3544static void pmac_ohci_off(struct pci_dev *dev)
2ed0f181
SR		 3545{
3546 if (machine_is(powermac)) {
3547 struct device_node *ofn = pci_device_to_OF_node(dev);
3548
3549 if (ofn) {
3550 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0);
3551 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0);
3552 }
3553 }
3554}
3555#else
5da3dac8
SR		 3556static inline void pmac_ohci_on(struct pci_dev *dev) {}
3557static inline void pmac_ohci_off(struct pci_dev *dev) {}
ea8d006b
SR		 3558#endif /* CONFIG_PPC_PMAC */
3559
03f94c0f 3560static int pci_probe(struct pci_dev *dev,
53dca511 3561 const struct pci_device_id *ent)
2ed0f181
SR		 3562{
3563 struct fw_ohci *ohci;
aa0170ff 3564 u32 bus_options, max_receive, link_speed, version;
2ed0f181 3565 u64 guid;
dd23736e 3566 int i, err;
2ed0f181
SR		 3567 size_t size;
3568
7f7e3711
SR		 3569 if (dev->vendor == PCI_VENDOR_ID_PINNACLE_SYSTEMS) {
3570 dev_err(&dev->dev, "Pinnacle MovieBoard is not yet supported\n");
3571 return -ENOSYS;
3572 }
3573
2d826cc5 3574 ohci = kzalloc(sizeof(*ohci), GFP_KERNEL);
ed568912 3575 if (ohci == NULL) {
7007a076
SR		 3576 err = -ENOMEM;
3577 goto fail;
ed568912
KH		 3578 }
3579
3580 fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev);
3581
5da3dac8 3582 pmac_ohci_on(dev);
130d5496 3583
d79406dd
KH		 3584 err = pci_enable_device(dev);
3585 if (err) {
64d21720 3586 dev_err(&dev->dev, "failed to enable OHCI hardware\n");
bd7dee63 3587 goto fail_free;
ed568912
KH		 3588 }
3589
3590 pci_set_master(dev);
3591 pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0);
3592 pci_set_drvdata(dev, ohci);
3593
3594 spin_lock_init(&ohci->lock);
02d37bed 3595 mutex_init(&ohci->phy_reg_mutex);
ed568912 3596
2d7a36e2 3597 INIT_WORK(&ohci->bus_reset_work, bus_reset_work);
ed568912 3598
7baab9ac
CL		 3599 if (!(pci_resource_flags(dev, 0) & IORESOURCE_MEM) ||
3600 pci_resource_len(dev, 0) < OHCI1394_REGISTER_SIZE) {
de97cb64 3601 ohci_err(ohci, "invalid MMIO resource\n");
7baab9ac
CL		 3602 err = -ENXIO;
3603 goto fail_disable;
3604 }
3605
d79406dd
KH		 3606 err = pci_request_region(dev, 0, ohci_driver_name);
3607 if (err) {
de97cb64 3608 ohci_err(ohci, "MMIO resource unavailable\n");
d79406dd 3609 goto fail_disable;
ed568912
KH		 3610 }
3611
3612 ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE);
3613 if (ohci->registers == NULL) {
de97cb64 3614 ohci_err(ohci, "failed to remap registers\n");
d79406dd
KH		 3615 err = -ENXIO;
3616 goto fail_iomem;
ed568912
KH		 3617 }
3618
4a635593 3619 for (i = 0; i < ARRAY_SIZE(ohci_quirks); i++)
9993e0fe
SR		 3620 if ((ohci_quirks[i].vendor == dev->vendor) &&
3621 (ohci_quirks[i].device == (unsigned short)PCI_ANY_ID ||
3622 ohci_quirks[i].device == dev->device) &&
3623 (ohci_quirks[i].revision == (unsigned short)PCI_ANY_ID ||
3624 ohci_quirks[i].revision >= dev->revision)) {
4a635593
SR		 3625 ohci->quirks = ohci_quirks[i].flags;
3626 break;
3627 }
3e9cc2f3
SR		 3628 if (param_quirks)
3629 ohci->quirks = param_quirks;
b677532b 3630
ec766a79
CL		 3631 /*
3632 * Because dma_alloc_coherent() allocates at least one page,
3633 * we save space by using a common buffer for the AR request/
3634 * response descriptors and the self IDs buffer.
3635 */
3636 BUILD_BUG_ON(AR_BUFFERS * sizeof(struct descriptor) > PAGE_SIZE/4);
3637 BUILD_BUG_ON(SELF_ID_BUF_SIZE > PAGE_SIZE/2);
3638 ohci->misc_buffer = dma_alloc_coherent(ohci->card.device,
3639 PAGE_SIZE,
3640 &ohci->misc_buffer_bus,
3641 GFP_KERNEL);
3642 if (!ohci->misc_buffer) {
3643 err = -ENOMEM;
3644 goto fail_iounmap;
3645 }
3646
3647 err = ar_context_init(&ohci->ar_request_ctx, ohci, 0,
7a39d8b8
CL		 3648 OHCI1394_AsReqRcvContextControlSet);
3649 if (err < 0)
ec766a79 3650 goto fail_misc_buf;
ed568912 3651
ec766a79 3652 err = ar_context_init(&ohci->ar_response_ctx, ohci, PAGE_SIZE/4,
7a39d8b8
CL		 3653 OHCI1394_AsRspRcvContextControlSet);
3654 if (err < 0)
3655 goto fail_arreq_ctx;
ed568912 3656
c088ab30
CL		 3657 err = context_init(&ohci->at_request_ctx, ohci,
3658 OHCI1394_AsReqTrContextControlSet, handle_at_packet);
3659 if (err < 0)
3660 goto fail_arrsp_ctx;
ed568912 3661
c088ab30
CL		 3662 err = context_init(&ohci->at_response_ctx, ohci,
3663 OHCI1394_AsRspTrContextControlSet, handle_at_packet);
3664 if (err < 0)
3665 goto fail_atreq_ctx;
ed568912 3666
ed568912 3667 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0);
4802f16d 3668 ohci->ir_context_channels = ~0ULL;
f117a3e3 3669 ohci->ir_context_support = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet);
ed568912 3670 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0);
f117a3e3 3671 ohci->ir_context_mask = ohci->ir_context_support;
dd23736e
ML		 3672 ohci->n_ir = hweight32(ohci->ir_context_mask);
3673 size = sizeof(struct iso_context) * ohci->n_ir;
4802f16d 3674 ohci->ir_context_list = kzalloc(size, GFP_KERNEL);
ed568912
KH		 3675
3676 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0);
f117a3e3 3677 ohci->it_context_support = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet);
100ceb66
SR		 3678 /* JMicron JMB38x often shows 0 at first read, just ignore it */
3679 if (!ohci->it_context_support) {
3680 ohci_notice(ohci, "overriding IsoXmitIntMask\n");
3681 ohci->it_context_support = 0xf;
3682 }
ed568912 3683 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0);
f117a3e3 3684 ohci->it_context_mask = ohci->it_context_support;
dd23736e
ML		 3685 ohci->n_it = hweight32(ohci->it_context_mask);
3686 size = sizeof(struct iso_context) * ohci->n_it;
4802f16d 3687 ohci->it_context_list = kzalloc(size, GFP_KERNEL);
ed568912
KH		 3688
3689 if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) {
d79406dd 3690 err = -ENOMEM;
7007a076 3691 goto fail_contexts;
ed568912
KH		 3692 }
3693
af53122a 3694 ohci->self_id = ohci->misc_buffer + PAGE_SIZE/2;
ec766a79 3695 ohci->self_id_bus = ohci->misc_buffer_bus + PAGE_SIZE/2;
ed568912 3696
ed568912
KH		 3697 bus_options = reg_read(ohci, OHCI1394_BusOptions);
3698 max_receive = (bus_options >> 12) & 0xf;
3699 link_speed = bus_options & 0x7;
3700 guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) |
3701 reg_read(ohci, OHCI1394_GUIDLo);
3702
247fd50b
PH		 3703 if (!(ohci->quirks & QUIRK_NO_MSI))
3704 pci_enable_msi(dev);
3705 if (request_irq(dev->irq, irq_handler,
3706 pci_dev_msi_enabled(dev) ? 0 : IRQF_SHARED,
3707 ohci_driver_name, ohci)) {
de97cb64 3708 ohci_err(ohci, "failed to allocate interrupt %d\n", dev->irq);
247fd50b
PH		 3709 err = -EIO;
3710 goto fail_msi;
3711 }
3712
d79406dd 3713 err = fw_card_add(&ohci->card, max_receive, link_speed, guid);
e1eff7a3 3714 if (err)
247fd50b 3715 goto fail_irq;
ed568912 3716
6fdb2ee2 3717 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
de97cb64
PH		 3718 ohci_notice(ohci,
3719 "added OHCI v%x.%x device as card %d, "
fcd46b34 3720 "%d IR + %d IT contexts, quirks 0x%x%s\n",
de97cb64 3721 version >> 16, version & 0xff, ohci->card.index,
fcd46b34
SR		 3722 ohci->n_ir, ohci->n_it, ohci->quirks,
3723 reg_read(ohci, OHCI1394_PhyUpperBound) ?
2fe2023a 3724 ", physUB" : "");
e1eff7a3 3725
ed568912 3726 return 0;
d79406dd 3727
247fd50b
PH		 3728 fail_irq:
3729 free_irq(dev->irq, ohci);
3730 fail_msi:
3731 pci_disable_msi(dev);
7007a076 3732 fail_contexts:
d79406dd 3733 kfree(ohci->ir_context_list);
7007a076
SR		 3734 kfree(ohci->it_context_list);
3735 context_release(&ohci->at_response_ctx);
c088ab30 3736 fail_atreq_ctx:
7007a076 3737 context_release(&ohci->at_request_ctx);
c088ab30 3738 fail_arrsp_ctx:
7007a076 3739 ar_context_release(&ohci->ar_response_ctx);
7a39d8b8 3740 fail_arreq_ctx:
7007a076 3741 ar_context_release(&ohci->ar_request_ctx);
ec766a79
CL		 3742 fail_misc_buf:
3743 dma_free_coherent(ohci->card.device, PAGE_SIZE,
3744 ohci->misc_buffer, ohci->misc_buffer_bus);
7a39d8b8 3745 fail_iounmap:
d79406dd
KH		 3746 pci_iounmap(dev, ohci->registers);
3747 fail_iomem:
3748 pci_release_region(dev, 0);
3749 fail_disable:
3750 pci_disable_device(dev);
bd7dee63 3751 fail_free:
d838d2c0 3752 kfree(ohci);
5da3dac8 3753 pmac_ohci_off(dev);
7007a076 3754 fail:
d79406dd 3755 return err;
ed568912
KH		 3756}
3757
3758static void pci_remove(struct pci_dev *dev)
3759{
8db49149 3760 struct fw_ohci *ohci = pci_get_drvdata(dev);
ed568912 3761
8db49149
PH		 3762 /*
3763 * If the removal is happening from the suspend state, LPS won't be
3764 * enabled and host registers (eg., IntMaskClear) won't be accessible.
3765 */
3766 if (reg_read(ohci, OHCI1394_HCControlSet) & OHCI1394_HCControl_LPS) {
3767 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
3768 flush_writes(ohci);
3769 }
2d7a36e2 3770 cancel_work_sync(&ohci->bus_reset_work);
ed568912
KH		 3771 fw_core_remove_card(&ohci->card);
3772
c781c06d
KH		 3773 /*
3774 * FIXME: Fail all pending packets here, now that the upper
3775 * layers can't queue any more.
3776 */
ed568912
KH		 3777
3778 software_reset(ohci);
3779 free_irq(dev->irq, ohci);
a55709ba
JF		 3780
3781 if (ohci->next_config_rom && ohci->next_config_rom != ohci->config_rom)
3782 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
3783 ohci->next_config_rom, ohci->next_config_rom_bus);
3784 if (ohci->config_rom)
3785 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
3786 ohci->config_rom, ohci->config_rom_bus);
a55709ba
JF		 3787 ar_context_release(&ohci->ar_request_ctx);
3788 ar_context_release(&ohci->ar_response_ctx);
ec766a79
CL		 3789 dma_free_coherent(ohci->card.device, PAGE_SIZE,
3790 ohci->misc_buffer, ohci->misc_buffer_bus);
a55709ba
JF		 3791 context_release(&ohci->at_request_ctx);
3792 context_release(&ohci->at_response_ctx);
d79406dd
KH		 3793 kfree(ohci->it_context_list);
3794 kfree(ohci->ir_context_list);
262444ee 3795 pci_disable_msi(dev);
d79406dd
KH		 3796 pci_iounmap(dev, ohci->registers);
3797 pci_release_region(dev, 0);
3798 pci_disable_device(dev);
d838d2c0 3799 kfree(ohci);
5da3dac8 3800 pmac_ohci_off(dev);
ea8d006b 3801
64d21720 3802 dev_notice(&dev->dev, "removed fw-ohci device\n");
ed568912
KH		 3803}
3804
2aef469a 3805#ifdef CONFIG_PM
2ed0f181 3806static int pci_suspend(struct pci_dev *dev, pm_message_t state)
2aef469a 3807{
2ed0f181 3808 struct fw_ohci *ohci = pci_get_drvdata(dev);
2aef469a
KH		 3809 int err;
3810
3811 software_reset(ohci);
2ed0f181 3812 err = pci_save_state(dev);
2aef469a 3813 if (err) {
de97cb64 3814 ohci_err(ohci, "pci_save_state failed\n");
2aef469a
KH		 3815 return err;
3816 }
2ed0f181 3817 err = pci_set_power_state(dev, pci_choose_state(dev, state));
55111428 3818 if (err)
de97cb64 3819 ohci_err(ohci, "pci_set_power_state failed with %d\n", err);
5da3dac8 3820 pmac_ohci_off(dev);
ea8d006b 3821
2aef469a
KH		 3822 return 0;
3823}
3824
2ed0f181 3825static int pci_resume(struct pci_dev *dev)
2aef469a 3826{
2ed0f181 3827 struct fw_ohci *ohci = pci_get_drvdata(dev);
2aef469a
KH		 3828 int err;
3829
5da3dac8 3830 pmac_ohci_on(dev);
2ed0f181
SR		 3831 pci_set_power_state(dev, PCI_D0);
3832 pci_restore_state(dev);
3833 err = pci_enable_device(dev);
2aef469a 3834 if (err) {
de97cb64 3835 ohci_err(ohci, "pci_enable_device failed\n");
2aef469a
KH		 3836 return err;
3837 }
3838
8662b6b0
ML		 3839 /* Some systems don't setup GUID register on resume from ram */
3840 if (!reg_read(ohci, OHCI1394_GUIDLo) &&
3841 !reg_read(ohci, OHCI1394_GUIDHi)) {
3842 reg_write(ohci, OHCI1394_GUIDLo, (u32)ohci->card.guid);
3843 reg_write(ohci, OHCI1394_GUIDHi, (u32)(ohci->card.guid >> 32));
3844 }
3845
dd23736e 3846 err = ohci_enable(&ohci->card, NULL, 0);
dd23736e
ML		 3847 if (err)
3848 return err;
3849
3850 ohci_resume_iso_dma(ohci);
693a50b5 3851
dd23736e 3852 return 0;
2aef469a
KH		 3853}
3854#endif
3855
a67483d2 3856static const struct pci_device_id pci_table[] = {
ed568912
KH		 3857 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) },
3858 { }
3859};
3860
3861MODULE_DEVICE_TABLE(pci, pci_table);
3862
3863static struct pci_driver fw_ohci_pci_driver = {
3864 .name = ohci_driver_name,
3865 .id_table = pci_table,
3866 .probe = pci_probe,
3867 .remove = pci_remove,
2aef469a
KH		 3868#ifdef CONFIG_PM
3869 .resume = pci_resume,
3870 .suspend = pci_suspend,
3871#endif
ed568912
KH		 3872};
3873
7a723c6e
SG		 3874static int __init fw_ohci_init(void)
3875{
db9ae8fe
SG		 3876 selfid_workqueue = alloc_workqueue(KBUILD_MODNAME, WQ_MEM_RECLAIM, 0);
3877 if (!selfid_workqueue)
3878 return -ENOMEM;
3879
7a723c6e
SG		 3880 return pci_register_driver(&fw_ohci_pci_driver);
3881}
3882
3883static void __exit fw_ohci_cleanup(void)
3884{
3885 pci_unregister_driver(&fw_ohci_pci_driver);
db9ae8fe 3886 destroy_workqueue(selfid_workqueue);
7a723c6e
SG		 3887}
3888
3889module_init(fw_ohci_init);
3890module_exit(fw_ohci_cleanup);
fe2af11c 3891
ed568912
KH		 3892MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
3893MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
3894MODULE_LICENSE("GPL");
3895
1e4c7b0d 3896/* Provide a module alias so root-on-sbp2 initrds don't break. */
1e4c7b0d 3897MODULE_ALIAS("ohci1394");
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