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Commit | Line | Data |
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c781c06d KH |
1 | /* |
2 | * Driver for OHCI 1394 controllers | |
ed568912 | 3 | * |
ed568912 KH |
4 | * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net> |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software Foundation, | |
18 | * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
19 | */ | |
20 | ||
65b2742a | 21 | #include <linux/bug.h> |
e524f616 | 22 | #include <linux/compiler.h> |
ed568912 | 23 | #include <linux/delay.h> |
e8ca9702 | 24 | #include <linux/device.h> |
cf3e72fd | 25 | #include <linux/dma-mapping.h> |
77c9a5da | 26 | #include <linux/firewire.h> |
e8ca9702 | 27 | #include <linux/firewire-constants.h> |
c26f0234 | 28 | #include <linux/gfp.h> |
a7fb60db SR |
29 | #include <linux/init.h> |
30 | #include <linux/interrupt.h> | |
e8ca9702 | 31 | #include <linux/io.h> |
a7fb60db | 32 | #include <linux/kernel.h> |
e8ca9702 | 33 | #include <linux/list.h> |
faa2fb4e | 34 | #include <linux/mm.h> |
a7fb60db | 35 | #include <linux/module.h> |
ad3c0fe8 | 36 | #include <linux/moduleparam.h> |
a7fb60db | 37 | #include <linux/pci.h> |
fc383796 | 38 | #include <linux/pci_ids.h> |
c26f0234 | 39 | #include <linux/spinlock.h> |
e8ca9702 | 40 | #include <linux/string.h> |
cf3e72fd | 41 | |
e8ca9702 | 42 | #include <asm/byteorder.h> |
c26f0234 | 43 | #include <asm/page.h> |
ee71c2f9 | 44 | #include <asm/system.h> |
ed568912 | 45 | |
ea8d006b SR |
46 | #ifdef CONFIG_PPC_PMAC |
47 | #include <asm/pmac_feature.h> | |
48 | #endif | |
49 | ||
77c9a5da SR |
50 | #include "core.h" |
51 | #include "ohci.h" | |
ed568912 | 52 | |
a77754a7 KH |
53 | #define DESCRIPTOR_OUTPUT_MORE 0 |
54 | #define DESCRIPTOR_OUTPUT_LAST (1 << 12) | |
55 | #define DESCRIPTOR_INPUT_MORE (2 << 12) | |
56 | #define DESCRIPTOR_INPUT_LAST (3 << 12) | |
57 | #define DESCRIPTOR_STATUS (1 << 11) | |
58 | #define DESCRIPTOR_KEY_IMMEDIATE (2 << 8) | |
59 | #define DESCRIPTOR_PING (1 << 7) | |
60 | #define DESCRIPTOR_YY (1 << 6) | |
61 | #define DESCRIPTOR_NO_IRQ (0 << 4) | |
62 | #define DESCRIPTOR_IRQ_ERROR (1 << 4) | |
63 | #define DESCRIPTOR_IRQ_ALWAYS (3 << 4) | |
64 | #define DESCRIPTOR_BRANCH_ALWAYS (3 << 2) | |
65 | #define DESCRIPTOR_WAIT (3 << 0) | |
ed568912 KH |
66 | |
67 | struct descriptor { | |
68 | __le16 req_count; | |
69 | __le16 control; | |
70 | __le32 data_address; | |
71 | __le32 branch_address; | |
72 | __le16 res_count; | |
73 | __le16 transfer_status; | |
74 | } __attribute__((aligned(16))); | |
75 | ||
a77754a7 KH |
76 | #define CONTROL_SET(regs) (regs) |
77 | #define CONTROL_CLEAR(regs) ((regs) + 4) | |
78 | #define COMMAND_PTR(regs) ((regs) + 12) | |
79 | #define CONTEXT_MATCH(regs) ((regs) + 16) | |
72e318e0 | 80 | |
32b46093 | 81 | struct ar_buffer { |
ed568912 | 82 | struct descriptor descriptor; |
32b46093 KH |
83 | struct ar_buffer *next; |
84 | __le32 data[0]; | |
85 | }; | |
ed568912 | 86 | |
32b46093 KH |
87 | struct ar_context { |
88 | struct fw_ohci *ohci; | |
89 | struct ar_buffer *current_buffer; | |
90 | struct ar_buffer *last_buffer; | |
91 | void *pointer; | |
72e318e0 | 92 | u32 regs; |
ed568912 KH |
93 | struct tasklet_struct tasklet; |
94 | }; | |
95 | ||
30200739 KH |
96 | struct context; |
97 | ||
98 | typedef int (*descriptor_callback_t)(struct context *ctx, | |
99 | struct descriptor *d, | |
100 | struct descriptor *last); | |
fe5ca634 DM |
101 | |
102 | /* | |
103 | * A buffer that contains a block of DMA-able coherent memory used for | |
104 | * storing a portion of a DMA descriptor program. | |
105 | */ | |
106 | struct descriptor_buffer { | |
107 | struct list_head list; | |
108 | dma_addr_t buffer_bus; | |
109 | size_t buffer_size; | |
110 | size_t used; | |
111 | struct descriptor buffer[0]; | |
112 | }; | |
113 | ||
30200739 | 114 | struct context { |
373b2edd | 115 | struct fw_ohci *ohci; |
30200739 | 116 | u32 regs; |
fe5ca634 | 117 | int total_allocation; |
373b2edd | 118 | |
fe5ca634 DM |
119 | /* |
120 | * List of page-sized buffers for storing DMA descriptors. | |
121 | * Head of list contains buffers in use and tail of list contains | |
122 | * free buffers. | |
123 | */ | |
124 | struct list_head buffer_list; | |
125 | ||
126 | /* | |
127 | * Pointer to a buffer inside buffer_list that contains the tail | |
128 | * end of the current DMA program. | |
129 | */ | |
130 | struct descriptor_buffer *buffer_tail; | |
131 | ||
132 | /* | |
133 | * The descriptor containing the branch address of the first | |
134 | * descriptor that has not yet been filled by the device. | |
135 | */ | |
136 | struct descriptor *last; | |
137 | ||
138 | /* | |
139 | * The last descriptor in the DMA program. It contains the branch | |
140 | * address that must be updated upon appending a new descriptor. | |
141 | */ | |
142 | struct descriptor *prev; | |
30200739 KH |
143 | |
144 | descriptor_callback_t callback; | |
145 | ||
373b2edd | 146 | struct tasklet_struct tasklet; |
30200739 | 147 | }; |
30200739 | 148 | |
a77754a7 KH |
149 | #define IT_HEADER_SY(v) ((v) << 0) |
150 | #define IT_HEADER_TCODE(v) ((v) << 4) | |
151 | #define IT_HEADER_CHANNEL(v) ((v) << 8) | |
152 | #define IT_HEADER_TAG(v) ((v) << 14) | |
153 | #define IT_HEADER_SPEED(v) ((v) << 16) | |
154 | #define IT_HEADER_DATA_LENGTH(v) ((v) << 16) | |
ed568912 KH |
155 | |
156 | struct iso_context { | |
157 | struct fw_iso_context base; | |
30200739 | 158 | struct context context; |
0642b657 | 159 | int excess_bytes; |
9b32d5f3 KH |
160 | void *header; |
161 | size_t header_length; | |
ed568912 KH |
162 | }; |
163 | ||
164 | #define CONFIG_ROM_SIZE 1024 | |
165 | ||
166 | struct fw_ohci { | |
167 | struct fw_card card; | |
168 | ||
169 | __iomem char *registers; | |
e636fe25 | 170 | int node_id; |
ed568912 | 171 | int generation; |
e09770db | 172 | int request_generation; /* for timestamping incoming requests */ |
4a635593 | 173 | unsigned quirks; |
a1a1132b | 174 | unsigned int pri_req_max; |
a48777e0 | 175 | u32 bus_time; |
4ffb7a6a | 176 | bool is_root; |
c8a94ded | 177 | bool csr_state_setclear_abdicate; |
ed568912 | 178 | |
c781c06d KH |
179 | /* |
180 | * Spinlock for accessing fw_ohci data. Never call out of | |
181 | * this driver with this lock held. | |
182 | */ | |
ed568912 | 183 | spinlock_t lock; |
ed568912 KH |
184 | |
185 | struct ar_context ar_request_ctx; | |
186 | struct ar_context ar_response_ctx; | |
f319b6a0 KH |
187 | struct context at_request_ctx; |
188 | struct context at_response_ctx; | |
ed568912 KH |
189 | |
190 | u32 it_context_mask; | |
191 | struct iso_context *it_context_list; | |
4817ed24 | 192 | u64 ir_context_channels; |
ed568912 KH |
193 | u32 ir_context_mask; |
194 | struct iso_context *ir_context_list; | |
ecb1cf9c SR |
195 | |
196 | __be32 *config_rom; | |
197 | dma_addr_t config_rom_bus; | |
198 | __be32 *next_config_rom; | |
199 | dma_addr_t next_config_rom_bus; | |
200 | __be32 next_header; | |
201 | ||
202 | __le32 *self_id_cpu; | |
203 | dma_addr_t self_id_bus; | |
204 | struct tasklet_struct bus_reset_tasklet; | |
205 | ||
206 | u32 self_id_buffer[512]; | |
ed568912 KH |
207 | }; |
208 | ||
95688e97 | 209 | static inline struct fw_ohci *fw_ohci(struct fw_card *card) |
ed568912 KH |
210 | { |
211 | return container_of(card, struct fw_ohci, card); | |
212 | } | |
213 | ||
295e3feb KH |
214 | #define IT_CONTEXT_CYCLE_MATCH_ENABLE 0x80000000 |
215 | #define IR_CONTEXT_BUFFER_FILL 0x80000000 | |
216 | #define IR_CONTEXT_ISOCH_HEADER 0x40000000 | |
217 | #define IR_CONTEXT_CYCLE_MATCH_ENABLE 0x20000000 | |
218 | #define IR_CONTEXT_MULTI_CHANNEL_MODE 0x10000000 | |
219 | #define IR_CONTEXT_DUAL_BUFFER_MODE 0x08000000 | |
ed568912 KH |
220 | |
221 | #define CONTEXT_RUN 0x8000 | |
222 | #define CONTEXT_WAKE 0x1000 | |
223 | #define CONTEXT_DEAD 0x0800 | |
224 | #define CONTEXT_ACTIVE 0x0400 | |
225 | ||
8b7b6afa | 226 | #define OHCI1394_MAX_AT_REQ_RETRIES 0xf |
ed568912 KH |
227 | #define OHCI1394_MAX_AT_RESP_RETRIES 0x2 |
228 | #define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8 | |
229 | ||
ed568912 KH |
230 | #define OHCI1394_REGISTER_SIZE 0x800 |
231 | #define OHCI_LOOP_COUNT 500 | |
232 | #define OHCI1394_PCI_HCI_Control 0x40 | |
233 | #define SELF_ID_BUF_SIZE 0x800 | |
32b46093 | 234 | #define OHCI_TCODE_PHY_PACKET 0x0e |
e364cf4e | 235 | #define OHCI_VERSION_1_1 0x010010 |
0edeefd9 | 236 | |
ed568912 KH |
237 | static char ohci_driver_name[] = KBUILD_MODNAME; |
238 | ||
262444ee | 239 | #define PCI_DEVICE_ID_JMICRON_JMB38X_FW 0x2380 |
8301b91b CL |
240 | #define PCI_DEVICE_ID_TI_TSB12LV22 0x8009 |
241 | ||
4a635593 SR |
242 | #define QUIRK_CYCLE_TIMER 1 |
243 | #define QUIRK_RESET_PACKET 2 | |
244 | #define QUIRK_BE_HEADERS 4 | |
925e7a65 | 245 | #define QUIRK_NO_1394A 8 |
262444ee | 246 | #define QUIRK_NO_MSI 16 |
4a635593 SR |
247 | |
248 | /* In case of multiple matches in ohci_quirks[], only the first one is used. */ | |
249 | static const struct { | |
250 | unsigned short vendor, device, flags; | |
251 | } ohci_quirks[] = { | |
8301b91b | 252 | {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV22, QUIRK_CYCLE_TIMER | |
925e7a65 CL |
253 | QUIRK_RESET_PACKET | |
254 | QUIRK_NO_1394A}, | |
4a635593 SR |
255 | {PCI_VENDOR_ID_TI, PCI_ANY_ID, QUIRK_RESET_PACKET}, |
256 | {PCI_VENDOR_ID_AL, PCI_ANY_ID, QUIRK_CYCLE_TIMER}, | |
262444ee | 257 | {PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB38X_FW, QUIRK_NO_MSI}, |
4a635593 SR |
258 | {PCI_VENDOR_ID_NEC, PCI_ANY_ID, QUIRK_CYCLE_TIMER}, |
259 | {PCI_VENDOR_ID_VIA, PCI_ANY_ID, QUIRK_CYCLE_TIMER}, | |
260 | {PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_FW, QUIRK_BE_HEADERS}, | |
261 | }; | |
262 | ||
3e9cc2f3 SR |
263 | /* This overrides anything that was found in ohci_quirks[]. */ |
264 | static int param_quirks; | |
265 | module_param_named(quirks, param_quirks, int, 0644); | |
266 | MODULE_PARM_DESC(quirks, "Chip quirks (default = 0" | |
267 | ", nonatomic cycle timer = " __stringify(QUIRK_CYCLE_TIMER) | |
268 | ", reset packet generation = " __stringify(QUIRK_RESET_PACKET) | |
269 | ", AR/selfID endianess = " __stringify(QUIRK_BE_HEADERS) | |
925e7a65 | 270 | ", no 1394a enhancements = " __stringify(QUIRK_NO_1394A) |
262444ee | 271 | ", disable MSI = " __stringify(QUIRK_NO_MSI) |
3e9cc2f3 SR |
272 | ")"); |
273 | ||
a007bb85 | 274 | #define OHCI_PARAM_DEBUG_AT_AR 1 |
ad3c0fe8 | 275 | #define OHCI_PARAM_DEBUG_SELFIDS 2 |
a007bb85 SR |
276 | #define OHCI_PARAM_DEBUG_IRQS 4 |
277 | #define OHCI_PARAM_DEBUG_BUSRESETS 8 /* only effective before chip init */ | |
ad3c0fe8 | 278 | |
5da3dac8 SR |
279 | #ifdef CONFIG_FIREWIRE_OHCI_DEBUG |
280 | ||
ad3c0fe8 SR |
281 | static int param_debug; |
282 | module_param_named(debug, param_debug, int, 0644); | |
283 | MODULE_PARM_DESC(debug, "Verbose logging (default = 0" | |
ad3c0fe8 | 284 | ", AT/AR events = " __stringify(OHCI_PARAM_DEBUG_AT_AR) |
a007bb85 SR |
285 | ", self-IDs = " __stringify(OHCI_PARAM_DEBUG_SELFIDS) |
286 | ", IRQs = " __stringify(OHCI_PARAM_DEBUG_IRQS) | |
287 | ", busReset events = " __stringify(OHCI_PARAM_DEBUG_BUSRESETS) | |
ad3c0fe8 SR |
288 | ", or a combination, or all = -1)"); |
289 | ||
290 | static void log_irqs(u32 evt) | |
291 | { | |
a007bb85 SR |
292 | if (likely(!(param_debug & |
293 | (OHCI_PARAM_DEBUG_IRQS | OHCI_PARAM_DEBUG_BUSRESETS)))) | |
294 | return; | |
295 | ||
296 | if (!(param_debug & OHCI_PARAM_DEBUG_IRQS) && | |
297 | !(evt & OHCI1394_busReset)) | |
ad3c0fe8 SR |
298 | return; |
299 | ||
a48777e0 | 300 | fw_notify("IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt, |
161b96e7 SR |
301 | evt & OHCI1394_selfIDComplete ? " selfID" : "", |
302 | evt & OHCI1394_RQPkt ? " AR_req" : "", | |
303 | evt & OHCI1394_RSPkt ? " AR_resp" : "", | |
304 | evt & OHCI1394_reqTxComplete ? " AT_req" : "", | |
305 | evt & OHCI1394_respTxComplete ? " AT_resp" : "", | |
306 | evt & OHCI1394_isochRx ? " IR" : "", | |
307 | evt & OHCI1394_isochTx ? " IT" : "", | |
308 | evt & OHCI1394_postedWriteErr ? " postedWriteErr" : "", | |
309 | evt & OHCI1394_cycleTooLong ? " cycleTooLong" : "", | |
a48777e0 | 310 | evt & OHCI1394_cycle64Seconds ? " cycle64Seconds" : "", |
5ed1f321 | 311 | evt & OHCI1394_cycleInconsistent ? " cycleInconsistent" : "", |
161b96e7 SR |
312 | evt & OHCI1394_regAccessFail ? " regAccessFail" : "", |
313 | evt & OHCI1394_busReset ? " busReset" : "", | |
314 | evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt | | |
315 | OHCI1394_RSPkt | OHCI1394_reqTxComplete | | |
316 | OHCI1394_respTxComplete | OHCI1394_isochRx | | |
317 | OHCI1394_isochTx | OHCI1394_postedWriteErr | | |
a48777e0 CL |
318 | OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds | |
319 | OHCI1394_cycleInconsistent | | |
161b96e7 | 320 | OHCI1394_regAccessFail | OHCI1394_busReset) |
ad3c0fe8 SR |
321 | ? " ?" : ""); |
322 | } | |
323 | ||
324 | static const char *speed[] = { | |
325 | [0] = "S100", [1] = "S200", [2] = "S400", [3] = "beta", | |
326 | }; | |
327 | static const char *power[] = { | |
328 | [0] = "+0W", [1] = "+15W", [2] = "+30W", [3] = "+45W", | |
329 | [4] = "-3W", [5] = " ?W", [6] = "-3..-6W", [7] = "-3..-10W", | |
330 | }; | |
331 | static const char port[] = { '.', '-', 'p', 'c', }; | |
332 | ||
333 | static char _p(u32 *s, int shift) | |
334 | { | |
335 | return port[*s >> shift & 3]; | |
336 | } | |
337 | ||
08ddb2f4 | 338 | static void log_selfids(int node_id, int generation, int self_id_count, u32 *s) |
ad3c0fe8 SR |
339 | { |
340 | if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS))) | |
341 | return; | |
342 | ||
161b96e7 SR |
343 | fw_notify("%d selfIDs, generation %d, local node ID %04x\n", |
344 | self_id_count, generation, node_id); | |
ad3c0fe8 SR |
345 | |
346 | for (; self_id_count--; ++s) | |
347 | if ((*s & 1 << 23) == 0) | |
161b96e7 SR |
348 | fw_notify("selfID 0: %08x, phy %d [%c%c%c] " |
349 | "%s gc=%d %s %s%s%s\n", | |
350 | *s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2), | |
351 | speed[*s >> 14 & 3], *s >> 16 & 63, | |
352 | power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "", | |
353 | *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : ""); | |
ad3c0fe8 | 354 | else |
161b96e7 SR |
355 | fw_notify("selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n", |
356 | *s, *s >> 24 & 63, | |
357 | _p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10), | |
358 | _p(s, 8), _p(s, 6), _p(s, 4), _p(s, 2)); | |
ad3c0fe8 SR |
359 | } |
360 | ||
361 | static const char *evts[] = { | |
362 | [0x00] = "evt_no_status", [0x01] = "-reserved-", | |
363 | [0x02] = "evt_long_packet", [0x03] = "evt_missing_ack", | |
364 | [0x04] = "evt_underrun", [0x05] = "evt_overrun", | |
365 | [0x06] = "evt_descriptor_read", [0x07] = "evt_data_read", | |
366 | [0x08] = "evt_data_write", [0x09] = "evt_bus_reset", | |
367 | [0x0a] = "evt_timeout", [0x0b] = "evt_tcode_err", | |
368 | [0x0c] = "-reserved-", [0x0d] = "-reserved-", | |
369 | [0x0e] = "evt_unknown", [0x0f] = "evt_flushed", | |
370 | [0x10] = "-reserved-", [0x11] = "ack_complete", | |
371 | [0x12] = "ack_pending ", [0x13] = "-reserved-", | |
372 | [0x14] = "ack_busy_X", [0x15] = "ack_busy_A", | |
373 | [0x16] = "ack_busy_B", [0x17] = "-reserved-", | |
374 | [0x18] = "-reserved-", [0x19] = "-reserved-", | |
375 | [0x1a] = "-reserved-", [0x1b] = "ack_tardy", | |
376 | [0x1c] = "-reserved-", [0x1d] = "ack_data_error", | |
377 | [0x1e] = "ack_type_error", [0x1f] = "-reserved-", | |
378 | [0x20] = "pending/cancelled", | |
379 | }; | |
380 | static const char *tcodes[] = { | |
381 | [0x0] = "QW req", [0x1] = "BW req", | |
382 | [0x2] = "W resp", [0x3] = "-reserved-", | |
383 | [0x4] = "QR req", [0x5] = "BR req", | |
384 | [0x6] = "QR resp", [0x7] = "BR resp", | |
385 | [0x8] = "cycle start", [0x9] = "Lk req", | |
386 | [0xa] = "async stream packet", [0xb] = "Lk resp", | |
387 | [0xc] = "-reserved-", [0xd] = "-reserved-", | |
388 | [0xe] = "link internal", [0xf] = "-reserved-", | |
389 | }; | |
390 | static const char *phys[] = { | |
391 | [0x0] = "phy config packet", [0x1] = "link-on packet", | |
392 | [0x2] = "self-id packet", [0x3] = "-reserved-", | |
393 | }; | |
394 | ||
395 | static void log_ar_at_event(char dir, int speed, u32 *header, int evt) | |
396 | { | |
397 | int tcode = header[0] >> 4 & 0xf; | |
398 | char specific[12]; | |
399 | ||
400 | if (likely(!(param_debug & OHCI_PARAM_DEBUG_AT_AR))) | |
401 | return; | |
402 | ||
403 | if (unlikely(evt >= ARRAY_SIZE(evts))) | |
404 | evt = 0x1f; | |
405 | ||
08ddb2f4 | 406 | if (evt == OHCI1394_evt_bus_reset) { |
161b96e7 SR |
407 | fw_notify("A%c evt_bus_reset, generation %d\n", |
408 | dir, (header[2] >> 16) & 0xff); | |
08ddb2f4 SR |
409 | return; |
410 | } | |
411 | ||
ad3c0fe8 | 412 | if (header[0] == ~header[1]) { |
161b96e7 SR |
413 | fw_notify("A%c %s, %s, %08x\n", |
414 | dir, evts[evt], phys[header[0] >> 30 & 0x3], header[0]); | |
ad3c0fe8 SR |
415 | return; |
416 | } | |
417 | ||
418 | switch (tcode) { | |
419 | case 0x0: case 0x6: case 0x8: | |
420 | snprintf(specific, sizeof(specific), " = %08x", | |
421 | be32_to_cpu((__force __be32)header[3])); | |
422 | break; | |
423 | case 0x1: case 0x5: case 0x7: case 0x9: case 0xb: | |
424 | snprintf(specific, sizeof(specific), " %x,%x", | |
425 | header[3] >> 16, header[3] & 0xffff); | |
426 | break; | |
427 | default: | |
428 | specific[0] = '\0'; | |
429 | } | |
430 | ||
431 | switch (tcode) { | |
432 | case 0xe: case 0xa: | |
161b96e7 | 433 | fw_notify("A%c %s, %s\n", dir, evts[evt], tcodes[tcode]); |
ad3c0fe8 SR |
434 | break; |
435 | case 0x0: case 0x1: case 0x4: case 0x5: case 0x9: | |
161b96e7 SR |
436 | fw_notify("A%c spd %x tl %02x, " |
437 | "%04x -> %04x, %s, " | |
438 | "%s, %04x%08x%s\n", | |
439 | dir, speed, header[0] >> 10 & 0x3f, | |
440 | header[1] >> 16, header[0] >> 16, evts[evt], | |
441 | tcodes[tcode], header[1] & 0xffff, header[2], specific); | |
ad3c0fe8 SR |
442 | break; |
443 | default: | |
161b96e7 SR |
444 | fw_notify("A%c spd %x tl %02x, " |
445 | "%04x -> %04x, %s, " | |
446 | "%s%s\n", | |
447 | dir, speed, header[0] >> 10 & 0x3f, | |
448 | header[1] >> 16, header[0] >> 16, evts[evt], | |
449 | tcodes[tcode], specific); | |
ad3c0fe8 SR |
450 | } |
451 | } | |
452 | ||
453 | #else | |
454 | ||
5da3dac8 SR |
455 | #define param_debug 0 |
456 | static inline void log_irqs(u32 evt) {} | |
457 | static inline void log_selfids(int node_id, int generation, int self_id_count, u32 *s) {} | |
458 | static inline void log_ar_at_event(char dir, int speed, u32 *header, int evt) {} | |
ad3c0fe8 SR |
459 | |
460 | #endif /* CONFIG_FIREWIRE_OHCI_DEBUG */ | |
461 | ||
95688e97 | 462 | static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data) |
ed568912 KH |
463 | { |
464 | writel(data, ohci->registers + offset); | |
465 | } | |
466 | ||
95688e97 | 467 | static inline u32 reg_read(const struct fw_ohci *ohci, int offset) |
ed568912 KH |
468 | { |
469 | return readl(ohci->registers + offset); | |
470 | } | |
471 | ||
95688e97 | 472 | static inline void flush_writes(const struct fw_ohci *ohci) |
ed568912 KH |
473 | { |
474 | /* Do a dummy read to flush writes. */ | |
475 | reg_read(ohci, OHCI1394_Version); | |
476 | } | |
477 | ||
35d999b1 | 478 | static int read_phy_reg(struct fw_ohci *ohci, int addr) |
ed568912 | 479 | { |
4a96b4fc | 480 | u32 val; |
35d999b1 | 481 | int i; |
ed568912 KH |
482 | |
483 | reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr)); | |
153e3979 | 484 | for (i = 0; i < 3 + 100; i++) { |
35d999b1 SR |
485 | val = reg_read(ohci, OHCI1394_PhyControl); |
486 | if (val & OHCI1394_PhyControl_ReadDone) | |
487 | return OHCI1394_PhyControl_ReadData(val); | |
488 | ||
153e3979 CL |
489 | /* |
490 | * Try a few times without waiting. Sleeping is necessary | |
491 | * only when the link/PHY interface is busy. | |
492 | */ | |
493 | if (i >= 3) | |
494 | msleep(1); | |
ed568912 | 495 | } |
35d999b1 | 496 | fw_error("failed to read phy reg\n"); |
ed568912 | 497 | |
35d999b1 SR |
498 | return -EBUSY; |
499 | } | |
4a96b4fc | 500 | |
35d999b1 SR |
501 | static int write_phy_reg(const struct fw_ohci *ohci, int addr, u32 val) |
502 | { | |
503 | int i; | |
504 | ||
505 | reg_write(ohci, OHCI1394_PhyControl, | |
506 | OHCI1394_PhyControl_Write(addr, val)); | |
153e3979 | 507 | for (i = 0; i < 3 + 100; i++) { |
35d999b1 SR |
508 | val = reg_read(ohci, OHCI1394_PhyControl); |
509 | if (!(val & OHCI1394_PhyControl_WritePending)) | |
510 | return 0; | |
511 | ||
153e3979 CL |
512 | if (i >= 3) |
513 | msleep(1); | |
35d999b1 SR |
514 | } |
515 | fw_error("failed to write phy reg\n"); | |
516 | ||
517 | return -EBUSY; | |
4a96b4fc CL |
518 | } |
519 | ||
520 | static int ohci_update_phy_reg(struct fw_card *card, int addr, | |
521 | int clear_bits, int set_bits) | |
522 | { | |
523 | struct fw_ohci *ohci = fw_ohci(card); | |
35d999b1 | 524 | int ret; |
4a96b4fc | 525 | |
35d999b1 SR |
526 | ret = read_phy_reg(ohci, addr); |
527 | if (ret < 0) | |
528 | return ret; | |
4a96b4fc | 529 | |
e7014dad CL |
530 | /* |
531 | * The interrupt status bits are cleared by writing a one bit. | |
532 | * Avoid clearing them unless explicitly requested in set_bits. | |
533 | */ | |
534 | if (addr == 5) | |
535 | clear_bits |= PHY_INT_STATUS_BITS; | |
536 | ||
35d999b1 | 537 | return write_phy_reg(ohci, addr, (ret & ~clear_bits) | set_bits); |
ed568912 KH |
538 | } |
539 | ||
35d999b1 | 540 | static int read_paged_phy_reg(struct fw_ohci *ohci, int page, int addr) |
925e7a65 | 541 | { |
35d999b1 | 542 | int ret; |
925e7a65 | 543 | |
35d999b1 SR |
544 | ret = ohci_update_phy_reg(&ohci->card, 7, PHY_PAGE_SELECT, page << 5); |
545 | if (ret < 0) | |
546 | return ret; | |
925e7a65 | 547 | |
35d999b1 | 548 | return read_phy_reg(ohci, addr); |
925e7a65 CL |
549 | } |
550 | ||
32b46093 | 551 | static int ar_context_add_page(struct ar_context *ctx) |
ed568912 | 552 | { |
32b46093 KH |
553 | struct device *dev = ctx->ohci->card.device; |
554 | struct ar_buffer *ab; | |
f5101d58 | 555 | dma_addr_t uninitialized_var(ab_bus); |
32b46093 KH |
556 | size_t offset; |
557 | ||
bde1709a | 558 | ab = dma_alloc_coherent(dev, PAGE_SIZE, &ab_bus, GFP_ATOMIC); |
32b46093 KH |
559 | if (ab == NULL) |
560 | return -ENOMEM; | |
561 | ||
a55709ba | 562 | ab->next = NULL; |
2d826cc5 | 563 | memset(&ab->descriptor, 0, sizeof(ab->descriptor)); |
a77754a7 KH |
564 | ab->descriptor.control = cpu_to_le16(DESCRIPTOR_INPUT_MORE | |
565 | DESCRIPTOR_STATUS | | |
566 | DESCRIPTOR_BRANCH_ALWAYS); | |
32b46093 KH |
567 | offset = offsetof(struct ar_buffer, data); |
568 | ab->descriptor.req_count = cpu_to_le16(PAGE_SIZE - offset); | |
569 | ab->descriptor.data_address = cpu_to_le32(ab_bus + offset); | |
570 | ab->descriptor.res_count = cpu_to_le16(PAGE_SIZE - offset); | |
571 | ab->descriptor.branch_address = 0; | |
572 | ||
ec839e43 | 573 | ctx->last_buffer->descriptor.branch_address = cpu_to_le32(ab_bus | 1); |
32b46093 KH |
574 | ctx->last_buffer->next = ab; |
575 | ctx->last_buffer = ab; | |
576 | ||
a77754a7 | 577 | reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE); |
ed568912 | 578 | flush_writes(ctx->ohci); |
32b46093 KH |
579 | |
580 | return 0; | |
ed568912 KH |
581 | } |
582 | ||
a55709ba JF |
583 | static void ar_context_release(struct ar_context *ctx) |
584 | { | |
585 | struct ar_buffer *ab, *ab_next; | |
586 | size_t offset; | |
587 | dma_addr_t ab_bus; | |
588 | ||
589 | for (ab = ctx->current_buffer; ab; ab = ab_next) { | |
590 | ab_next = ab->next; | |
591 | offset = offsetof(struct ar_buffer, data); | |
592 | ab_bus = le32_to_cpu(ab->descriptor.data_address) - offset; | |
593 | dma_free_coherent(ctx->ohci->card.device, PAGE_SIZE, | |
594 | ab, ab_bus); | |
595 | } | |
596 | } | |
597 | ||
11bf20ad SR |
598 | #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32) |
599 | #define cond_le32_to_cpu(v) \ | |
4a635593 | 600 | (ohci->quirks & QUIRK_BE_HEADERS ? (__force __u32)(v) : le32_to_cpu(v)) |
11bf20ad SR |
601 | #else |
602 | #define cond_le32_to_cpu(v) le32_to_cpu(v) | |
603 | #endif | |
604 | ||
32b46093 | 605 | static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer) |
ed568912 | 606 | { |
ed568912 | 607 | struct fw_ohci *ohci = ctx->ohci; |
2639a6fb KH |
608 | struct fw_packet p; |
609 | u32 status, length, tcode; | |
43286568 | 610 | int evt; |
2639a6fb | 611 | |
11bf20ad SR |
612 | p.header[0] = cond_le32_to_cpu(buffer[0]); |
613 | p.header[1] = cond_le32_to_cpu(buffer[1]); | |
614 | p.header[2] = cond_le32_to_cpu(buffer[2]); | |
2639a6fb KH |
615 | |
616 | tcode = (p.header[0] >> 4) & 0x0f; | |
617 | switch (tcode) { | |
618 | case TCODE_WRITE_QUADLET_REQUEST: | |
619 | case TCODE_READ_QUADLET_RESPONSE: | |
32b46093 | 620 | p.header[3] = (__force __u32) buffer[3]; |
2639a6fb | 621 | p.header_length = 16; |
32b46093 | 622 | p.payload_length = 0; |
2639a6fb KH |
623 | break; |
624 | ||
2639a6fb | 625 | case TCODE_READ_BLOCK_REQUEST : |
11bf20ad | 626 | p.header[3] = cond_le32_to_cpu(buffer[3]); |
32b46093 KH |
627 | p.header_length = 16; |
628 | p.payload_length = 0; | |
629 | break; | |
630 | ||
631 | case TCODE_WRITE_BLOCK_REQUEST: | |
2639a6fb KH |
632 | case TCODE_READ_BLOCK_RESPONSE: |
633 | case TCODE_LOCK_REQUEST: | |
634 | case TCODE_LOCK_RESPONSE: | |
11bf20ad | 635 | p.header[3] = cond_le32_to_cpu(buffer[3]); |
2639a6fb | 636 | p.header_length = 16; |
32b46093 | 637 | p.payload_length = p.header[3] >> 16; |
2639a6fb KH |
638 | break; |
639 | ||
640 | case TCODE_WRITE_RESPONSE: | |
641 | case TCODE_READ_QUADLET_REQUEST: | |
32b46093 | 642 | case OHCI_TCODE_PHY_PACKET: |
2639a6fb | 643 | p.header_length = 12; |
32b46093 | 644 | p.payload_length = 0; |
2639a6fb | 645 | break; |
ccff9629 SR |
646 | |
647 | default: | |
648 | /* FIXME: Stop context, discard everything, and restart? */ | |
649 | p.header_length = 0; | |
650 | p.payload_length = 0; | |
2639a6fb | 651 | } |
ed568912 | 652 | |
32b46093 KH |
653 | p.payload = (void *) buffer + p.header_length; |
654 | ||
655 | /* FIXME: What to do about evt_* errors? */ | |
656 | length = (p.header_length + p.payload_length + 3) / 4; | |
11bf20ad | 657 | status = cond_le32_to_cpu(buffer[length]); |
43286568 | 658 | evt = (status >> 16) & 0x1f; |
32b46093 | 659 | |
43286568 | 660 | p.ack = evt - 16; |
32b46093 KH |
661 | p.speed = (status >> 21) & 0x7; |
662 | p.timestamp = status & 0xffff; | |
663 | p.generation = ohci->request_generation; | |
ed568912 | 664 | |
43286568 | 665 | log_ar_at_event('R', p.speed, p.header, evt); |
ad3c0fe8 | 666 | |
c781c06d KH |
667 | /* |
668 | * The OHCI bus reset handler synthesizes a phy packet with | |
ed568912 KH |
669 | * the new generation number when a bus reset happens (see |
670 | * section 8.4.2.3). This helps us determine when a request | |
671 | * was received and make sure we send the response in the same | |
672 | * generation. We only need this for requests; for responses | |
673 | * we use the unique tlabel for finding the matching | |
c781c06d | 674 | * request. |
d34316a4 SR |
675 | * |
676 | * Alas some chips sometimes emit bus reset packets with a | |
677 | * wrong generation. We set the correct generation for these | |
678 | * at a slightly incorrect time (in bus_reset_tasklet). | |
c781c06d | 679 | */ |
d34316a4 | 680 | if (evt == OHCI1394_evt_bus_reset) { |
4a635593 | 681 | if (!(ohci->quirks & QUIRK_RESET_PACKET)) |
d34316a4 SR |
682 | ohci->request_generation = (p.header[2] >> 16) & 0xff; |
683 | } else if (ctx == &ohci->ar_request_ctx) { | |
2639a6fb | 684 | fw_core_handle_request(&ohci->card, &p); |
d34316a4 | 685 | } else { |
2639a6fb | 686 | fw_core_handle_response(&ohci->card, &p); |
d34316a4 | 687 | } |
ed568912 | 688 | |
32b46093 KH |
689 | return buffer + length + 1; |
690 | } | |
ed568912 | 691 | |
32b46093 KH |
692 | static void ar_context_tasklet(unsigned long data) |
693 | { | |
694 | struct ar_context *ctx = (struct ar_context *)data; | |
695 | struct fw_ohci *ohci = ctx->ohci; | |
696 | struct ar_buffer *ab; | |
697 | struct descriptor *d; | |
698 | void *buffer, *end; | |
699 | ||
700 | ab = ctx->current_buffer; | |
701 | d = &ab->descriptor; | |
702 | ||
703 | if (d->res_count == 0) { | |
704 | size_t size, rest, offset; | |
6b84236d JW |
705 | dma_addr_t start_bus; |
706 | void *start; | |
32b46093 | 707 | |
c781c06d KH |
708 | /* |
709 | * This descriptor is finished and we may have a | |
32b46093 | 710 | * packet split across this and the next buffer. We |
c781c06d KH |
711 | * reuse the page for reassembling the split packet. |
712 | */ | |
32b46093 KH |
713 | |
714 | offset = offsetof(struct ar_buffer, data); | |
6b84236d JW |
715 | start = buffer = ab; |
716 | start_bus = le32_to_cpu(ab->descriptor.data_address) - offset; | |
32b46093 | 717 | |
32b46093 KH |
718 | ab = ab->next; |
719 | d = &ab->descriptor; | |
720 | size = buffer + PAGE_SIZE - ctx->pointer; | |
721 | rest = le16_to_cpu(d->req_count) - le16_to_cpu(d->res_count); | |
722 | memmove(buffer, ctx->pointer, size); | |
723 | memcpy(buffer + size, ab->data, rest); | |
724 | ctx->current_buffer = ab; | |
725 | ctx->pointer = (void *) ab->data + rest; | |
726 | end = buffer + size + rest; | |
727 | ||
728 | while (buffer < end) | |
729 | buffer = handle_ar_packet(ctx, buffer); | |
730 | ||
bde1709a | 731 | dma_free_coherent(ohci->card.device, PAGE_SIZE, |
6b84236d | 732 | start, start_bus); |
32b46093 KH |
733 | ar_context_add_page(ctx); |
734 | } else { | |
735 | buffer = ctx->pointer; | |
736 | ctx->pointer = end = | |
737 | (void *) ab + PAGE_SIZE - le16_to_cpu(d->res_count); | |
738 | ||
739 | while (buffer < end) | |
740 | buffer = handle_ar_packet(ctx, buffer); | |
741 | } | |
ed568912 KH |
742 | } |
743 | ||
53dca511 SR |
744 | static int ar_context_init(struct ar_context *ctx, |
745 | struct fw_ohci *ohci, u32 regs) | |
ed568912 | 746 | { |
32b46093 | 747 | struct ar_buffer ab; |
ed568912 | 748 | |
72e318e0 KH |
749 | ctx->regs = regs; |
750 | ctx->ohci = ohci; | |
751 | ctx->last_buffer = &ab; | |
ed568912 KH |
752 | tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx); |
753 | ||
32b46093 KH |
754 | ar_context_add_page(ctx); |
755 | ar_context_add_page(ctx); | |
756 | ctx->current_buffer = ab.next; | |
757 | ctx->pointer = ctx->current_buffer->data; | |
758 | ||
2aef469a KH |
759 | return 0; |
760 | } | |
761 | ||
762 | static void ar_context_run(struct ar_context *ctx) | |
763 | { | |
764 | struct ar_buffer *ab = ctx->current_buffer; | |
765 | dma_addr_t ab_bus; | |
766 | size_t offset; | |
767 | ||
768 | offset = offsetof(struct ar_buffer, data); | |
0a9972ba | 769 | ab_bus = le32_to_cpu(ab->descriptor.data_address) - offset; |
2aef469a KH |
770 | |
771 | reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ab_bus | 1); | |
a77754a7 | 772 | reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN); |
32b46093 | 773 | flush_writes(ctx->ohci); |
ed568912 | 774 | } |
373b2edd | 775 | |
53dca511 | 776 | static struct descriptor *find_branch_descriptor(struct descriptor *d, int z) |
a186b4a6 JW |
777 | { |
778 | int b, key; | |
779 | ||
780 | b = (le16_to_cpu(d->control) & DESCRIPTOR_BRANCH_ALWAYS) >> 2; | |
781 | key = (le16_to_cpu(d->control) & DESCRIPTOR_KEY_IMMEDIATE) >> 8; | |
782 | ||
783 | /* figure out which descriptor the branch address goes in */ | |
784 | if (z == 2 && (b == 3 || key == 2)) | |
785 | return d; | |
786 | else | |
787 | return d + z - 1; | |
788 | } | |
789 | ||
30200739 KH |
790 | static void context_tasklet(unsigned long data) |
791 | { | |
792 | struct context *ctx = (struct context *) data; | |
30200739 KH |
793 | struct descriptor *d, *last; |
794 | u32 address; | |
795 | int z; | |
fe5ca634 | 796 | struct descriptor_buffer *desc; |
30200739 | 797 | |
fe5ca634 DM |
798 | desc = list_entry(ctx->buffer_list.next, |
799 | struct descriptor_buffer, list); | |
800 | last = ctx->last; | |
30200739 | 801 | while (last->branch_address != 0) { |
fe5ca634 | 802 | struct descriptor_buffer *old_desc = desc; |
30200739 KH |
803 | address = le32_to_cpu(last->branch_address); |
804 | z = address & 0xf; | |
fe5ca634 DM |
805 | address &= ~0xf; |
806 | ||
807 | /* If the branch address points to a buffer outside of the | |
808 | * current buffer, advance to the next buffer. */ | |
809 | if (address < desc->buffer_bus || | |
810 | address >= desc->buffer_bus + desc->used) | |
811 | desc = list_entry(desc->list.next, | |
812 | struct descriptor_buffer, list); | |
813 | d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d); | |
a186b4a6 | 814 | last = find_branch_descriptor(d, z); |
30200739 KH |
815 | |
816 | if (!ctx->callback(ctx, d, last)) | |
817 | break; | |
818 | ||
fe5ca634 DM |
819 | if (old_desc != desc) { |
820 | /* If we've advanced to the next buffer, move the | |
821 | * previous buffer to the free list. */ | |
822 | unsigned long flags; | |
823 | old_desc->used = 0; | |
824 | spin_lock_irqsave(&ctx->ohci->lock, flags); | |
825 | list_move_tail(&old_desc->list, &ctx->buffer_list); | |
826 | spin_unlock_irqrestore(&ctx->ohci->lock, flags); | |
827 | } | |
828 | ctx->last = last; | |
30200739 KH |
829 | } |
830 | } | |
831 | ||
fe5ca634 DM |
832 | /* |
833 | * Allocate a new buffer and add it to the list of free buffers for this | |
834 | * context. Must be called with ohci->lock held. | |
835 | */ | |
53dca511 | 836 | static int context_add_buffer(struct context *ctx) |
fe5ca634 DM |
837 | { |
838 | struct descriptor_buffer *desc; | |
f5101d58 | 839 | dma_addr_t uninitialized_var(bus_addr); |
fe5ca634 DM |
840 | int offset; |
841 | ||
842 | /* | |
843 | * 16MB of descriptors should be far more than enough for any DMA | |
844 | * program. This will catch run-away userspace or DoS attacks. | |
845 | */ | |
846 | if (ctx->total_allocation >= 16*1024*1024) | |
847 | return -ENOMEM; | |
848 | ||
849 | desc = dma_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE, | |
850 | &bus_addr, GFP_ATOMIC); | |
851 | if (!desc) | |
852 | return -ENOMEM; | |
853 | ||
854 | offset = (void *)&desc->buffer - (void *)desc; | |
855 | desc->buffer_size = PAGE_SIZE - offset; | |
856 | desc->buffer_bus = bus_addr + offset; | |
857 | desc->used = 0; | |
858 | ||
859 | list_add_tail(&desc->list, &ctx->buffer_list); | |
860 | ctx->total_allocation += PAGE_SIZE; | |
861 | ||
862 | return 0; | |
863 | } | |
864 | ||
53dca511 SR |
865 | static int context_init(struct context *ctx, struct fw_ohci *ohci, |
866 | u32 regs, descriptor_callback_t callback) | |
30200739 KH |
867 | { |
868 | ctx->ohci = ohci; | |
869 | ctx->regs = regs; | |
fe5ca634 DM |
870 | ctx->total_allocation = 0; |
871 | ||
872 | INIT_LIST_HEAD(&ctx->buffer_list); | |
873 | if (context_add_buffer(ctx) < 0) | |
30200739 KH |
874 | return -ENOMEM; |
875 | ||
fe5ca634 DM |
876 | ctx->buffer_tail = list_entry(ctx->buffer_list.next, |
877 | struct descriptor_buffer, list); | |
878 | ||
30200739 KH |
879 | tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx); |
880 | ctx->callback = callback; | |
881 | ||
c781c06d KH |
882 | /* |
883 | * We put a dummy descriptor in the buffer that has a NULL | |
30200739 | 884 | * branch address and looks like it's been sent. That way we |
fe5ca634 | 885 | * have a descriptor to append DMA programs to. |
c781c06d | 886 | */ |
fe5ca634 DM |
887 | memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer)); |
888 | ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST); | |
889 | ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011); | |
890 | ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer); | |
891 | ctx->last = ctx->buffer_tail->buffer; | |
892 | ctx->prev = ctx->buffer_tail->buffer; | |
30200739 KH |
893 | |
894 | return 0; | |
895 | } | |
896 | ||
53dca511 | 897 | static void context_release(struct context *ctx) |
30200739 KH |
898 | { |
899 | struct fw_card *card = &ctx->ohci->card; | |
fe5ca634 | 900 | struct descriptor_buffer *desc, *tmp; |
30200739 | 901 | |
fe5ca634 DM |
902 | list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list) |
903 | dma_free_coherent(card->device, PAGE_SIZE, desc, | |
904 | desc->buffer_bus - | |
905 | ((void *)&desc->buffer - (void *)desc)); | |
30200739 KH |
906 | } |
907 | ||
fe5ca634 | 908 | /* Must be called with ohci->lock held */ |
53dca511 SR |
909 | static struct descriptor *context_get_descriptors(struct context *ctx, |
910 | int z, dma_addr_t *d_bus) | |
30200739 | 911 | { |
fe5ca634 DM |
912 | struct descriptor *d = NULL; |
913 | struct descriptor_buffer *desc = ctx->buffer_tail; | |
914 | ||
915 | if (z * sizeof(*d) > desc->buffer_size) | |
916 | return NULL; | |
917 | ||
918 | if (z * sizeof(*d) > desc->buffer_size - desc->used) { | |
919 | /* No room for the descriptor in this buffer, so advance to the | |
920 | * next one. */ | |
30200739 | 921 | |
fe5ca634 DM |
922 | if (desc->list.next == &ctx->buffer_list) { |
923 | /* If there is no free buffer next in the list, | |
924 | * allocate one. */ | |
925 | if (context_add_buffer(ctx) < 0) | |
926 | return NULL; | |
927 | } | |
928 | desc = list_entry(desc->list.next, | |
929 | struct descriptor_buffer, list); | |
930 | ctx->buffer_tail = desc; | |
931 | } | |
30200739 | 932 | |
fe5ca634 | 933 | d = desc->buffer + desc->used / sizeof(*d); |
2d826cc5 | 934 | memset(d, 0, z * sizeof(*d)); |
fe5ca634 | 935 | *d_bus = desc->buffer_bus + desc->used; |
30200739 KH |
936 | |
937 | return d; | |
938 | } | |
939 | ||
295e3feb | 940 | static void context_run(struct context *ctx, u32 extra) |
30200739 KH |
941 | { |
942 | struct fw_ohci *ohci = ctx->ohci; | |
943 | ||
a77754a7 | 944 | reg_write(ohci, COMMAND_PTR(ctx->regs), |
fe5ca634 | 945 | le32_to_cpu(ctx->last->branch_address)); |
a77754a7 KH |
946 | reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0); |
947 | reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra); | |
30200739 KH |
948 | flush_writes(ohci); |
949 | } | |
950 | ||
951 | static void context_append(struct context *ctx, | |
952 | struct descriptor *d, int z, int extra) | |
953 | { | |
954 | dma_addr_t d_bus; | |
fe5ca634 | 955 | struct descriptor_buffer *desc = ctx->buffer_tail; |
30200739 | 956 | |
fe5ca634 | 957 | d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d); |
30200739 | 958 | |
fe5ca634 DM |
959 | desc->used += (z + extra) * sizeof(*d); |
960 | ctx->prev->branch_address = cpu_to_le32(d_bus | z); | |
961 | ctx->prev = find_branch_descriptor(d, z); | |
30200739 | 962 | |
a77754a7 | 963 | reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE); |
30200739 KH |
964 | flush_writes(ctx->ohci); |
965 | } | |
966 | ||
967 | static void context_stop(struct context *ctx) | |
968 | { | |
969 | u32 reg; | |
b8295668 | 970 | int i; |
30200739 | 971 | |
a77754a7 | 972 | reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN); |
b8295668 | 973 | flush_writes(ctx->ohci); |
30200739 | 974 | |
b8295668 | 975 | for (i = 0; i < 10; i++) { |
a77754a7 | 976 | reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs)); |
b8295668 | 977 | if ((reg & CONTEXT_ACTIVE) == 0) |
b0068549 | 978 | return; |
b8295668 | 979 | |
b980f5a2 | 980 | mdelay(1); |
b8295668 | 981 | } |
b0068549 | 982 | fw_error("Error: DMA context still active (0x%08x)\n", reg); |
30200739 | 983 | } |
ed568912 | 984 | |
f319b6a0 KH |
985 | struct driver_data { |
986 | struct fw_packet *packet; | |
987 | }; | |
ed568912 | 988 | |
c781c06d KH |
989 | /* |
990 | * This function apppends a packet to the DMA queue for transmission. | |
f319b6a0 | 991 | * Must always be called with the ochi->lock held to ensure proper |
c781c06d KH |
992 | * generation handling and locking around packet queue manipulation. |
993 | */ | |
53dca511 SR |
994 | static int at_context_queue_packet(struct context *ctx, |
995 | struct fw_packet *packet) | |
ed568912 | 996 | { |
ed568912 | 997 | struct fw_ohci *ohci = ctx->ohci; |
4b6d51ec | 998 | dma_addr_t d_bus, uninitialized_var(payload_bus); |
f319b6a0 KH |
999 | struct driver_data *driver_data; |
1000 | struct descriptor *d, *last; | |
1001 | __le32 *header; | |
ed568912 | 1002 | int z, tcode; |
f319b6a0 | 1003 | u32 reg; |
ed568912 | 1004 | |
f319b6a0 KH |
1005 | d = context_get_descriptors(ctx, 4, &d_bus); |
1006 | if (d == NULL) { | |
1007 | packet->ack = RCODE_SEND_ERROR; | |
1008 | return -1; | |
ed568912 KH |
1009 | } |
1010 | ||
a77754a7 | 1011 | d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE); |
f319b6a0 KH |
1012 | d[0].res_count = cpu_to_le16(packet->timestamp); |
1013 | ||
c781c06d KH |
1014 | /* |
1015 | * The DMA format for asyncronous link packets is different | |
ed568912 KH |
1016 | * from the IEEE1394 layout, so shift the fields around |
1017 | * accordingly. If header_length is 8, it's a PHY packet, to | |
c781c06d KH |
1018 | * which we need to prepend an extra quadlet. |
1019 | */ | |
f319b6a0 KH |
1020 | |
1021 | header = (__le32 *) &d[1]; | |
f8c2287c JF |
1022 | switch (packet->header_length) { |
1023 | case 16: | |
1024 | case 12: | |
f319b6a0 KH |
1025 | header[0] = cpu_to_le32((packet->header[0] & 0xffff) | |
1026 | (packet->speed << 16)); | |
1027 | header[1] = cpu_to_le32((packet->header[1] & 0xffff) | | |
1028 | (packet->header[0] & 0xffff0000)); | |
1029 | header[2] = cpu_to_le32(packet->header[2]); | |
ed568912 KH |
1030 | |
1031 | tcode = (packet->header[0] >> 4) & 0x0f; | |
1032 | if (TCODE_IS_BLOCK_PACKET(tcode)) | |
f319b6a0 | 1033 | header[3] = cpu_to_le32(packet->header[3]); |
ed568912 | 1034 | else |
f319b6a0 KH |
1035 | header[3] = (__force __le32) packet->header[3]; |
1036 | ||
1037 | d[0].req_count = cpu_to_le16(packet->header_length); | |
f8c2287c JF |
1038 | break; |
1039 | ||
1040 | case 8: | |
f319b6a0 KH |
1041 | header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) | |
1042 | (packet->speed << 16)); | |
1043 | header[1] = cpu_to_le32(packet->header[0]); | |
1044 | header[2] = cpu_to_le32(packet->header[1]); | |
1045 | d[0].req_count = cpu_to_le16(12); | |
f8c2287c JF |
1046 | break; |
1047 | ||
1048 | case 4: | |
1049 | header[0] = cpu_to_le32((packet->header[0] & 0xffff) | | |
1050 | (packet->speed << 16)); | |
1051 | header[1] = cpu_to_le32(packet->header[0] & 0xffff0000); | |
1052 | d[0].req_count = cpu_to_le16(8); | |
1053 | break; | |
1054 | ||
1055 | default: | |
1056 | /* BUG(); */ | |
1057 | packet->ack = RCODE_SEND_ERROR; | |
1058 | return -1; | |
ed568912 KH |
1059 | } |
1060 | ||
f319b6a0 KH |
1061 | driver_data = (struct driver_data *) &d[3]; |
1062 | driver_data->packet = packet; | |
20d11673 | 1063 | packet->driver_data = driver_data; |
a186b4a6 | 1064 | |
f319b6a0 KH |
1065 | if (packet->payload_length > 0) { |
1066 | payload_bus = | |
1067 | dma_map_single(ohci->card.device, packet->payload, | |
1068 | packet->payload_length, DMA_TO_DEVICE); | |
8d8bb39b | 1069 | if (dma_mapping_error(ohci->card.device, payload_bus)) { |
f319b6a0 KH |
1070 | packet->ack = RCODE_SEND_ERROR; |
1071 | return -1; | |
1072 | } | |
19593ffd SR |
1073 | packet->payload_bus = payload_bus; |
1074 | packet->payload_mapped = true; | |
f319b6a0 KH |
1075 | |
1076 | d[2].req_count = cpu_to_le16(packet->payload_length); | |
1077 | d[2].data_address = cpu_to_le32(payload_bus); | |
1078 | last = &d[2]; | |
1079 | z = 3; | |
ed568912 | 1080 | } else { |
f319b6a0 KH |
1081 | last = &d[0]; |
1082 | z = 2; | |
ed568912 | 1083 | } |
ed568912 | 1084 | |
a77754a7 KH |
1085 | last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST | |
1086 | DESCRIPTOR_IRQ_ALWAYS | | |
1087 | DESCRIPTOR_BRANCH_ALWAYS); | |
ed568912 | 1088 | |
76f73ca1 JW |
1089 | /* |
1090 | * If the controller and packet generations don't match, we need to | |
1091 | * bail out and try again. If IntEvent.busReset is set, the AT context | |
1092 | * is halted, so appending to the context and trying to run it is | |
1093 | * futile. Most controllers do the right thing and just flush the AT | |
1094 | * queue (per section 7.2.3.2 of the OHCI 1.1 specification), but | |
1095 | * some controllers (like a JMicron JMB381 PCI-e) misbehave and wind | |
1096 | * up stalling out. So we just bail out in software and try again | |
1097 | * later, and everyone is happy. | |
1098 | * FIXME: Document how the locking works. | |
1099 | */ | |
1100 | if (ohci->generation != packet->generation || | |
1101 | reg_read(ohci, OHCI1394_IntEventSet) & OHCI1394_busReset) { | |
19593ffd | 1102 | if (packet->payload_mapped) |
ab88ca48 SR |
1103 | dma_unmap_single(ohci->card.device, payload_bus, |
1104 | packet->payload_length, DMA_TO_DEVICE); | |
f319b6a0 KH |
1105 | packet->ack = RCODE_GENERATION; |
1106 | return -1; | |
1107 | } | |
1108 | ||
1109 | context_append(ctx, d, z, 4 - z); | |
ed568912 | 1110 | |
f319b6a0 | 1111 | /* If the context isn't already running, start it up. */ |
a77754a7 | 1112 | reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs)); |
053b3080 | 1113 | if ((reg & CONTEXT_RUN) == 0) |
f319b6a0 KH |
1114 | context_run(ctx, 0); |
1115 | ||
1116 | return 0; | |
ed568912 KH |
1117 | } |
1118 | ||
f319b6a0 KH |
1119 | static int handle_at_packet(struct context *context, |
1120 | struct descriptor *d, | |
1121 | struct descriptor *last) | |
ed568912 | 1122 | { |
f319b6a0 | 1123 | struct driver_data *driver_data; |
ed568912 | 1124 | struct fw_packet *packet; |
f319b6a0 | 1125 | struct fw_ohci *ohci = context->ohci; |
ed568912 KH |
1126 | int evt; |
1127 | ||
f319b6a0 KH |
1128 | if (last->transfer_status == 0) |
1129 | /* This descriptor isn't done yet, stop iteration. */ | |
1130 | return 0; | |
ed568912 | 1131 | |
f319b6a0 KH |
1132 | driver_data = (struct driver_data *) &d[3]; |
1133 | packet = driver_data->packet; | |
1134 | if (packet == NULL) | |
1135 | /* This packet was cancelled, just continue. */ | |
1136 | return 1; | |
730c32f5 | 1137 | |
19593ffd | 1138 | if (packet->payload_mapped) |
1d1dc5e8 | 1139 | dma_unmap_single(ohci->card.device, packet->payload_bus, |
ed568912 | 1140 | packet->payload_length, DMA_TO_DEVICE); |
ed568912 | 1141 | |
f319b6a0 KH |
1142 | evt = le16_to_cpu(last->transfer_status) & 0x1f; |
1143 | packet->timestamp = le16_to_cpu(last->res_count); | |
ed568912 | 1144 | |
ad3c0fe8 SR |
1145 | log_ar_at_event('T', packet->speed, packet->header, evt); |
1146 | ||
f319b6a0 KH |
1147 | switch (evt) { |
1148 | case OHCI1394_evt_timeout: | |
1149 | /* Async response transmit timed out. */ | |
1150 | packet->ack = RCODE_CANCELLED; | |
1151 | break; | |
ed568912 | 1152 | |
f319b6a0 | 1153 | case OHCI1394_evt_flushed: |
c781c06d KH |
1154 | /* |
1155 | * The packet was flushed should give same error as | |
1156 | * when we try to use a stale generation count. | |
1157 | */ | |
f319b6a0 KH |
1158 | packet->ack = RCODE_GENERATION; |
1159 | break; | |
ed568912 | 1160 | |
f319b6a0 | 1161 | case OHCI1394_evt_missing_ack: |
c781c06d KH |
1162 | /* |
1163 | * Using a valid (current) generation count, but the | |
1164 | * node is not on the bus or not sending acks. | |
1165 | */ | |
f319b6a0 KH |
1166 | packet->ack = RCODE_NO_ACK; |
1167 | break; | |
ed568912 | 1168 | |
f319b6a0 KH |
1169 | case ACK_COMPLETE + 0x10: |
1170 | case ACK_PENDING + 0x10: | |
1171 | case ACK_BUSY_X + 0x10: | |
1172 | case ACK_BUSY_A + 0x10: | |
1173 | case ACK_BUSY_B + 0x10: | |
1174 | case ACK_DATA_ERROR + 0x10: | |
1175 | case ACK_TYPE_ERROR + 0x10: | |
1176 | packet->ack = evt - 0x10; | |
1177 | break; | |
ed568912 | 1178 | |
f319b6a0 KH |
1179 | default: |
1180 | packet->ack = RCODE_SEND_ERROR; | |
1181 | break; | |
1182 | } | |
ed568912 | 1183 | |
f319b6a0 | 1184 | packet->callback(packet, &ohci->card, packet->ack); |
ed568912 | 1185 | |
f319b6a0 | 1186 | return 1; |
ed568912 KH |
1187 | } |
1188 | ||
a77754a7 KH |
1189 | #define HEADER_GET_DESTINATION(q) (((q) >> 16) & 0xffff) |
1190 | #define HEADER_GET_TCODE(q) (((q) >> 4) & 0x0f) | |
1191 | #define HEADER_GET_OFFSET_HIGH(q) (((q) >> 0) & 0xffff) | |
1192 | #define HEADER_GET_DATA_LENGTH(q) (((q) >> 16) & 0xffff) | |
1193 | #define HEADER_GET_EXTENDED_TCODE(q) (((q) >> 0) & 0xffff) | |
93c4cceb | 1194 | |
53dca511 SR |
1195 | static void handle_local_rom(struct fw_ohci *ohci, |
1196 | struct fw_packet *packet, u32 csr) | |
93c4cceb KH |
1197 | { |
1198 | struct fw_packet response; | |
1199 | int tcode, length, i; | |
1200 | ||
a77754a7 | 1201 | tcode = HEADER_GET_TCODE(packet->header[0]); |
93c4cceb | 1202 | if (TCODE_IS_BLOCK_PACKET(tcode)) |
a77754a7 | 1203 | length = HEADER_GET_DATA_LENGTH(packet->header[3]); |
93c4cceb KH |
1204 | else |
1205 | length = 4; | |
1206 | ||
1207 | i = csr - CSR_CONFIG_ROM; | |
1208 | if (i + length > CONFIG_ROM_SIZE) { | |
1209 | fw_fill_response(&response, packet->header, | |
1210 | RCODE_ADDRESS_ERROR, NULL, 0); | |
1211 | } else if (!TCODE_IS_READ_REQUEST(tcode)) { | |
1212 | fw_fill_response(&response, packet->header, | |
1213 | RCODE_TYPE_ERROR, NULL, 0); | |
1214 | } else { | |
1215 | fw_fill_response(&response, packet->header, RCODE_COMPLETE, | |
1216 | (void *) ohci->config_rom + i, length); | |
1217 | } | |
1218 | ||
1219 | fw_core_handle_response(&ohci->card, &response); | |
1220 | } | |
1221 | ||
53dca511 SR |
1222 | static void handle_local_lock(struct fw_ohci *ohci, |
1223 | struct fw_packet *packet, u32 csr) | |
93c4cceb KH |
1224 | { |
1225 | struct fw_packet response; | |
1226 | int tcode, length, ext_tcode, sel; | |
1227 | __be32 *payload, lock_old; | |
1228 | u32 lock_arg, lock_data; | |
1229 | ||
a77754a7 KH |
1230 | tcode = HEADER_GET_TCODE(packet->header[0]); |
1231 | length = HEADER_GET_DATA_LENGTH(packet->header[3]); | |
93c4cceb | 1232 | payload = packet->payload; |
a77754a7 | 1233 | ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]); |
93c4cceb KH |
1234 | |
1235 | if (tcode == TCODE_LOCK_REQUEST && | |
1236 | ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) { | |
1237 | lock_arg = be32_to_cpu(payload[0]); | |
1238 | lock_data = be32_to_cpu(payload[1]); | |
1239 | } else if (tcode == TCODE_READ_QUADLET_REQUEST) { | |
1240 | lock_arg = 0; | |
1241 | lock_data = 0; | |
1242 | } else { | |
1243 | fw_fill_response(&response, packet->header, | |
1244 | RCODE_TYPE_ERROR, NULL, 0); | |
1245 | goto out; | |
1246 | } | |
1247 | ||
1248 | sel = (csr - CSR_BUS_MANAGER_ID) / 4; | |
1249 | reg_write(ohci, OHCI1394_CSRData, lock_data); | |
1250 | reg_write(ohci, OHCI1394_CSRCompareData, lock_arg); | |
1251 | reg_write(ohci, OHCI1394_CSRControl, sel); | |
1252 | ||
1253 | if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000) | |
1254 | lock_old = cpu_to_be32(reg_read(ohci, OHCI1394_CSRData)); | |
1255 | else | |
1256 | fw_notify("swap not done yet\n"); | |
1257 | ||
1258 | fw_fill_response(&response, packet->header, | |
2d826cc5 | 1259 | RCODE_COMPLETE, &lock_old, sizeof(lock_old)); |
93c4cceb KH |
1260 | out: |
1261 | fw_core_handle_response(&ohci->card, &response); | |
1262 | } | |
1263 | ||
53dca511 | 1264 | static void handle_local_request(struct context *ctx, struct fw_packet *packet) |
93c4cceb KH |
1265 | { |
1266 | u64 offset; | |
1267 | u32 csr; | |
1268 | ||
473d28c7 KH |
1269 | if (ctx == &ctx->ohci->at_request_ctx) { |
1270 | packet->ack = ACK_PENDING; | |
1271 | packet->callback(packet, &ctx->ohci->card, packet->ack); | |
1272 | } | |
93c4cceb KH |
1273 | |
1274 | offset = | |
1275 | ((unsigned long long) | |
a77754a7 | 1276 | HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) | |
93c4cceb KH |
1277 | packet->header[2]; |
1278 | csr = offset - CSR_REGISTER_BASE; | |
1279 | ||
1280 | /* Handle config rom reads. */ | |
1281 | if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END) | |
1282 | handle_local_rom(ctx->ohci, packet, csr); | |
1283 | else switch (csr) { | |
1284 | case CSR_BUS_MANAGER_ID: | |
1285 | case CSR_BANDWIDTH_AVAILABLE: | |
1286 | case CSR_CHANNELS_AVAILABLE_HI: | |
1287 | case CSR_CHANNELS_AVAILABLE_LO: | |
1288 | handle_local_lock(ctx->ohci, packet, csr); | |
1289 | break; | |
1290 | default: | |
1291 | if (ctx == &ctx->ohci->at_request_ctx) | |
1292 | fw_core_handle_request(&ctx->ohci->card, packet); | |
1293 | else | |
1294 | fw_core_handle_response(&ctx->ohci->card, packet); | |
1295 | break; | |
1296 | } | |
473d28c7 KH |
1297 | |
1298 | if (ctx == &ctx->ohci->at_response_ctx) { | |
1299 | packet->ack = ACK_COMPLETE; | |
1300 | packet->callback(packet, &ctx->ohci->card, packet->ack); | |
1301 | } | |
93c4cceb | 1302 | } |
e636fe25 | 1303 | |
53dca511 | 1304 | static void at_context_transmit(struct context *ctx, struct fw_packet *packet) |
ed568912 | 1305 | { |
ed568912 | 1306 | unsigned long flags; |
2dbd7d7e | 1307 | int ret; |
ed568912 KH |
1308 | |
1309 | spin_lock_irqsave(&ctx->ohci->lock, flags); | |
1310 | ||
a77754a7 | 1311 | if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id && |
e636fe25 | 1312 | ctx->ohci->generation == packet->generation) { |
93c4cceb KH |
1313 | spin_unlock_irqrestore(&ctx->ohci->lock, flags); |
1314 | handle_local_request(ctx, packet); | |
1315 | return; | |
e636fe25 | 1316 | } |
ed568912 | 1317 | |
2dbd7d7e | 1318 | ret = at_context_queue_packet(ctx, packet); |
ed568912 KH |
1319 | spin_unlock_irqrestore(&ctx->ohci->lock, flags); |
1320 | ||
2dbd7d7e | 1321 | if (ret < 0) |
f319b6a0 | 1322 | packet->callback(packet, &ctx->ohci->card, packet->ack); |
a186b4a6 | 1323 | |
ed568912 KH |
1324 | } |
1325 | ||
a48777e0 CL |
1326 | static u32 cycle_timer_ticks(u32 cycle_timer) |
1327 | { | |
1328 | u32 ticks; | |
1329 | ||
1330 | ticks = cycle_timer & 0xfff; | |
1331 | ticks += 3072 * ((cycle_timer >> 12) & 0x1fff); | |
1332 | ticks += (3072 * 8000) * (cycle_timer >> 25); | |
1333 | ||
1334 | return ticks; | |
1335 | } | |
1336 | ||
1337 | /* | |
1338 | * Some controllers exhibit one or more of the following bugs when updating the | |
1339 | * iso cycle timer register: | |
1340 | * - When the lowest six bits are wrapping around to zero, a read that happens | |
1341 | * at the same time will return garbage in the lowest ten bits. | |
1342 | * - When the cycleOffset field wraps around to zero, the cycleCount field is | |
1343 | * not incremented for about 60 ns. | |
1344 | * - Occasionally, the entire register reads zero. | |
1345 | * | |
1346 | * To catch these, we read the register three times and ensure that the | |
1347 | * difference between each two consecutive reads is approximately the same, i.e. | |
1348 | * less than twice the other. Furthermore, any negative difference indicates an | |
1349 | * error. (A PCI read should take at least 20 ticks of the 24.576 MHz timer to | |
1350 | * execute, so we have enough precision to compute the ratio of the differences.) | |
1351 | */ | |
1352 | static u32 get_cycle_time(struct fw_ohci *ohci) | |
1353 | { | |
1354 | u32 c0, c1, c2; | |
1355 | u32 t0, t1, t2; | |
1356 | s32 diff01, diff12; | |
1357 | int i; | |
1358 | ||
1359 | c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer); | |
1360 | ||
1361 | if (ohci->quirks & QUIRK_CYCLE_TIMER) { | |
1362 | i = 0; | |
1363 | c1 = c2; | |
1364 | c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer); | |
1365 | do { | |
1366 | c0 = c1; | |
1367 | c1 = c2; | |
1368 | c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer); | |
1369 | t0 = cycle_timer_ticks(c0); | |
1370 | t1 = cycle_timer_ticks(c1); | |
1371 | t2 = cycle_timer_ticks(c2); | |
1372 | diff01 = t1 - t0; | |
1373 | diff12 = t2 - t1; | |
1374 | } while ((diff01 <= 0 || diff12 <= 0 || | |
1375 | diff01 / diff12 >= 2 || diff12 / diff01 >= 2) | |
1376 | && i++ < 20); | |
1377 | } | |
1378 | ||
1379 | return c2; | |
1380 | } | |
1381 | ||
1382 | /* | |
1383 | * This function has to be called at least every 64 seconds. The bus_time | |
1384 | * field stores not only the upper 25 bits of the BUS_TIME register but also | |
1385 | * the most significant bit of the cycle timer in bit 6 so that we can detect | |
1386 | * changes in this bit. | |
1387 | */ | |
1388 | static u32 update_bus_time(struct fw_ohci *ohci) | |
1389 | { | |
1390 | u32 cycle_time_seconds = get_cycle_time(ohci) >> 25; | |
1391 | ||
1392 | if ((ohci->bus_time & 0x40) != (cycle_time_seconds & 0x40)) | |
1393 | ohci->bus_time += 0x40; | |
1394 | ||
1395 | return ohci->bus_time | cycle_time_seconds; | |
1396 | } | |
1397 | ||
ed568912 KH |
1398 | static void bus_reset_tasklet(unsigned long data) |
1399 | { | |
1400 | struct fw_ohci *ohci = (struct fw_ohci *)data; | |
e636fe25 | 1401 | int self_id_count, i, j, reg; |
ed568912 KH |
1402 | int generation, new_generation; |
1403 | unsigned long flags; | |
4eaff7d6 SR |
1404 | void *free_rom = NULL; |
1405 | dma_addr_t free_rom_bus = 0; | |
4ffb7a6a | 1406 | bool is_new_root; |
ed568912 KH |
1407 | |
1408 | reg = reg_read(ohci, OHCI1394_NodeID); | |
1409 | if (!(reg & OHCI1394_NodeID_idValid)) { | |
02ff8f8e | 1410 | fw_notify("node ID not valid, new bus reset in progress\n"); |
ed568912 KH |
1411 | return; |
1412 | } | |
02ff8f8e SR |
1413 | if ((reg & OHCI1394_NodeID_nodeNumber) == 63) { |
1414 | fw_notify("malconfigured bus\n"); | |
1415 | return; | |
1416 | } | |
1417 | ohci->node_id = reg & (OHCI1394_NodeID_busNumber | | |
1418 | OHCI1394_NodeID_nodeNumber); | |
ed568912 | 1419 | |
4ffb7a6a CL |
1420 | is_new_root = (reg & OHCI1394_NodeID_root) != 0; |
1421 | if (!(ohci->is_root && is_new_root)) | |
1422 | reg_write(ohci, OHCI1394_LinkControlSet, | |
1423 | OHCI1394_LinkControl_cycleMaster); | |
1424 | ohci->is_root = is_new_root; | |
1425 | ||
c8a9a498 SR |
1426 | reg = reg_read(ohci, OHCI1394_SelfIDCount); |
1427 | if (reg & OHCI1394_SelfIDCount_selfIDError) { | |
1428 | fw_notify("inconsistent self IDs\n"); | |
1429 | return; | |
1430 | } | |
c781c06d KH |
1431 | /* |
1432 | * The count in the SelfIDCount register is the number of | |
ed568912 KH |
1433 | * bytes in the self ID receive buffer. Since we also receive |
1434 | * the inverted quadlets and a header quadlet, we shift one | |
c781c06d KH |
1435 | * bit extra to get the actual number of self IDs. |
1436 | */ | |
928ec5f1 SR |
1437 | self_id_count = (reg >> 3) & 0xff; |
1438 | if (self_id_count == 0 || self_id_count > 252) { | |
016bf3df SR |
1439 | fw_notify("inconsistent self IDs\n"); |
1440 | return; | |
1441 | } | |
11bf20ad | 1442 | generation = (cond_le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff; |
ee71c2f9 | 1443 | rmb(); |
ed568912 KH |
1444 | |
1445 | for (i = 1, j = 0; j < self_id_count; i += 2, j++) { | |
c8a9a498 SR |
1446 | if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1]) { |
1447 | fw_notify("inconsistent self IDs\n"); | |
1448 | return; | |
1449 | } | |
11bf20ad SR |
1450 | ohci->self_id_buffer[j] = |
1451 | cond_le32_to_cpu(ohci->self_id_cpu[i]); | |
ed568912 | 1452 | } |
ee71c2f9 | 1453 | rmb(); |
ed568912 | 1454 | |
c781c06d KH |
1455 | /* |
1456 | * Check the consistency of the self IDs we just read. The | |
ed568912 KH |
1457 | * problem we face is that a new bus reset can start while we |
1458 | * read out the self IDs from the DMA buffer. If this happens, | |
1459 | * the DMA buffer will be overwritten with new self IDs and we | |
1460 | * will read out inconsistent data. The OHCI specification | |
1461 | * (section 11.2) recommends a technique similar to | |
1462 | * linux/seqlock.h, where we remember the generation of the | |
1463 | * self IDs in the buffer before reading them out and compare | |
1464 | * it to the current generation after reading them out. If | |
1465 | * the two generations match we know we have a consistent set | |
c781c06d KH |
1466 | * of self IDs. |
1467 | */ | |
ed568912 KH |
1468 | |
1469 | new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff; | |
1470 | if (new_generation != generation) { | |
1471 | fw_notify("recursive bus reset detected, " | |
1472 | "discarding self ids\n"); | |
1473 | return; | |
1474 | } | |
1475 | ||
1476 | /* FIXME: Document how the locking works. */ | |
1477 | spin_lock_irqsave(&ohci->lock, flags); | |
1478 | ||
1479 | ohci->generation = generation; | |
f319b6a0 KH |
1480 | context_stop(&ohci->at_request_ctx); |
1481 | context_stop(&ohci->at_response_ctx); | |
ed568912 KH |
1482 | reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset); |
1483 | ||
4a635593 | 1484 | if (ohci->quirks & QUIRK_RESET_PACKET) |
d34316a4 SR |
1485 | ohci->request_generation = generation; |
1486 | ||
c781c06d KH |
1487 | /* |
1488 | * This next bit is unrelated to the AT context stuff but we | |
ed568912 KH |
1489 | * have to do it under the spinlock also. If a new config rom |
1490 | * was set up before this reset, the old one is now no longer | |
1491 | * in use and we can free it. Update the config rom pointers | |
1492 | * to point to the current config rom and clear the | |
c781c06d KH |
1493 | * next_config_rom pointer so a new udpate can take place. |
1494 | */ | |
ed568912 KH |
1495 | |
1496 | if (ohci->next_config_rom != NULL) { | |
0bd243c4 KH |
1497 | if (ohci->next_config_rom != ohci->config_rom) { |
1498 | free_rom = ohci->config_rom; | |
1499 | free_rom_bus = ohci->config_rom_bus; | |
1500 | } | |
ed568912 KH |
1501 | ohci->config_rom = ohci->next_config_rom; |
1502 | ohci->config_rom_bus = ohci->next_config_rom_bus; | |
1503 | ohci->next_config_rom = NULL; | |
1504 | ||
c781c06d KH |
1505 | /* |
1506 | * Restore config_rom image and manually update | |
ed568912 KH |
1507 | * config_rom registers. Writing the header quadlet |
1508 | * will indicate that the config rom is ready, so we | |
c781c06d KH |
1509 | * do that last. |
1510 | */ | |
ed568912 KH |
1511 | reg_write(ohci, OHCI1394_BusOptions, |
1512 | be32_to_cpu(ohci->config_rom[2])); | |
8e85973e SR |
1513 | ohci->config_rom[0] = ohci->next_header; |
1514 | reg_write(ohci, OHCI1394_ConfigROMhdr, | |
1515 | be32_to_cpu(ohci->next_header)); | |
ed568912 KH |
1516 | } |
1517 | ||
080de8c2 SR |
1518 | #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA |
1519 | reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0); | |
1520 | reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0); | |
1521 | #endif | |
1522 | ||
ed568912 KH |
1523 | spin_unlock_irqrestore(&ohci->lock, flags); |
1524 | ||
4eaff7d6 SR |
1525 | if (free_rom) |
1526 | dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, | |
1527 | free_rom, free_rom_bus); | |
1528 | ||
08ddb2f4 SR |
1529 | log_selfids(ohci->node_id, generation, |
1530 | self_id_count, ohci->self_id_buffer); | |
ad3c0fe8 | 1531 | |
e636fe25 | 1532 | fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation, |
c8a94ded SR |
1533 | self_id_count, ohci->self_id_buffer, |
1534 | ohci->csr_state_setclear_abdicate); | |
1535 | ohci->csr_state_setclear_abdicate = false; | |
ed568912 KH |
1536 | } |
1537 | ||
1538 | static irqreturn_t irq_handler(int irq, void *data) | |
1539 | { | |
1540 | struct fw_ohci *ohci = data; | |
168cf9af | 1541 | u32 event, iso_event; |
ed568912 KH |
1542 | int i; |
1543 | ||
1544 | event = reg_read(ohci, OHCI1394_IntEventClear); | |
1545 | ||
a515958d | 1546 | if (!event || !~event) |
ed568912 KH |
1547 | return IRQ_NONE; |
1548 | ||
a007bb85 SR |
1549 | /* busReset must not be cleared yet, see OHCI 1.1 clause 7.2.3.2 */ |
1550 | reg_write(ohci, OHCI1394_IntEventClear, event & ~OHCI1394_busReset); | |
ad3c0fe8 | 1551 | log_irqs(event); |
ed568912 KH |
1552 | |
1553 | if (event & OHCI1394_selfIDComplete) | |
1554 | tasklet_schedule(&ohci->bus_reset_tasklet); | |
1555 | ||
1556 | if (event & OHCI1394_RQPkt) | |
1557 | tasklet_schedule(&ohci->ar_request_ctx.tasklet); | |
1558 | ||
1559 | if (event & OHCI1394_RSPkt) | |
1560 | tasklet_schedule(&ohci->ar_response_ctx.tasklet); | |
1561 | ||
1562 | if (event & OHCI1394_reqTxComplete) | |
1563 | tasklet_schedule(&ohci->at_request_ctx.tasklet); | |
1564 | ||
1565 | if (event & OHCI1394_respTxComplete) | |
1566 | tasklet_schedule(&ohci->at_response_ctx.tasklet); | |
1567 | ||
c889475f | 1568 | iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear); |
ed568912 KH |
1569 | reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event); |
1570 | ||
1571 | while (iso_event) { | |
1572 | i = ffs(iso_event) - 1; | |
30200739 | 1573 | tasklet_schedule(&ohci->ir_context_list[i].context.tasklet); |
ed568912 KH |
1574 | iso_event &= ~(1 << i); |
1575 | } | |
1576 | ||
c889475f | 1577 | iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear); |
ed568912 KH |
1578 | reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event); |
1579 | ||
1580 | while (iso_event) { | |
1581 | i = ffs(iso_event) - 1; | |
30200739 | 1582 | tasklet_schedule(&ohci->it_context_list[i].context.tasklet); |
ed568912 KH |
1583 | iso_event &= ~(1 << i); |
1584 | } | |
1585 | ||
75f7832e JW |
1586 | if (unlikely(event & OHCI1394_regAccessFail)) |
1587 | fw_error("Register access failure - " | |
1588 | "please notify linux1394-devel@lists.sf.net\n"); | |
1589 | ||
e524f616 SR |
1590 | if (unlikely(event & OHCI1394_postedWriteErr)) |
1591 | fw_error("PCI posted write error\n"); | |
1592 | ||
bb9f2206 SR |
1593 | if (unlikely(event & OHCI1394_cycleTooLong)) { |
1594 | if (printk_ratelimit()) | |
1595 | fw_notify("isochronous cycle too long\n"); | |
1596 | reg_write(ohci, OHCI1394_LinkControlSet, | |
1597 | OHCI1394_LinkControl_cycleMaster); | |
1598 | } | |
1599 | ||
5ed1f321 JF |
1600 | if (unlikely(event & OHCI1394_cycleInconsistent)) { |
1601 | /* | |
1602 | * We need to clear this event bit in order to make | |
1603 | * cycleMatch isochronous I/O work. In theory we should | |
1604 | * stop active cycleMatch iso contexts now and restart | |
1605 | * them at least two cycles later. (FIXME?) | |
1606 | */ | |
1607 | if (printk_ratelimit()) | |
1608 | fw_notify("isochronous cycle inconsistent\n"); | |
1609 | } | |
1610 | ||
a48777e0 CL |
1611 | if (event & OHCI1394_cycle64Seconds) { |
1612 | spin_lock(&ohci->lock); | |
1613 | update_bus_time(ohci); | |
1614 | spin_unlock(&ohci->lock); | |
1615 | } | |
1616 | ||
ed568912 KH |
1617 | return IRQ_HANDLED; |
1618 | } | |
1619 | ||
2aef469a KH |
1620 | static int software_reset(struct fw_ohci *ohci) |
1621 | { | |
1622 | int i; | |
1623 | ||
1624 | reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset); | |
1625 | ||
1626 | for (i = 0; i < OHCI_LOOP_COUNT; i++) { | |
1627 | if ((reg_read(ohci, OHCI1394_HCControlSet) & | |
1628 | OHCI1394_HCControl_softReset) == 0) | |
1629 | return 0; | |
1630 | msleep(1); | |
1631 | } | |
1632 | ||
1633 | return -EBUSY; | |
1634 | } | |
1635 | ||
8e85973e SR |
1636 | static void copy_config_rom(__be32 *dest, const __be32 *src, size_t length) |
1637 | { | |
1638 | size_t size = length * 4; | |
1639 | ||
1640 | memcpy(dest, src, size); | |
1641 | if (size < CONFIG_ROM_SIZE) | |
1642 | memset(&dest[length], 0, CONFIG_ROM_SIZE - size); | |
1643 | } | |
1644 | ||
925e7a65 CL |
1645 | static int configure_1394a_enhancements(struct fw_ohci *ohci) |
1646 | { | |
1647 | bool enable_1394a; | |
35d999b1 | 1648 | int ret, clear, set, offset; |
925e7a65 CL |
1649 | |
1650 | /* Check if the driver should configure link and PHY. */ | |
1651 | if (!(reg_read(ohci, OHCI1394_HCControlSet) & | |
1652 | OHCI1394_HCControl_programPhyEnable)) | |
1653 | return 0; | |
1654 | ||
1655 | /* Paranoia: check whether the PHY supports 1394a, too. */ | |
1656 | enable_1394a = false; | |
35d999b1 SR |
1657 | ret = read_phy_reg(ohci, 2); |
1658 | if (ret < 0) | |
1659 | return ret; | |
1660 | if ((ret & PHY_EXTENDED_REGISTERS) == PHY_EXTENDED_REGISTERS) { | |
1661 | ret = read_paged_phy_reg(ohci, 1, 8); | |
1662 | if (ret < 0) | |
1663 | return ret; | |
1664 | if (ret >= 1) | |
925e7a65 CL |
1665 | enable_1394a = true; |
1666 | } | |
1667 | ||
1668 | if (ohci->quirks & QUIRK_NO_1394A) | |
1669 | enable_1394a = false; | |
1670 | ||
1671 | /* Configure PHY and link consistently. */ | |
1672 | if (enable_1394a) { | |
1673 | clear = 0; | |
1674 | set = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI; | |
1675 | } else { | |
1676 | clear = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI; | |
1677 | set = 0; | |
1678 | } | |
35d999b1 SR |
1679 | ret = ohci_update_phy_reg(&ohci->card, 5, clear, set); |
1680 | if (ret < 0) | |
1681 | return ret; | |
925e7a65 CL |
1682 | |
1683 | if (enable_1394a) | |
1684 | offset = OHCI1394_HCControlSet; | |
1685 | else | |
1686 | offset = OHCI1394_HCControlClear; | |
1687 | reg_write(ohci, offset, OHCI1394_HCControl_aPhyEnhanceEnable); | |
1688 | ||
1689 | /* Clean up: configuration has been taken care of. */ | |
1690 | reg_write(ohci, OHCI1394_HCControlClear, | |
1691 | OHCI1394_HCControl_programPhyEnable); | |
1692 | ||
1693 | return 0; | |
1694 | } | |
1695 | ||
8e85973e SR |
1696 | static int ohci_enable(struct fw_card *card, |
1697 | const __be32 *config_rom, size_t length) | |
ed568912 KH |
1698 | { |
1699 | struct fw_ohci *ohci = fw_ohci(card); | |
1700 | struct pci_dev *dev = to_pci_dev(card->device); | |
e91b2787 | 1701 | u32 lps, seconds, version, irqs; |
35d999b1 | 1702 | int i, ret; |
ed568912 | 1703 | |
2aef469a KH |
1704 | if (software_reset(ohci)) { |
1705 | fw_error("Failed to reset ohci card.\n"); | |
1706 | return -EBUSY; | |
1707 | } | |
1708 | ||
1709 | /* | |
1710 | * Now enable LPS, which we need in order to start accessing | |
1711 | * most of the registers. In fact, on some cards (ALI M5251), | |
1712 | * accessing registers in the SClk domain without LPS enabled | |
1713 | * will lock up the machine. Wait 50msec to make sure we have | |
02214724 JW |
1714 | * full link enabled. However, with some cards (well, at least |
1715 | * a JMicron PCIe card), we have to try again sometimes. | |
2aef469a KH |
1716 | */ |
1717 | reg_write(ohci, OHCI1394_HCControlSet, | |
1718 | OHCI1394_HCControl_LPS | | |
1719 | OHCI1394_HCControl_postedWriteEnable); | |
1720 | flush_writes(ohci); | |
02214724 JW |
1721 | |
1722 | for (lps = 0, i = 0; !lps && i < 3; i++) { | |
1723 | msleep(50); | |
1724 | lps = reg_read(ohci, OHCI1394_HCControlSet) & | |
1725 | OHCI1394_HCControl_LPS; | |
1726 | } | |
1727 | ||
1728 | if (!lps) { | |
1729 | fw_error("Failed to set Link Power Status\n"); | |
1730 | return -EIO; | |
1731 | } | |
2aef469a KH |
1732 | |
1733 | reg_write(ohci, OHCI1394_HCControlClear, | |
1734 | OHCI1394_HCControl_noByteSwapData); | |
1735 | ||
affc9c24 | 1736 | reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus); |
e896ec43 SR |
1737 | reg_write(ohci, OHCI1394_LinkControlClear, |
1738 | OHCI1394_LinkControl_rcvPhyPkt); | |
2aef469a KH |
1739 | reg_write(ohci, OHCI1394_LinkControlSet, |
1740 | OHCI1394_LinkControl_rcvSelfID | | |
1741 | OHCI1394_LinkControl_cycleTimerEnable | | |
1742 | OHCI1394_LinkControl_cycleMaster); | |
1743 | ||
1744 | reg_write(ohci, OHCI1394_ATRetries, | |
1745 | OHCI1394_MAX_AT_REQ_RETRIES | | |
1746 | (OHCI1394_MAX_AT_RESP_RETRIES << 4) | | |
27a2329f CL |
1747 | (OHCI1394_MAX_PHYS_RESP_RETRIES << 8) | |
1748 | (200 << 16)); | |
2aef469a | 1749 | |
a48777e0 CL |
1750 | seconds = lower_32_bits(get_seconds()); |
1751 | reg_write(ohci, OHCI1394_IsochronousCycleTimer, seconds << 25); | |
1752 | ohci->bus_time = seconds & ~0x3f; | |
1753 | ||
e91b2787 CL |
1754 | version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff; |
1755 | if (version >= OHCI_VERSION_1_1) { | |
1756 | reg_write(ohci, OHCI1394_InitialChannelsAvailableHi, | |
1757 | 0xfffffffe); | |
db3c9cc1 | 1758 | card->broadcast_channel_auto_allocated = true; |
e91b2787 CL |
1759 | } |
1760 | ||
a1a1132b CL |
1761 | /* Get implemented bits of the priority arbitration request counter. */ |
1762 | reg_write(ohci, OHCI1394_FairnessControl, 0x3f); | |
1763 | ohci->pri_req_max = reg_read(ohci, OHCI1394_FairnessControl) & 0x3f; | |
1764 | reg_write(ohci, OHCI1394_FairnessControl, 0); | |
db3c9cc1 | 1765 | card->priority_budget_implemented = ohci->pri_req_max != 0; |
a1a1132b | 1766 | |
2aef469a KH |
1767 | ar_context_run(&ohci->ar_request_ctx); |
1768 | ar_context_run(&ohci->ar_response_ctx); | |
1769 | ||
2aef469a KH |
1770 | reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000); |
1771 | reg_write(ohci, OHCI1394_IntEventClear, ~0); | |
1772 | reg_write(ohci, OHCI1394_IntMaskClear, ~0); | |
2aef469a | 1773 | |
35d999b1 SR |
1774 | ret = configure_1394a_enhancements(ohci); |
1775 | if (ret < 0) | |
1776 | return ret; | |
925e7a65 | 1777 | |
2aef469a | 1778 | /* Activate link_on bit and contender bit in our self ID packets.*/ |
35d999b1 SR |
1779 | ret = ohci_update_phy_reg(card, 4, 0, PHY_LINK_ACTIVE | PHY_CONTENDER); |
1780 | if (ret < 0) | |
1781 | return ret; | |
2aef469a | 1782 | |
c781c06d KH |
1783 | /* |
1784 | * When the link is not yet enabled, the atomic config rom | |
ed568912 KH |
1785 | * update mechanism described below in ohci_set_config_rom() |
1786 | * is not active. We have to update ConfigRomHeader and | |
1787 | * BusOptions manually, and the write to ConfigROMmap takes | |
1788 | * effect immediately. We tie this to the enabling of the | |
1789 | * link, so we have a valid config rom before enabling - the | |
1790 | * OHCI requires that ConfigROMhdr and BusOptions have valid | |
1791 | * values before enabling. | |
1792 | * | |
1793 | * However, when the ConfigROMmap is written, some controllers | |
1794 | * always read back quadlets 0 and 2 from the config rom to | |
1795 | * the ConfigRomHeader and BusOptions registers on bus reset. | |
1796 | * They shouldn't do that in this initial case where the link | |
1797 | * isn't enabled. This means we have to use the same | |
1798 | * workaround here, setting the bus header to 0 and then write | |
1799 | * the right values in the bus reset tasklet. | |
1800 | */ | |
1801 | ||
0bd243c4 KH |
1802 | if (config_rom) { |
1803 | ohci->next_config_rom = | |
1804 | dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE, | |
1805 | &ohci->next_config_rom_bus, | |
1806 | GFP_KERNEL); | |
1807 | if (ohci->next_config_rom == NULL) | |
1808 | return -ENOMEM; | |
ed568912 | 1809 | |
8e85973e | 1810 | copy_config_rom(ohci->next_config_rom, config_rom, length); |
0bd243c4 KH |
1811 | } else { |
1812 | /* | |
1813 | * In the suspend case, config_rom is NULL, which | |
1814 | * means that we just reuse the old config rom. | |
1815 | */ | |
1816 | ohci->next_config_rom = ohci->config_rom; | |
1817 | ohci->next_config_rom_bus = ohci->config_rom_bus; | |
1818 | } | |
ed568912 | 1819 | |
8e85973e | 1820 | ohci->next_header = ohci->next_config_rom[0]; |
ed568912 KH |
1821 | ohci->next_config_rom[0] = 0; |
1822 | reg_write(ohci, OHCI1394_ConfigROMhdr, 0); | |
0bd243c4 KH |
1823 | reg_write(ohci, OHCI1394_BusOptions, |
1824 | be32_to_cpu(ohci->next_config_rom[2])); | |
ed568912 KH |
1825 | reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus); |
1826 | ||
1827 | reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000); | |
1828 | ||
262444ee CL |
1829 | if (!(ohci->quirks & QUIRK_NO_MSI)) |
1830 | pci_enable_msi(dev); | |
ed568912 | 1831 | if (request_irq(dev->irq, irq_handler, |
262444ee CL |
1832 | pci_dev_msi_enabled(dev) ? 0 : IRQF_SHARED, |
1833 | ohci_driver_name, ohci)) { | |
1834 | fw_error("Failed to allocate interrupt %d.\n", dev->irq); | |
1835 | pci_disable_msi(dev); | |
ed568912 KH |
1836 | dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, |
1837 | ohci->config_rom, ohci->config_rom_bus); | |
1838 | return -EIO; | |
1839 | } | |
1840 | ||
148c7866 SR |
1841 | irqs = OHCI1394_reqTxComplete | OHCI1394_respTxComplete | |
1842 | OHCI1394_RQPkt | OHCI1394_RSPkt | | |
1843 | OHCI1394_isochTx | OHCI1394_isochRx | | |
1844 | OHCI1394_postedWriteErr | | |
1845 | OHCI1394_selfIDComplete | | |
1846 | OHCI1394_regAccessFail | | |
a48777e0 | 1847 | OHCI1394_cycle64Seconds | |
148c7866 SR |
1848 | OHCI1394_cycleInconsistent | OHCI1394_cycleTooLong | |
1849 | OHCI1394_masterIntEnable; | |
1850 | if (param_debug & OHCI_PARAM_DEBUG_BUSRESETS) | |
1851 | irqs |= OHCI1394_busReset; | |
1852 | reg_write(ohci, OHCI1394_IntMaskSet, irqs); | |
1853 | ||
ed568912 KH |
1854 | reg_write(ohci, OHCI1394_HCControlSet, |
1855 | OHCI1394_HCControl_linkEnable | | |
1856 | OHCI1394_HCControl_BIBimageValid); | |
1857 | flush_writes(ohci); | |
1858 | ||
c781c06d KH |
1859 | /* |
1860 | * We are ready to go, initiate bus reset to finish the | |
1861 | * initialization. | |
1862 | */ | |
ed568912 KH |
1863 | |
1864 | fw_core_initiate_bus_reset(&ohci->card, 1); | |
1865 | ||
1866 | return 0; | |
1867 | } | |
1868 | ||
53dca511 | 1869 | static int ohci_set_config_rom(struct fw_card *card, |
8e85973e | 1870 | const __be32 *config_rom, size_t length) |
ed568912 KH |
1871 | { |
1872 | struct fw_ohci *ohci; | |
1873 | unsigned long flags; | |
2dbd7d7e | 1874 | int ret = -EBUSY; |
ed568912 | 1875 | __be32 *next_config_rom; |
f5101d58 | 1876 | dma_addr_t uninitialized_var(next_config_rom_bus); |
ed568912 KH |
1877 | |
1878 | ohci = fw_ohci(card); | |
1879 | ||
c781c06d KH |
1880 | /* |
1881 | * When the OHCI controller is enabled, the config rom update | |
ed568912 KH |
1882 | * mechanism is a bit tricky, but easy enough to use. See |
1883 | * section 5.5.6 in the OHCI specification. | |
1884 | * | |
1885 | * The OHCI controller caches the new config rom address in a | |
1886 | * shadow register (ConfigROMmapNext) and needs a bus reset | |
1887 | * for the changes to take place. When the bus reset is | |
1888 | * detected, the controller loads the new values for the | |
1889 | * ConfigRomHeader and BusOptions registers from the specified | |
1890 | * config rom and loads ConfigROMmap from the ConfigROMmapNext | |
1891 | * shadow register. All automatically and atomically. | |
1892 | * | |
1893 | * Now, there's a twist to this story. The automatic load of | |
1894 | * ConfigRomHeader and BusOptions doesn't honor the | |
1895 | * noByteSwapData bit, so with a be32 config rom, the | |
1896 | * controller will load be32 values in to these registers | |
1897 | * during the atomic update, even on litte endian | |
1898 | * architectures. The workaround we use is to put a 0 in the | |
1899 | * header quadlet; 0 is endian agnostic and means that the | |
1900 | * config rom isn't ready yet. In the bus reset tasklet we | |
1901 | * then set up the real values for the two registers. | |
1902 | * | |
1903 | * We use ohci->lock to avoid racing with the code that sets | |
1904 | * ohci->next_config_rom to NULL (see bus_reset_tasklet). | |
1905 | */ | |
1906 | ||
1907 | next_config_rom = | |
1908 | dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE, | |
1909 | &next_config_rom_bus, GFP_KERNEL); | |
1910 | if (next_config_rom == NULL) | |
1911 | return -ENOMEM; | |
1912 | ||
1913 | spin_lock_irqsave(&ohci->lock, flags); | |
1914 | ||
1915 | if (ohci->next_config_rom == NULL) { | |
1916 | ohci->next_config_rom = next_config_rom; | |
1917 | ohci->next_config_rom_bus = next_config_rom_bus; | |
1918 | ||
8e85973e | 1919 | copy_config_rom(ohci->next_config_rom, config_rom, length); |
ed568912 KH |
1920 | |
1921 | ohci->next_header = config_rom[0]; | |
1922 | ohci->next_config_rom[0] = 0; | |
1923 | ||
1924 | reg_write(ohci, OHCI1394_ConfigROMmap, | |
1925 | ohci->next_config_rom_bus); | |
2dbd7d7e | 1926 | ret = 0; |
ed568912 KH |
1927 | } |
1928 | ||
1929 | spin_unlock_irqrestore(&ohci->lock, flags); | |
1930 | ||
c781c06d KH |
1931 | /* |
1932 | * Now initiate a bus reset to have the changes take | |
ed568912 KH |
1933 | * effect. We clean up the old config rom memory and DMA |
1934 | * mappings in the bus reset tasklet, since the OHCI | |
1935 | * controller could need to access it before the bus reset | |
c781c06d KH |
1936 | * takes effect. |
1937 | */ | |
2dbd7d7e | 1938 | if (ret == 0) |
ed568912 | 1939 | fw_core_initiate_bus_reset(&ohci->card, 1); |
4eaff7d6 SR |
1940 | else |
1941 | dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, | |
1942 | next_config_rom, next_config_rom_bus); | |
ed568912 | 1943 | |
2dbd7d7e | 1944 | return ret; |
ed568912 KH |
1945 | } |
1946 | ||
1947 | static void ohci_send_request(struct fw_card *card, struct fw_packet *packet) | |
1948 | { | |
1949 | struct fw_ohci *ohci = fw_ohci(card); | |
1950 | ||
1951 | at_context_transmit(&ohci->at_request_ctx, packet); | |
1952 | } | |
1953 | ||
1954 | static void ohci_send_response(struct fw_card *card, struct fw_packet *packet) | |
1955 | { | |
1956 | struct fw_ohci *ohci = fw_ohci(card); | |
1957 | ||
1958 | at_context_transmit(&ohci->at_response_ctx, packet); | |
1959 | } | |
1960 | ||
730c32f5 KH |
1961 | static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet) |
1962 | { | |
1963 | struct fw_ohci *ohci = fw_ohci(card); | |
f319b6a0 KH |
1964 | struct context *ctx = &ohci->at_request_ctx; |
1965 | struct driver_data *driver_data = packet->driver_data; | |
2dbd7d7e | 1966 | int ret = -ENOENT; |
730c32f5 | 1967 | |
f319b6a0 | 1968 | tasklet_disable(&ctx->tasklet); |
730c32f5 | 1969 | |
f319b6a0 KH |
1970 | if (packet->ack != 0) |
1971 | goto out; | |
730c32f5 | 1972 | |
19593ffd | 1973 | if (packet->payload_mapped) |
1d1dc5e8 SR |
1974 | dma_unmap_single(ohci->card.device, packet->payload_bus, |
1975 | packet->payload_length, DMA_TO_DEVICE); | |
1976 | ||
ad3c0fe8 | 1977 | log_ar_at_event('T', packet->speed, packet->header, 0x20); |
f319b6a0 KH |
1978 | driver_data->packet = NULL; |
1979 | packet->ack = RCODE_CANCELLED; | |
1980 | packet->callback(packet, &ohci->card, packet->ack); | |
2dbd7d7e | 1981 | ret = 0; |
f319b6a0 KH |
1982 | out: |
1983 | tasklet_enable(&ctx->tasklet); | |
730c32f5 | 1984 | |
2dbd7d7e | 1985 | return ret; |
730c32f5 KH |
1986 | } |
1987 | ||
53dca511 SR |
1988 | static int ohci_enable_phys_dma(struct fw_card *card, |
1989 | int node_id, int generation) | |
ed568912 | 1990 | { |
080de8c2 SR |
1991 | #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA |
1992 | return 0; | |
1993 | #else | |
ed568912 KH |
1994 | struct fw_ohci *ohci = fw_ohci(card); |
1995 | unsigned long flags; | |
2dbd7d7e | 1996 | int n, ret = 0; |
ed568912 | 1997 | |
c781c06d KH |
1998 | /* |
1999 | * FIXME: Make sure this bitmask is cleared when we clear the busReset | |
2000 | * interrupt bit. Clear physReqResourceAllBuses on bus reset. | |
2001 | */ | |
ed568912 KH |
2002 | |
2003 | spin_lock_irqsave(&ohci->lock, flags); | |
2004 | ||
2005 | if (ohci->generation != generation) { | |
2dbd7d7e | 2006 | ret = -ESTALE; |
ed568912 KH |
2007 | goto out; |
2008 | } | |
2009 | ||
c781c06d KH |
2010 | /* |
2011 | * Note, if the node ID contains a non-local bus ID, physical DMA is | |
2012 | * enabled for _all_ nodes on remote buses. | |
2013 | */ | |
907293d7 SR |
2014 | |
2015 | n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63; | |
2016 | if (n < 32) | |
2017 | reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n); | |
2018 | else | |
2019 | reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32)); | |
2020 | ||
ed568912 | 2021 | flush_writes(ohci); |
ed568912 | 2022 | out: |
6cad95fe | 2023 | spin_unlock_irqrestore(&ohci->lock, flags); |
2dbd7d7e SR |
2024 | |
2025 | return ret; | |
080de8c2 | 2026 | #endif /* CONFIG_FIREWIRE_OHCI_REMOTE_DMA */ |
ed568912 | 2027 | } |
373b2edd | 2028 | |
60d32970 CL |
2029 | static u32 ohci_read_csr_reg(struct fw_card *card, int csr_offset) |
2030 | { | |
2031 | struct fw_ohci *ohci = fw_ohci(card); | |
a48777e0 CL |
2032 | unsigned long flags; |
2033 | u32 value; | |
60d32970 CL |
2034 | |
2035 | switch (csr_offset) { | |
4ffb7a6a CL |
2036 | case CSR_STATE_CLEAR: |
2037 | case CSR_STATE_SET: | |
4ffb7a6a CL |
2038 | if (ohci->is_root && |
2039 | (reg_read(ohci, OHCI1394_LinkControlSet) & | |
2040 | OHCI1394_LinkControl_cycleMaster)) | |
c8a94ded | 2041 | value = CSR_STATE_BIT_CMSTR; |
4ffb7a6a | 2042 | else |
c8a94ded SR |
2043 | value = 0; |
2044 | if (ohci->csr_state_setclear_abdicate) | |
2045 | value |= CSR_STATE_BIT_ABDICATE; | |
2046 | ||
2047 | return value; | |
4ffb7a6a | 2048 | |
506f1a31 CL |
2049 | case CSR_NODE_IDS: |
2050 | return reg_read(ohci, OHCI1394_NodeID) << 16; | |
2051 | ||
60d32970 CL |
2052 | case CSR_CYCLE_TIME: |
2053 | return get_cycle_time(ohci); | |
2054 | ||
a48777e0 CL |
2055 | case CSR_BUS_TIME: |
2056 | /* | |
2057 | * We might be called just after the cycle timer has wrapped | |
2058 | * around but just before the cycle64Seconds handler, so we | |
2059 | * better check here, too, if the bus time needs to be updated. | |
2060 | */ | |
2061 | spin_lock_irqsave(&ohci->lock, flags); | |
2062 | value = update_bus_time(ohci); | |
2063 | spin_unlock_irqrestore(&ohci->lock, flags); | |
2064 | return value; | |
2065 | ||
27a2329f CL |
2066 | case CSR_BUSY_TIMEOUT: |
2067 | value = reg_read(ohci, OHCI1394_ATRetries); | |
2068 | return (value >> 4) & 0x0ffff00f; | |
2069 | ||
a1a1132b CL |
2070 | case CSR_PRIORITY_BUDGET: |
2071 | return (reg_read(ohci, OHCI1394_FairnessControl) & 0x3f) | | |
2072 | (ohci->pri_req_max << 8); | |
2073 | ||
60d32970 CL |
2074 | default: |
2075 | WARN_ON(1); | |
2076 | return 0; | |
2077 | } | |
2078 | } | |
2079 | ||
506f1a31 CL |
2080 | static void ohci_write_csr_reg(struct fw_card *card, int csr_offset, u32 value) |
2081 | { | |
2082 | struct fw_ohci *ohci = fw_ohci(card); | |
a48777e0 | 2083 | unsigned long flags; |
506f1a31 CL |
2084 | |
2085 | switch (csr_offset) { | |
4ffb7a6a | 2086 | case CSR_STATE_CLEAR: |
4ffb7a6a CL |
2087 | if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) { |
2088 | reg_write(ohci, OHCI1394_LinkControlClear, | |
2089 | OHCI1394_LinkControl_cycleMaster); | |
2090 | flush_writes(ohci); | |
2091 | } | |
c8a94ded SR |
2092 | if (value & CSR_STATE_BIT_ABDICATE) |
2093 | ohci->csr_state_setclear_abdicate = false; | |
4ffb7a6a CL |
2094 | break; |
2095 | ||
2096 | case CSR_STATE_SET: | |
2097 | if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) { | |
2098 | reg_write(ohci, OHCI1394_LinkControlSet, | |
2099 | OHCI1394_LinkControl_cycleMaster); | |
2100 | flush_writes(ohci); | |
2101 | } | |
c8a94ded SR |
2102 | if (value & CSR_STATE_BIT_ABDICATE) |
2103 | ohci->csr_state_setclear_abdicate = true; | |
4ffb7a6a CL |
2104 | break; |
2105 | ||
506f1a31 CL |
2106 | case CSR_NODE_IDS: |
2107 | reg_write(ohci, OHCI1394_NodeID, value >> 16); | |
2108 | flush_writes(ohci); | |
2109 | break; | |
2110 | ||
9ab5071c CL |
2111 | case CSR_CYCLE_TIME: |
2112 | reg_write(ohci, OHCI1394_IsochronousCycleTimer, value); | |
2113 | reg_write(ohci, OHCI1394_IntEventSet, | |
2114 | OHCI1394_cycleInconsistent); | |
2115 | flush_writes(ohci); | |
2116 | break; | |
2117 | ||
a48777e0 CL |
2118 | case CSR_BUS_TIME: |
2119 | spin_lock_irqsave(&ohci->lock, flags); | |
2120 | ohci->bus_time = (ohci->bus_time & 0x7f) | (value & ~0x7f); | |
2121 | spin_unlock_irqrestore(&ohci->lock, flags); | |
2122 | break; | |
2123 | ||
27a2329f CL |
2124 | case CSR_BUSY_TIMEOUT: |
2125 | value = (value & 0xf) | ((value & 0xf) << 4) | | |
2126 | ((value & 0xf) << 8) | ((value & 0x0ffff000) << 4); | |
2127 | reg_write(ohci, OHCI1394_ATRetries, value); | |
2128 | flush_writes(ohci); | |
2129 | break; | |
2130 | ||
a1a1132b CL |
2131 | case CSR_PRIORITY_BUDGET: |
2132 | reg_write(ohci, OHCI1394_FairnessControl, value & 0x3f); | |
2133 | flush_writes(ohci); | |
2134 | break; | |
2135 | ||
506f1a31 CL |
2136 | default: |
2137 | WARN_ON(1); | |
2138 | break; | |
2139 | } | |
2140 | } | |
2141 | ||
1aa292bb DM |
2142 | static void copy_iso_headers(struct iso_context *ctx, void *p) |
2143 | { | |
2144 | int i = ctx->header_length; | |
2145 | ||
2146 | if (i + ctx->base.header_size > PAGE_SIZE) | |
2147 | return; | |
2148 | ||
2149 | /* | |
2150 | * The iso header is byteswapped to little endian by | |
2151 | * the controller, but the remaining header quadlets | |
2152 | * are big endian. We want to present all the headers | |
2153 | * as big endian, so we have to swap the first quadlet. | |
2154 | */ | |
2155 | if (ctx->base.header_size > 0) | |
2156 | *(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4)); | |
2157 | if (ctx->base.header_size > 4) | |
2158 | *(u32 *) (ctx->header + i + 4) = __swab32(*(u32 *) p); | |
2159 | if (ctx->base.header_size > 8) | |
2160 | memcpy(ctx->header + i + 8, p + 8, ctx->base.header_size - 8); | |
2161 | ctx->header_length += ctx->base.header_size; | |
2162 | } | |
2163 | ||
a186b4a6 JW |
2164 | static int handle_ir_packet_per_buffer(struct context *context, |
2165 | struct descriptor *d, | |
2166 | struct descriptor *last) | |
2167 | { | |
2168 | struct iso_context *ctx = | |
2169 | container_of(context, struct iso_context, context); | |
bcee893c | 2170 | struct descriptor *pd; |
a186b4a6 | 2171 | __le32 *ir_header; |
bcee893c | 2172 | void *p; |
a186b4a6 | 2173 | |
bcee893c DM |
2174 | for (pd = d; pd <= last; pd++) { |
2175 | if (pd->transfer_status) | |
2176 | break; | |
2177 | } | |
2178 | if (pd > last) | |
a186b4a6 JW |
2179 | /* Descriptor(s) not done yet, stop iteration */ |
2180 | return 0; | |
2181 | ||
1aa292bb DM |
2182 | p = last + 1; |
2183 | copy_iso_headers(ctx, p); | |
a186b4a6 | 2184 | |
bcee893c DM |
2185 | if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) { |
2186 | ir_header = (__le32 *) p; | |
a186b4a6 JW |
2187 | ctx->base.callback(&ctx->base, |
2188 | le32_to_cpu(ir_header[0]) & 0xffff, | |
2189 | ctx->header_length, ctx->header, | |
2190 | ctx->base.callback_data); | |
2191 | ctx->header_length = 0; | |
2192 | } | |
2193 | ||
a186b4a6 JW |
2194 | return 1; |
2195 | } | |
2196 | ||
30200739 KH |
2197 | static int handle_it_packet(struct context *context, |
2198 | struct descriptor *d, | |
2199 | struct descriptor *last) | |
ed568912 | 2200 | { |
30200739 KH |
2201 | struct iso_context *ctx = |
2202 | container_of(context, struct iso_context, context); | |
31769cef JF |
2203 | int i; |
2204 | struct descriptor *pd; | |
373b2edd | 2205 | |
31769cef JF |
2206 | for (pd = d; pd <= last; pd++) |
2207 | if (pd->transfer_status) | |
2208 | break; | |
2209 | if (pd > last) | |
2210 | /* Descriptor(s) not done yet, stop iteration */ | |
30200739 KH |
2211 | return 0; |
2212 | ||
31769cef JF |
2213 | i = ctx->header_length; |
2214 | if (i + 4 < PAGE_SIZE) { | |
2215 | /* Present this value as big-endian to match the receive code */ | |
2216 | *(__be32 *)(ctx->header + i) = cpu_to_be32( | |
2217 | ((u32)le16_to_cpu(pd->transfer_status) << 16) | | |
2218 | le16_to_cpu(pd->res_count)); | |
2219 | ctx->header_length += 4; | |
2220 | } | |
2221 | if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) { | |
9b32d5f3 | 2222 | ctx->base.callback(&ctx->base, le16_to_cpu(last->res_count), |
31769cef JF |
2223 | ctx->header_length, ctx->header, |
2224 | ctx->base.callback_data); | |
2225 | ctx->header_length = 0; | |
2226 | } | |
30200739 | 2227 | return 1; |
ed568912 KH |
2228 | } |
2229 | ||
53dca511 | 2230 | static struct fw_iso_context *ohci_allocate_iso_context(struct fw_card *card, |
4817ed24 | 2231 | int type, int channel, size_t header_size) |
ed568912 KH |
2232 | { |
2233 | struct fw_ohci *ohci = fw_ohci(card); | |
2234 | struct iso_context *ctx, *list; | |
30200739 | 2235 | descriptor_callback_t callback; |
4817ed24 | 2236 | u64 *channels, dont_care = ~0ULL; |
295e3feb | 2237 | u32 *mask, regs; |
ed568912 | 2238 | unsigned long flags; |
2dbd7d7e | 2239 | int index, ret = -ENOMEM; |
ed568912 KH |
2240 | |
2241 | if (type == FW_ISO_CONTEXT_TRANSMIT) { | |
4817ed24 | 2242 | channels = &dont_care; |
ed568912 KH |
2243 | mask = &ohci->it_context_mask; |
2244 | list = ohci->it_context_list; | |
30200739 | 2245 | callback = handle_it_packet; |
ed568912 | 2246 | } else { |
4817ed24 | 2247 | channels = &ohci->ir_context_channels; |
373b2edd SR |
2248 | mask = &ohci->ir_context_mask; |
2249 | list = ohci->ir_context_list; | |
6498ba04 | 2250 | callback = handle_ir_packet_per_buffer; |
ed568912 KH |
2251 | } |
2252 | ||
2253 | spin_lock_irqsave(&ohci->lock, flags); | |
4817ed24 SR |
2254 | index = *channels & 1ULL << channel ? ffs(*mask) - 1 : -1; |
2255 | if (index >= 0) { | |
2256 | *channels &= ~(1ULL << channel); | |
ed568912 | 2257 | *mask &= ~(1 << index); |
4817ed24 | 2258 | } |
ed568912 KH |
2259 | spin_unlock_irqrestore(&ohci->lock, flags); |
2260 | ||
2261 | if (index < 0) | |
2262 | return ERR_PTR(-EBUSY); | |
2263 | ||
373b2edd SR |
2264 | if (type == FW_ISO_CONTEXT_TRANSMIT) |
2265 | regs = OHCI1394_IsoXmitContextBase(index); | |
2266 | else | |
2267 | regs = OHCI1394_IsoRcvContextBase(index); | |
2268 | ||
ed568912 | 2269 | ctx = &list[index]; |
2d826cc5 | 2270 | memset(ctx, 0, sizeof(*ctx)); |
9b32d5f3 KH |
2271 | ctx->header_length = 0; |
2272 | ctx->header = (void *) __get_free_page(GFP_KERNEL); | |
2273 | if (ctx->header == NULL) | |
2274 | goto out; | |
2275 | ||
2dbd7d7e SR |
2276 | ret = context_init(&ctx->context, ohci, regs, callback); |
2277 | if (ret < 0) | |
9b32d5f3 | 2278 | goto out_with_header; |
ed568912 KH |
2279 | |
2280 | return &ctx->base; | |
9b32d5f3 KH |
2281 | |
2282 | out_with_header: | |
2283 | free_page((unsigned long)ctx->header); | |
2284 | out: | |
2285 | spin_lock_irqsave(&ohci->lock, flags); | |
2286 | *mask |= 1 << index; | |
2287 | spin_unlock_irqrestore(&ohci->lock, flags); | |
2288 | ||
2dbd7d7e | 2289 | return ERR_PTR(ret); |
ed568912 KH |
2290 | } |
2291 | ||
eb0306ea KH |
2292 | static int ohci_start_iso(struct fw_iso_context *base, |
2293 | s32 cycle, u32 sync, u32 tags) | |
ed568912 | 2294 | { |
373b2edd | 2295 | struct iso_context *ctx = container_of(base, struct iso_context, base); |
30200739 | 2296 | struct fw_ohci *ohci = ctx->context.ohci; |
8a2f7d93 | 2297 | u32 control, match; |
ed568912 KH |
2298 | int index; |
2299 | ||
295e3feb KH |
2300 | if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) { |
2301 | index = ctx - ohci->it_context_list; | |
8a2f7d93 KH |
2302 | match = 0; |
2303 | if (cycle >= 0) | |
2304 | match = IT_CONTEXT_CYCLE_MATCH_ENABLE | | |
295e3feb | 2305 | (cycle & 0x7fff) << 16; |
21efb3cf | 2306 | |
295e3feb KH |
2307 | reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index); |
2308 | reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index); | |
8a2f7d93 | 2309 | context_run(&ctx->context, match); |
295e3feb KH |
2310 | } else { |
2311 | index = ctx - ohci->ir_context_list; | |
a186b4a6 | 2312 | control = IR_CONTEXT_ISOCH_HEADER; |
8a2f7d93 KH |
2313 | match = (tags << 28) | (sync << 8) | ctx->base.channel; |
2314 | if (cycle >= 0) { | |
2315 | match |= (cycle & 0x07fff) << 12; | |
2316 | control |= IR_CONTEXT_CYCLE_MATCH_ENABLE; | |
2317 | } | |
ed568912 | 2318 | |
295e3feb KH |
2319 | reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index); |
2320 | reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index); | |
a77754a7 | 2321 | reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match); |
8a2f7d93 | 2322 | context_run(&ctx->context, control); |
295e3feb | 2323 | } |
ed568912 KH |
2324 | |
2325 | return 0; | |
2326 | } | |
2327 | ||
b8295668 KH |
2328 | static int ohci_stop_iso(struct fw_iso_context *base) |
2329 | { | |
2330 | struct fw_ohci *ohci = fw_ohci(base->card); | |
373b2edd | 2331 | struct iso_context *ctx = container_of(base, struct iso_context, base); |
b8295668 KH |
2332 | int index; |
2333 | ||
2334 | if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) { | |
2335 | index = ctx - ohci->it_context_list; | |
2336 | reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index); | |
2337 | } else { | |
2338 | index = ctx - ohci->ir_context_list; | |
2339 | reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index); | |
2340 | } | |
2341 | flush_writes(ohci); | |
2342 | context_stop(&ctx->context); | |
2343 | ||
2344 | return 0; | |
2345 | } | |
2346 | ||
ed568912 KH |
2347 | static void ohci_free_iso_context(struct fw_iso_context *base) |
2348 | { | |
2349 | struct fw_ohci *ohci = fw_ohci(base->card); | |
373b2edd | 2350 | struct iso_context *ctx = container_of(base, struct iso_context, base); |
ed568912 KH |
2351 | unsigned long flags; |
2352 | int index; | |
2353 | ||
b8295668 KH |
2354 | ohci_stop_iso(base); |
2355 | context_release(&ctx->context); | |
9b32d5f3 | 2356 | free_page((unsigned long)ctx->header); |
b8295668 | 2357 | |
ed568912 KH |
2358 | spin_lock_irqsave(&ohci->lock, flags); |
2359 | ||
2360 | if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) { | |
2361 | index = ctx - ohci->it_context_list; | |
ed568912 KH |
2362 | ohci->it_context_mask |= 1 << index; |
2363 | } else { | |
2364 | index = ctx - ohci->ir_context_list; | |
ed568912 | 2365 | ohci->ir_context_mask |= 1 << index; |
4817ed24 | 2366 | ohci->ir_context_channels |= 1ULL << base->channel; |
ed568912 | 2367 | } |
ed568912 KH |
2368 | |
2369 | spin_unlock_irqrestore(&ohci->lock, flags); | |
2370 | } | |
2371 | ||
53dca511 SR |
2372 | static int ohci_queue_iso_transmit(struct fw_iso_context *base, |
2373 | struct fw_iso_packet *packet, | |
2374 | struct fw_iso_buffer *buffer, | |
2375 | unsigned long payload) | |
ed568912 | 2376 | { |
373b2edd | 2377 | struct iso_context *ctx = container_of(base, struct iso_context, base); |
30200739 | 2378 | struct descriptor *d, *last, *pd; |
ed568912 KH |
2379 | struct fw_iso_packet *p; |
2380 | __le32 *header; | |
9aad8125 | 2381 | dma_addr_t d_bus, page_bus; |
ed568912 KH |
2382 | u32 z, header_z, payload_z, irq; |
2383 | u32 payload_index, payload_end_index, next_page_index; | |
30200739 | 2384 | int page, end_page, i, length, offset; |
ed568912 | 2385 | |
ed568912 | 2386 | p = packet; |
9aad8125 | 2387 | payload_index = payload; |
ed568912 KH |
2388 | |
2389 | if (p->skip) | |
2390 | z = 1; | |
2391 | else | |
2392 | z = 2; | |
2393 | if (p->header_length > 0) | |
2394 | z++; | |
2395 | ||
2396 | /* Determine the first page the payload isn't contained in. */ | |
2397 | end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT; | |
2398 | if (p->payload_length > 0) | |
2399 | payload_z = end_page - (payload_index >> PAGE_SHIFT); | |
2400 | else | |
2401 | payload_z = 0; | |
2402 | ||
2403 | z += payload_z; | |
2404 | ||
2405 | /* Get header size in number of descriptors. */ | |
2d826cc5 | 2406 | header_z = DIV_ROUND_UP(p->header_length, sizeof(*d)); |
ed568912 | 2407 | |
30200739 KH |
2408 | d = context_get_descriptors(&ctx->context, z + header_z, &d_bus); |
2409 | if (d == NULL) | |
2410 | return -ENOMEM; | |
ed568912 KH |
2411 | |
2412 | if (!p->skip) { | |
a77754a7 | 2413 | d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE); |
ed568912 | 2414 | d[0].req_count = cpu_to_le16(8); |
7f51a100 CL |
2415 | /* |
2416 | * Link the skip address to this descriptor itself. This causes | |
2417 | * a context to skip a cycle whenever lost cycles or FIFO | |
2418 | * overruns occur, without dropping the data. The application | |
2419 | * should then decide whether this is an error condition or not. | |
2420 | * FIXME: Make the context's cycle-lost behaviour configurable? | |
2421 | */ | |
2422 | d[0].branch_address = cpu_to_le32(d_bus | z); | |
ed568912 KH |
2423 | |
2424 | header = (__le32 *) &d[1]; | |
a77754a7 KH |
2425 | header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) | |
2426 | IT_HEADER_TAG(p->tag) | | |
2427 | IT_HEADER_TCODE(TCODE_STREAM_DATA) | | |
2428 | IT_HEADER_CHANNEL(ctx->base.channel) | | |
2429 | IT_HEADER_SPEED(ctx->base.speed)); | |
ed568912 | 2430 | header[1] = |
a77754a7 | 2431 | cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length + |
ed568912 KH |
2432 | p->payload_length)); |
2433 | } | |
2434 | ||
2435 | if (p->header_length > 0) { | |
2436 | d[2].req_count = cpu_to_le16(p->header_length); | |
2d826cc5 | 2437 | d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d)); |
ed568912 KH |
2438 | memcpy(&d[z], p->header, p->header_length); |
2439 | } | |
2440 | ||
2441 | pd = d + z - payload_z; | |
2442 | payload_end_index = payload_index + p->payload_length; | |
2443 | for (i = 0; i < payload_z; i++) { | |
2444 | page = payload_index >> PAGE_SHIFT; | |
2445 | offset = payload_index & ~PAGE_MASK; | |
2446 | next_page_index = (page + 1) << PAGE_SHIFT; | |
2447 | length = | |
2448 | min(next_page_index, payload_end_index) - payload_index; | |
2449 | pd[i].req_count = cpu_to_le16(length); | |
9aad8125 KH |
2450 | |
2451 | page_bus = page_private(buffer->pages[page]); | |
2452 | pd[i].data_address = cpu_to_le32(page_bus + offset); | |
ed568912 KH |
2453 | |
2454 | payload_index += length; | |
2455 | } | |
2456 | ||
ed568912 | 2457 | if (p->interrupt) |
a77754a7 | 2458 | irq = DESCRIPTOR_IRQ_ALWAYS; |
ed568912 | 2459 | else |
a77754a7 | 2460 | irq = DESCRIPTOR_NO_IRQ; |
ed568912 | 2461 | |
30200739 | 2462 | last = z == 2 ? d : d + z - 1; |
a77754a7 KH |
2463 | last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST | |
2464 | DESCRIPTOR_STATUS | | |
2465 | DESCRIPTOR_BRANCH_ALWAYS | | |
cbb59da7 | 2466 | irq); |
ed568912 | 2467 | |
30200739 | 2468 | context_append(&ctx->context, d, z, header_z); |
ed568912 KH |
2469 | |
2470 | return 0; | |
2471 | } | |
373b2edd | 2472 | |
53dca511 SR |
2473 | static int ohci_queue_iso_receive_packet_per_buffer(struct fw_iso_context *base, |
2474 | struct fw_iso_packet *packet, | |
2475 | struct fw_iso_buffer *buffer, | |
2476 | unsigned long payload) | |
a186b4a6 JW |
2477 | { |
2478 | struct iso_context *ctx = container_of(base, struct iso_context, base); | |
8c0c0cc2 | 2479 | struct descriptor *d, *pd; |
bcee893c | 2480 | struct fw_iso_packet *p = packet; |
a186b4a6 JW |
2481 | dma_addr_t d_bus, page_bus; |
2482 | u32 z, header_z, rest; | |
bcee893c DM |
2483 | int i, j, length; |
2484 | int page, offset, packet_count, header_size, payload_per_buffer; | |
a186b4a6 JW |
2485 | |
2486 | /* | |
1aa292bb DM |
2487 | * The OHCI controller puts the isochronous header and trailer in the |
2488 | * buffer, so we need at least 8 bytes. | |
a186b4a6 JW |
2489 | */ |
2490 | packet_count = p->header_length / ctx->base.header_size; | |
1aa292bb | 2491 | header_size = max(ctx->base.header_size, (size_t)8); |
a186b4a6 JW |
2492 | |
2493 | /* Get header size in number of descriptors. */ | |
2494 | header_z = DIV_ROUND_UP(header_size, sizeof(*d)); | |
2495 | page = payload >> PAGE_SHIFT; | |
2496 | offset = payload & ~PAGE_MASK; | |
bcee893c | 2497 | payload_per_buffer = p->payload_length / packet_count; |
a186b4a6 JW |
2498 | |
2499 | for (i = 0; i < packet_count; i++) { | |
2500 | /* d points to the header descriptor */ | |
bcee893c | 2501 | z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1; |
a186b4a6 | 2502 | d = context_get_descriptors(&ctx->context, |
bcee893c | 2503 | z + header_z, &d_bus); |
a186b4a6 JW |
2504 | if (d == NULL) |
2505 | return -ENOMEM; | |
2506 | ||
bcee893c DM |
2507 | d->control = cpu_to_le16(DESCRIPTOR_STATUS | |
2508 | DESCRIPTOR_INPUT_MORE); | |
2509 | if (p->skip && i == 0) | |
2510 | d->control |= cpu_to_le16(DESCRIPTOR_WAIT); | |
a186b4a6 JW |
2511 | d->req_count = cpu_to_le16(header_size); |
2512 | d->res_count = d->req_count; | |
bcee893c | 2513 | d->transfer_status = 0; |
a186b4a6 JW |
2514 | d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d))); |
2515 | ||
bcee893c | 2516 | rest = payload_per_buffer; |
8c0c0cc2 | 2517 | pd = d; |
bcee893c | 2518 | for (j = 1; j < z; j++) { |
8c0c0cc2 | 2519 | pd++; |
bcee893c DM |
2520 | pd->control = cpu_to_le16(DESCRIPTOR_STATUS | |
2521 | DESCRIPTOR_INPUT_MORE); | |
2522 | ||
2523 | if (offset + rest < PAGE_SIZE) | |
2524 | length = rest; | |
2525 | else | |
2526 | length = PAGE_SIZE - offset; | |
2527 | pd->req_count = cpu_to_le16(length); | |
2528 | pd->res_count = pd->req_count; | |
2529 | pd->transfer_status = 0; | |
2530 | ||
2531 | page_bus = page_private(buffer->pages[page]); | |
2532 | pd->data_address = cpu_to_le32(page_bus + offset); | |
2533 | ||
2534 | offset = (offset + length) & ~PAGE_MASK; | |
2535 | rest -= length; | |
2536 | if (offset == 0) | |
2537 | page++; | |
2538 | } | |
a186b4a6 JW |
2539 | pd->control = cpu_to_le16(DESCRIPTOR_STATUS | |
2540 | DESCRIPTOR_INPUT_LAST | | |
2541 | DESCRIPTOR_BRANCH_ALWAYS); | |
bcee893c | 2542 | if (p->interrupt && i == packet_count - 1) |
a186b4a6 JW |
2543 | pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS); |
2544 | ||
a186b4a6 JW |
2545 | context_append(&ctx->context, d, z, header_z); |
2546 | } | |
2547 | ||
2548 | return 0; | |
2549 | } | |
2550 | ||
53dca511 SR |
2551 | static int ohci_queue_iso(struct fw_iso_context *base, |
2552 | struct fw_iso_packet *packet, | |
2553 | struct fw_iso_buffer *buffer, | |
2554 | unsigned long payload) | |
295e3feb | 2555 | { |
e364cf4e | 2556 | struct iso_context *ctx = container_of(base, struct iso_context, base); |
fe5ca634 | 2557 | unsigned long flags; |
2dbd7d7e | 2558 | int ret; |
e364cf4e | 2559 | |
fe5ca634 | 2560 | spin_lock_irqsave(&ctx->context.ohci->lock, flags); |
295e3feb | 2561 | if (base->type == FW_ISO_CONTEXT_TRANSMIT) |
2dbd7d7e | 2562 | ret = ohci_queue_iso_transmit(base, packet, buffer, payload); |
e364cf4e | 2563 | else |
2dbd7d7e SR |
2564 | ret = ohci_queue_iso_receive_packet_per_buffer(base, packet, |
2565 | buffer, payload); | |
fe5ca634 DM |
2566 | spin_unlock_irqrestore(&ctx->context.ohci->lock, flags); |
2567 | ||
2dbd7d7e | 2568 | return ret; |
295e3feb KH |
2569 | } |
2570 | ||
21ebcd12 | 2571 | static const struct fw_card_driver ohci_driver = { |
ed568912 KH |
2572 | .enable = ohci_enable, |
2573 | .update_phy_reg = ohci_update_phy_reg, | |
2574 | .set_config_rom = ohci_set_config_rom, | |
2575 | .send_request = ohci_send_request, | |
2576 | .send_response = ohci_send_response, | |
730c32f5 | 2577 | .cancel_packet = ohci_cancel_packet, |
ed568912 | 2578 | .enable_phys_dma = ohci_enable_phys_dma, |
60d32970 | 2579 | .read_csr_reg = ohci_read_csr_reg, |
506f1a31 | 2580 | .write_csr_reg = ohci_write_csr_reg, |
ed568912 KH |
2581 | |
2582 | .allocate_iso_context = ohci_allocate_iso_context, | |
2583 | .free_iso_context = ohci_free_iso_context, | |
2584 | .queue_iso = ohci_queue_iso, | |
69cdb726 | 2585 | .start_iso = ohci_start_iso, |
b8295668 | 2586 | .stop_iso = ohci_stop_iso, |
ed568912 KH |
2587 | }; |
2588 | ||
ea8d006b | 2589 | #ifdef CONFIG_PPC_PMAC |
5da3dac8 | 2590 | static void pmac_ohci_on(struct pci_dev *dev) |
2ed0f181 | 2591 | { |
ea8d006b SR |
2592 | if (machine_is(powermac)) { |
2593 | struct device_node *ofn = pci_device_to_OF_node(dev); | |
2594 | ||
2595 | if (ofn) { | |
2596 | pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1); | |
2597 | pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1); | |
2598 | } | |
2599 | } | |
2ed0f181 SR |
2600 | } |
2601 | ||
5da3dac8 | 2602 | static void pmac_ohci_off(struct pci_dev *dev) |
2ed0f181 SR |
2603 | { |
2604 | if (machine_is(powermac)) { | |
2605 | struct device_node *ofn = pci_device_to_OF_node(dev); | |
2606 | ||
2607 | if (ofn) { | |
2608 | pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0); | |
2609 | pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0); | |
2610 | } | |
2611 | } | |
2612 | } | |
2613 | #else | |
5da3dac8 SR |
2614 | static inline void pmac_ohci_on(struct pci_dev *dev) {} |
2615 | static inline void pmac_ohci_off(struct pci_dev *dev) {} | |
ea8d006b SR |
2616 | #endif /* CONFIG_PPC_PMAC */ |
2617 | ||
53dca511 SR |
2618 | static int __devinit pci_probe(struct pci_dev *dev, |
2619 | const struct pci_device_id *ent) | |
2ed0f181 SR |
2620 | { |
2621 | struct fw_ohci *ohci; | |
54672386 | 2622 | u32 bus_options, max_receive, link_speed, version, link_enh; |
2ed0f181 | 2623 | u64 guid; |
6fdb2ee2 | 2624 | int i, err, n_ir, n_it; |
2ed0f181 SR |
2625 | size_t size; |
2626 | ||
2d826cc5 | 2627 | ohci = kzalloc(sizeof(*ohci), GFP_KERNEL); |
ed568912 | 2628 | if (ohci == NULL) { |
7007a076 SR |
2629 | err = -ENOMEM; |
2630 | goto fail; | |
ed568912 KH |
2631 | } |
2632 | ||
2633 | fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev); | |
2634 | ||
5da3dac8 | 2635 | pmac_ohci_on(dev); |
130d5496 | 2636 | |
d79406dd KH |
2637 | err = pci_enable_device(dev); |
2638 | if (err) { | |
7007a076 | 2639 | fw_error("Failed to enable OHCI hardware\n"); |
bd7dee63 | 2640 | goto fail_free; |
ed568912 KH |
2641 | } |
2642 | ||
2643 | pci_set_master(dev); | |
2644 | pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0); | |
2645 | pci_set_drvdata(dev, ohci); | |
2646 | ||
2647 | spin_lock_init(&ohci->lock); | |
2648 | ||
2649 | tasklet_init(&ohci->bus_reset_tasklet, | |
2650 | bus_reset_tasklet, (unsigned long)ohci); | |
2651 | ||
d79406dd KH |
2652 | err = pci_request_region(dev, 0, ohci_driver_name); |
2653 | if (err) { | |
ed568912 | 2654 | fw_error("MMIO resource unavailable\n"); |
d79406dd | 2655 | goto fail_disable; |
ed568912 KH |
2656 | } |
2657 | ||
2658 | ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE); | |
2659 | if (ohci->registers == NULL) { | |
2660 | fw_error("Failed to remap registers\n"); | |
d79406dd KH |
2661 | err = -ENXIO; |
2662 | goto fail_iomem; | |
ed568912 KH |
2663 | } |
2664 | ||
4a635593 SR |
2665 | for (i = 0; i < ARRAY_SIZE(ohci_quirks); i++) |
2666 | if (ohci_quirks[i].vendor == dev->vendor && | |
2667 | (ohci_quirks[i].device == dev->device || | |
2668 | ohci_quirks[i].device == (unsigned short)PCI_ANY_ID)) { | |
2669 | ohci->quirks = ohci_quirks[i].flags; | |
2670 | break; | |
2671 | } | |
3e9cc2f3 SR |
2672 | if (param_quirks) |
2673 | ohci->quirks = param_quirks; | |
b677532b | 2674 | |
54672386 CL |
2675 | /* TI OHCI-Lynx and compatible: set recommended configuration bits. */ |
2676 | if (dev->vendor == PCI_VENDOR_ID_TI) { | |
2677 | pci_read_config_dword(dev, PCI_CFG_TI_LinkEnh, &link_enh); | |
2678 | ||
2679 | /* adjust latency of ATx FIFO: use 1.7 KB threshold */ | |
2680 | link_enh &= ~TI_LinkEnh_atx_thresh_mask; | |
2681 | link_enh |= TI_LinkEnh_atx_thresh_1_7K; | |
2682 | ||
2683 | /* use priority arbitration for asynchronous responses */ | |
2684 | link_enh |= TI_LinkEnh_enab_unfair; | |
2685 | ||
2686 | /* required for aPhyEnhanceEnable to work */ | |
2687 | link_enh |= TI_LinkEnh_enab_accel; | |
2688 | ||
2689 | pci_write_config_dword(dev, PCI_CFG_TI_LinkEnh, link_enh); | |
2690 | } | |
2691 | ||
ed568912 KH |
2692 | ar_context_init(&ohci->ar_request_ctx, ohci, |
2693 | OHCI1394_AsReqRcvContextControlSet); | |
2694 | ||
2695 | ar_context_init(&ohci->ar_response_ctx, ohci, | |
2696 | OHCI1394_AsRspRcvContextControlSet); | |
2697 | ||
fe5ca634 | 2698 | context_init(&ohci->at_request_ctx, ohci, |
f319b6a0 | 2699 | OHCI1394_AsReqTrContextControlSet, handle_at_packet); |
ed568912 | 2700 | |
fe5ca634 | 2701 | context_init(&ohci->at_response_ctx, ohci, |
f319b6a0 | 2702 | OHCI1394_AsRspTrContextControlSet, handle_at_packet); |
ed568912 | 2703 | |
ed568912 | 2704 | reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0); |
4802f16d SR |
2705 | ohci->ir_context_channels = ~0ULL; |
2706 | ohci->ir_context_mask = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet); | |
ed568912 | 2707 | reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0); |
6fdb2ee2 SR |
2708 | n_ir = hweight32(ohci->ir_context_mask); |
2709 | size = sizeof(struct iso_context) * n_ir; | |
4802f16d | 2710 | ohci->ir_context_list = kzalloc(size, GFP_KERNEL); |
ed568912 KH |
2711 | |
2712 | reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0); | |
4802f16d | 2713 | ohci->it_context_mask = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet); |
ed568912 | 2714 | reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0); |
6fdb2ee2 SR |
2715 | n_it = hweight32(ohci->it_context_mask); |
2716 | size = sizeof(struct iso_context) * n_it; | |
4802f16d | 2717 | ohci->it_context_list = kzalloc(size, GFP_KERNEL); |
ed568912 KH |
2718 | |
2719 | if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) { | |
d79406dd | 2720 | err = -ENOMEM; |
7007a076 | 2721 | goto fail_contexts; |
ed568912 KH |
2722 | } |
2723 | ||
2724 | /* self-id dma buffer allocation */ | |
2725 | ohci->self_id_cpu = dma_alloc_coherent(ohci->card.device, | |
2726 | SELF_ID_BUF_SIZE, | |
2727 | &ohci->self_id_bus, | |
2728 | GFP_KERNEL); | |
2729 | if (ohci->self_id_cpu == NULL) { | |
d79406dd | 2730 | err = -ENOMEM; |
7007a076 | 2731 | goto fail_contexts; |
ed568912 KH |
2732 | } |
2733 | ||
ed568912 KH |
2734 | bus_options = reg_read(ohci, OHCI1394_BusOptions); |
2735 | max_receive = (bus_options >> 12) & 0xf; | |
2736 | link_speed = bus_options & 0x7; | |
2737 | guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) | | |
2738 | reg_read(ohci, OHCI1394_GUIDLo); | |
2739 | ||
d79406dd | 2740 | err = fw_card_add(&ohci->card, max_receive, link_speed, guid); |
e1eff7a3 | 2741 | if (err) |
d79406dd | 2742 | goto fail_self_id; |
ed568912 | 2743 | |
6fdb2ee2 SR |
2744 | version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff; |
2745 | fw_notify("Added fw-ohci device %s, OHCI v%x.%x, " | |
2746 | "%d IR + %d IT contexts, quirks 0x%x\n", | |
2747 | dev_name(&dev->dev), version >> 16, version & 0xff, | |
2748 | n_ir, n_it, ohci->quirks); | |
e1eff7a3 | 2749 | |
ed568912 | 2750 | return 0; |
d79406dd KH |
2751 | |
2752 | fail_self_id: | |
2753 | dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE, | |
2754 | ohci->self_id_cpu, ohci->self_id_bus); | |
7007a076 | 2755 | fail_contexts: |
d79406dd | 2756 | kfree(ohci->ir_context_list); |
7007a076 SR |
2757 | kfree(ohci->it_context_list); |
2758 | context_release(&ohci->at_response_ctx); | |
2759 | context_release(&ohci->at_request_ctx); | |
2760 | ar_context_release(&ohci->ar_response_ctx); | |
2761 | ar_context_release(&ohci->ar_request_ctx); | |
d79406dd KH |
2762 | pci_iounmap(dev, ohci->registers); |
2763 | fail_iomem: | |
2764 | pci_release_region(dev, 0); | |
2765 | fail_disable: | |
2766 | pci_disable_device(dev); | |
bd7dee63 SR |
2767 | fail_free: |
2768 | kfree(&ohci->card); | |
5da3dac8 | 2769 | pmac_ohci_off(dev); |
7007a076 SR |
2770 | fail: |
2771 | if (err == -ENOMEM) | |
2772 | fw_error("Out of memory\n"); | |
d79406dd KH |
2773 | |
2774 | return err; | |
ed568912 KH |
2775 | } |
2776 | ||
2777 | static void pci_remove(struct pci_dev *dev) | |
2778 | { | |
2779 | struct fw_ohci *ohci; | |
2780 | ||
2781 | ohci = pci_get_drvdata(dev); | |
e254a4b4 KH |
2782 | reg_write(ohci, OHCI1394_IntMaskClear, ~0); |
2783 | flush_writes(ohci); | |
ed568912 KH |
2784 | fw_core_remove_card(&ohci->card); |
2785 | ||
c781c06d KH |
2786 | /* |
2787 | * FIXME: Fail all pending packets here, now that the upper | |
2788 | * layers can't queue any more. | |
2789 | */ | |
ed568912 KH |
2790 | |
2791 | software_reset(ohci); | |
2792 | free_irq(dev->irq, ohci); | |
a55709ba JF |
2793 | |
2794 | if (ohci->next_config_rom && ohci->next_config_rom != ohci->config_rom) | |
2795 | dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, | |
2796 | ohci->next_config_rom, ohci->next_config_rom_bus); | |
2797 | if (ohci->config_rom) | |
2798 | dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, | |
2799 | ohci->config_rom, ohci->config_rom_bus); | |
d79406dd KH |
2800 | dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE, |
2801 | ohci->self_id_cpu, ohci->self_id_bus); | |
a55709ba JF |
2802 | ar_context_release(&ohci->ar_request_ctx); |
2803 | ar_context_release(&ohci->ar_response_ctx); | |
2804 | context_release(&ohci->at_request_ctx); | |
2805 | context_release(&ohci->at_response_ctx); | |
d79406dd KH |
2806 | kfree(ohci->it_context_list); |
2807 | kfree(ohci->ir_context_list); | |
262444ee | 2808 | pci_disable_msi(dev); |
d79406dd KH |
2809 | pci_iounmap(dev, ohci->registers); |
2810 | pci_release_region(dev, 0); | |
2811 | pci_disable_device(dev); | |
bd7dee63 | 2812 | kfree(&ohci->card); |
5da3dac8 | 2813 | pmac_ohci_off(dev); |
ea8d006b | 2814 | |
ed568912 KH |
2815 | fw_notify("Removed fw-ohci device.\n"); |
2816 | } | |
2817 | ||
2aef469a | 2818 | #ifdef CONFIG_PM |
2ed0f181 | 2819 | static int pci_suspend(struct pci_dev *dev, pm_message_t state) |
2aef469a | 2820 | { |
2ed0f181 | 2821 | struct fw_ohci *ohci = pci_get_drvdata(dev); |
2aef469a KH |
2822 | int err; |
2823 | ||
2824 | software_reset(ohci); | |
2ed0f181 | 2825 | free_irq(dev->irq, ohci); |
262444ee | 2826 | pci_disable_msi(dev); |
2ed0f181 | 2827 | err = pci_save_state(dev); |
2aef469a | 2828 | if (err) { |
8a8cea27 | 2829 | fw_error("pci_save_state failed\n"); |
2aef469a KH |
2830 | return err; |
2831 | } | |
2ed0f181 | 2832 | err = pci_set_power_state(dev, pci_choose_state(dev, state)); |
55111428 SR |
2833 | if (err) |
2834 | fw_error("pci_set_power_state failed with %d\n", err); | |
5da3dac8 | 2835 | pmac_ohci_off(dev); |
ea8d006b | 2836 | |
2aef469a KH |
2837 | return 0; |
2838 | } | |
2839 | ||
2ed0f181 | 2840 | static int pci_resume(struct pci_dev *dev) |
2aef469a | 2841 | { |
2ed0f181 | 2842 | struct fw_ohci *ohci = pci_get_drvdata(dev); |
2aef469a KH |
2843 | int err; |
2844 | ||
5da3dac8 | 2845 | pmac_ohci_on(dev); |
2ed0f181 SR |
2846 | pci_set_power_state(dev, PCI_D0); |
2847 | pci_restore_state(dev); | |
2848 | err = pci_enable_device(dev); | |
2aef469a | 2849 | if (err) { |
8a8cea27 | 2850 | fw_error("pci_enable_device failed\n"); |
2aef469a KH |
2851 | return err; |
2852 | } | |
2853 | ||
0bd243c4 | 2854 | return ohci_enable(&ohci->card, NULL, 0); |
2aef469a KH |
2855 | } |
2856 | #endif | |
2857 | ||
a67483d2 | 2858 | static const struct pci_device_id pci_table[] = { |
ed568912 KH |
2859 | { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) }, |
2860 | { } | |
2861 | }; | |
2862 | ||
2863 | MODULE_DEVICE_TABLE(pci, pci_table); | |
2864 | ||
2865 | static struct pci_driver fw_ohci_pci_driver = { | |
2866 | .name = ohci_driver_name, | |
2867 | .id_table = pci_table, | |
2868 | .probe = pci_probe, | |
2869 | .remove = pci_remove, | |
2aef469a KH |
2870 | #ifdef CONFIG_PM |
2871 | .resume = pci_resume, | |
2872 | .suspend = pci_suspend, | |
2873 | #endif | |
ed568912 KH |
2874 | }; |
2875 | ||
2876 | MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>"); | |
2877 | MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers"); | |
2878 | MODULE_LICENSE("GPL"); | |
2879 | ||
1e4c7b0d OH |
2880 | /* Provide a module alias so root-on-sbp2 initrds don't break. */ |
2881 | #ifndef CONFIG_IEEE1394_OHCI1394_MODULE | |
2882 | MODULE_ALIAS("ohci1394"); | |
2883 | #endif | |
2884 | ||
ed568912 KH |
2885 | static int __init fw_ohci_init(void) |
2886 | { | |
2887 | return pci_register_driver(&fw_ohci_pci_driver); | |
2888 | } | |
2889 | ||
2890 | static void __exit fw_ohci_cleanup(void) | |
2891 | { | |
2892 | pci_unregister_driver(&fw_ohci_pci_driver); | |
2893 | } | |
2894 | ||
2895 | module_init(fw_ohci_init); | |
2896 | module_exit(fw_ohci_cleanup); |