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Commit | Line | Data |
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c781c06d KH |
1 | /* |
2 | * Driver for OHCI 1394 controllers | |
ed568912 | 3 | * |
ed568912 KH |
4 | * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net> |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software Foundation, | |
18 | * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
19 | */ | |
20 | ||
dd23736e | 21 | #include <linux/bitops.h> |
65b2742a | 22 | #include <linux/bug.h> |
e524f616 | 23 | #include <linux/compiler.h> |
ed568912 | 24 | #include <linux/delay.h> |
e8ca9702 | 25 | #include <linux/device.h> |
cf3e72fd | 26 | #include <linux/dma-mapping.h> |
77c9a5da | 27 | #include <linux/firewire.h> |
e8ca9702 | 28 | #include <linux/firewire-constants.h> |
a7fb60db SR |
29 | #include <linux/init.h> |
30 | #include <linux/interrupt.h> | |
e8ca9702 | 31 | #include <linux/io.h> |
a7fb60db | 32 | #include <linux/kernel.h> |
e8ca9702 | 33 | #include <linux/list.h> |
faa2fb4e | 34 | #include <linux/mm.h> |
a7fb60db | 35 | #include <linux/module.h> |
ad3c0fe8 | 36 | #include <linux/moduleparam.h> |
02d37bed | 37 | #include <linux/mutex.h> |
a7fb60db | 38 | #include <linux/pci.h> |
fc383796 | 39 | #include <linux/pci_ids.h> |
5a0e3ad6 | 40 | #include <linux/slab.h> |
c26f0234 | 41 | #include <linux/spinlock.h> |
e8ca9702 | 42 | #include <linux/string.h> |
e78483c5 | 43 | #include <linux/time.h> |
7a39d8b8 | 44 | #include <linux/vmalloc.h> |
cf3e72fd | 45 | |
e8ca9702 | 46 | #include <asm/byteorder.h> |
c26f0234 | 47 | #include <asm/page.h> |
ee71c2f9 | 48 | #include <asm/system.h> |
ed568912 | 49 | |
ea8d006b SR |
50 | #ifdef CONFIG_PPC_PMAC |
51 | #include <asm/pmac_feature.h> | |
52 | #endif | |
53 | ||
77c9a5da SR |
54 | #include "core.h" |
55 | #include "ohci.h" | |
ed568912 | 56 | |
a77754a7 KH |
57 | #define DESCRIPTOR_OUTPUT_MORE 0 |
58 | #define DESCRIPTOR_OUTPUT_LAST (1 << 12) | |
59 | #define DESCRIPTOR_INPUT_MORE (2 << 12) | |
60 | #define DESCRIPTOR_INPUT_LAST (3 << 12) | |
61 | #define DESCRIPTOR_STATUS (1 << 11) | |
62 | #define DESCRIPTOR_KEY_IMMEDIATE (2 << 8) | |
63 | #define DESCRIPTOR_PING (1 << 7) | |
64 | #define DESCRIPTOR_YY (1 << 6) | |
65 | #define DESCRIPTOR_NO_IRQ (0 << 4) | |
66 | #define DESCRIPTOR_IRQ_ERROR (1 << 4) | |
67 | #define DESCRIPTOR_IRQ_ALWAYS (3 << 4) | |
68 | #define DESCRIPTOR_BRANCH_ALWAYS (3 << 2) | |
69 | #define DESCRIPTOR_WAIT (3 << 0) | |
ed568912 KH |
70 | |
71 | struct descriptor { | |
72 | __le16 req_count; | |
73 | __le16 control; | |
74 | __le32 data_address; | |
75 | __le32 branch_address; | |
76 | __le16 res_count; | |
77 | __le16 transfer_status; | |
78 | } __attribute__((aligned(16))); | |
79 | ||
a77754a7 KH |
80 | #define CONTROL_SET(regs) (regs) |
81 | #define CONTROL_CLEAR(regs) ((regs) + 4) | |
82 | #define COMMAND_PTR(regs) ((regs) + 12) | |
83 | #define CONTEXT_MATCH(regs) ((regs) + 16) | |
72e318e0 | 84 | |
7a39d8b8 CL |
85 | #define AR_BUFFER_SIZE (32*1024) |
86 | #define AR_BUFFERS_MIN DIV_ROUND_UP(AR_BUFFER_SIZE, PAGE_SIZE) | |
87 | /* we need at least two pages for proper list management */ | |
88 | #define AR_BUFFERS (AR_BUFFERS_MIN >= 2 ? AR_BUFFERS_MIN : 2) | |
89 | ||
90 | #define MAX_ASYNC_PAYLOAD 4096 | |
91 | #define MAX_AR_PACKET_SIZE (16 + MAX_ASYNC_PAYLOAD + 4) | |
92 | #define AR_WRAPAROUND_PAGES DIV_ROUND_UP(MAX_AR_PACKET_SIZE, PAGE_SIZE) | |
ed568912 | 93 | |
32b46093 KH |
94 | struct ar_context { |
95 | struct fw_ohci *ohci; | |
7a39d8b8 CL |
96 | struct page *pages[AR_BUFFERS]; |
97 | void *buffer; | |
98 | struct descriptor *descriptors; | |
99 | dma_addr_t descriptors_bus; | |
32b46093 | 100 | void *pointer; |
7a39d8b8 | 101 | unsigned int last_buffer_index; |
72e318e0 | 102 | u32 regs; |
ed568912 KH |
103 | struct tasklet_struct tasklet; |
104 | }; | |
105 | ||
30200739 KH |
106 | struct context; |
107 | ||
108 | typedef int (*descriptor_callback_t)(struct context *ctx, | |
109 | struct descriptor *d, | |
110 | struct descriptor *last); | |
fe5ca634 DM |
111 | |
112 | /* | |
113 | * A buffer that contains a block of DMA-able coherent memory used for | |
114 | * storing a portion of a DMA descriptor program. | |
115 | */ | |
116 | struct descriptor_buffer { | |
117 | struct list_head list; | |
118 | dma_addr_t buffer_bus; | |
119 | size_t buffer_size; | |
120 | size_t used; | |
121 | struct descriptor buffer[0]; | |
122 | }; | |
123 | ||
30200739 | 124 | struct context { |
373b2edd | 125 | struct fw_ohci *ohci; |
30200739 | 126 | u32 regs; |
fe5ca634 | 127 | int total_allocation; |
373b2edd | 128 | |
fe5ca634 DM |
129 | /* |
130 | * List of page-sized buffers for storing DMA descriptors. | |
131 | * Head of list contains buffers in use and tail of list contains | |
132 | * free buffers. | |
133 | */ | |
134 | struct list_head buffer_list; | |
135 | ||
136 | /* | |
137 | * Pointer to a buffer inside buffer_list that contains the tail | |
138 | * end of the current DMA program. | |
139 | */ | |
140 | struct descriptor_buffer *buffer_tail; | |
141 | ||
142 | /* | |
143 | * The descriptor containing the branch address of the first | |
144 | * descriptor that has not yet been filled by the device. | |
145 | */ | |
146 | struct descriptor *last; | |
147 | ||
148 | /* | |
149 | * The last descriptor in the DMA program. It contains the branch | |
150 | * address that must be updated upon appending a new descriptor. | |
151 | */ | |
152 | struct descriptor *prev; | |
30200739 KH |
153 | |
154 | descriptor_callback_t callback; | |
155 | ||
373b2edd | 156 | struct tasklet_struct tasklet; |
dd23736e | 157 | bool active; |
30200739 | 158 | }; |
30200739 | 159 | |
a77754a7 KH |
160 | #define IT_HEADER_SY(v) ((v) << 0) |
161 | #define IT_HEADER_TCODE(v) ((v) << 4) | |
162 | #define IT_HEADER_CHANNEL(v) ((v) << 8) | |
163 | #define IT_HEADER_TAG(v) ((v) << 14) | |
164 | #define IT_HEADER_SPEED(v) ((v) << 16) | |
165 | #define IT_HEADER_DATA_LENGTH(v) ((v) << 16) | |
ed568912 KH |
166 | |
167 | struct iso_context { | |
168 | struct fw_iso_context base; | |
30200739 | 169 | struct context context; |
0642b657 | 170 | int excess_bytes; |
9b32d5f3 KH |
171 | void *header; |
172 | size_t header_length; | |
dd23736e ML |
173 | |
174 | u8 sync; | |
175 | u8 tags; | |
ed568912 KH |
176 | }; |
177 | ||
178 | #define CONFIG_ROM_SIZE 1024 | |
179 | ||
180 | struct fw_ohci { | |
181 | struct fw_card card; | |
182 | ||
183 | __iomem char *registers; | |
e636fe25 | 184 | int node_id; |
ed568912 | 185 | int generation; |
e09770db | 186 | int request_generation; /* for timestamping incoming requests */ |
4a635593 | 187 | unsigned quirks; |
a1a1132b | 188 | unsigned int pri_req_max; |
a48777e0 | 189 | u32 bus_time; |
4ffb7a6a | 190 | bool is_root; |
c8a94ded | 191 | bool csr_state_setclear_abdicate; |
dd23736e ML |
192 | int n_ir; |
193 | int n_it; | |
c781c06d KH |
194 | /* |
195 | * Spinlock for accessing fw_ohci data. Never call out of | |
196 | * this driver with this lock held. | |
197 | */ | |
ed568912 | 198 | spinlock_t lock; |
ed568912 | 199 | |
02d37bed SR |
200 | struct mutex phy_reg_mutex; |
201 | ||
ec766a79 CL |
202 | void *misc_buffer; |
203 | dma_addr_t misc_buffer_bus; | |
204 | ||
ed568912 KH |
205 | struct ar_context ar_request_ctx; |
206 | struct ar_context ar_response_ctx; | |
f319b6a0 KH |
207 | struct context at_request_ctx; |
208 | struct context at_response_ctx; | |
ed568912 | 209 | |
872e330e | 210 | u32 it_context_mask; /* unoccupied IT contexts */ |
ed568912 | 211 | struct iso_context *it_context_list; |
872e330e SR |
212 | u64 ir_context_channels; /* unoccupied channels */ |
213 | u32 ir_context_mask; /* unoccupied IR contexts */ | |
ed568912 | 214 | struct iso_context *ir_context_list; |
872e330e SR |
215 | u64 mc_channels; /* channels in use by the multichannel IR context */ |
216 | bool mc_allocated; | |
ecb1cf9c SR |
217 | |
218 | __be32 *config_rom; | |
219 | dma_addr_t config_rom_bus; | |
220 | __be32 *next_config_rom; | |
221 | dma_addr_t next_config_rom_bus; | |
222 | __be32 next_header; | |
223 | ||
224 | __le32 *self_id_cpu; | |
225 | dma_addr_t self_id_bus; | |
226 | struct tasklet_struct bus_reset_tasklet; | |
227 | ||
228 | u32 self_id_buffer[512]; | |
ed568912 KH |
229 | }; |
230 | ||
95688e97 | 231 | static inline struct fw_ohci *fw_ohci(struct fw_card *card) |
ed568912 KH |
232 | { |
233 | return container_of(card, struct fw_ohci, card); | |
234 | } | |
235 | ||
295e3feb KH |
236 | #define IT_CONTEXT_CYCLE_MATCH_ENABLE 0x80000000 |
237 | #define IR_CONTEXT_BUFFER_FILL 0x80000000 | |
238 | #define IR_CONTEXT_ISOCH_HEADER 0x40000000 | |
239 | #define IR_CONTEXT_CYCLE_MATCH_ENABLE 0x20000000 | |
240 | #define IR_CONTEXT_MULTI_CHANNEL_MODE 0x10000000 | |
241 | #define IR_CONTEXT_DUAL_BUFFER_MODE 0x08000000 | |
ed568912 KH |
242 | |
243 | #define CONTEXT_RUN 0x8000 | |
244 | #define CONTEXT_WAKE 0x1000 | |
245 | #define CONTEXT_DEAD 0x0800 | |
246 | #define CONTEXT_ACTIVE 0x0400 | |
247 | ||
8b7b6afa | 248 | #define OHCI1394_MAX_AT_REQ_RETRIES 0xf |
ed568912 KH |
249 | #define OHCI1394_MAX_AT_RESP_RETRIES 0x2 |
250 | #define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8 | |
251 | ||
ed568912 KH |
252 | #define OHCI1394_REGISTER_SIZE 0x800 |
253 | #define OHCI_LOOP_COUNT 500 | |
254 | #define OHCI1394_PCI_HCI_Control 0x40 | |
255 | #define SELF_ID_BUF_SIZE 0x800 | |
32b46093 | 256 | #define OHCI_TCODE_PHY_PACKET 0x0e |
e364cf4e | 257 | #define OHCI_VERSION_1_1 0x010010 |
0edeefd9 | 258 | |
ed568912 KH |
259 | static char ohci_driver_name[] = KBUILD_MODNAME; |
260 | ||
9993e0fe | 261 | #define PCI_DEVICE_ID_AGERE_FW643 0x5901 |
262444ee | 262 | #define PCI_DEVICE_ID_JMICRON_JMB38X_FW 0x2380 |
8301b91b CL |
263 | #define PCI_DEVICE_ID_TI_TSB12LV22 0x8009 |
264 | ||
4a635593 SR |
265 | #define QUIRK_CYCLE_TIMER 1 |
266 | #define QUIRK_RESET_PACKET 2 | |
267 | #define QUIRK_BE_HEADERS 4 | |
925e7a65 | 268 | #define QUIRK_NO_1394A 8 |
262444ee | 269 | #define QUIRK_NO_MSI 16 |
4a635593 SR |
270 | |
271 | /* In case of multiple matches in ohci_quirks[], only the first one is used. */ | |
272 | static const struct { | |
9993e0fe | 273 | unsigned short vendor, device, revision, flags; |
4a635593 | 274 | } ohci_quirks[] = { |
9993e0fe SR |
275 | {PCI_VENDOR_ID_AL, PCI_ANY_ID, PCI_ANY_ID, |
276 | QUIRK_CYCLE_TIMER}, | |
277 | ||
278 | {PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_FW, PCI_ANY_ID, | |
279 | QUIRK_BE_HEADERS}, | |
280 | ||
281 | {PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_AGERE_FW643, 6, | |
282 | QUIRK_NO_MSI}, | |
283 | ||
284 | {PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB38X_FW, PCI_ANY_ID, | |
285 | QUIRK_NO_MSI}, | |
286 | ||
287 | {PCI_VENDOR_ID_NEC, PCI_ANY_ID, PCI_ANY_ID, | |
288 | QUIRK_CYCLE_TIMER}, | |
289 | ||
290 | {PCI_VENDOR_ID_RICOH, PCI_ANY_ID, PCI_ANY_ID, | |
291 | QUIRK_CYCLE_TIMER}, | |
292 | ||
293 | {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV22, PCI_ANY_ID, | |
294 | QUIRK_CYCLE_TIMER | QUIRK_RESET_PACKET | QUIRK_NO_1394A}, | |
295 | ||
296 | {PCI_VENDOR_ID_TI, PCI_ANY_ID, PCI_ANY_ID, | |
297 | QUIRK_RESET_PACKET}, | |
298 | ||
299 | {PCI_VENDOR_ID_VIA, PCI_ANY_ID, PCI_ANY_ID, | |
300 | QUIRK_CYCLE_TIMER | QUIRK_NO_MSI}, | |
4a635593 SR |
301 | }; |
302 | ||
3e9cc2f3 SR |
303 | /* This overrides anything that was found in ohci_quirks[]. */ |
304 | static int param_quirks; | |
305 | module_param_named(quirks, param_quirks, int, 0644); | |
306 | MODULE_PARM_DESC(quirks, "Chip quirks (default = 0" | |
307 | ", nonatomic cycle timer = " __stringify(QUIRK_CYCLE_TIMER) | |
308 | ", reset packet generation = " __stringify(QUIRK_RESET_PACKET) | |
309 | ", AR/selfID endianess = " __stringify(QUIRK_BE_HEADERS) | |
925e7a65 | 310 | ", no 1394a enhancements = " __stringify(QUIRK_NO_1394A) |
262444ee | 311 | ", disable MSI = " __stringify(QUIRK_NO_MSI) |
3e9cc2f3 SR |
312 | ")"); |
313 | ||
a007bb85 | 314 | #define OHCI_PARAM_DEBUG_AT_AR 1 |
ad3c0fe8 | 315 | #define OHCI_PARAM_DEBUG_SELFIDS 2 |
a007bb85 SR |
316 | #define OHCI_PARAM_DEBUG_IRQS 4 |
317 | #define OHCI_PARAM_DEBUG_BUSRESETS 8 /* only effective before chip init */ | |
ad3c0fe8 | 318 | |
5da3dac8 SR |
319 | #ifdef CONFIG_FIREWIRE_OHCI_DEBUG |
320 | ||
ad3c0fe8 SR |
321 | static int param_debug; |
322 | module_param_named(debug, param_debug, int, 0644); | |
323 | MODULE_PARM_DESC(debug, "Verbose logging (default = 0" | |
ad3c0fe8 | 324 | ", AT/AR events = " __stringify(OHCI_PARAM_DEBUG_AT_AR) |
a007bb85 SR |
325 | ", self-IDs = " __stringify(OHCI_PARAM_DEBUG_SELFIDS) |
326 | ", IRQs = " __stringify(OHCI_PARAM_DEBUG_IRQS) | |
327 | ", busReset events = " __stringify(OHCI_PARAM_DEBUG_BUSRESETS) | |
ad3c0fe8 SR |
328 | ", or a combination, or all = -1)"); |
329 | ||
330 | static void log_irqs(u32 evt) | |
331 | { | |
a007bb85 SR |
332 | if (likely(!(param_debug & |
333 | (OHCI_PARAM_DEBUG_IRQS | OHCI_PARAM_DEBUG_BUSRESETS)))) | |
334 | return; | |
335 | ||
336 | if (!(param_debug & OHCI_PARAM_DEBUG_IRQS) && | |
337 | !(evt & OHCI1394_busReset)) | |
ad3c0fe8 SR |
338 | return; |
339 | ||
a48777e0 | 340 | fw_notify("IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt, |
161b96e7 SR |
341 | evt & OHCI1394_selfIDComplete ? " selfID" : "", |
342 | evt & OHCI1394_RQPkt ? " AR_req" : "", | |
343 | evt & OHCI1394_RSPkt ? " AR_resp" : "", | |
344 | evt & OHCI1394_reqTxComplete ? " AT_req" : "", | |
345 | evt & OHCI1394_respTxComplete ? " AT_resp" : "", | |
346 | evt & OHCI1394_isochRx ? " IR" : "", | |
347 | evt & OHCI1394_isochTx ? " IT" : "", | |
348 | evt & OHCI1394_postedWriteErr ? " postedWriteErr" : "", | |
349 | evt & OHCI1394_cycleTooLong ? " cycleTooLong" : "", | |
a48777e0 | 350 | evt & OHCI1394_cycle64Seconds ? " cycle64Seconds" : "", |
5ed1f321 | 351 | evt & OHCI1394_cycleInconsistent ? " cycleInconsistent" : "", |
161b96e7 SR |
352 | evt & OHCI1394_regAccessFail ? " regAccessFail" : "", |
353 | evt & OHCI1394_busReset ? " busReset" : "", | |
354 | evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt | | |
355 | OHCI1394_RSPkt | OHCI1394_reqTxComplete | | |
356 | OHCI1394_respTxComplete | OHCI1394_isochRx | | |
357 | OHCI1394_isochTx | OHCI1394_postedWriteErr | | |
a48777e0 CL |
358 | OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds | |
359 | OHCI1394_cycleInconsistent | | |
161b96e7 | 360 | OHCI1394_regAccessFail | OHCI1394_busReset) |
ad3c0fe8 SR |
361 | ? " ?" : ""); |
362 | } | |
363 | ||
364 | static const char *speed[] = { | |
365 | [0] = "S100", [1] = "S200", [2] = "S400", [3] = "beta", | |
366 | }; | |
367 | static const char *power[] = { | |
368 | [0] = "+0W", [1] = "+15W", [2] = "+30W", [3] = "+45W", | |
369 | [4] = "-3W", [5] = " ?W", [6] = "-3..-6W", [7] = "-3..-10W", | |
370 | }; | |
371 | static const char port[] = { '.', '-', 'p', 'c', }; | |
372 | ||
373 | static char _p(u32 *s, int shift) | |
374 | { | |
375 | return port[*s >> shift & 3]; | |
376 | } | |
377 | ||
08ddb2f4 | 378 | static void log_selfids(int node_id, int generation, int self_id_count, u32 *s) |
ad3c0fe8 SR |
379 | { |
380 | if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS))) | |
381 | return; | |
382 | ||
161b96e7 SR |
383 | fw_notify("%d selfIDs, generation %d, local node ID %04x\n", |
384 | self_id_count, generation, node_id); | |
ad3c0fe8 SR |
385 | |
386 | for (; self_id_count--; ++s) | |
387 | if ((*s & 1 << 23) == 0) | |
161b96e7 SR |
388 | fw_notify("selfID 0: %08x, phy %d [%c%c%c] " |
389 | "%s gc=%d %s %s%s%s\n", | |
390 | *s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2), | |
391 | speed[*s >> 14 & 3], *s >> 16 & 63, | |
392 | power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "", | |
393 | *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : ""); | |
ad3c0fe8 | 394 | else |
161b96e7 SR |
395 | fw_notify("selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n", |
396 | *s, *s >> 24 & 63, | |
397 | _p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10), | |
398 | _p(s, 8), _p(s, 6), _p(s, 4), _p(s, 2)); | |
ad3c0fe8 SR |
399 | } |
400 | ||
401 | static const char *evts[] = { | |
402 | [0x00] = "evt_no_status", [0x01] = "-reserved-", | |
403 | [0x02] = "evt_long_packet", [0x03] = "evt_missing_ack", | |
404 | [0x04] = "evt_underrun", [0x05] = "evt_overrun", | |
405 | [0x06] = "evt_descriptor_read", [0x07] = "evt_data_read", | |
406 | [0x08] = "evt_data_write", [0x09] = "evt_bus_reset", | |
407 | [0x0a] = "evt_timeout", [0x0b] = "evt_tcode_err", | |
408 | [0x0c] = "-reserved-", [0x0d] = "-reserved-", | |
409 | [0x0e] = "evt_unknown", [0x0f] = "evt_flushed", | |
410 | [0x10] = "-reserved-", [0x11] = "ack_complete", | |
411 | [0x12] = "ack_pending ", [0x13] = "-reserved-", | |
412 | [0x14] = "ack_busy_X", [0x15] = "ack_busy_A", | |
413 | [0x16] = "ack_busy_B", [0x17] = "-reserved-", | |
414 | [0x18] = "-reserved-", [0x19] = "-reserved-", | |
415 | [0x1a] = "-reserved-", [0x1b] = "ack_tardy", | |
416 | [0x1c] = "-reserved-", [0x1d] = "ack_data_error", | |
417 | [0x1e] = "ack_type_error", [0x1f] = "-reserved-", | |
418 | [0x20] = "pending/cancelled", | |
419 | }; | |
420 | static const char *tcodes[] = { | |
421 | [0x0] = "QW req", [0x1] = "BW req", | |
422 | [0x2] = "W resp", [0x3] = "-reserved-", | |
423 | [0x4] = "QR req", [0x5] = "BR req", | |
424 | [0x6] = "QR resp", [0x7] = "BR resp", | |
425 | [0x8] = "cycle start", [0x9] = "Lk req", | |
426 | [0xa] = "async stream packet", [0xb] = "Lk resp", | |
427 | [0xc] = "-reserved-", [0xd] = "-reserved-", | |
428 | [0xe] = "link internal", [0xf] = "-reserved-", | |
429 | }; | |
ad3c0fe8 SR |
430 | |
431 | static void log_ar_at_event(char dir, int speed, u32 *header, int evt) | |
432 | { | |
433 | int tcode = header[0] >> 4 & 0xf; | |
434 | char specific[12]; | |
435 | ||
436 | if (likely(!(param_debug & OHCI_PARAM_DEBUG_AT_AR))) | |
437 | return; | |
438 | ||
439 | if (unlikely(evt >= ARRAY_SIZE(evts))) | |
440 | evt = 0x1f; | |
441 | ||
08ddb2f4 | 442 | if (evt == OHCI1394_evt_bus_reset) { |
161b96e7 SR |
443 | fw_notify("A%c evt_bus_reset, generation %d\n", |
444 | dir, (header[2] >> 16) & 0xff); | |
08ddb2f4 SR |
445 | return; |
446 | } | |
447 | ||
ad3c0fe8 SR |
448 | switch (tcode) { |
449 | case 0x0: case 0x6: case 0x8: | |
450 | snprintf(specific, sizeof(specific), " = %08x", | |
451 | be32_to_cpu((__force __be32)header[3])); | |
452 | break; | |
453 | case 0x1: case 0x5: case 0x7: case 0x9: case 0xb: | |
454 | snprintf(specific, sizeof(specific), " %x,%x", | |
455 | header[3] >> 16, header[3] & 0xffff); | |
456 | break; | |
457 | default: | |
458 | specific[0] = '\0'; | |
459 | } | |
460 | ||
461 | switch (tcode) { | |
5b06db16 | 462 | case 0xa: |
161b96e7 | 463 | fw_notify("A%c %s, %s\n", dir, evts[evt], tcodes[tcode]); |
ad3c0fe8 | 464 | break; |
5b06db16 CL |
465 | case 0xe: |
466 | fw_notify("A%c %s, PHY %08x %08x\n", | |
467 | dir, evts[evt], header[1], header[2]); | |
468 | break; | |
ad3c0fe8 | 469 | case 0x0: case 0x1: case 0x4: case 0x5: case 0x9: |
161b96e7 SR |
470 | fw_notify("A%c spd %x tl %02x, " |
471 | "%04x -> %04x, %s, " | |
472 | "%s, %04x%08x%s\n", | |
473 | dir, speed, header[0] >> 10 & 0x3f, | |
474 | header[1] >> 16, header[0] >> 16, evts[evt], | |
475 | tcodes[tcode], header[1] & 0xffff, header[2], specific); | |
ad3c0fe8 SR |
476 | break; |
477 | default: | |
161b96e7 SR |
478 | fw_notify("A%c spd %x tl %02x, " |
479 | "%04x -> %04x, %s, " | |
480 | "%s%s\n", | |
481 | dir, speed, header[0] >> 10 & 0x3f, | |
482 | header[1] >> 16, header[0] >> 16, evts[evt], | |
483 | tcodes[tcode], specific); | |
ad3c0fe8 SR |
484 | } |
485 | } | |
486 | ||
487 | #else | |
488 | ||
5da3dac8 SR |
489 | #define param_debug 0 |
490 | static inline void log_irqs(u32 evt) {} | |
491 | static inline void log_selfids(int node_id, int generation, int self_id_count, u32 *s) {} | |
492 | static inline void log_ar_at_event(char dir, int speed, u32 *header, int evt) {} | |
ad3c0fe8 SR |
493 | |
494 | #endif /* CONFIG_FIREWIRE_OHCI_DEBUG */ | |
495 | ||
95688e97 | 496 | static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data) |
ed568912 KH |
497 | { |
498 | writel(data, ohci->registers + offset); | |
499 | } | |
500 | ||
95688e97 | 501 | static inline u32 reg_read(const struct fw_ohci *ohci, int offset) |
ed568912 KH |
502 | { |
503 | return readl(ohci->registers + offset); | |
504 | } | |
505 | ||
95688e97 | 506 | static inline void flush_writes(const struct fw_ohci *ohci) |
ed568912 KH |
507 | { |
508 | /* Do a dummy read to flush writes. */ | |
509 | reg_read(ohci, OHCI1394_Version); | |
510 | } | |
511 | ||
35d999b1 | 512 | static int read_phy_reg(struct fw_ohci *ohci, int addr) |
ed568912 | 513 | { |
4a96b4fc | 514 | u32 val; |
35d999b1 | 515 | int i; |
ed568912 KH |
516 | |
517 | reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr)); | |
153e3979 | 518 | for (i = 0; i < 3 + 100; i++) { |
35d999b1 SR |
519 | val = reg_read(ohci, OHCI1394_PhyControl); |
520 | if (val & OHCI1394_PhyControl_ReadDone) | |
521 | return OHCI1394_PhyControl_ReadData(val); | |
522 | ||
153e3979 CL |
523 | /* |
524 | * Try a few times without waiting. Sleeping is necessary | |
525 | * only when the link/PHY interface is busy. | |
526 | */ | |
527 | if (i >= 3) | |
528 | msleep(1); | |
ed568912 | 529 | } |
35d999b1 | 530 | fw_error("failed to read phy reg\n"); |
ed568912 | 531 | |
35d999b1 SR |
532 | return -EBUSY; |
533 | } | |
4a96b4fc | 534 | |
35d999b1 SR |
535 | static int write_phy_reg(const struct fw_ohci *ohci, int addr, u32 val) |
536 | { | |
537 | int i; | |
ed568912 | 538 | |
ed568912 | 539 | reg_write(ohci, OHCI1394_PhyControl, |
35d999b1 | 540 | OHCI1394_PhyControl_Write(addr, val)); |
153e3979 | 541 | for (i = 0; i < 3 + 100; i++) { |
35d999b1 SR |
542 | val = reg_read(ohci, OHCI1394_PhyControl); |
543 | if (!(val & OHCI1394_PhyControl_WritePending)) | |
544 | return 0; | |
ed568912 | 545 | |
153e3979 CL |
546 | if (i >= 3) |
547 | msleep(1); | |
35d999b1 SR |
548 | } |
549 | fw_error("failed to write phy reg\n"); | |
550 | ||
551 | return -EBUSY; | |
4a96b4fc CL |
552 | } |
553 | ||
02d37bed SR |
554 | static int update_phy_reg(struct fw_ohci *ohci, int addr, |
555 | int clear_bits, int set_bits) | |
4a96b4fc | 556 | { |
02d37bed | 557 | int ret = read_phy_reg(ohci, addr); |
35d999b1 SR |
558 | if (ret < 0) |
559 | return ret; | |
4a96b4fc | 560 | |
e7014dad CL |
561 | /* |
562 | * The interrupt status bits are cleared by writing a one bit. | |
563 | * Avoid clearing them unless explicitly requested in set_bits. | |
564 | */ | |
565 | if (addr == 5) | |
566 | clear_bits |= PHY_INT_STATUS_BITS; | |
567 | ||
35d999b1 | 568 | return write_phy_reg(ohci, addr, (ret & ~clear_bits) | set_bits); |
ed568912 KH |
569 | } |
570 | ||
35d999b1 | 571 | static int read_paged_phy_reg(struct fw_ohci *ohci, int page, int addr) |
925e7a65 | 572 | { |
35d999b1 | 573 | int ret; |
925e7a65 | 574 | |
02d37bed | 575 | ret = update_phy_reg(ohci, 7, PHY_PAGE_SELECT, page << 5); |
35d999b1 SR |
576 | if (ret < 0) |
577 | return ret; | |
925e7a65 | 578 | |
35d999b1 | 579 | return read_phy_reg(ohci, addr); |
ed568912 KH |
580 | } |
581 | ||
02d37bed SR |
582 | static int ohci_read_phy_reg(struct fw_card *card, int addr) |
583 | { | |
584 | struct fw_ohci *ohci = fw_ohci(card); | |
585 | int ret; | |
586 | ||
587 | mutex_lock(&ohci->phy_reg_mutex); | |
588 | ret = read_phy_reg(ohci, addr); | |
589 | mutex_unlock(&ohci->phy_reg_mutex); | |
590 | ||
591 | return ret; | |
592 | } | |
593 | ||
594 | static int ohci_update_phy_reg(struct fw_card *card, int addr, | |
595 | int clear_bits, int set_bits) | |
596 | { | |
597 | struct fw_ohci *ohci = fw_ohci(card); | |
598 | int ret; | |
599 | ||
600 | mutex_lock(&ohci->phy_reg_mutex); | |
601 | ret = update_phy_reg(ohci, addr, clear_bits, set_bits); | |
602 | mutex_unlock(&ohci->phy_reg_mutex); | |
603 | ||
604 | return ret; | |
ed568912 KH |
605 | } |
606 | ||
7a39d8b8 CL |
607 | static inline dma_addr_t ar_buffer_bus(struct ar_context *ctx, unsigned int i) |
608 | { | |
609 | return page_private(ctx->pages[i]); | |
610 | } | |
611 | ||
612 | static void ar_context_link_page(struct ar_context *ctx, unsigned int index) | |
ed568912 | 613 | { |
7a39d8b8 | 614 | struct descriptor *d; |
32b46093 | 615 | |
7a39d8b8 CL |
616 | d = &ctx->descriptors[index]; |
617 | d->branch_address &= cpu_to_le32(~0xf); | |
618 | d->res_count = cpu_to_le16(PAGE_SIZE); | |
619 | d->transfer_status = 0; | |
32b46093 | 620 | |
071595eb | 621 | wmb(); /* finish init of new descriptors before branch_address update */ |
7a39d8b8 CL |
622 | d = &ctx->descriptors[ctx->last_buffer_index]; |
623 | d->branch_address |= cpu_to_le32(1); | |
624 | ||
625 | ctx->last_buffer_index = index; | |
32b46093 | 626 | |
a77754a7 | 627 | reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE); |
ed568912 | 628 | flush_writes(ctx->ohci); |
837596a6 CL |
629 | } |
630 | ||
7a39d8b8 | 631 | static void ar_context_release(struct ar_context *ctx) |
837596a6 | 632 | { |
7a39d8b8 | 633 | unsigned int i; |
837596a6 | 634 | |
7a39d8b8 CL |
635 | if (ctx->buffer) |
636 | vm_unmap_ram(ctx->buffer, AR_BUFFERS + AR_WRAPAROUND_PAGES); | |
32b46093 | 637 | |
7a39d8b8 CL |
638 | for (i = 0; i < AR_BUFFERS; i++) |
639 | if (ctx->pages[i]) { | |
640 | dma_unmap_page(ctx->ohci->card.device, | |
641 | ar_buffer_bus(ctx, i), | |
642 | PAGE_SIZE, DMA_FROM_DEVICE); | |
643 | __free_page(ctx->pages[i]); | |
644 | } | |
ed568912 KH |
645 | } |
646 | ||
7a39d8b8 | 647 | static void ar_context_abort(struct ar_context *ctx, const char *error_msg) |
a55709ba | 648 | { |
7a39d8b8 CL |
649 | if (reg_read(ctx->ohci, CONTROL_CLEAR(ctx->regs)) & CONTEXT_RUN) { |
650 | reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN); | |
651 | flush_writes(ctx->ohci); | |
a55709ba | 652 | |
7a39d8b8 | 653 | fw_error("AR error: %s; DMA stopped\n", error_msg); |
a55709ba | 654 | } |
7a39d8b8 CL |
655 | /* FIXME: restart? */ |
656 | } | |
657 | ||
658 | static inline unsigned int ar_next_buffer_index(unsigned int index) | |
659 | { | |
660 | return (index + 1) % AR_BUFFERS; | |
661 | } | |
662 | ||
663 | static inline unsigned int ar_prev_buffer_index(unsigned int index) | |
664 | { | |
665 | return (index - 1 + AR_BUFFERS) % AR_BUFFERS; | |
666 | } | |
667 | ||
668 | static inline unsigned int ar_first_buffer_index(struct ar_context *ctx) | |
669 | { | |
670 | return ar_next_buffer_index(ctx->last_buffer_index); | |
671 | } | |
672 | ||
673 | /* | |
674 | * We search for the buffer that contains the last AR packet DMA data written | |
675 | * by the controller. | |
676 | */ | |
677 | static unsigned int ar_search_last_active_buffer(struct ar_context *ctx, | |
678 | unsigned int *buffer_offset) | |
679 | { | |
680 | unsigned int i, next_i, last = ctx->last_buffer_index; | |
681 | __le16 res_count, next_res_count; | |
682 | ||
683 | i = ar_first_buffer_index(ctx); | |
684 | res_count = ACCESS_ONCE(ctx->descriptors[i].res_count); | |
685 | ||
686 | /* A buffer that is not yet completely filled must be the last one. */ | |
687 | while (i != last && res_count == 0) { | |
688 | ||
689 | /* Peek at the next descriptor. */ | |
690 | next_i = ar_next_buffer_index(i); | |
691 | rmb(); /* read descriptors in order */ | |
692 | next_res_count = ACCESS_ONCE( | |
693 | ctx->descriptors[next_i].res_count); | |
694 | /* | |
695 | * If the next descriptor is still empty, we must stop at this | |
696 | * descriptor. | |
697 | */ | |
698 | if (next_res_count == cpu_to_le16(PAGE_SIZE)) { | |
699 | /* | |
700 | * The exception is when the DMA data for one packet is | |
701 | * split over three buffers; in this case, the middle | |
702 | * buffer's descriptor might be never updated by the | |
703 | * controller and look still empty, and we have to peek | |
704 | * at the third one. | |
705 | */ | |
706 | if (MAX_AR_PACKET_SIZE > PAGE_SIZE && i != last) { | |
707 | next_i = ar_next_buffer_index(next_i); | |
708 | rmb(); | |
709 | next_res_count = ACCESS_ONCE( | |
710 | ctx->descriptors[next_i].res_count); | |
711 | if (next_res_count != cpu_to_le16(PAGE_SIZE)) | |
712 | goto next_buffer_is_active; | |
713 | } | |
714 | ||
715 | break; | |
716 | } | |
717 | ||
718 | next_buffer_is_active: | |
719 | i = next_i; | |
720 | res_count = next_res_count; | |
721 | } | |
722 | ||
723 | rmb(); /* read res_count before the DMA data */ | |
724 | ||
725 | *buffer_offset = PAGE_SIZE - le16_to_cpu(res_count); | |
726 | if (*buffer_offset > PAGE_SIZE) { | |
727 | *buffer_offset = 0; | |
728 | ar_context_abort(ctx, "corrupted descriptor"); | |
729 | } | |
730 | ||
731 | return i; | |
732 | } | |
733 | ||
734 | static void ar_sync_buffers_for_cpu(struct ar_context *ctx, | |
735 | unsigned int end_buffer_index, | |
736 | unsigned int end_buffer_offset) | |
737 | { | |
738 | unsigned int i; | |
739 | ||
740 | i = ar_first_buffer_index(ctx); | |
741 | while (i != end_buffer_index) { | |
742 | dma_sync_single_for_cpu(ctx->ohci->card.device, | |
743 | ar_buffer_bus(ctx, i), | |
744 | PAGE_SIZE, DMA_FROM_DEVICE); | |
745 | i = ar_next_buffer_index(i); | |
746 | } | |
747 | if (end_buffer_offset > 0) | |
748 | dma_sync_single_for_cpu(ctx->ohci->card.device, | |
749 | ar_buffer_bus(ctx, i), | |
750 | end_buffer_offset, DMA_FROM_DEVICE); | |
a55709ba JF |
751 | } |
752 | ||
11bf20ad SR |
753 | #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32) |
754 | #define cond_le32_to_cpu(v) \ | |
4a635593 | 755 | (ohci->quirks & QUIRK_BE_HEADERS ? (__force __u32)(v) : le32_to_cpu(v)) |
11bf20ad SR |
756 | #else |
757 | #define cond_le32_to_cpu(v) le32_to_cpu(v) | |
758 | #endif | |
759 | ||
32b46093 | 760 | static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer) |
ed568912 | 761 | { |
ed568912 | 762 | struct fw_ohci *ohci = ctx->ohci; |
2639a6fb KH |
763 | struct fw_packet p; |
764 | u32 status, length, tcode; | |
43286568 | 765 | int evt; |
2639a6fb | 766 | |
11bf20ad SR |
767 | p.header[0] = cond_le32_to_cpu(buffer[0]); |
768 | p.header[1] = cond_le32_to_cpu(buffer[1]); | |
769 | p.header[2] = cond_le32_to_cpu(buffer[2]); | |
2639a6fb KH |
770 | |
771 | tcode = (p.header[0] >> 4) & 0x0f; | |
772 | switch (tcode) { | |
773 | case TCODE_WRITE_QUADLET_REQUEST: | |
774 | case TCODE_READ_QUADLET_RESPONSE: | |
32b46093 | 775 | p.header[3] = (__force __u32) buffer[3]; |
2639a6fb | 776 | p.header_length = 16; |
32b46093 | 777 | p.payload_length = 0; |
2639a6fb KH |
778 | break; |
779 | ||
2639a6fb | 780 | case TCODE_READ_BLOCK_REQUEST : |
11bf20ad | 781 | p.header[3] = cond_le32_to_cpu(buffer[3]); |
32b46093 KH |
782 | p.header_length = 16; |
783 | p.payload_length = 0; | |
784 | break; | |
785 | ||
786 | case TCODE_WRITE_BLOCK_REQUEST: | |
2639a6fb KH |
787 | case TCODE_READ_BLOCK_RESPONSE: |
788 | case TCODE_LOCK_REQUEST: | |
789 | case TCODE_LOCK_RESPONSE: | |
11bf20ad | 790 | p.header[3] = cond_le32_to_cpu(buffer[3]); |
2639a6fb | 791 | p.header_length = 16; |
32b46093 | 792 | p.payload_length = p.header[3] >> 16; |
7a39d8b8 CL |
793 | if (p.payload_length > MAX_ASYNC_PAYLOAD) { |
794 | ar_context_abort(ctx, "invalid packet length"); | |
795 | return NULL; | |
796 | } | |
2639a6fb KH |
797 | break; |
798 | ||
799 | case TCODE_WRITE_RESPONSE: | |
800 | case TCODE_READ_QUADLET_REQUEST: | |
32b46093 | 801 | case OHCI_TCODE_PHY_PACKET: |
2639a6fb | 802 | p.header_length = 12; |
32b46093 | 803 | p.payload_length = 0; |
2639a6fb | 804 | break; |
ccff9629 SR |
805 | |
806 | default: | |
7a39d8b8 CL |
807 | ar_context_abort(ctx, "invalid tcode"); |
808 | return NULL; | |
2639a6fb | 809 | } |
ed568912 | 810 | |
32b46093 KH |
811 | p.payload = (void *) buffer + p.header_length; |
812 | ||
813 | /* FIXME: What to do about evt_* errors? */ | |
814 | length = (p.header_length + p.payload_length + 3) / 4; | |
11bf20ad | 815 | status = cond_le32_to_cpu(buffer[length]); |
43286568 | 816 | evt = (status >> 16) & 0x1f; |
32b46093 | 817 | |
43286568 | 818 | p.ack = evt - 16; |
32b46093 KH |
819 | p.speed = (status >> 21) & 0x7; |
820 | p.timestamp = status & 0xffff; | |
821 | p.generation = ohci->request_generation; | |
ed568912 | 822 | |
43286568 | 823 | log_ar_at_event('R', p.speed, p.header, evt); |
ad3c0fe8 | 824 | |
c781c06d | 825 | /* |
a4dc090b SR |
826 | * Several controllers, notably from NEC and VIA, forget to |
827 | * write ack_complete status at PHY packet reception. | |
828 | */ | |
829 | if (evt == OHCI1394_evt_no_status && | |
830 | (p.header[0] & 0xff) == (OHCI1394_phy_tcode << 4)) | |
831 | p.ack = ACK_COMPLETE; | |
832 | ||
833 | /* | |
834 | * The OHCI bus reset handler synthesizes a PHY packet with | |
ed568912 KH |
835 | * the new generation number when a bus reset happens (see |
836 | * section 8.4.2.3). This helps us determine when a request | |
837 | * was received and make sure we send the response in the same | |
838 | * generation. We only need this for requests; for responses | |
839 | * we use the unique tlabel for finding the matching | |
c781c06d | 840 | * request. |
d34316a4 SR |
841 | * |
842 | * Alas some chips sometimes emit bus reset packets with a | |
843 | * wrong generation. We set the correct generation for these | |
844 | * at a slightly incorrect time (in bus_reset_tasklet). | |
c781c06d | 845 | */ |
d34316a4 | 846 | if (evt == OHCI1394_evt_bus_reset) { |
4a635593 | 847 | if (!(ohci->quirks & QUIRK_RESET_PACKET)) |
d34316a4 SR |
848 | ohci->request_generation = (p.header[2] >> 16) & 0xff; |
849 | } else if (ctx == &ohci->ar_request_ctx) { | |
2639a6fb | 850 | fw_core_handle_request(&ohci->card, &p); |
d34316a4 | 851 | } else { |
2639a6fb | 852 | fw_core_handle_response(&ohci->card, &p); |
d34316a4 | 853 | } |
ed568912 | 854 | |
32b46093 KH |
855 | return buffer + length + 1; |
856 | } | |
ed568912 | 857 | |
7a39d8b8 CL |
858 | static void *handle_ar_packets(struct ar_context *ctx, void *p, void *end) |
859 | { | |
860 | void *next; | |
861 | ||
862 | while (p < end) { | |
863 | next = handle_ar_packet(ctx, p); | |
864 | if (!next) | |
865 | return p; | |
866 | p = next; | |
867 | } | |
868 | ||
869 | return p; | |
870 | } | |
871 | ||
872 | static void ar_recycle_buffers(struct ar_context *ctx, unsigned int end_buffer) | |
873 | { | |
874 | unsigned int i; | |
875 | ||
876 | i = ar_first_buffer_index(ctx); | |
877 | while (i != end_buffer) { | |
878 | dma_sync_single_for_device(ctx->ohci->card.device, | |
879 | ar_buffer_bus(ctx, i), | |
880 | PAGE_SIZE, DMA_FROM_DEVICE); | |
881 | ar_context_link_page(ctx, i); | |
882 | i = ar_next_buffer_index(i); | |
883 | } | |
884 | } | |
885 | ||
32b46093 KH |
886 | static void ar_context_tasklet(unsigned long data) |
887 | { | |
888 | struct ar_context *ctx = (struct ar_context *)data; | |
7a39d8b8 CL |
889 | unsigned int end_buffer_index, end_buffer_offset; |
890 | void *p, *end; | |
32b46093 | 891 | |
7a39d8b8 CL |
892 | p = ctx->pointer; |
893 | if (!p) | |
894 | return; | |
32b46093 | 895 | |
7a39d8b8 CL |
896 | end_buffer_index = ar_search_last_active_buffer(ctx, |
897 | &end_buffer_offset); | |
898 | ar_sync_buffers_for_cpu(ctx, end_buffer_index, end_buffer_offset); | |
899 | end = ctx->buffer + end_buffer_index * PAGE_SIZE + end_buffer_offset; | |
32b46093 | 900 | |
7a39d8b8 | 901 | if (end_buffer_index < ar_first_buffer_index(ctx)) { |
c781c06d | 902 | /* |
7a39d8b8 CL |
903 | * The filled part of the overall buffer wraps around; handle |
904 | * all packets up to the buffer end here. If the last packet | |
905 | * wraps around, its tail will be visible after the buffer end | |
906 | * because the buffer start pages are mapped there again. | |
c781c06d | 907 | */ |
7a39d8b8 CL |
908 | void *buffer_end = ctx->buffer + AR_BUFFERS * PAGE_SIZE; |
909 | p = handle_ar_packets(ctx, p, buffer_end); | |
910 | if (p < buffer_end) | |
911 | goto error; | |
912 | /* adjust p to point back into the actual buffer */ | |
913 | p -= AR_BUFFERS * PAGE_SIZE; | |
914 | } | |
32b46093 | 915 | |
7a39d8b8 CL |
916 | p = handle_ar_packets(ctx, p, end); |
917 | if (p != end) { | |
918 | if (p > end) | |
919 | ar_context_abort(ctx, "inconsistent descriptor"); | |
920 | goto error; | |
921 | } | |
32b46093 | 922 | |
7a39d8b8 CL |
923 | ctx->pointer = p; |
924 | ar_recycle_buffers(ctx, end_buffer_index); | |
32b46093 | 925 | |
7a39d8b8 | 926 | return; |
a1f805e5 | 927 | |
7a39d8b8 CL |
928 | error: |
929 | ctx->pointer = NULL; | |
ed568912 KH |
930 | } |
931 | ||
ec766a79 CL |
932 | static int ar_context_init(struct ar_context *ctx, struct fw_ohci *ohci, |
933 | unsigned int descriptors_offset, u32 regs) | |
ed568912 | 934 | { |
7a39d8b8 CL |
935 | unsigned int i; |
936 | dma_addr_t dma_addr; | |
937 | struct page *pages[AR_BUFFERS + AR_WRAPAROUND_PAGES]; | |
938 | struct descriptor *d; | |
ed568912 | 939 | |
72e318e0 KH |
940 | ctx->regs = regs; |
941 | ctx->ohci = ohci; | |
ed568912 KH |
942 | tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx); |
943 | ||
7a39d8b8 CL |
944 | for (i = 0; i < AR_BUFFERS; i++) { |
945 | ctx->pages[i] = alloc_page(GFP_KERNEL | GFP_DMA32); | |
946 | if (!ctx->pages[i]) | |
947 | goto out_of_memory; | |
948 | dma_addr = dma_map_page(ohci->card.device, ctx->pages[i], | |
949 | 0, PAGE_SIZE, DMA_FROM_DEVICE); | |
950 | if (dma_mapping_error(ohci->card.device, dma_addr)) { | |
951 | __free_page(ctx->pages[i]); | |
952 | ctx->pages[i] = NULL; | |
953 | goto out_of_memory; | |
954 | } | |
955 | set_page_private(ctx->pages[i], dma_addr); | |
956 | } | |
957 | ||
958 | for (i = 0; i < AR_BUFFERS; i++) | |
959 | pages[i] = ctx->pages[i]; | |
960 | for (i = 0; i < AR_WRAPAROUND_PAGES; i++) | |
961 | pages[AR_BUFFERS + i] = ctx->pages[i]; | |
962 | ctx->buffer = vm_map_ram(pages, AR_BUFFERS + AR_WRAPAROUND_PAGES, | |
963 | -1, PAGE_KERNEL_RO); | |
964 | if (!ctx->buffer) | |
965 | goto out_of_memory; | |
966 | ||
ec766a79 CL |
967 | ctx->descriptors = ohci->misc_buffer + descriptors_offset; |
968 | ctx->descriptors_bus = ohci->misc_buffer_bus + descriptors_offset; | |
7a39d8b8 CL |
969 | |
970 | for (i = 0; i < AR_BUFFERS; i++) { | |
971 | d = &ctx->descriptors[i]; | |
972 | d->req_count = cpu_to_le16(PAGE_SIZE); | |
973 | d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE | | |
974 | DESCRIPTOR_STATUS | | |
975 | DESCRIPTOR_BRANCH_ALWAYS); | |
976 | d->data_address = cpu_to_le32(ar_buffer_bus(ctx, i)); | |
977 | d->branch_address = cpu_to_le32(ctx->descriptors_bus + | |
978 | ar_next_buffer_index(i) * sizeof(struct descriptor)); | |
979 | } | |
32b46093 | 980 | |
2aef469a | 981 | return 0; |
7a39d8b8 CL |
982 | |
983 | out_of_memory: | |
984 | ar_context_release(ctx); | |
985 | ||
986 | return -ENOMEM; | |
2aef469a KH |
987 | } |
988 | ||
989 | static void ar_context_run(struct ar_context *ctx) | |
990 | { | |
7a39d8b8 CL |
991 | unsigned int i; |
992 | ||
993 | for (i = 0; i < AR_BUFFERS; i++) | |
994 | ar_context_link_page(ctx, i); | |
2aef469a | 995 | |
7a39d8b8 | 996 | ctx->pointer = ctx->buffer; |
2aef469a | 997 | |
7a39d8b8 | 998 | reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ctx->descriptors_bus | 1); |
a77754a7 | 999 | reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN); |
32b46093 | 1000 | flush_writes(ctx->ohci); |
ed568912 | 1001 | } |
373b2edd | 1002 | |
53dca511 | 1003 | static struct descriptor *find_branch_descriptor(struct descriptor *d, int z) |
a186b4a6 JW |
1004 | { |
1005 | int b, key; | |
1006 | ||
1007 | b = (le16_to_cpu(d->control) & DESCRIPTOR_BRANCH_ALWAYS) >> 2; | |
1008 | key = (le16_to_cpu(d->control) & DESCRIPTOR_KEY_IMMEDIATE) >> 8; | |
1009 | ||
1010 | /* figure out which descriptor the branch address goes in */ | |
1011 | if (z == 2 && (b == 3 || key == 2)) | |
1012 | return d; | |
1013 | else | |
1014 | return d + z - 1; | |
1015 | } | |
1016 | ||
30200739 KH |
1017 | static void context_tasklet(unsigned long data) |
1018 | { | |
1019 | struct context *ctx = (struct context *) data; | |
30200739 KH |
1020 | struct descriptor *d, *last; |
1021 | u32 address; | |
1022 | int z; | |
fe5ca634 | 1023 | struct descriptor_buffer *desc; |
30200739 | 1024 | |
fe5ca634 DM |
1025 | desc = list_entry(ctx->buffer_list.next, |
1026 | struct descriptor_buffer, list); | |
1027 | last = ctx->last; | |
30200739 | 1028 | while (last->branch_address != 0) { |
fe5ca634 | 1029 | struct descriptor_buffer *old_desc = desc; |
30200739 KH |
1030 | address = le32_to_cpu(last->branch_address); |
1031 | z = address & 0xf; | |
fe5ca634 DM |
1032 | address &= ~0xf; |
1033 | ||
1034 | /* If the branch address points to a buffer outside of the | |
1035 | * current buffer, advance to the next buffer. */ | |
1036 | if (address < desc->buffer_bus || | |
1037 | address >= desc->buffer_bus + desc->used) | |
1038 | desc = list_entry(desc->list.next, | |
1039 | struct descriptor_buffer, list); | |
1040 | d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d); | |
a186b4a6 | 1041 | last = find_branch_descriptor(d, z); |
30200739 KH |
1042 | |
1043 | if (!ctx->callback(ctx, d, last)) | |
1044 | break; | |
1045 | ||
fe5ca634 DM |
1046 | if (old_desc != desc) { |
1047 | /* If we've advanced to the next buffer, move the | |
1048 | * previous buffer to the free list. */ | |
1049 | unsigned long flags; | |
1050 | old_desc->used = 0; | |
1051 | spin_lock_irqsave(&ctx->ohci->lock, flags); | |
1052 | list_move_tail(&old_desc->list, &ctx->buffer_list); | |
1053 | spin_unlock_irqrestore(&ctx->ohci->lock, flags); | |
1054 | } | |
1055 | ctx->last = last; | |
30200739 KH |
1056 | } |
1057 | } | |
1058 | ||
fe5ca634 DM |
1059 | /* |
1060 | * Allocate a new buffer and add it to the list of free buffers for this | |
1061 | * context. Must be called with ohci->lock held. | |
1062 | */ | |
53dca511 | 1063 | static int context_add_buffer(struct context *ctx) |
fe5ca634 DM |
1064 | { |
1065 | struct descriptor_buffer *desc; | |
f5101d58 | 1066 | dma_addr_t uninitialized_var(bus_addr); |
fe5ca634 DM |
1067 | int offset; |
1068 | ||
1069 | /* | |
1070 | * 16MB of descriptors should be far more than enough for any DMA | |
1071 | * program. This will catch run-away userspace or DoS attacks. | |
1072 | */ | |
1073 | if (ctx->total_allocation >= 16*1024*1024) | |
1074 | return -ENOMEM; | |
1075 | ||
1076 | desc = dma_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE, | |
1077 | &bus_addr, GFP_ATOMIC); | |
1078 | if (!desc) | |
1079 | return -ENOMEM; | |
1080 | ||
1081 | offset = (void *)&desc->buffer - (void *)desc; | |
1082 | desc->buffer_size = PAGE_SIZE - offset; | |
1083 | desc->buffer_bus = bus_addr + offset; | |
1084 | desc->used = 0; | |
1085 | ||
1086 | list_add_tail(&desc->list, &ctx->buffer_list); | |
1087 | ctx->total_allocation += PAGE_SIZE; | |
1088 | ||
1089 | return 0; | |
1090 | } | |
1091 | ||
53dca511 SR |
1092 | static int context_init(struct context *ctx, struct fw_ohci *ohci, |
1093 | u32 regs, descriptor_callback_t callback) | |
30200739 KH |
1094 | { |
1095 | ctx->ohci = ohci; | |
1096 | ctx->regs = regs; | |
fe5ca634 DM |
1097 | ctx->total_allocation = 0; |
1098 | ||
1099 | INIT_LIST_HEAD(&ctx->buffer_list); | |
1100 | if (context_add_buffer(ctx) < 0) | |
30200739 KH |
1101 | return -ENOMEM; |
1102 | ||
fe5ca634 DM |
1103 | ctx->buffer_tail = list_entry(ctx->buffer_list.next, |
1104 | struct descriptor_buffer, list); | |
1105 | ||
30200739 KH |
1106 | tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx); |
1107 | ctx->callback = callback; | |
1108 | ||
c781c06d KH |
1109 | /* |
1110 | * We put a dummy descriptor in the buffer that has a NULL | |
30200739 | 1111 | * branch address and looks like it's been sent. That way we |
fe5ca634 | 1112 | * have a descriptor to append DMA programs to. |
c781c06d | 1113 | */ |
fe5ca634 DM |
1114 | memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer)); |
1115 | ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST); | |
1116 | ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011); | |
1117 | ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer); | |
1118 | ctx->last = ctx->buffer_tail->buffer; | |
1119 | ctx->prev = ctx->buffer_tail->buffer; | |
30200739 KH |
1120 | |
1121 | return 0; | |
1122 | } | |
1123 | ||
53dca511 | 1124 | static void context_release(struct context *ctx) |
30200739 KH |
1125 | { |
1126 | struct fw_card *card = &ctx->ohci->card; | |
fe5ca634 | 1127 | struct descriptor_buffer *desc, *tmp; |
30200739 | 1128 | |
fe5ca634 DM |
1129 | list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list) |
1130 | dma_free_coherent(card->device, PAGE_SIZE, desc, | |
1131 | desc->buffer_bus - | |
1132 | ((void *)&desc->buffer - (void *)desc)); | |
30200739 KH |
1133 | } |
1134 | ||
fe5ca634 | 1135 | /* Must be called with ohci->lock held */ |
53dca511 SR |
1136 | static struct descriptor *context_get_descriptors(struct context *ctx, |
1137 | int z, dma_addr_t *d_bus) | |
30200739 | 1138 | { |
fe5ca634 DM |
1139 | struct descriptor *d = NULL; |
1140 | struct descriptor_buffer *desc = ctx->buffer_tail; | |
1141 | ||
1142 | if (z * sizeof(*d) > desc->buffer_size) | |
1143 | return NULL; | |
1144 | ||
1145 | if (z * sizeof(*d) > desc->buffer_size - desc->used) { | |
1146 | /* No room for the descriptor in this buffer, so advance to the | |
1147 | * next one. */ | |
30200739 | 1148 | |
fe5ca634 DM |
1149 | if (desc->list.next == &ctx->buffer_list) { |
1150 | /* If there is no free buffer next in the list, | |
1151 | * allocate one. */ | |
1152 | if (context_add_buffer(ctx) < 0) | |
1153 | return NULL; | |
1154 | } | |
1155 | desc = list_entry(desc->list.next, | |
1156 | struct descriptor_buffer, list); | |
1157 | ctx->buffer_tail = desc; | |
1158 | } | |
30200739 | 1159 | |
fe5ca634 | 1160 | d = desc->buffer + desc->used / sizeof(*d); |
2d826cc5 | 1161 | memset(d, 0, z * sizeof(*d)); |
fe5ca634 | 1162 | *d_bus = desc->buffer_bus + desc->used; |
30200739 KH |
1163 | |
1164 | return d; | |
1165 | } | |
1166 | ||
295e3feb | 1167 | static void context_run(struct context *ctx, u32 extra) |
30200739 KH |
1168 | { |
1169 | struct fw_ohci *ohci = ctx->ohci; | |
dd23736e | 1170 | ctx->active = true; |
30200739 | 1171 | |
a77754a7 | 1172 | reg_write(ohci, COMMAND_PTR(ctx->regs), |
fe5ca634 | 1173 | le32_to_cpu(ctx->last->branch_address)); |
a77754a7 KH |
1174 | reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0); |
1175 | reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra); | |
30200739 KH |
1176 | flush_writes(ohci); |
1177 | } | |
1178 | ||
1179 | static void context_append(struct context *ctx, | |
1180 | struct descriptor *d, int z, int extra) | |
1181 | { | |
1182 | dma_addr_t d_bus; | |
fe5ca634 | 1183 | struct descriptor_buffer *desc = ctx->buffer_tail; |
30200739 | 1184 | |
fe5ca634 | 1185 | d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d); |
30200739 | 1186 | |
fe5ca634 | 1187 | desc->used += (z + extra) * sizeof(*d); |
071595eb SR |
1188 | |
1189 | wmb(); /* finish init of new descriptors before branch_address update */ | |
fe5ca634 DM |
1190 | ctx->prev->branch_address = cpu_to_le32(d_bus | z); |
1191 | ctx->prev = find_branch_descriptor(d, z); | |
30200739 | 1192 | |
a77754a7 | 1193 | reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE); |
30200739 KH |
1194 | flush_writes(ctx->ohci); |
1195 | } | |
1196 | ||
1197 | static void context_stop(struct context *ctx) | |
1198 | { | |
1199 | u32 reg; | |
b8295668 | 1200 | int i; |
30200739 | 1201 | |
dd23736e | 1202 | ctx->active = false; |
a77754a7 | 1203 | reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN); |
b8295668 | 1204 | flush_writes(ctx->ohci); |
30200739 | 1205 | |
b8295668 | 1206 | for (i = 0; i < 10; i++) { |
a77754a7 | 1207 | reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs)); |
b8295668 | 1208 | if ((reg & CONTEXT_ACTIVE) == 0) |
b0068549 | 1209 | return; |
b8295668 | 1210 | |
b980f5a2 | 1211 | mdelay(1); |
b8295668 | 1212 | } |
b0068549 | 1213 | fw_error("Error: DMA context still active (0x%08x)\n", reg); |
30200739 | 1214 | } |
ed568912 | 1215 | |
f319b6a0 KH |
1216 | struct driver_data { |
1217 | struct fw_packet *packet; | |
1218 | }; | |
ed568912 | 1219 | |
c781c06d KH |
1220 | /* |
1221 | * This function apppends a packet to the DMA queue for transmission. | |
f319b6a0 | 1222 | * Must always be called with the ochi->lock held to ensure proper |
c781c06d KH |
1223 | * generation handling and locking around packet queue manipulation. |
1224 | */ | |
53dca511 SR |
1225 | static int at_context_queue_packet(struct context *ctx, |
1226 | struct fw_packet *packet) | |
ed568912 | 1227 | { |
ed568912 | 1228 | struct fw_ohci *ohci = ctx->ohci; |
4b6d51ec | 1229 | dma_addr_t d_bus, uninitialized_var(payload_bus); |
f319b6a0 KH |
1230 | struct driver_data *driver_data; |
1231 | struct descriptor *d, *last; | |
1232 | __le32 *header; | |
ed568912 | 1233 | int z, tcode; |
f319b6a0 | 1234 | u32 reg; |
ed568912 | 1235 | |
f319b6a0 KH |
1236 | d = context_get_descriptors(ctx, 4, &d_bus); |
1237 | if (d == NULL) { | |
1238 | packet->ack = RCODE_SEND_ERROR; | |
1239 | return -1; | |
ed568912 KH |
1240 | } |
1241 | ||
a77754a7 | 1242 | d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE); |
f319b6a0 KH |
1243 | d[0].res_count = cpu_to_le16(packet->timestamp); |
1244 | ||
c781c06d KH |
1245 | /* |
1246 | * The DMA format for asyncronous link packets is different | |
ed568912 | 1247 | * from the IEEE1394 layout, so shift the fields around |
5b06db16 | 1248 | * accordingly. |
c781c06d | 1249 | */ |
f319b6a0 | 1250 | |
5b06db16 | 1251 | tcode = (packet->header[0] >> 4) & 0x0f; |
f319b6a0 | 1252 | header = (__le32 *) &d[1]; |
5b06db16 CL |
1253 | switch (tcode) { |
1254 | case TCODE_WRITE_QUADLET_REQUEST: | |
1255 | case TCODE_WRITE_BLOCK_REQUEST: | |
1256 | case TCODE_WRITE_RESPONSE: | |
1257 | case TCODE_READ_QUADLET_REQUEST: | |
1258 | case TCODE_READ_BLOCK_REQUEST: | |
1259 | case TCODE_READ_QUADLET_RESPONSE: | |
1260 | case TCODE_READ_BLOCK_RESPONSE: | |
1261 | case TCODE_LOCK_REQUEST: | |
1262 | case TCODE_LOCK_RESPONSE: | |
f319b6a0 KH |
1263 | header[0] = cpu_to_le32((packet->header[0] & 0xffff) | |
1264 | (packet->speed << 16)); | |
1265 | header[1] = cpu_to_le32((packet->header[1] & 0xffff) | | |
1266 | (packet->header[0] & 0xffff0000)); | |
1267 | header[2] = cpu_to_le32(packet->header[2]); | |
ed568912 | 1268 | |
ed568912 | 1269 | if (TCODE_IS_BLOCK_PACKET(tcode)) |
f319b6a0 | 1270 | header[3] = cpu_to_le32(packet->header[3]); |
ed568912 | 1271 | else |
f319b6a0 KH |
1272 | header[3] = (__force __le32) packet->header[3]; |
1273 | ||
1274 | d[0].req_count = cpu_to_le16(packet->header_length); | |
f8c2287c JF |
1275 | break; |
1276 | ||
5b06db16 | 1277 | case TCODE_LINK_INTERNAL: |
f319b6a0 KH |
1278 | header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) | |
1279 | (packet->speed << 16)); | |
5b06db16 CL |
1280 | header[1] = cpu_to_le32(packet->header[1]); |
1281 | header[2] = cpu_to_le32(packet->header[2]); | |
f319b6a0 | 1282 | d[0].req_count = cpu_to_le16(12); |
cc550216 | 1283 | |
5b06db16 | 1284 | if (is_ping_packet(&packet->header[1])) |
cc550216 | 1285 | d[0].control |= cpu_to_le16(DESCRIPTOR_PING); |
f8c2287c JF |
1286 | break; |
1287 | ||
5b06db16 | 1288 | case TCODE_STREAM_DATA: |
f8c2287c JF |
1289 | header[0] = cpu_to_le32((packet->header[0] & 0xffff) | |
1290 | (packet->speed << 16)); | |
1291 | header[1] = cpu_to_le32(packet->header[0] & 0xffff0000); | |
1292 | d[0].req_count = cpu_to_le16(8); | |
1293 | break; | |
1294 | ||
1295 | default: | |
1296 | /* BUG(); */ | |
1297 | packet->ack = RCODE_SEND_ERROR; | |
1298 | return -1; | |
ed568912 KH |
1299 | } |
1300 | ||
f319b6a0 KH |
1301 | driver_data = (struct driver_data *) &d[3]; |
1302 | driver_data->packet = packet; | |
20d11673 | 1303 | packet->driver_data = driver_data; |
a186b4a6 | 1304 | |
f319b6a0 KH |
1305 | if (packet->payload_length > 0) { |
1306 | payload_bus = | |
1307 | dma_map_single(ohci->card.device, packet->payload, | |
1308 | packet->payload_length, DMA_TO_DEVICE); | |
8d8bb39b | 1309 | if (dma_mapping_error(ohci->card.device, payload_bus)) { |
f319b6a0 KH |
1310 | packet->ack = RCODE_SEND_ERROR; |
1311 | return -1; | |
1312 | } | |
19593ffd SR |
1313 | packet->payload_bus = payload_bus; |
1314 | packet->payload_mapped = true; | |
f319b6a0 KH |
1315 | |
1316 | d[2].req_count = cpu_to_le16(packet->payload_length); | |
1317 | d[2].data_address = cpu_to_le32(payload_bus); | |
1318 | last = &d[2]; | |
1319 | z = 3; | |
ed568912 | 1320 | } else { |
f319b6a0 KH |
1321 | last = &d[0]; |
1322 | z = 2; | |
ed568912 | 1323 | } |
ed568912 | 1324 | |
a77754a7 KH |
1325 | last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST | |
1326 | DESCRIPTOR_IRQ_ALWAYS | | |
1327 | DESCRIPTOR_BRANCH_ALWAYS); | |
ed568912 | 1328 | |
76f73ca1 JW |
1329 | /* |
1330 | * If the controller and packet generations don't match, we need to | |
1331 | * bail out and try again. If IntEvent.busReset is set, the AT context | |
1332 | * is halted, so appending to the context and trying to run it is | |
1333 | * futile. Most controllers do the right thing and just flush the AT | |
1334 | * queue (per section 7.2.3.2 of the OHCI 1.1 specification), but | |
1335 | * some controllers (like a JMicron JMB381 PCI-e) misbehave and wind | |
1336 | * up stalling out. So we just bail out in software and try again | |
1337 | * later, and everyone is happy. | |
1338 | * FIXME: Document how the locking works. | |
1339 | */ | |
1340 | if (ohci->generation != packet->generation || | |
1341 | reg_read(ohci, OHCI1394_IntEventSet) & OHCI1394_busReset) { | |
19593ffd | 1342 | if (packet->payload_mapped) |
ab88ca48 SR |
1343 | dma_unmap_single(ohci->card.device, payload_bus, |
1344 | packet->payload_length, DMA_TO_DEVICE); | |
f319b6a0 KH |
1345 | packet->ack = RCODE_GENERATION; |
1346 | return -1; | |
1347 | } | |
1348 | ||
1349 | context_append(ctx, d, z, 4 - z); | |
ed568912 | 1350 | |
f319b6a0 | 1351 | /* If the context isn't already running, start it up. */ |
a77754a7 | 1352 | reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs)); |
053b3080 | 1353 | if ((reg & CONTEXT_RUN) == 0) |
f319b6a0 KH |
1354 | context_run(ctx, 0); |
1355 | ||
1356 | return 0; | |
ed568912 KH |
1357 | } |
1358 | ||
f319b6a0 KH |
1359 | static int handle_at_packet(struct context *context, |
1360 | struct descriptor *d, | |
1361 | struct descriptor *last) | |
ed568912 | 1362 | { |
f319b6a0 | 1363 | struct driver_data *driver_data; |
ed568912 | 1364 | struct fw_packet *packet; |
f319b6a0 | 1365 | struct fw_ohci *ohci = context->ohci; |
ed568912 KH |
1366 | int evt; |
1367 | ||
f319b6a0 KH |
1368 | if (last->transfer_status == 0) |
1369 | /* This descriptor isn't done yet, stop iteration. */ | |
1370 | return 0; | |
ed568912 | 1371 | |
f319b6a0 KH |
1372 | driver_data = (struct driver_data *) &d[3]; |
1373 | packet = driver_data->packet; | |
1374 | if (packet == NULL) | |
1375 | /* This packet was cancelled, just continue. */ | |
1376 | return 1; | |
730c32f5 | 1377 | |
19593ffd | 1378 | if (packet->payload_mapped) |
1d1dc5e8 | 1379 | dma_unmap_single(ohci->card.device, packet->payload_bus, |
ed568912 | 1380 | packet->payload_length, DMA_TO_DEVICE); |
ed568912 | 1381 | |
f319b6a0 KH |
1382 | evt = le16_to_cpu(last->transfer_status) & 0x1f; |
1383 | packet->timestamp = le16_to_cpu(last->res_count); | |
ed568912 | 1384 | |
ad3c0fe8 SR |
1385 | log_ar_at_event('T', packet->speed, packet->header, evt); |
1386 | ||
f319b6a0 KH |
1387 | switch (evt) { |
1388 | case OHCI1394_evt_timeout: | |
1389 | /* Async response transmit timed out. */ | |
1390 | packet->ack = RCODE_CANCELLED; | |
1391 | break; | |
ed568912 | 1392 | |
f319b6a0 | 1393 | case OHCI1394_evt_flushed: |
c781c06d KH |
1394 | /* |
1395 | * The packet was flushed should give same error as | |
1396 | * when we try to use a stale generation count. | |
1397 | */ | |
f319b6a0 KH |
1398 | packet->ack = RCODE_GENERATION; |
1399 | break; | |
ed568912 | 1400 | |
f319b6a0 | 1401 | case OHCI1394_evt_missing_ack: |
c781c06d KH |
1402 | /* |
1403 | * Using a valid (current) generation count, but the | |
1404 | * node is not on the bus or not sending acks. | |
1405 | */ | |
f319b6a0 KH |
1406 | packet->ack = RCODE_NO_ACK; |
1407 | break; | |
ed568912 | 1408 | |
f319b6a0 KH |
1409 | case ACK_COMPLETE + 0x10: |
1410 | case ACK_PENDING + 0x10: | |
1411 | case ACK_BUSY_X + 0x10: | |
1412 | case ACK_BUSY_A + 0x10: | |
1413 | case ACK_BUSY_B + 0x10: | |
1414 | case ACK_DATA_ERROR + 0x10: | |
1415 | case ACK_TYPE_ERROR + 0x10: | |
1416 | packet->ack = evt - 0x10; | |
1417 | break; | |
ed568912 | 1418 | |
f319b6a0 KH |
1419 | default: |
1420 | packet->ack = RCODE_SEND_ERROR; | |
1421 | break; | |
1422 | } | |
ed568912 | 1423 | |
f319b6a0 | 1424 | packet->callback(packet, &ohci->card, packet->ack); |
ed568912 | 1425 | |
f319b6a0 | 1426 | return 1; |
ed568912 KH |
1427 | } |
1428 | ||
a77754a7 KH |
1429 | #define HEADER_GET_DESTINATION(q) (((q) >> 16) & 0xffff) |
1430 | #define HEADER_GET_TCODE(q) (((q) >> 4) & 0x0f) | |
1431 | #define HEADER_GET_OFFSET_HIGH(q) (((q) >> 0) & 0xffff) | |
1432 | #define HEADER_GET_DATA_LENGTH(q) (((q) >> 16) & 0xffff) | |
1433 | #define HEADER_GET_EXTENDED_TCODE(q) (((q) >> 0) & 0xffff) | |
93c4cceb | 1434 | |
53dca511 SR |
1435 | static void handle_local_rom(struct fw_ohci *ohci, |
1436 | struct fw_packet *packet, u32 csr) | |
93c4cceb KH |
1437 | { |
1438 | struct fw_packet response; | |
1439 | int tcode, length, i; | |
1440 | ||
a77754a7 | 1441 | tcode = HEADER_GET_TCODE(packet->header[0]); |
93c4cceb | 1442 | if (TCODE_IS_BLOCK_PACKET(tcode)) |
a77754a7 | 1443 | length = HEADER_GET_DATA_LENGTH(packet->header[3]); |
93c4cceb KH |
1444 | else |
1445 | length = 4; | |
1446 | ||
1447 | i = csr - CSR_CONFIG_ROM; | |
1448 | if (i + length > CONFIG_ROM_SIZE) { | |
1449 | fw_fill_response(&response, packet->header, | |
1450 | RCODE_ADDRESS_ERROR, NULL, 0); | |
1451 | } else if (!TCODE_IS_READ_REQUEST(tcode)) { | |
1452 | fw_fill_response(&response, packet->header, | |
1453 | RCODE_TYPE_ERROR, NULL, 0); | |
1454 | } else { | |
1455 | fw_fill_response(&response, packet->header, RCODE_COMPLETE, | |
1456 | (void *) ohci->config_rom + i, length); | |
1457 | } | |
1458 | ||
1459 | fw_core_handle_response(&ohci->card, &response); | |
1460 | } | |
1461 | ||
53dca511 SR |
1462 | static void handle_local_lock(struct fw_ohci *ohci, |
1463 | struct fw_packet *packet, u32 csr) | |
93c4cceb KH |
1464 | { |
1465 | struct fw_packet response; | |
e1393667 | 1466 | int tcode, length, ext_tcode, sel, try; |
93c4cceb KH |
1467 | __be32 *payload, lock_old; |
1468 | u32 lock_arg, lock_data; | |
1469 | ||
a77754a7 KH |
1470 | tcode = HEADER_GET_TCODE(packet->header[0]); |
1471 | length = HEADER_GET_DATA_LENGTH(packet->header[3]); | |
93c4cceb | 1472 | payload = packet->payload; |
a77754a7 | 1473 | ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]); |
93c4cceb KH |
1474 | |
1475 | if (tcode == TCODE_LOCK_REQUEST && | |
1476 | ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) { | |
1477 | lock_arg = be32_to_cpu(payload[0]); | |
1478 | lock_data = be32_to_cpu(payload[1]); | |
1479 | } else if (tcode == TCODE_READ_QUADLET_REQUEST) { | |
1480 | lock_arg = 0; | |
1481 | lock_data = 0; | |
1482 | } else { | |
1483 | fw_fill_response(&response, packet->header, | |
1484 | RCODE_TYPE_ERROR, NULL, 0); | |
1485 | goto out; | |
1486 | } | |
1487 | ||
1488 | sel = (csr - CSR_BUS_MANAGER_ID) / 4; | |
1489 | reg_write(ohci, OHCI1394_CSRData, lock_data); | |
1490 | reg_write(ohci, OHCI1394_CSRCompareData, lock_arg); | |
1491 | reg_write(ohci, OHCI1394_CSRControl, sel); | |
1492 | ||
e1393667 CL |
1493 | for (try = 0; try < 20; try++) |
1494 | if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000) { | |
1495 | lock_old = cpu_to_be32(reg_read(ohci, | |
1496 | OHCI1394_CSRData)); | |
1497 | fw_fill_response(&response, packet->header, | |
1498 | RCODE_COMPLETE, | |
1499 | &lock_old, sizeof(lock_old)); | |
1500 | goto out; | |
1501 | } | |
1502 | ||
1503 | fw_error("swap not done (CSR lock timeout)\n"); | |
1504 | fw_fill_response(&response, packet->header, RCODE_BUSY, NULL, 0); | |
93c4cceb | 1505 | |
93c4cceb KH |
1506 | out: |
1507 | fw_core_handle_response(&ohci->card, &response); | |
1508 | } | |
1509 | ||
53dca511 | 1510 | static void handle_local_request(struct context *ctx, struct fw_packet *packet) |
93c4cceb | 1511 | { |
2608203d | 1512 | u64 offset, csr; |
93c4cceb | 1513 | |
473d28c7 KH |
1514 | if (ctx == &ctx->ohci->at_request_ctx) { |
1515 | packet->ack = ACK_PENDING; | |
1516 | packet->callback(packet, &ctx->ohci->card, packet->ack); | |
1517 | } | |
93c4cceb KH |
1518 | |
1519 | offset = | |
1520 | ((unsigned long long) | |
a77754a7 | 1521 | HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) | |
93c4cceb KH |
1522 | packet->header[2]; |
1523 | csr = offset - CSR_REGISTER_BASE; | |
1524 | ||
1525 | /* Handle config rom reads. */ | |
1526 | if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END) | |
1527 | handle_local_rom(ctx->ohci, packet, csr); | |
1528 | else switch (csr) { | |
1529 | case CSR_BUS_MANAGER_ID: | |
1530 | case CSR_BANDWIDTH_AVAILABLE: | |
1531 | case CSR_CHANNELS_AVAILABLE_HI: | |
1532 | case CSR_CHANNELS_AVAILABLE_LO: | |
1533 | handle_local_lock(ctx->ohci, packet, csr); | |
1534 | break; | |
1535 | default: | |
1536 | if (ctx == &ctx->ohci->at_request_ctx) | |
1537 | fw_core_handle_request(&ctx->ohci->card, packet); | |
1538 | else | |
1539 | fw_core_handle_response(&ctx->ohci->card, packet); | |
1540 | break; | |
1541 | } | |
473d28c7 KH |
1542 | |
1543 | if (ctx == &ctx->ohci->at_response_ctx) { | |
1544 | packet->ack = ACK_COMPLETE; | |
1545 | packet->callback(packet, &ctx->ohci->card, packet->ack); | |
1546 | } | |
93c4cceb | 1547 | } |
e636fe25 | 1548 | |
53dca511 | 1549 | static void at_context_transmit(struct context *ctx, struct fw_packet *packet) |
ed568912 | 1550 | { |
ed568912 | 1551 | unsigned long flags; |
2dbd7d7e | 1552 | int ret; |
ed568912 KH |
1553 | |
1554 | spin_lock_irqsave(&ctx->ohci->lock, flags); | |
1555 | ||
a77754a7 | 1556 | if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id && |
e636fe25 | 1557 | ctx->ohci->generation == packet->generation) { |
93c4cceb KH |
1558 | spin_unlock_irqrestore(&ctx->ohci->lock, flags); |
1559 | handle_local_request(ctx, packet); | |
1560 | return; | |
e636fe25 | 1561 | } |
ed568912 | 1562 | |
2dbd7d7e | 1563 | ret = at_context_queue_packet(ctx, packet); |
ed568912 KH |
1564 | spin_unlock_irqrestore(&ctx->ohci->lock, flags); |
1565 | ||
2dbd7d7e | 1566 | if (ret < 0) |
f319b6a0 | 1567 | packet->callback(packet, &ctx->ohci->card, packet->ack); |
a186b4a6 | 1568 | |
ed568912 KH |
1569 | } |
1570 | ||
a48777e0 CL |
1571 | static u32 cycle_timer_ticks(u32 cycle_timer) |
1572 | { | |
1573 | u32 ticks; | |
1574 | ||
1575 | ticks = cycle_timer & 0xfff; | |
1576 | ticks += 3072 * ((cycle_timer >> 12) & 0x1fff); | |
1577 | ticks += (3072 * 8000) * (cycle_timer >> 25); | |
1578 | ||
1579 | return ticks; | |
1580 | } | |
1581 | ||
1582 | /* | |
1583 | * Some controllers exhibit one or more of the following bugs when updating the | |
1584 | * iso cycle timer register: | |
1585 | * - When the lowest six bits are wrapping around to zero, a read that happens | |
1586 | * at the same time will return garbage in the lowest ten bits. | |
1587 | * - When the cycleOffset field wraps around to zero, the cycleCount field is | |
1588 | * not incremented for about 60 ns. | |
1589 | * - Occasionally, the entire register reads zero. | |
1590 | * | |
1591 | * To catch these, we read the register three times and ensure that the | |
1592 | * difference between each two consecutive reads is approximately the same, i.e. | |
1593 | * less than twice the other. Furthermore, any negative difference indicates an | |
1594 | * error. (A PCI read should take at least 20 ticks of the 24.576 MHz timer to | |
1595 | * execute, so we have enough precision to compute the ratio of the differences.) | |
1596 | */ | |
1597 | static u32 get_cycle_time(struct fw_ohci *ohci) | |
1598 | { | |
1599 | u32 c0, c1, c2; | |
1600 | u32 t0, t1, t2; | |
1601 | s32 diff01, diff12; | |
1602 | int i; | |
1603 | ||
1604 | c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer); | |
1605 | ||
1606 | if (ohci->quirks & QUIRK_CYCLE_TIMER) { | |
1607 | i = 0; | |
1608 | c1 = c2; | |
1609 | c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer); | |
1610 | do { | |
1611 | c0 = c1; | |
1612 | c1 = c2; | |
1613 | c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer); | |
1614 | t0 = cycle_timer_ticks(c0); | |
1615 | t1 = cycle_timer_ticks(c1); | |
1616 | t2 = cycle_timer_ticks(c2); | |
1617 | diff01 = t1 - t0; | |
1618 | diff12 = t2 - t1; | |
1619 | } while ((diff01 <= 0 || diff12 <= 0 || | |
1620 | diff01 / diff12 >= 2 || diff12 / diff01 >= 2) | |
1621 | && i++ < 20); | |
1622 | } | |
1623 | ||
1624 | return c2; | |
1625 | } | |
1626 | ||
1627 | /* | |
1628 | * This function has to be called at least every 64 seconds. The bus_time | |
1629 | * field stores not only the upper 25 bits of the BUS_TIME register but also | |
1630 | * the most significant bit of the cycle timer in bit 6 so that we can detect | |
1631 | * changes in this bit. | |
1632 | */ | |
1633 | static u32 update_bus_time(struct fw_ohci *ohci) | |
1634 | { | |
1635 | u32 cycle_time_seconds = get_cycle_time(ohci) >> 25; | |
1636 | ||
1637 | if ((ohci->bus_time & 0x40) != (cycle_time_seconds & 0x40)) | |
1638 | ohci->bus_time += 0x40; | |
1639 | ||
1640 | return ohci->bus_time | cycle_time_seconds; | |
1641 | } | |
1642 | ||
ed568912 KH |
1643 | static void bus_reset_tasklet(unsigned long data) |
1644 | { | |
1645 | struct fw_ohci *ohci = (struct fw_ohci *)data; | |
e636fe25 | 1646 | int self_id_count, i, j, reg; |
ed568912 KH |
1647 | int generation, new_generation; |
1648 | unsigned long flags; | |
4eaff7d6 SR |
1649 | void *free_rom = NULL; |
1650 | dma_addr_t free_rom_bus = 0; | |
4ffb7a6a | 1651 | bool is_new_root; |
ed568912 KH |
1652 | |
1653 | reg = reg_read(ohci, OHCI1394_NodeID); | |
1654 | if (!(reg & OHCI1394_NodeID_idValid)) { | |
02ff8f8e | 1655 | fw_notify("node ID not valid, new bus reset in progress\n"); |
ed568912 KH |
1656 | return; |
1657 | } | |
02ff8f8e SR |
1658 | if ((reg & OHCI1394_NodeID_nodeNumber) == 63) { |
1659 | fw_notify("malconfigured bus\n"); | |
1660 | return; | |
1661 | } | |
1662 | ohci->node_id = reg & (OHCI1394_NodeID_busNumber | | |
1663 | OHCI1394_NodeID_nodeNumber); | |
ed568912 | 1664 | |
4ffb7a6a CL |
1665 | is_new_root = (reg & OHCI1394_NodeID_root) != 0; |
1666 | if (!(ohci->is_root && is_new_root)) | |
1667 | reg_write(ohci, OHCI1394_LinkControlSet, | |
1668 | OHCI1394_LinkControl_cycleMaster); | |
1669 | ohci->is_root = is_new_root; | |
1670 | ||
c8a9a498 SR |
1671 | reg = reg_read(ohci, OHCI1394_SelfIDCount); |
1672 | if (reg & OHCI1394_SelfIDCount_selfIDError) { | |
1673 | fw_notify("inconsistent self IDs\n"); | |
1674 | return; | |
1675 | } | |
c781c06d KH |
1676 | /* |
1677 | * The count in the SelfIDCount register is the number of | |
ed568912 KH |
1678 | * bytes in the self ID receive buffer. Since we also receive |
1679 | * the inverted quadlets and a header quadlet, we shift one | |
c781c06d KH |
1680 | * bit extra to get the actual number of self IDs. |
1681 | */ | |
928ec5f1 SR |
1682 | self_id_count = (reg >> 3) & 0xff; |
1683 | if (self_id_count == 0 || self_id_count > 252) { | |
016bf3df SR |
1684 | fw_notify("inconsistent self IDs\n"); |
1685 | return; | |
1686 | } | |
11bf20ad | 1687 | generation = (cond_le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff; |
ee71c2f9 | 1688 | rmb(); |
ed568912 KH |
1689 | |
1690 | for (i = 1, j = 0; j < self_id_count; i += 2, j++) { | |
c8a9a498 SR |
1691 | if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1]) { |
1692 | fw_notify("inconsistent self IDs\n"); | |
1693 | return; | |
1694 | } | |
11bf20ad SR |
1695 | ohci->self_id_buffer[j] = |
1696 | cond_le32_to_cpu(ohci->self_id_cpu[i]); | |
ed568912 | 1697 | } |
ee71c2f9 | 1698 | rmb(); |
ed568912 | 1699 | |
c781c06d KH |
1700 | /* |
1701 | * Check the consistency of the self IDs we just read. The | |
ed568912 KH |
1702 | * problem we face is that a new bus reset can start while we |
1703 | * read out the self IDs from the DMA buffer. If this happens, | |
1704 | * the DMA buffer will be overwritten with new self IDs and we | |
1705 | * will read out inconsistent data. The OHCI specification | |
1706 | * (section 11.2) recommends a technique similar to | |
1707 | * linux/seqlock.h, where we remember the generation of the | |
1708 | * self IDs in the buffer before reading them out and compare | |
1709 | * it to the current generation after reading them out. If | |
1710 | * the two generations match we know we have a consistent set | |
c781c06d KH |
1711 | * of self IDs. |
1712 | */ | |
ed568912 KH |
1713 | |
1714 | new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff; | |
1715 | if (new_generation != generation) { | |
1716 | fw_notify("recursive bus reset detected, " | |
1717 | "discarding self ids\n"); | |
1718 | return; | |
1719 | } | |
1720 | ||
1721 | /* FIXME: Document how the locking works. */ | |
1722 | spin_lock_irqsave(&ohci->lock, flags); | |
1723 | ||
1724 | ohci->generation = generation; | |
f319b6a0 KH |
1725 | context_stop(&ohci->at_request_ctx); |
1726 | context_stop(&ohci->at_response_ctx); | |
ed568912 KH |
1727 | reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset); |
1728 | ||
4a635593 | 1729 | if (ohci->quirks & QUIRK_RESET_PACKET) |
d34316a4 SR |
1730 | ohci->request_generation = generation; |
1731 | ||
c781c06d KH |
1732 | /* |
1733 | * This next bit is unrelated to the AT context stuff but we | |
ed568912 KH |
1734 | * have to do it under the spinlock also. If a new config rom |
1735 | * was set up before this reset, the old one is now no longer | |
1736 | * in use and we can free it. Update the config rom pointers | |
1737 | * to point to the current config rom and clear the | |
88393161 | 1738 | * next_config_rom pointer so a new update can take place. |
c781c06d | 1739 | */ |
ed568912 KH |
1740 | |
1741 | if (ohci->next_config_rom != NULL) { | |
0bd243c4 KH |
1742 | if (ohci->next_config_rom != ohci->config_rom) { |
1743 | free_rom = ohci->config_rom; | |
1744 | free_rom_bus = ohci->config_rom_bus; | |
1745 | } | |
ed568912 KH |
1746 | ohci->config_rom = ohci->next_config_rom; |
1747 | ohci->config_rom_bus = ohci->next_config_rom_bus; | |
1748 | ohci->next_config_rom = NULL; | |
1749 | ||
c781c06d KH |
1750 | /* |
1751 | * Restore config_rom image and manually update | |
ed568912 KH |
1752 | * config_rom registers. Writing the header quadlet |
1753 | * will indicate that the config rom is ready, so we | |
c781c06d KH |
1754 | * do that last. |
1755 | */ | |
ed568912 KH |
1756 | reg_write(ohci, OHCI1394_BusOptions, |
1757 | be32_to_cpu(ohci->config_rom[2])); | |
8e85973e SR |
1758 | ohci->config_rom[0] = ohci->next_header; |
1759 | reg_write(ohci, OHCI1394_ConfigROMhdr, | |
1760 | be32_to_cpu(ohci->next_header)); | |
ed568912 KH |
1761 | } |
1762 | ||
080de8c2 SR |
1763 | #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA |
1764 | reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0); | |
1765 | reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0); | |
1766 | #endif | |
1767 | ||
ed568912 KH |
1768 | spin_unlock_irqrestore(&ohci->lock, flags); |
1769 | ||
4eaff7d6 SR |
1770 | if (free_rom) |
1771 | dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, | |
1772 | free_rom, free_rom_bus); | |
1773 | ||
08ddb2f4 SR |
1774 | log_selfids(ohci->node_id, generation, |
1775 | self_id_count, ohci->self_id_buffer); | |
ad3c0fe8 | 1776 | |
e636fe25 | 1777 | fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation, |
c8a94ded SR |
1778 | self_id_count, ohci->self_id_buffer, |
1779 | ohci->csr_state_setclear_abdicate); | |
1780 | ohci->csr_state_setclear_abdicate = false; | |
ed568912 KH |
1781 | } |
1782 | ||
1783 | static irqreturn_t irq_handler(int irq, void *data) | |
1784 | { | |
1785 | struct fw_ohci *ohci = data; | |
168cf9af | 1786 | u32 event, iso_event; |
ed568912 KH |
1787 | int i; |
1788 | ||
1789 | event = reg_read(ohci, OHCI1394_IntEventClear); | |
1790 | ||
a515958d | 1791 | if (!event || !~event) |
ed568912 KH |
1792 | return IRQ_NONE; |
1793 | ||
8327b37b CL |
1794 | /* |
1795 | * busReset and postedWriteErr must not be cleared yet | |
1796 | * (OHCI 1.1 clauses 7.2.3.2 and 13.2.8.1) | |
1797 | */ | |
1798 | reg_write(ohci, OHCI1394_IntEventClear, | |
1799 | event & ~(OHCI1394_busReset | OHCI1394_postedWriteErr)); | |
ad3c0fe8 | 1800 | log_irqs(event); |
ed568912 KH |
1801 | |
1802 | if (event & OHCI1394_selfIDComplete) | |
1803 | tasklet_schedule(&ohci->bus_reset_tasklet); | |
1804 | ||
1805 | if (event & OHCI1394_RQPkt) | |
1806 | tasklet_schedule(&ohci->ar_request_ctx.tasklet); | |
1807 | ||
1808 | if (event & OHCI1394_RSPkt) | |
1809 | tasklet_schedule(&ohci->ar_response_ctx.tasklet); | |
1810 | ||
1811 | if (event & OHCI1394_reqTxComplete) | |
1812 | tasklet_schedule(&ohci->at_request_ctx.tasklet); | |
1813 | ||
1814 | if (event & OHCI1394_respTxComplete) | |
1815 | tasklet_schedule(&ohci->at_response_ctx.tasklet); | |
1816 | ||
2dd5bed5 CL |
1817 | if (event & OHCI1394_isochRx) { |
1818 | iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear); | |
1819 | reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event); | |
1820 | ||
1821 | while (iso_event) { | |
1822 | i = ffs(iso_event) - 1; | |
1823 | tasklet_schedule( | |
1824 | &ohci->ir_context_list[i].context.tasklet); | |
1825 | iso_event &= ~(1 << i); | |
1826 | } | |
ed568912 KH |
1827 | } |
1828 | ||
2dd5bed5 CL |
1829 | if (event & OHCI1394_isochTx) { |
1830 | iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear); | |
1831 | reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event); | |
ed568912 | 1832 | |
2dd5bed5 CL |
1833 | while (iso_event) { |
1834 | i = ffs(iso_event) - 1; | |
1835 | tasklet_schedule( | |
1836 | &ohci->it_context_list[i].context.tasklet); | |
1837 | iso_event &= ~(1 << i); | |
1838 | } | |
ed568912 KH |
1839 | } |
1840 | ||
75f7832e JW |
1841 | if (unlikely(event & OHCI1394_regAccessFail)) |
1842 | fw_error("Register access failure - " | |
1843 | "please notify linux1394-devel@lists.sf.net\n"); | |
1844 | ||
8327b37b CL |
1845 | if (unlikely(event & OHCI1394_postedWriteErr)) { |
1846 | reg_read(ohci, OHCI1394_PostedWriteAddressHi); | |
1847 | reg_read(ohci, OHCI1394_PostedWriteAddressLo); | |
1848 | reg_write(ohci, OHCI1394_IntEventClear, | |
1849 | OHCI1394_postedWriteErr); | |
e524f616 | 1850 | fw_error("PCI posted write error\n"); |
8327b37b | 1851 | } |
e524f616 | 1852 | |
bb9f2206 SR |
1853 | if (unlikely(event & OHCI1394_cycleTooLong)) { |
1854 | if (printk_ratelimit()) | |
1855 | fw_notify("isochronous cycle too long\n"); | |
1856 | reg_write(ohci, OHCI1394_LinkControlSet, | |
1857 | OHCI1394_LinkControl_cycleMaster); | |
1858 | } | |
1859 | ||
5ed1f321 JF |
1860 | if (unlikely(event & OHCI1394_cycleInconsistent)) { |
1861 | /* | |
1862 | * We need to clear this event bit in order to make | |
1863 | * cycleMatch isochronous I/O work. In theory we should | |
1864 | * stop active cycleMatch iso contexts now and restart | |
1865 | * them at least two cycles later. (FIXME?) | |
1866 | */ | |
1867 | if (printk_ratelimit()) | |
1868 | fw_notify("isochronous cycle inconsistent\n"); | |
1869 | } | |
1870 | ||
a48777e0 CL |
1871 | if (event & OHCI1394_cycle64Seconds) { |
1872 | spin_lock(&ohci->lock); | |
1873 | update_bus_time(ohci); | |
1874 | spin_unlock(&ohci->lock); | |
e597e989 CL |
1875 | } else |
1876 | flush_writes(ohci); | |
a48777e0 | 1877 | |
ed568912 KH |
1878 | return IRQ_HANDLED; |
1879 | } | |
1880 | ||
2aef469a KH |
1881 | static int software_reset(struct fw_ohci *ohci) |
1882 | { | |
1883 | int i; | |
1884 | ||
1885 | reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset); | |
1886 | ||
1887 | for (i = 0; i < OHCI_LOOP_COUNT; i++) { | |
1888 | if ((reg_read(ohci, OHCI1394_HCControlSet) & | |
1889 | OHCI1394_HCControl_softReset) == 0) | |
1890 | return 0; | |
1891 | msleep(1); | |
1892 | } | |
1893 | ||
1894 | return -EBUSY; | |
1895 | } | |
1896 | ||
8e85973e SR |
1897 | static void copy_config_rom(__be32 *dest, const __be32 *src, size_t length) |
1898 | { | |
1899 | size_t size = length * 4; | |
1900 | ||
1901 | memcpy(dest, src, size); | |
1902 | if (size < CONFIG_ROM_SIZE) | |
1903 | memset(&dest[length], 0, CONFIG_ROM_SIZE - size); | |
1904 | } | |
1905 | ||
925e7a65 CL |
1906 | static int configure_1394a_enhancements(struct fw_ohci *ohci) |
1907 | { | |
1908 | bool enable_1394a; | |
35d999b1 | 1909 | int ret, clear, set, offset; |
925e7a65 CL |
1910 | |
1911 | /* Check if the driver should configure link and PHY. */ | |
1912 | if (!(reg_read(ohci, OHCI1394_HCControlSet) & | |
1913 | OHCI1394_HCControl_programPhyEnable)) | |
1914 | return 0; | |
1915 | ||
1916 | /* Paranoia: check whether the PHY supports 1394a, too. */ | |
1917 | enable_1394a = false; | |
35d999b1 SR |
1918 | ret = read_phy_reg(ohci, 2); |
1919 | if (ret < 0) | |
1920 | return ret; | |
1921 | if ((ret & PHY_EXTENDED_REGISTERS) == PHY_EXTENDED_REGISTERS) { | |
1922 | ret = read_paged_phy_reg(ohci, 1, 8); | |
1923 | if (ret < 0) | |
1924 | return ret; | |
1925 | if (ret >= 1) | |
925e7a65 CL |
1926 | enable_1394a = true; |
1927 | } | |
1928 | ||
1929 | if (ohci->quirks & QUIRK_NO_1394A) | |
1930 | enable_1394a = false; | |
1931 | ||
1932 | /* Configure PHY and link consistently. */ | |
1933 | if (enable_1394a) { | |
1934 | clear = 0; | |
1935 | set = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI; | |
1936 | } else { | |
1937 | clear = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI; | |
1938 | set = 0; | |
1939 | } | |
02d37bed | 1940 | ret = update_phy_reg(ohci, 5, clear, set); |
35d999b1 SR |
1941 | if (ret < 0) |
1942 | return ret; | |
925e7a65 CL |
1943 | |
1944 | if (enable_1394a) | |
1945 | offset = OHCI1394_HCControlSet; | |
1946 | else | |
1947 | offset = OHCI1394_HCControlClear; | |
1948 | reg_write(ohci, offset, OHCI1394_HCControl_aPhyEnhanceEnable); | |
1949 | ||
1950 | /* Clean up: configuration has been taken care of. */ | |
1951 | reg_write(ohci, OHCI1394_HCControlClear, | |
1952 | OHCI1394_HCControl_programPhyEnable); | |
1953 | ||
1954 | return 0; | |
1955 | } | |
1956 | ||
8e85973e SR |
1957 | static int ohci_enable(struct fw_card *card, |
1958 | const __be32 *config_rom, size_t length) | |
ed568912 KH |
1959 | { |
1960 | struct fw_ohci *ohci = fw_ohci(card); | |
1961 | struct pci_dev *dev = to_pci_dev(card->device); | |
e91b2787 | 1962 | u32 lps, seconds, version, irqs; |
35d999b1 | 1963 | int i, ret; |
ed568912 | 1964 | |
2aef469a KH |
1965 | if (software_reset(ohci)) { |
1966 | fw_error("Failed to reset ohci card.\n"); | |
1967 | return -EBUSY; | |
1968 | } | |
1969 | ||
1970 | /* | |
1971 | * Now enable LPS, which we need in order to start accessing | |
1972 | * most of the registers. In fact, on some cards (ALI M5251), | |
1973 | * accessing registers in the SClk domain without LPS enabled | |
1974 | * will lock up the machine. Wait 50msec to make sure we have | |
02214724 JW |
1975 | * full link enabled. However, with some cards (well, at least |
1976 | * a JMicron PCIe card), we have to try again sometimes. | |
2aef469a KH |
1977 | */ |
1978 | reg_write(ohci, OHCI1394_HCControlSet, | |
1979 | OHCI1394_HCControl_LPS | | |
1980 | OHCI1394_HCControl_postedWriteEnable); | |
1981 | flush_writes(ohci); | |
02214724 JW |
1982 | |
1983 | for (lps = 0, i = 0; !lps && i < 3; i++) { | |
1984 | msleep(50); | |
1985 | lps = reg_read(ohci, OHCI1394_HCControlSet) & | |
1986 | OHCI1394_HCControl_LPS; | |
1987 | } | |
1988 | ||
1989 | if (!lps) { | |
1990 | fw_error("Failed to set Link Power Status\n"); | |
1991 | return -EIO; | |
1992 | } | |
2aef469a KH |
1993 | |
1994 | reg_write(ohci, OHCI1394_HCControlClear, | |
1995 | OHCI1394_HCControl_noByteSwapData); | |
1996 | ||
affc9c24 | 1997 | reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus); |
2aef469a KH |
1998 | reg_write(ohci, OHCI1394_LinkControlSet, |
1999 | OHCI1394_LinkControl_rcvSelfID | | |
bf54e146 | 2000 | OHCI1394_LinkControl_rcvPhyPkt | |
2aef469a KH |
2001 | OHCI1394_LinkControl_cycleTimerEnable | |
2002 | OHCI1394_LinkControl_cycleMaster); | |
2003 | ||
2004 | reg_write(ohci, OHCI1394_ATRetries, | |
2005 | OHCI1394_MAX_AT_REQ_RETRIES | | |
2006 | (OHCI1394_MAX_AT_RESP_RETRIES << 4) | | |
27a2329f CL |
2007 | (OHCI1394_MAX_PHYS_RESP_RETRIES << 8) | |
2008 | (200 << 16)); | |
2aef469a | 2009 | |
a48777e0 CL |
2010 | seconds = lower_32_bits(get_seconds()); |
2011 | reg_write(ohci, OHCI1394_IsochronousCycleTimer, seconds << 25); | |
2012 | ohci->bus_time = seconds & ~0x3f; | |
2013 | ||
e91b2787 CL |
2014 | version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff; |
2015 | if (version >= OHCI_VERSION_1_1) { | |
2016 | reg_write(ohci, OHCI1394_InitialChannelsAvailableHi, | |
2017 | 0xfffffffe); | |
db3c9cc1 | 2018 | card->broadcast_channel_auto_allocated = true; |
e91b2787 CL |
2019 | } |
2020 | ||
a1a1132b CL |
2021 | /* Get implemented bits of the priority arbitration request counter. */ |
2022 | reg_write(ohci, OHCI1394_FairnessControl, 0x3f); | |
2023 | ohci->pri_req_max = reg_read(ohci, OHCI1394_FairnessControl) & 0x3f; | |
2024 | reg_write(ohci, OHCI1394_FairnessControl, 0); | |
db3c9cc1 | 2025 | card->priority_budget_implemented = ohci->pri_req_max != 0; |
2aef469a KH |
2026 | |
2027 | ar_context_run(&ohci->ar_request_ctx); | |
2028 | ar_context_run(&ohci->ar_response_ctx); | |
2029 | ||
2aef469a KH |
2030 | reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000); |
2031 | reg_write(ohci, OHCI1394_IntEventClear, ~0); | |
2032 | reg_write(ohci, OHCI1394_IntMaskClear, ~0); | |
2aef469a | 2033 | |
35d999b1 SR |
2034 | ret = configure_1394a_enhancements(ohci); |
2035 | if (ret < 0) | |
2036 | return ret; | |
925e7a65 | 2037 | |
2aef469a | 2038 | /* Activate link_on bit and contender bit in our self ID packets.*/ |
35d999b1 SR |
2039 | ret = ohci_update_phy_reg(card, 4, 0, PHY_LINK_ACTIVE | PHY_CONTENDER); |
2040 | if (ret < 0) | |
2041 | return ret; | |
2aef469a | 2042 | |
c781c06d KH |
2043 | /* |
2044 | * When the link is not yet enabled, the atomic config rom | |
ed568912 KH |
2045 | * update mechanism described below in ohci_set_config_rom() |
2046 | * is not active. We have to update ConfigRomHeader and | |
2047 | * BusOptions manually, and the write to ConfigROMmap takes | |
2048 | * effect immediately. We tie this to the enabling of the | |
2049 | * link, so we have a valid config rom before enabling - the | |
2050 | * OHCI requires that ConfigROMhdr and BusOptions have valid | |
2051 | * values before enabling. | |
2052 | * | |
2053 | * However, when the ConfigROMmap is written, some controllers | |
2054 | * always read back quadlets 0 and 2 from the config rom to | |
2055 | * the ConfigRomHeader and BusOptions registers on bus reset. | |
2056 | * They shouldn't do that in this initial case where the link | |
2057 | * isn't enabled. This means we have to use the same | |
2058 | * workaround here, setting the bus header to 0 and then write | |
2059 | * the right values in the bus reset tasklet. | |
2060 | */ | |
2061 | ||
0bd243c4 KH |
2062 | if (config_rom) { |
2063 | ohci->next_config_rom = | |
2064 | dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE, | |
2065 | &ohci->next_config_rom_bus, | |
2066 | GFP_KERNEL); | |
2067 | if (ohci->next_config_rom == NULL) | |
2068 | return -ENOMEM; | |
ed568912 | 2069 | |
8e85973e | 2070 | copy_config_rom(ohci->next_config_rom, config_rom, length); |
0bd243c4 KH |
2071 | } else { |
2072 | /* | |
2073 | * In the suspend case, config_rom is NULL, which | |
2074 | * means that we just reuse the old config rom. | |
2075 | */ | |
2076 | ohci->next_config_rom = ohci->config_rom; | |
2077 | ohci->next_config_rom_bus = ohci->config_rom_bus; | |
2078 | } | |
ed568912 | 2079 | |
8e85973e | 2080 | ohci->next_header = ohci->next_config_rom[0]; |
ed568912 KH |
2081 | ohci->next_config_rom[0] = 0; |
2082 | reg_write(ohci, OHCI1394_ConfigROMhdr, 0); | |
0bd243c4 KH |
2083 | reg_write(ohci, OHCI1394_BusOptions, |
2084 | be32_to_cpu(ohci->next_config_rom[2])); | |
ed568912 KH |
2085 | reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus); |
2086 | ||
2087 | reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000); | |
2088 | ||
262444ee CL |
2089 | if (!(ohci->quirks & QUIRK_NO_MSI)) |
2090 | pci_enable_msi(dev); | |
ed568912 | 2091 | if (request_irq(dev->irq, irq_handler, |
262444ee CL |
2092 | pci_dev_msi_enabled(dev) ? 0 : IRQF_SHARED, |
2093 | ohci_driver_name, ohci)) { | |
2094 | fw_error("Failed to allocate interrupt %d.\n", dev->irq); | |
2095 | pci_disable_msi(dev); | |
ed568912 KH |
2096 | dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, |
2097 | ohci->config_rom, ohci->config_rom_bus); | |
2098 | return -EIO; | |
2099 | } | |
2100 | ||
148c7866 SR |
2101 | irqs = OHCI1394_reqTxComplete | OHCI1394_respTxComplete | |
2102 | OHCI1394_RQPkt | OHCI1394_RSPkt | | |
2103 | OHCI1394_isochTx | OHCI1394_isochRx | | |
2104 | OHCI1394_postedWriteErr | | |
2105 | OHCI1394_selfIDComplete | | |
2106 | OHCI1394_regAccessFail | | |
a48777e0 | 2107 | OHCI1394_cycle64Seconds | |
148c7866 SR |
2108 | OHCI1394_cycleInconsistent | OHCI1394_cycleTooLong | |
2109 | OHCI1394_masterIntEnable; | |
2110 | if (param_debug & OHCI_PARAM_DEBUG_BUSRESETS) | |
2111 | irqs |= OHCI1394_busReset; | |
2112 | reg_write(ohci, OHCI1394_IntMaskSet, irqs); | |
2113 | ||
ed568912 KH |
2114 | reg_write(ohci, OHCI1394_HCControlSet, |
2115 | OHCI1394_HCControl_linkEnable | | |
2116 | OHCI1394_HCControl_BIBimageValid); | |
2117 | flush_writes(ohci); | |
2118 | ||
02d37bed SR |
2119 | /* We are ready to go, reset bus to finish initialization. */ |
2120 | fw_schedule_bus_reset(&ohci->card, false, true); | |
ed568912 KH |
2121 | |
2122 | return 0; | |
2123 | } | |
2124 | ||
53dca511 | 2125 | static int ohci_set_config_rom(struct fw_card *card, |
8e85973e | 2126 | const __be32 *config_rom, size_t length) |
ed568912 KH |
2127 | { |
2128 | struct fw_ohci *ohci; | |
2129 | unsigned long flags; | |
2dbd7d7e | 2130 | int ret = -EBUSY; |
ed568912 | 2131 | __be32 *next_config_rom; |
f5101d58 | 2132 | dma_addr_t uninitialized_var(next_config_rom_bus); |
ed568912 KH |
2133 | |
2134 | ohci = fw_ohci(card); | |
2135 | ||
c781c06d KH |
2136 | /* |
2137 | * When the OHCI controller is enabled, the config rom update | |
ed568912 KH |
2138 | * mechanism is a bit tricky, but easy enough to use. See |
2139 | * section 5.5.6 in the OHCI specification. | |
2140 | * | |
2141 | * The OHCI controller caches the new config rom address in a | |
2142 | * shadow register (ConfigROMmapNext) and needs a bus reset | |
2143 | * for the changes to take place. When the bus reset is | |
2144 | * detected, the controller loads the new values for the | |
2145 | * ConfigRomHeader and BusOptions registers from the specified | |
2146 | * config rom and loads ConfigROMmap from the ConfigROMmapNext | |
2147 | * shadow register. All automatically and atomically. | |
2148 | * | |
2149 | * Now, there's a twist to this story. The automatic load of | |
2150 | * ConfigRomHeader and BusOptions doesn't honor the | |
2151 | * noByteSwapData bit, so with a be32 config rom, the | |
2152 | * controller will load be32 values in to these registers | |
2153 | * during the atomic update, even on litte endian | |
2154 | * architectures. The workaround we use is to put a 0 in the | |
2155 | * header quadlet; 0 is endian agnostic and means that the | |
2156 | * config rom isn't ready yet. In the bus reset tasklet we | |
2157 | * then set up the real values for the two registers. | |
2158 | * | |
2159 | * We use ohci->lock to avoid racing with the code that sets | |
2160 | * ohci->next_config_rom to NULL (see bus_reset_tasklet). | |
2161 | */ | |
2162 | ||
2163 | next_config_rom = | |
2164 | dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE, | |
2165 | &next_config_rom_bus, GFP_KERNEL); | |
2166 | if (next_config_rom == NULL) | |
2167 | return -ENOMEM; | |
2168 | ||
2169 | spin_lock_irqsave(&ohci->lock, flags); | |
2170 | ||
2171 | if (ohci->next_config_rom == NULL) { | |
2172 | ohci->next_config_rom = next_config_rom; | |
2173 | ohci->next_config_rom_bus = next_config_rom_bus; | |
2174 | ||
8e85973e | 2175 | copy_config_rom(ohci->next_config_rom, config_rom, length); |
ed568912 KH |
2176 | |
2177 | ohci->next_header = config_rom[0]; | |
2178 | ohci->next_config_rom[0] = 0; | |
2179 | ||
2180 | reg_write(ohci, OHCI1394_ConfigROMmap, | |
2181 | ohci->next_config_rom_bus); | |
2dbd7d7e | 2182 | ret = 0; |
ed568912 KH |
2183 | } |
2184 | ||
2185 | spin_unlock_irqrestore(&ohci->lock, flags); | |
2186 | ||
c781c06d KH |
2187 | /* |
2188 | * Now initiate a bus reset to have the changes take | |
ed568912 KH |
2189 | * effect. We clean up the old config rom memory and DMA |
2190 | * mappings in the bus reset tasklet, since the OHCI | |
2191 | * controller could need to access it before the bus reset | |
c781c06d KH |
2192 | * takes effect. |
2193 | */ | |
2dbd7d7e | 2194 | if (ret == 0) |
02d37bed | 2195 | fw_schedule_bus_reset(&ohci->card, true, true); |
4eaff7d6 SR |
2196 | else |
2197 | dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, | |
2198 | next_config_rom, next_config_rom_bus); | |
ed568912 | 2199 | |
2dbd7d7e | 2200 | return ret; |
ed568912 KH |
2201 | } |
2202 | ||
2203 | static void ohci_send_request(struct fw_card *card, struct fw_packet *packet) | |
2204 | { | |
2205 | struct fw_ohci *ohci = fw_ohci(card); | |
2206 | ||
2207 | at_context_transmit(&ohci->at_request_ctx, packet); | |
2208 | } | |
2209 | ||
2210 | static void ohci_send_response(struct fw_card *card, struct fw_packet *packet) | |
2211 | { | |
2212 | struct fw_ohci *ohci = fw_ohci(card); | |
2213 | ||
2214 | at_context_transmit(&ohci->at_response_ctx, packet); | |
2215 | } | |
2216 | ||
730c32f5 KH |
2217 | static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet) |
2218 | { | |
2219 | struct fw_ohci *ohci = fw_ohci(card); | |
f319b6a0 KH |
2220 | struct context *ctx = &ohci->at_request_ctx; |
2221 | struct driver_data *driver_data = packet->driver_data; | |
2dbd7d7e | 2222 | int ret = -ENOENT; |
730c32f5 | 2223 | |
f319b6a0 | 2224 | tasklet_disable(&ctx->tasklet); |
730c32f5 | 2225 | |
f319b6a0 KH |
2226 | if (packet->ack != 0) |
2227 | goto out; | |
730c32f5 | 2228 | |
19593ffd | 2229 | if (packet->payload_mapped) |
1d1dc5e8 SR |
2230 | dma_unmap_single(ohci->card.device, packet->payload_bus, |
2231 | packet->payload_length, DMA_TO_DEVICE); | |
2232 | ||
ad3c0fe8 | 2233 | log_ar_at_event('T', packet->speed, packet->header, 0x20); |
f319b6a0 KH |
2234 | driver_data->packet = NULL; |
2235 | packet->ack = RCODE_CANCELLED; | |
2236 | packet->callback(packet, &ohci->card, packet->ack); | |
2dbd7d7e | 2237 | ret = 0; |
f319b6a0 KH |
2238 | out: |
2239 | tasklet_enable(&ctx->tasklet); | |
730c32f5 | 2240 | |
2dbd7d7e | 2241 | return ret; |
730c32f5 KH |
2242 | } |
2243 | ||
53dca511 SR |
2244 | static int ohci_enable_phys_dma(struct fw_card *card, |
2245 | int node_id, int generation) | |
ed568912 | 2246 | { |
080de8c2 SR |
2247 | #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA |
2248 | return 0; | |
2249 | #else | |
ed568912 KH |
2250 | struct fw_ohci *ohci = fw_ohci(card); |
2251 | unsigned long flags; | |
2dbd7d7e | 2252 | int n, ret = 0; |
ed568912 | 2253 | |
c781c06d KH |
2254 | /* |
2255 | * FIXME: Make sure this bitmask is cleared when we clear the busReset | |
2256 | * interrupt bit. Clear physReqResourceAllBuses on bus reset. | |
2257 | */ | |
ed568912 KH |
2258 | |
2259 | spin_lock_irqsave(&ohci->lock, flags); | |
2260 | ||
2261 | if (ohci->generation != generation) { | |
2dbd7d7e | 2262 | ret = -ESTALE; |
ed568912 KH |
2263 | goto out; |
2264 | } | |
2265 | ||
c781c06d KH |
2266 | /* |
2267 | * Note, if the node ID contains a non-local bus ID, physical DMA is | |
2268 | * enabled for _all_ nodes on remote buses. | |
2269 | */ | |
907293d7 SR |
2270 | |
2271 | n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63; | |
2272 | if (n < 32) | |
2273 | reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n); | |
2274 | else | |
2275 | reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32)); | |
2276 | ||
ed568912 | 2277 | flush_writes(ohci); |
ed568912 | 2278 | out: |
6cad95fe | 2279 | spin_unlock_irqrestore(&ohci->lock, flags); |
2dbd7d7e SR |
2280 | |
2281 | return ret; | |
080de8c2 | 2282 | #endif /* CONFIG_FIREWIRE_OHCI_REMOTE_DMA */ |
ed568912 | 2283 | } |
373b2edd | 2284 | |
0fcff4e3 | 2285 | static u32 ohci_read_csr(struct fw_card *card, int csr_offset) |
b677532b | 2286 | { |
60d32970 | 2287 | struct fw_ohci *ohci = fw_ohci(card); |
a48777e0 CL |
2288 | unsigned long flags; |
2289 | u32 value; | |
60d32970 CL |
2290 | |
2291 | switch (csr_offset) { | |
4ffb7a6a CL |
2292 | case CSR_STATE_CLEAR: |
2293 | case CSR_STATE_SET: | |
4ffb7a6a CL |
2294 | if (ohci->is_root && |
2295 | (reg_read(ohci, OHCI1394_LinkControlSet) & | |
2296 | OHCI1394_LinkControl_cycleMaster)) | |
c8a94ded | 2297 | value = CSR_STATE_BIT_CMSTR; |
4ffb7a6a | 2298 | else |
c8a94ded SR |
2299 | value = 0; |
2300 | if (ohci->csr_state_setclear_abdicate) | |
2301 | value |= CSR_STATE_BIT_ABDICATE; | |
b677532b | 2302 | |
c8a94ded | 2303 | return value; |
4a9bde9b | 2304 | |
506f1a31 CL |
2305 | case CSR_NODE_IDS: |
2306 | return reg_read(ohci, OHCI1394_NodeID) << 16; | |
2307 | ||
60d32970 CL |
2308 | case CSR_CYCLE_TIME: |
2309 | return get_cycle_time(ohci); | |
2310 | ||
a48777e0 CL |
2311 | case CSR_BUS_TIME: |
2312 | /* | |
2313 | * We might be called just after the cycle timer has wrapped | |
2314 | * around but just before the cycle64Seconds handler, so we | |
2315 | * better check here, too, if the bus time needs to be updated. | |
2316 | */ | |
2317 | spin_lock_irqsave(&ohci->lock, flags); | |
2318 | value = update_bus_time(ohci); | |
2319 | spin_unlock_irqrestore(&ohci->lock, flags); | |
2320 | return value; | |
2321 | ||
27a2329f CL |
2322 | case CSR_BUSY_TIMEOUT: |
2323 | value = reg_read(ohci, OHCI1394_ATRetries); | |
2324 | return (value >> 4) & 0x0ffff00f; | |
2325 | ||
a1a1132b CL |
2326 | case CSR_PRIORITY_BUDGET: |
2327 | return (reg_read(ohci, OHCI1394_FairnessControl) & 0x3f) | | |
2328 | (ohci->pri_req_max << 8); | |
2329 | ||
60d32970 CL |
2330 | default: |
2331 | WARN_ON(1); | |
2332 | return 0; | |
2333 | } | |
b677532b CL |
2334 | } |
2335 | ||
0fcff4e3 | 2336 | static void ohci_write_csr(struct fw_card *card, int csr_offset, u32 value) |
d60d7f1d KH |
2337 | { |
2338 | struct fw_ohci *ohci = fw_ohci(card); | |
a48777e0 | 2339 | unsigned long flags; |
d60d7f1d | 2340 | |
506f1a31 | 2341 | switch (csr_offset) { |
4ffb7a6a | 2342 | case CSR_STATE_CLEAR: |
4ffb7a6a CL |
2343 | if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) { |
2344 | reg_write(ohci, OHCI1394_LinkControlClear, | |
2345 | OHCI1394_LinkControl_cycleMaster); | |
2346 | flush_writes(ohci); | |
2347 | } | |
c8a94ded SR |
2348 | if (value & CSR_STATE_BIT_ABDICATE) |
2349 | ohci->csr_state_setclear_abdicate = false; | |
4ffb7a6a | 2350 | break; |
4a9bde9b | 2351 | |
4ffb7a6a CL |
2352 | case CSR_STATE_SET: |
2353 | if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) { | |
2354 | reg_write(ohci, OHCI1394_LinkControlSet, | |
2355 | OHCI1394_LinkControl_cycleMaster); | |
2356 | flush_writes(ohci); | |
2357 | } | |
c8a94ded SR |
2358 | if (value & CSR_STATE_BIT_ABDICATE) |
2359 | ohci->csr_state_setclear_abdicate = true; | |
4ffb7a6a | 2360 | break; |
d60d7f1d | 2361 | |
506f1a31 CL |
2362 | case CSR_NODE_IDS: |
2363 | reg_write(ohci, OHCI1394_NodeID, value >> 16); | |
2364 | flush_writes(ohci); | |
2365 | break; | |
2366 | ||
9ab5071c CL |
2367 | case CSR_CYCLE_TIME: |
2368 | reg_write(ohci, OHCI1394_IsochronousCycleTimer, value); | |
2369 | reg_write(ohci, OHCI1394_IntEventSet, | |
2370 | OHCI1394_cycleInconsistent); | |
2371 | flush_writes(ohci); | |
2372 | break; | |
2373 | ||
a48777e0 CL |
2374 | case CSR_BUS_TIME: |
2375 | spin_lock_irqsave(&ohci->lock, flags); | |
2376 | ohci->bus_time = (ohci->bus_time & 0x7f) | (value & ~0x7f); | |
2377 | spin_unlock_irqrestore(&ohci->lock, flags); | |
2378 | break; | |
2379 | ||
27a2329f CL |
2380 | case CSR_BUSY_TIMEOUT: |
2381 | value = (value & 0xf) | ((value & 0xf) << 4) | | |
2382 | ((value & 0xf) << 8) | ((value & 0x0ffff000) << 4); | |
2383 | reg_write(ohci, OHCI1394_ATRetries, value); | |
2384 | flush_writes(ohci); | |
2385 | break; | |
2386 | ||
a1a1132b CL |
2387 | case CSR_PRIORITY_BUDGET: |
2388 | reg_write(ohci, OHCI1394_FairnessControl, value & 0x3f); | |
2389 | flush_writes(ohci); | |
2390 | break; | |
2391 | ||
506f1a31 CL |
2392 | default: |
2393 | WARN_ON(1); | |
2394 | break; | |
2395 | } | |
d60d7f1d KH |
2396 | } |
2397 | ||
1aa292bb DM |
2398 | static void copy_iso_headers(struct iso_context *ctx, void *p) |
2399 | { | |
2400 | int i = ctx->header_length; | |
2401 | ||
2402 | if (i + ctx->base.header_size > PAGE_SIZE) | |
2403 | return; | |
2404 | ||
2405 | /* | |
2406 | * The iso header is byteswapped to little endian by | |
2407 | * the controller, but the remaining header quadlets | |
2408 | * are big endian. We want to present all the headers | |
2409 | * as big endian, so we have to swap the first quadlet. | |
2410 | */ | |
2411 | if (ctx->base.header_size > 0) | |
2412 | *(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4)); | |
2413 | if (ctx->base.header_size > 4) | |
2414 | *(u32 *) (ctx->header + i + 4) = __swab32(*(u32 *) p); | |
2415 | if (ctx->base.header_size > 8) | |
2416 | memcpy(ctx->header + i + 8, p + 8, ctx->base.header_size - 8); | |
2417 | ctx->header_length += ctx->base.header_size; | |
2418 | } | |
2419 | ||
a186b4a6 JW |
2420 | static int handle_ir_packet_per_buffer(struct context *context, |
2421 | struct descriptor *d, | |
2422 | struct descriptor *last) | |
2423 | { | |
2424 | struct iso_context *ctx = | |
2425 | container_of(context, struct iso_context, context); | |
bcee893c | 2426 | struct descriptor *pd; |
a186b4a6 | 2427 | __le32 *ir_header; |
bcee893c | 2428 | void *p; |
a186b4a6 | 2429 | |
872e330e | 2430 | for (pd = d; pd <= last; pd++) |
bcee893c DM |
2431 | if (pd->transfer_status) |
2432 | break; | |
bcee893c | 2433 | if (pd > last) |
a186b4a6 JW |
2434 | /* Descriptor(s) not done yet, stop iteration */ |
2435 | return 0; | |
2436 | ||
1aa292bb DM |
2437 | p = last + 1; |
2438 | copy_iso_headers(ctx, p); | |
a186b4a6 | 2439 | |
bcee893c DM |
2440 | if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) { |
2441 | ir_header = (__le32 *) p; | |
872e330e SR |
2442 | ctx->base.callback.sc(&ctx->base, |
2443 | le32_to_cpu(ir_header[0]) & 0xffff, | |
2444 | ctx->header_length, ctx->header, | |
2445 | ctx->base.callback_data); | |
a186b4a6 JW |
2446 | ctx->header_length = 0; |
2447 | } | |
2448 | ||
a186b4a6 JW |
2449 | return 1; |
2450 | } | |
2451 | ||
872e330e SR |
2452 | /* d == last because each descriptor block is only a single descriptor. */ |
2453 | static int handle_ir_buffer_fill(struct context *context, | |
2454 | struct descriptor *d, | |
2455 | struct descriptor *last) | |
2456 | { | |
2457 | struct iso_context *ctx = | |
2458 | container_of(context, struct iso_context, context); | |
2459 | ||
2460 | if (!last->transfer_status) | |
2461 | /* Descriptor(s) not done yet, stop iteration */ | |
2462 | return 0; | |
2463 | ||
2464 | if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) | |
2465 | ctx->base.callback.mc(&ctx->base, | |
2466 | le32_to_cpu(last->data_address) + | |
2467 | le16_to_cpu(last->req_count) - | |
2468 | le16_to_cpu(last->res_count), | |
2469 | ctx->base.callback_data); | |
2470 | ||
2471 | return 1; | |
2472 | } | |
2473 | ||
30200739 KH |
2474 | static int handle_it_packet(struct context *context, |
2475 | struct descriptor *d, | |
2476 | struct descriptor *last) | |
ed568912 | 2477 | { |
30200739 KH |
2478 | struct iso_context *ctx = |
2479 | container_of(context, struct iso_context, context); | |
31769cef JF |
2480 | int i; |
2481 | struct descriptor *pd; | |
373b2edd | 2482 | |
31769cef JF |
2483 | for (pd = d; pd <= last; pd++) |
2484 | if (pd->transfer_status) | |
2485 | break; | |
2486 | if (pd > last) | |
2487 | /* Descriptor(s) not done yet, stop iteration */ | |
30200739 KH |
2488 | return 0; |
2489 | ||
31769cef JF |
2490 | i = ctx->header_length; |
2491 | if (i + 4 < PAGE_SIZE) { | |
2492 | /* Present this value as big-endian to match the receive code */ | |
2493 | *(__be32 *)(ctx->header + i) = cpu_to_be32( | |
2494 | ((u32)le16_to_cpu(pd->transfer_status) << 16) | | |
2495 | le16_to_cpu(pd->res_count)); | |
2496 | ctx->header_length += 4; | |
2497 | } | |
2498 | if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) { | |
872e330e SR |
2499 | ctx->base.callback.sc(&ctx->base, le16_to_cpu(last->res_count), |
2500 | ctx->header_length, ctx->header, | |
2501 | ctx->base.callback_data); | |
31769cef JF |
2502 | ctx->header_length = 0; |
2503 | } | |
30200739 | 2504 | return 1; |
ed568912 KH |
2505 | } |
2506 | ||
872e330e SR |
2507 | static void set_multichannel_mask(struct fw_ohci *ohci, u64 channels) |
2508 | { | |
2509 | u32 hi = channels >> 32, lo = channels; | |
2510 | ||
2511 | reg_write(ohci, OHCI1394_IRMultiChanMaskHiClear, ~hi); | |
2512 | reg_write(ohci, OHCI1394_IRMultiChanMaskLoClear, ~lo); | |
2513 | reg_write(ohci, OHCI1394_IRMultiChanMaskHiSet, hi); | |
2514 | reg_write(ohci, OHCI1394_IRMultiChanMaskLoSet, lo); | |
2515 | mmiowb(); | |
2516 | ohci->mc_channels = channels; | |
2517 | } | |
2518 | ||
53dca511 | 2519 | static struct fw_iso_context *ohci_allocate_iso_context(struct fw_card *card, |
4817ed24 | 2520 | int type, int channel, size_t header_size) |
ed568912 KH |
2521 | { |
2522 | struct fw_ohci *ohci = fw_ohci(card); | |
872e330e SR |
2523 | struct iso_context *uninitialized_var(ctx); |
2524 | descriptor_callback_t uninitialized_var(callback); | |
2525 | u64 *uninitialized_var(channels); | |
2526 | u32 *uninitialized_var(mask), uninitialized_var(regs); | |
ed568912 | 2527 | unsigned long flags; |
872e330e | 2528 | int index, ret = -EBUSY; |
ed568912 | 2529 | |
872e330e | 2530 | spin_lock_irqsave(&ohci->lock, flags); |
ed568912 | 2531 | |
872e330e SR |
2532 | switch (type) { |
2533 | case FW_ISO_CONTEXT_TRANSMIT: | |
2534 | mask = &ohci->it_context_mask; | |
30200739 | 2535 | callback = handle_it_packet; |
872e330e SR |
2536 | index = ffs(*mask) - 1; |
2537 | if (index >= 0) { | |
2538 | *mask &= ~(1 << index); | |
2539 | regs = OHCI1394_IsoXmitContextBase(index); | |
2540 | ctx = &ohci->it_context_list[index]; | |
2541 | } | |
2542 | break; | |
2543 | ||
2544 | case FW_ISO_CONTEXT_RECEIVE: | |
4817ed24 | 2545 | channels = &ohci->ir_context_channels; |
872e330e | 2546 | mask = &ohci->ir_context_mask; |
6498ba04 | 2547 | callback = handle_ir_packet_per_buffer; |
872e330e SR |
2548 | index = *channels & 1ULL << channel ? ffs(*mask) - 1 : -1; |
2549 | if (index >= 0) { | |
2550 | *channels &= ~(1ULL << channel); | |
2551 | *mask &= ~(1 << index); | |
2552 | regs = OHCI1394_IsoRcvContextBase(index); | |
2553 | ctx = &ohci->ir_context_list[index]; | |
2554 | } | |
2555 | break; | |
ed568912 | 2556 | |
872e330e SR |
2557 | case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: |
2558 | mask = &ohci->ir_context_mask; | |
2559 | callback = handle_ir_buffer_fill; | |
2560 | index = !ohci->mc_allocated ? ffs(*mask) - 1 : -1; | |
2561 | if (index >= 0) { | |
2562 | ohci->mc_allocated = true; | |
2563 | *mask &= ~(1 << index); | |
2564 | regs = OHCI1394_IsoRcvContextBase(index); | |
2565 | ctx = &ohci->ir_context_list[index]; | |
2566 | } | |
2567 | break; | |
2568 | ||
2569 | default: | |
2570 | index = -1; | |
2571 | ret = -ENOSYS; | |
4817ed24 | 2572 | } |
872e330e | 2573 | |
ed568912 KH |
2574 | spin_unlock_irqrestore(&ohci->lock, flags); |
2575 | ||
2576 | if (index < 0) | |
872e330e | 2577 | return ERR_PTR(ret); |
373b2edd | 2578 | |
2d826cc5 | 2579 | memset(ctx, 0, sizeof(*ctx)); |
9b32d5f3 KH |
2580 | ctx->header_length = 0; |
2581 | ctx->header = (void *) __get_free_page(GFP_KERNEL); | |
872e330e SR |
2582 | if (ctx->header == NULL) { |
2583 | ret = -ENOMEM; | |
9b32d5f3 | 2584 | goto out; |
872e330e | 2585 | } |
2dbd7d7e SR |
2586 | ret = context_init(&ctx->context, ohci, regs, callback); |
2587 | if (ret < 0) | |
9b32d5f3 | 2588 | goto out_with_header; |
ed568912 | 2589 | |
872e330e SR |
2590 | if (type == FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL) |
2591 | set_multichannel_mask(ohci, 0); | |
2592 | ||
ed568912 | 2593 | return &ctx->base; |
9b32d5f3 KH |
2594 | |
2595 | out_with_header: | |
2596 | free_page((unsigned long)ctx->header); | |
2597 | out: | |
2598 | spin_lock_irqsave(&ohci->lock, flags); | |
872e330e SR |
2599 | |
2600 | switch (type) { | |
2601 | case FW_ISO_CONTEXT_RECEIVE: | |
2602 | *channels |= 1ULL << channel; | |
2603 | break; | |
2604 | ||
2605 | case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: | |
2606 | ohci->mc_allocated = false; | |
2607 | break; | |
2608 | } | |
9b32d5f3 | 2609 | *mask |= 1 << index; |
872e330e | 2610 | |
9b32d5f3 KH |
2611 | spin_unlock_irqrestore(&ohci->lock, flags); |
2612 | ||
2dbd7d7e | 2613 | return ERR_PTR(ret); |
ed568912 KH |
2614 | } |
2615 | ||
eb0306ea KH |
2616 | static int ohci_start_iso(struct fw_iso_context *base, |
2617 | s32 cycle, u32 sync, u32 tags) | |
ed568912 | 2618 | { |
373b2edd | 2619 | struct iso_context *ctx = container_of(base, struct iso_context, base); |
30200739 | 2620 | struct fw_ohci *ohci = ctx->context.ohci; |
872e330e | 2621 | u32 control = IR_CONTEXT_ISOCH_HEADER, match; |
ed568912 KH |
2622 | int index; |
2623 | ||
872e330e SR |
2624 | switch (ctx->base.type) { |
2625 | case FW_ISO_CONTEXT_TRANSMIT: | |
295e3feb | 2626 | index = ctx - ohci->it_context_list; |
8a2f7d93 KH |
2627 | match = 0; |
2628 | if (cycle >= 0) | |
2629 | match = IT_CONTEXT_CYCLE_MATCH_ENABLE | | |
295e3feb | 2630 | (cycle & 0x7fff) << 16; |
21efb3cf | 2631 | |
295e3feb KH |
2632 | reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index); |
2633 | reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index); | |
8a2f7d93 | 2634 | context_run(&ctx->context, match); |
872e330e SR |
2635 | break; |
2636 | ||
2637 | case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: | |
2638 | control |= IR_CONTEXT_BUFFER_FILL|IR_CONTEXT_MULTI_CHANNEL_MODE; | |
2639 | /* fall through */ | |
2640 | case FW_ISO_CONTEXT_RECEIVE: | |
295e3feb | 2641 | index = ctx - ohci->ir_context_list; |
8a2f7d93 KH |
2642 | match = (tags << 28) | (sync << 8) | ctx->base.channel; |
2643 | if (cycle >= 0) { | |
2644 | match |= (cycle & 0x07fff) << 12; | |
2645 | control |= IR_CONTEXT_CYCLE_MATCH_ENABLE; | |
2646 | } | |
ed568912 | 2647 | |
295e3feb KH |
2648 | reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index); |
2649 | reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index); | |
a77754a7 | 2650 | reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match); |
8a2f7d93 | 2651 | context_run(&ctx->context, control); |
dd23736e ML |
2652 | |
2653 | ctx->sync = sync; | |
2654 | ctx->tags = tags; | |
2655 | ||
872e330e | 2656 | break; |
295e3feb | 2657 | } |
ed568912 KH |
2658 | |
2659 | return 0; | |
2660 | } | |
2661 | ||
b8295668 KH |
2662 | static int ohci_stop_iso(struct fw_iso_context *base) |
2663 | { | |
2664 | struct fw_ohci *ohci = fw_ohci(base->card); | |
373b2edd | 2665 | struct iso_context *ctx = container_of(base, struct iso_context, base); |
b8295668 KH |
2666 | int index; |
2667 | ||
872e330e SR |
2668 | switch (ctx->base.type) { |
2669 | case FW_ISO_CONTEXT_TRANSMIT: | |
b8295668 KH |
2670 | index = ctx - ohci->it_context_list; |
2671 | reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index); | |
872e330e SR |
2672 | break; |
2673 | ||
2674 | case FW_ISO_CONTEXT_RECEIVE: | |
2675 | case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: | |
b8295668 KH |
2676 | index = ctx - ohci->ir_context_list; |
2677 | reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index); | |
872e330e | 2678 | break; |
b8295668 KH |
2679 | } |
2680 | flush_writes(ohci); | |
2681 | context_stop(&ctx->context); | |
2682 | ||
2683 | return 0; | |
2684 | } | |
2685 | ||
ed568912 KH |
2686 | static void ohci_free_iso_context(struct fw_iso_context *base) |
2687 | { | |
2688 | struct fw_ohci *ohci = fw_ohci(base->card); | |
373b2edd | 2689 | struct iso_context *ctx = container_of(base, struct iso_context, base); |
ed568912 KH |
2690 | unsigned long flags; |
2691 | int index; | |
2692 | ||
b8295668 KH |
2693 | ohci_stop_iso(base); |
2694 | context_release(&ctx->context); | |
9b32d5f3 | 2695 | free_page((unsigned long)ctx->header); |
b8295668 | 2696 | |
ed568912 KH |
2697 | spin_lock_irqsave(&ohci->lock, flags); |
2698 | ||
872e330e SR |
2699 | switch (base->type) { |
2700 | case FW_ISO_CONTEXT_TRANSMIT: | |
ed568912 | 2701 | index = ctx - ohci->it_context_list; |
ed568912 | 2702 | ohci->it_context_mask |= 1 << index; |
872e330e SR |
2703 | break; |
2704 | ||
2705 | case FW_ISO_CONTEXT_RECEIVE: | |
ed568912 | 2706 | index = ctx - ohci->ir_context_list; |
ed568912 | 2707 | ohci->ir_context_mask |= 1 << index; |
4817ed24 | 2708 | ohci->ir_context_channels |= 1ULL << base->channel; |
872e330e SR |
2709 | break; |
2710 | ||
2711 | case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: | |
2712 | index = ctx - ohci->ir_context_list; | |
2713 | ohci->ir_context_mask |= 1 << index; | |
2714 | ohci->ir_context_channels |= ohci->mc_channels; | |
2715 | ohci->mc_channels = 0; | |
2716 | ohci->mc_allocated = false; | |
2717 | break; | |
ed568912 | 2718 | } |
ed568912 KH |
2719 | |
2720 | spin_unlock_irqrestore(&ohci->lock, flags); | |
2721 | } | |
2722 | ||
872e330e SR |
2723 | static int ohci_set_iso_channels(struct fw_iso_context *base, u64 *channels) |
2724 | { | |
2725 | struct fw_ohci *ohci = fw_ohci(base->card); | |
2726 | unsigned long flags; | |
2727 | int ret; | |
2728 | ||
2729 | switch (base->type) { | |
2730 | case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: | |
2731 | ||
2732 | spin_lock_irqsave(&ohci->lock, flags); | |
2733 | ||
2734 | /* Don't allow multichannel to grab other contexts' channels. */ | |
2735 | if (~ohci->ir_context_channels & ~ohci->mc_channels & *channels) { | |
2736 | *channels = ohci->ir_context_channels; | |
2737 | ret = -EBUSY; | |
2738 | } else { | |
2739 | set_multichannel_mask(ohci, *channels); | |
2740 | ret = 0; | |
2741 | } | |
2742 | ||
2743 | spin_unlock_irqrestore(&ohci->lock, flags); | |
2744 | ||
2745 | break; | |
2746 | default: | |
2747 | ret = -EINVAL; | |
2748 | } | |
2749 | ||
2750 | return ret; | |
2751 | } | |
2752 | ||
dd23736e ML |
2753 | #ifdef CONFIG_PM |
2754 | static void ohci_resume_iso_dma(struct fw_ohci *ohci) | |
2755 | { | |
2756 | int i; | |
2757 | struct iso_context *ctx; | |
2758 | ||
2759 | for (i = 0 ; i < ohci->n_ir ; i++) { | |
2760 | ctx = &ohci->ir_context_list[i]; | |
2761 | if (ctx->context.active) | |
2762 | ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags); | |
2763 | } | |
2764 | ||
2765 | for (i = 0 ; i < ohci->n_it ; i++) { | |
2766 | ctx = &ohci->it_context_list[i]; | |
2767 | if (ctx->context.active) | |
2768 | ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags); | |
2769 | } | |
2770 | } | |
2771 | #endif | |
2772 | ||
872e330e SR |
2773 | static int queue_iso_transmit(struct iso_context *ctx, |
2774 | struct fw_iso_packet *packet, | |
2775 | struct fw_iso_buffer *buffer, | |
2776 | unsigned long payload) | |
ed568912 | 2777 | { |
30200739 | 2778 | struct descriptor *d, *last, *pd; |
ed568912 KH |
2779 | struct fw_iso_packet *p; |
2780 | __le32 *header; | |
9aad8125 | 2781 | dma_addr_t d_bus, page_bus; |
ed568912 KH |
2782 | u32 z, header_z, payload_z, irq; |
2783 | u32 payload_index, payload_end_index, next_page_index; | |
30200739 | 2784 | int page, end_page, i, length, offset; |
ed568912 | 2785 | |
ed568912 | 2786 | p = packet; |
9aad8125 | 2787 | payload_index = payload; |
ed568912 KH |
2788 | |
2789 | if (p->skip) | |
2790 | z = 1; | |
2791 | else | |
2792 | z = 2; | |
2793 | if (p->header_length > 0) | |
2794 | z++; | |
2795 | ||
2796 | /* Determine the first page the payload isn't contained in. */ | |
2797 | end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT; | |
2798 | if (p->payload_length > 0) | |
2799 | payload_z = end_page - (payload_index >> PAGE_SHIFT); | |
2800 | else | |
2801 | payload_z = 0; | |
2802 | ||
2803 | z += payload_z; | |
2804 | ||
2805 | /* Get header size in number of descriptors. */ | |
2d826cc5 | 2806 | header_z = DIV_ROUND_UP(p->header_length, sizeof(*d)); |
ed568912 | 2807 | |
30200739 KH |
2808 | d = context_get_descriptors(&ctx->context, z + header_z, &d_bus); |
2809 | if (d == NULL) | |
2810 | return -ENOMEM; | |
ed568912 KH |
2811 | |
2812 | if (!p->skip) { | |
a77754a7 | 2813 | d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE); |
ed568912 | 2814 | d[0].req_count = cpu_to_le16(8); |
7f51a100 CL |
2815 | /* |
2816 | * Link the skip address to this descriptor itself. This causes | |
2817 | * a context to skip a cycle whenever lost cycles or FIFO | |
2818 | * overruns occur, without dropping the data. The application | |
2819 | * should then decide whether this is an error condition or not. | |
2820 | * FIXME: Make the context's cycle-lost behaviour configurable? | |
2821 | */ | |
2822 | d[0].branch_address = cpu_to_le32(d_bus | z); | |
ed568912 KH |
2823 | |
2824 | header = (__le32 *) &d[1]; | |
a77754a7 KH |
2825 | header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) | |
2826 | IT_HEADER_TAG(p->tag) | | |
2827 | IT_HEADER_TCODE(TCODE_STREAM_DATA) | | |
2828 | IT_HEADER_CHANNEL(ctx->base.channel) | | |
2829 | IT_HEADER_SPEED(ctx->base.speed)); | |
ed568912 | 2830 | header[1] = |
a77754a7 | 2831 | cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length + |
ed568912 KH |
2832 | p->payload_length)); |
2833 | } | |
2834 | ||
2835 | if (p->header_length > 0) { | |
2836 | d[2].req_count = cpu_to_le16(p->header_length); | |
2d826cc5 | 2837 | d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d)); |
ed568912 KH |
2838 | memcpy(&d[z], p->header, p->header_length); |
2839 | } | |
2840 | ||
2841 | pd = d + z - payload_z; | |
2842 | payload_end_index = payload_index + p->payload_length; | |
2843 | for (i = 0; i < payload_z; i++) { | |
2844 | page = payload_index >> PAGE_SHIFT; | |
2845 | offset = payload_index & ~PAGE_MASK; | |
2846 | next_page_index = (page + 1) << PAGE_SHIFT; | |
2847 | length = | |
2848 | min(next_page_index, payload_end_index) - payload_index; | |
2849 | pd[i].req_count = cpu_to_le16(length); | |
9aad8125 KH |
2850 | |
2851 | page_bus = page_private(buffer->pages[page]); | |
2852 | pd[i].data_address = cpu_to_le32(page_bus + offset); | |
ed568912 KH |
2853 | |
2854 | payload_index += length; | |
2855 | } | |
2856 | ||
ed568912 | 2857 | if (p->interrupt) |
a77754a7 | 2858 | irq = DESCRIPTOR_IRQ_ALWAYS; |
ed568912 | 2859 | else |
a77754a7 | 2860 | irq = DESCRIPTOR_NO_IRQ; |
ed568912 | 2861 | |
30200739 | 2862 | last = z == 2 ? d : d + z - 1; |
a77754a7 KH |
2863 | last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST | |
2864 | DESCRIPTOR_STATUS | | |
2865 | DESCRIPTOR_BRANCH_ALWAYS | | |
cbb59da7 | 2866 | irq); |
ed568912 | 2867 | |
30200739 | 2868 | context_append(&ctx->context, d, z, header_z); |
ed568912 KH |
2869 | |
2870 | return 0; | |
2871 | } | |
373b2edd | 2872 | |
872e330e SR |
2873 | static int queue_iso_packet_per_buffer(struct iso_context *ctx, |
2874 | struct fw_iso_packet *packet, | |
2875 | struct fw_iso_buffer *buffer, | |
2876 | unsigned long payload) | |
a186b4a6 | 2877 | { |
8c0c0cc2 | 2878 | struct descriptor *d, *pd; |
a186b4a6 JW |
2879 | dma_addr_t d_bus, page_bus; |
2880 | u32 z, header_z, rest; | |
bcee893c DM |
2881 | int i, j, length; |
2882 | int page, offset, packet_count, header_size, payload_per_buffer; | |
a186b4a6 JW |
2883 | |
2884 | /* | |
1aa292bb DM |
2885 | * The OHCI controller puts the isochronous header and trailer in the |
2886 | * buffer, so we need at least 8 bytes. | |
a186b4a6 | 2887 | */ |
872e330e | 2888 | packet_count = packet->header_length / ctx->base.header_size; |
1aa292bb | 2889 | header_size = max(ctx->base.header_size, (size_t)8); |
a186b4a6 JW |
2890 | |
2891 | /* Get header size in number of descriptors. */ | |
2892 | header_z = DIV_ROUND_UP(header_size, sizeof(*d)); | |
2893 | page = payload >> PAGE_SHIFT; | |
2894 | offset = payload & ~PAGE_MASK; | |
872e330e | 2895 | payload_per_buffer = packet->payload_length / packet_count; |
a186b4a6 JW |
2896 | |
2897 | for (i = 0; i < packet_count; i++) { | |
2898 | /* d points to the header descriptor */ | |
bcee893c | 2899 | z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1; |
a186b4a6 | 2900 | d = context_get_descriptors(&ctx->context, |
bcee893c | 2901 | z + header_z, &d_bus); |
a186b4a6 JW |
2902 | if (d == NULL) |
2903 | return -ENOMEM; | |
2904 | ||
bcee893c DM |
2905 | d->control = cpu_to_le16(DESCRIPTOR_STATUS | |
2906 | DESCRIPTOR_INPUT_MORE); | |
872e330e | 2907 | if (packet->skip && i == 0) |
bcee893c | 2908 | d->control |= cpu_to_le16(DESCRIPTOR_WAIT); |
a186b4a6 JW |
2909 | d->req_count = cpu_to_le16(header_size); |
2910 | d->res_count = d->req_count; | |
bcee893c | 2911 | d->transfer_status = 0; |
a186b4a6 JW |
2912 | d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d))); |
2913 | ||
bcee893c | 2914 | rest = payload_per_buffer; |
8c0c0cc2 | 2915 | pd = d; |
bcee893c | 2916 | for (j = 1; j < z; j++) { |
8c0c0cc2 | 2917 | pd++; |
bcee893c DM |
2918 | pd->control = cpu_to_le16(DESCRIPTOR_STATUS | |
2919 | DESCRIPTOR_INPUT_MORE); | |
2920 | ||
2921 | if (offset + rest < PAGE_SIZE) | |
2922 | length = rest; | |
2923 | else | |
2924 | length = PAGE_SIZE - offset; | |
2925 | pd->req_count = cpu_to_le16(length); | |
2926 | pd->res_count = pd->req_count; | |
2927 | pd->transfer_status = 0; | |
2928 | ||
2929 | page_bus = page_private(buffer->pages[page]); | |
2930 | pd->data_address = cpu_to_le32(page_bus + offset); | |
2931 | ||
2932 | offset = (offset + length) & ~PAGE_MASK; | |
2933 | rest -= length; | |
2934 | if (offset == 0) | |
2935 | page++; | |
2936 | } | |
a186b4a6 JW |
2937 | pd->control = cpu_to_le16(DESCRIPTOR_STATUS | |
2938 | DESCRIPTOR_INPUT_LAST | | |
2939 | DESCRIPTOR_BRANCH_ALWAYS); | |
872e330e | 2940 | if (packet->interrupt && i == packet_count - 1) |
a186b4a6 JW |
2941 | pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS); |
2942 | ||
a186b4a6 JW |
2943 | context_append(&ctx->context, d, z, header_z); |
2944 | } | |
2945 | ||
2946 | return 0; | |
2947 | } | |
2948 | ||
872e330e SR |
2949 | static int queue_iso_buffer_fill(struct iso_context *ctx, |
2950 | struct fw_iso_packet *packet, | |
2951 | struct fw_iso_buffer *buffer, | |
2952 | unsigned long payload) | |
2953 | { | |
2954 | struct descriptor *d; | |
2955 | dma_addr_t d_bus, page_bus; | |
2956 | int page, offset, rest, z, i, length; | |
2957 | ||
2958 | page = payload >> PAGE_SHIFT; | |
2959 | offset = payload & ~PAGE_MASK; | |
2960 | rest = packet->payload_length; | |
2961 | ||
2962 | /* We need one descriptor for each page in the buffer. */ | |
2963 | z = DIV_ROUND_UP(offset + rest, PAGE_SIZE); | |
2964 | ||
2965 | if (WARN_ON(offset & 3 || rest & 3 || page + z > buffer->page_count)) | |
2966 | return -EFAULT; | |
2967 | ||
2968 | for (i = 0; i < z; i++) { | |
2969 | d = context_get_descriptors(&ctx->context, 1, &d_bus); | |
2970 | if (d == NULL) | |
2971 | return -ENOMEM; | |
2972 | ||
2973 | d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE | | |
2974 | DESCRIPTOR_BRANCH_ALWAYS); | |
2975 | if (packet->skip && i == 0) | |
2976 | d->control |= cpu_to_le16(DESCRIPTOR_WAIT); | |
2977 | if (packet->interrupt && i == z - 1) | |
2978 | d->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS); | |
2979 | ||
2980 | if (offset + rest < PAGE_SIZE) | |
2981 | length = rest; | |
2982 | else | |
2983 | length = PAGE_SIZE - offset; | |
2984 | d->req_count = cpu_to_le16(length); | |
2985 | d->res_count = d->req_count; | |
2986 | d->transfer_status = 0; | |
2987 | ||
2988 | page_bus = page_private(buffer->pages[page]); | |
2989 | d->data_address = cpu_to_le32(page_bus + offset); | |
2990 | ||
2991 | rest -= length; | |
2992 | offset = 0; | |
2993 | page++; | |
2994 | ||
2995 | context_append(&ctx->context, d, 1, 0); | |
2996 | } | |
2997 | ||
2998 | return 0; | |
2999 | } | |
3000 | ||
53dca511 SR |
3001 | static int ohci_queue_iso(struct fw_iso_context *base, |
3002 | struct fw_iso_packet *packet, | |
3003 | struct fw_iso_buffer *buffer, | |
3004 | unsigned long payload) | |
295e3feb | 3005 | { |
e364cf4e | 3006 | struct iso_context *ctx = container_of(base, struct iso_context, base); |
fe5ca634 | 3007 | unsigned long flags; |
872e330e | 3008 | int ret = -ENOSYS; |
e364cf4e | 3009 | |
fe5ca634 | 3010 | spin_lock_irqsave(&ctx->context.ohci->lock, flags); |
872e330e SR |
3011 | switch (base->type) { |
3012 | case FW_ISO_CONTEXT_TRANSMIT: | |
3013 | ret = queue_iso_transmit(ctx, packet, buffer, payload); | |
3014 | break; | |
3015 | case FW_ISO_CONTEXT_RECEIVE: | |
3016 | ret = queue_iso_packet_per_buffer(ctx, packet, buffer, payload); | |
3017 | break; | |
3018 | case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL: | |
3019 | ret = queue_iso_buffer_fill(ctx, packet, buffer, payload); | |
3020 | break; | |
3021 | } | |
fe5ca634 DM |
3022 | spin_unlock_irqrestore(&ctx->context.ohci->lock, flags); |
3023 | ||
2dbd7d7e | 3024 | return ret; |
295e3feb KH |
3025 | } |
3026 | ||
21ebcd12 | 3027 | static const struct fw_card_driver ohci_driver = { |
ed568912 | 3028 | .enable = ohci_enable, |
02d37bed | 3029 | .read_phy_reg = ohci_read_phy_reg, |
ed568912 KH |
3030 | .update_phy_reg = ohci_update_phy_reg, |
3031 | .set_config_rom = ohci_set_config_rom, | |
3032 | .send_request = ohci_send_request, | |
3033 | .send_response = ohci_send_response, | |
730c32f5 | 3034 | .cancel_packet = ohci_cancel_packet, |
ed568912 | 3035 | .enable_phys_dma = ohci_enable_phys_dma, |
0fcff4e3 SR |
3036 | .read_csr = ohci_read_csr, |
3037 | .write_csr = ohci_write_csr, | |
ed568912 KH |
3038 | |
3039 | .allocate_iso_context = ohci_allocate_iso_context, | |
3040 | .free_iso_context = ohci_free_iso_context, | |
872e330e | 3041 | .set_iso_channels = ohci_set_iso_channels, |
ed568912 | 3042 | .queue_iso = ohci_queue_iso, |
69cdb726 | 3043 | .start_iso = ohci_start_iso, |
b8295668 | 3044 | .stop_iso = ohci_stop_iso, |
ed568912 KH |
3045 | }; |
3046 | ||
ea8d006b | 3047 | #ifdef CONFIG_PPC_PMAC |
5da3dac8 | 3048 | static void pmac_ohci_on(struct pci_dev *dev) |
2ed0f181 | 3049 | { |
ea8d006b SR |
3050 | if (machine_is(powermac)) { |
3051 | struct device_node *ofn = pci_device_to_OF_node(dev); | |
3052 | ||
3053 | if (ofn) { | |
3054 | pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1); | |
3055 | pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1); | |
3056 | } | |
3057 | } | |
2ed0f181 SR |
3058 | } |
3059 | ||
5da3dac8 | 3060 | static void pmac_ohci_off(struct pci_dev *dev) |
2ed0f181 SR |
3061 | { |
3062 | if (machine_is(powermac)) { | |
3063 | struct device_node *ofn = pci_device_to_OF_node(dev); | |
3064 | ||
3065 | if (ofn) { | |
3066 | pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0); | |
3067 | pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0); | |
3068 | } | |
3069 | } | |
3070 | } | |
3071 | #else | |
5da3dac8 SR |
3072 | static inline void pmac_ohci_on(struct pci_dev *dev) {} |
3073 | static inline void pmac_ohci_off(struct pci_dev *dev) {} | |
ea8d006b SR |
3074 | #endif /* CONFIG_PPC_PMAC */ |
3075 | ||
53dca511 SR |
3076 | static int __devinit pci_probe(struct pci_dev *dev, |
3077 | const struct pci_device_id *ent) | |
2ed0f181 SR |
3078 | { |
3079 | struct fw_ohci *ohci; | |
aa0170ff | 3080 | u32 bus_options, max_receive, link_speed, version; |
2ed0f181 | 3081 | u64 guid; |
dd23736e | 3082 | int i, err; |
2ed0f181 SR |
3083 | size_t size; |
3084 | ||
2d826cc5 | 3085 | ohci = kzalloc(sizeof(*ohci), GFP_KERNEL); |
ed568912 | 3086 | if (ohci == NULL) { |
7007a076 SR |
3087 | err = -ENOMEM; |
3088 | goto fail; | |
ed568912 KH |
3089 | } |
3090 | ||
3091 | fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev); | |
3092 | ||
5da3dac8 | 3093 | pmac_ohci_on(dev); |
130d5496 | 3094 | |
d79406dd KH |
3095 | err = pci_enable_device(dev); |
3096 | if (err) { | |
7007a076 | 3097 | fw_error("Failed to enable OHCI hardware\n"); |
bd7dee63 | 3098 | goto fail_free; |
ed568912 KH |
3099 | } |
3100 | ||
3101 | pci_set_master(dev); | |
3102 | pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0); | |
3103 | pci_set_drvdata(dev, ohci); | |
3104 | ||
3105 | spin_lock_init(&ohci->lock); | |
02d37bed | 3106 | mutex_init(&ohci->phy_reg_mutex); |
ed568912 KH |
3107 | |
3108 | tasklet_init(&ohci->bus_reset_tasklet, | |
3109 | bus_reset_tasklet, (unsigned long)ohci); | |
3110 | ||
d79406dd KH |
3111 | err = pci_request_region(dev, 0, ohci_driver_name); |
3112 | if (err) { | |
ed568912 | 3113 | fw_error("MMIO resource unavailable\n"); |
d79406dd | 3114 | goto fail_disable; |
ed568912 KH |
3115 | } |
3116 | ||
3117 | ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE); | |
3118 | if (ohci->registers == NULL) { | |
3119 | fw_error("Failed to remap registers\n"); | |
d79406dd KH |
3120 | err = -ENXIO; |
3121 | goto fail_iomem; | |
ed568912 KH |
3122 | } |
3123 | ||
4a635593 | 3124 | for (i = 0; i < ARRAY_SIZE(ohci_quirks); i++) |
9993e0fe SR |
3125 | if ((ohci_quirks[i].vendor == dev->vendor) && |
3126 | (ohci_quirks[i].device == (unsigned short)PCI_ANY_ID || | |
3127 | ohci_quirks[i].device == dev->device) && | |
3128 | (ohci_quirks[i].revision == (unsigned short)PCI_ANY_ID || | |
3129 | ohci_quirks[i].revision >= dev->revision)) { | |
4a635593 SR |
3130 | ohci->quirks = ohci_quirks[i].flags; |
3131 | break; | |
3132 | } | |
3e9cc2f3 SR |
3133 | if (param_quirks) |
3134 | ohci->quirks = param_quirks; | |
b677532b | 3135 | |
ec766a79 CL |
3136 | /* |
3137 | * Because dma_alloc_coherent() allocates at least one page, | |
3138 | * we save space by using a common buffer for the AR request/ | |
3139 | * response descriptors and the self IDs buffer. | |
3140 | */ | |
3141 | BUILD_BUG_ON(AR_BUFFERS * sizeof(struct descriptor) > PAGE_SIZE/4); | |
3142 | BUILD_BUG_ON(SELF_ID_BUF_SIZE > PAGE_SIZE/2); | |
3143 | ohci->misc_buffer = dma_alloc_coherent(ohci->card.device, | |
3144 | PAGE_SIZE, | |
3145 | &ohci->misc_buffer_bus, | |
3146 | GFP_KERNEL); | |
3147 | if (!ohci->misc_buffer) { | |
3148 | err = -ENOMEM; | |
3149 | goto fail_iounmap; | |
3150 | } | |
3151 | ||
3152 | err = ar_context_init(&ohci->ar_request_ctx, ohci, 0, | |
7a39d8b8 CL |
3153 | OHCI1394_AsReqRcvContextControlSet); |
3154 | if (err < 0) | |
ec766a79 | 3155 | goto fail_misc_buf; |
ed568912 | 3156 | |
ec766a79 | 3157 | err = ar_context_init(&ohci->ar_response_ctx, ohci, PAGE_SIZE/4, |
7a39d8b8 CL |
3158 | OHCI1394_AsRspRcvContextControlSet); |
3159 | if (err < 0) | |
3160 | goto fail_arreq_ctx; | |
ed568912 | 3161 | |
c088ab30 CL |
3162 | err = context_init(&ohci->at_request_ctx, ohci, |
3163 | OHCI1394_AsReqTrContextControlSet, handle_at_packet); | |
3164 | if (err < 0) | |
3165 | goto fail_arrsp_ctx; | |
ed568912 | 3166 | |
c088ab30 CL |
3167 | err = context_init(&ohci->at_response_ctx, ohci, |
3168 | OHCI1394_AsRspTrContextControlSet, handle_at_packet); | |
3169 | if (err < 0) | |
3170 | goto fail_atreq_ctx; | |
ed568912 | 3171 | |
ed568912 | 3172 | reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0); |
4802f16d SR |
3173 | ohci->ir_context_channels = ~0ULL; |
3174 | ohci->ir_context_mask = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet); | |
ed568912 | 3175 | reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0); |
dd23736e ML |
3176 | ohci->n_ir = hweight32(ohci->ir_context_mask); |
3177 | size = sizeof(struct iso_context) * ohci->n_ir; | |
4802f16d | 3178 | ohci->ir_context_list = kzalloc(size, GFP_KERNEL); |
ed568912 KH |
3179 | |
3180 | reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0); | |
4802f16d | 3181 | ohci->it_context_mask = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet); |
ed568912 | 3182 | reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0); |
dd23736e ML |
3183 | ohci->n_it = hweight32(ohci->it_context_mask); |
3184 | size = sizeof(struct iso_context) * ohci->n_it; | |
4802f16d | 3185 | ohci->it_context_list = kzalloc(size, GFP_KERNEL); |
ed568912 KH |
3186 | |
3187 | if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) { | |
d79406dd | 3188 | err = -ENOMEM; |
7007a076 | 3189 | goto fail_contexts; |
ed568912 KH |
3190 | } |
3191 | ||
ec766a79 CL |
3192 | ohci->self_id_cpu = ohci->misc_buffer + PAGE_SIZE/2; |
3193 | ohci->self_id_bus = ohci->misc_buffer_bus + PAGE_SIZE/2; | |
ed568912 | 3194 | |
ed568912 KH |
3195 | bus_options = reg_read(ohci, OHCI1394_BusOptions); |
3196 | max_receive = (bus_options >> 12) & 0xf; | |
3197 | link_speed = bus_options & 0x7; | |
3198 | guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) | | |
3199 | reg_read(ohci, OHCI1394_GUIDLo); | |
3200 | ||
d79406dd | 3201 | err = fw_card_add(&ohci->card, max_receive, link_speed, guid); |
e1eff7a3 | 3202 | if (err) |
ec766a79 | 3203 | goto fail_contexts; |
ed568912 | 3204 | |
6fdb2ee2 SR |
3205 | version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff; |
3206 | fw_notify("Added fw-ohci device %s, OHCI v%x.%x, " | |
3207 | "%d IR + %d IT contexts, quirks 0x%x\n", | |
3208 | dev_name(&dev->dev), version >> 16, version & 0xff, | |
dd23736e | 3209 | ohci->n_ir, ohci->n_it, ohci->quirks); |
e1eff7a3 | 3210 | |
ed568912 | 3211 | return 0; |
d79406dd | 3212 | |
7007a076 | 3213 | fail_contexts: |
d79406dd | 3214 | kfree(ohci->ir_context_list); |
7007a076 SR |
3215 | kfree(ohci->it_context_list); |
3216 | context_release(&ohci->at_response_ctx); | |
c088ab30 | 3217 | fail_atreq_ctx: |
7007a076 | 3218 | context_release(&ohci->at_request_ctx); |
c088ab30 | 3219 | fail_arrsp_ctx: |
7007a076 | 3220 | ar_context_release(&ohci->ar_response_ctx); |
7a39d8b8 | 3221 | fail_arreq_ctx: |
7007a076 | 3222 | ar_context_release(&ohci->ar_request_ctx); |
ec766a79 CL |
3223 | fail_misc_buf: |
3224 | dma_free_coherent(ohci->card.device, PAGE_SIZE, | |
3225 | ohci->misc_buffer, ohci->misc_buffer_bus); | |
7a39d8b8 | 3226 | fail_iounmap: |
d79406dd KH |
3227 | pci_iounmap(dev, ohci->registers); |
3228 | fail_iomem: | |
3229 | pci_release_region(dev, 0); | |
3230 | fail_disable: | |
3231 | pci_disable_device(dev); | |
bd7dee63 SR |
3232 | fail_free: |
3233 | kfree(&ohci->card); | |
5da3dac8 | 3234 | pmac_ohci_off(dev); |
7007a076 SR |
3235 | fail: |
3236 | if (err == -ENOMEM) | |
3237 | fw_error("Out of memory\n"); | |
d79406dd KH |
3238 | |
3239 | return err; | |
ed568912 KH |
3240 | } |
3241 | ||
3242 | static void pci_remove(struct pci_dev *dev) | |
3243 | { | |
3244 | struct fw_ohci *ohci; | |
3245 | ||
3246 | ohci = pci_get_drvdata(dev); | |
e254a4b4 KH |
3247 | reg_write(ohci, OHCI1394_IntMaskClear, ~0); |
3248 | flush_writes(ohci); | |
ed568912 KH |
3249 | fw_core_remove_card(&ohci->card); |
3250 | ||
c781c06d KH |
3251 | /* |
3252 | * FIXME: Fail all pending packets here, now that the upper | |
3253 | * layers can't queue any more. | |
3254 | */ | |
ed568912 KH |
3255 | |
3256 | software_reset(ohci); | |
3257 | free_irq(dev->irq, ohci); | |
a55709ba JF |
3258 | |
3259 | if (ohci->next_config_rom && ohci->next_config_rom != ohci->config_rom) | |
3260 | dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, | |
3261 | ohci->next_config_rom, ohci->next_config_rom_bus); | |
3262 | if (ohci->config_rom) | |
3263 | dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, | |
3264 | ohci->config_rom, ohci->config_rom_bus); | |
a55709ba JF |
3265 | ar_context_release(&ohci->ar_request_ctx); |
3266 | ar_context_release(&ohci->ar_response_ctx); | |
ec766a79 CL |
3267 | dma_free_coherent(ohci->card.device, PAGE_SIZE, |
3268 | ohci->misc_buffer, ohci->misc_buffer_bus); | |
a55709ba JF |
3269 | context_release(&ohci->at_request_ctx); |
3270 | context_release(&ohci->at_response_ctx); | |
d79406dd KH |
3271 | kfree(ohci->it_context_list); |
3272 | kfree(ohci->ir_context_list); | |
262444ee | 3273 | pci_disable_msi(dev); |
d79406dd KH |
3274 | pci_iounmap(dev, ohci->registers); |
3275 | pci_release_region(dev, 0); | |
3276 | pci_disable_device(dev); | |
bd7dee63 | 3277 | kfree(&ohci->card); |
5da3dac8 | 3278 | pmac_ohci_off(dev); |
ea8d006b | 3279 | |
ed568912 KH |
3280 | fw_notify("Removed fw-ohci device.\n"); |
3281 | } | |
3282 | ||
2aef469a | 3283 | #ifdef CONFIG_PM |
2ed0f181 | 3284 | static int pci_suspend(struct pci_dev *dev, pm_message_t state) |
2aef469a | 3285 | { |
2ed0f181 | 3286 | struct fw_ohci *ohci = pci_get_drvdata(dev); |
2aef469a KH |
3287 | int err; |
3288 | ||
3289 | software_reset(ohci); | |
2ed0f181 | 3290 | free_irq(dev->irq, ohci); |
262444ee | 3291 | pci_disable_msi(dev); |
2ed0f181 | 3292 | err = pci_save_state(dev); |
2aef469a | 3293 | if (err) { |
8a8cea27 | 3294 | fw_error("pci_save_state failed\n"); |
2aef469a KH |
3295 | return err; |
3296 | } | |
2ed0f181 | 3297 | err = pci_set_power_state(dev, pci_choose_state(dev, state)); |
55111428 SR |
3298 | if (err) |
3299 | fw_error("pci_set_power_state failed with %d\n", err); | |
5da3dac8 | 3300 | pmac_ohci_off(dev); |
ea8d006b | 3301 | |
2aef469a KH |
3302 | return 0; |
3303 | } | |
3304 | ||
2ed0f181 | 3305 | static int pci_resume(struct pci_dev *dev) |
2aef469a | 3306 | { |
2ed0f181 | 3307 | struct fw_ohci *ohci = pci_get_drvdata(dev); |
2aef469a KH |
3308 | int err; |
3309 | ||
5da3dac8 | 3310 | pmac_ohci_on(dev); |
2ed0f181 SR |
3311 | pci_set_power_state(dev, PCI_D0); |
3312 | pci_restore_state(dev); | |
3313 | err = pci_enable_device(dev); | |
2aef469a | 3314 | if (err) { |
8a8cea27 | 3315 | fw_error("pci_enable_device failed\n"); |
2aef469a KH |
3316 | return err; |
3317 | } | |
3318 | ||
8662b6b0 ML |
3319 | /* Some systems don't setup GUID register on resume from ram */ |
3320 | if (!reg_read(ohci, OHCI1394_GUIDLo) && | |
3321 | !reg_read(ohci, OHCI1394_GUIDHi)) { | |
3322 | reg_write(ohci, OHCI1394_GUIDLo, (u32)ohci->card.guid); | |
3323 | reg_write(ohci, OHCI1394_GUIDHi, (u32)(ohci->card.guid >> 32)); | |
3324 | } | |
3325 | ||
dd23736e ML |
3326 | err = ohci_enable(&ohci->card, NULL, 0); |
3327 | ||
3328 | if (err) | |
3329 | return err; | |
3330 | ||
3331 | ohci_resume_iso_dma(ohci); | |
3332 | return 0; | |
2aef469a KH |
3333 | } |
3334 | #endif | |
3335 | ||
a67483d2 | 3336 | static const struct pci_device_id pci_table[] = { |
ed568912 KH |
3337 | { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) }, |
3338 | { } | |
3339 | }; | |
3340 | ||
3341 | MODULE_DEVICE_TABLE(pci, pci_table); | |
3342 | ||
3343 | static struct pci_driver fw_ohci_pci_driver = { | |
3344 | .name = ohci_driver_name, | |
3345 | .id_table = pci_table, | |
3346 | .probe = pci_probe, | |
3347 | .remove = pci_remove, | |
2aef469a KH |
3348 | #ifdef CONFIG_PM |
3349 | .resume = pci_resume, | |
3350 | .suspend = pci_suspend, | |
3351 | #endif | |
ed568912 KH |
3352 | }; |
3353 | ||
3354 | MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>"); | |
3355 | MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers"); | |
3356 | MODULE_LICENSE("GPL"); | |
3357 | ||
1e4c7b0d OH |
3358 | /* Provide a module alias so root-on-sbp2 initrds don't break. */ |
3359 | #ifndef CONFIG_IEEE1394_OHCI1394_MODULE | |
3360 | MODULE_ALIAS("ohci1394"); | |
3361 | #endif | |
3362 | ||
ed568912 KH |
3363 | static int __init fw_ohci_init(void) |
3364 | { | |
3365 | return pci_register_driver(&fw_ohci_pci_driver); | |
3366 | } | |
3367 | ||
3368 | static void __exit fw_ohci_cleanup(void) | |
3369 | { | |
3370 | pci_unregister_driver(&fw_ohci_pci_driver); | |
3371 | } | |
3372 | ||
3373 | module_init(fw_ohci_init); | |
3374 | module_exit(fw_ohci_cleanup); |