[mirror_ubuntu-hirsute-kernel.git] / drivers / firmware / qcom_scm-32.c

// SPDX-License-Identifier: GPL-2.0-only
/* Copyright (c) 2010,2015,2019 The Linux Foundation. All rights reserved.
 * Copyright (C) 2015 Linaro Ltd.
 */

#include <linux/slab.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/errno.h>
#include <linux/err.h>
#include <linux/qcom_scm.h>
#include <linux/arm-smccc.h>
#include <linux/dma-mapping.h>

#include "qcom_scm.h"

#define QCOM_SCM_FLAG_COLDBOOT_CPU0	0x00
#define QCOM_SCM_FLAG_COLDBOOT_CPU1	0x01
#define QCOM_SCM_FLAG_COLDBOOT_CPU2	0x08
#define QCOM_SCM_FLAG_COLDBOOT_CPU3	0x20

#define QCOM_SCM_FLAG_WARMBOOT_CPU0	0x04
#define QCOM_SCM_FLAG_WARMBOOT_CPU1	0x02
#define QCOM_SCM_FLAG_WARMBOOT_CPU2	0x10
#define QCOM_SCM_FLAG_WARMBOOT_CPU3	0x40

struct qcom_scm_entry {
	int flag;
	void *entry;
};

static struct qcom_scm_entry qcom_scm_wb[] = {
	{ .flag = QCOM_SCM_FLAG_WARMBOOT_CPU0 },
	{ .flag = QCOM_SCM_FLAG_WARMBOOT_CPU1 },
	{ .flag = QCOM_SCM_FLAG_WARMBOOT_CPU2 },
	{ .flag = QCOM_SCM_FLAG_WARMBOOT_CPU3 },
};

static DEFINE_MUTEX(qcom_scm_lock);

#define MAX_QCOM_SCM_ARGS 10
#define MAX_QCOM_SCM_RETS 3

enum qcom_scm_arg_types {
	QCOM_SCM_VAL,
	QCOM_SCM_RO,
	QCOM_SCM_RW,
	QCOM_SCM_BUFVAL,
};

#define QCOM_SCM_ARGS_IMPL(num, a, b, c, d, e, f, g, h, i, j, ...) (\
			   (((a) & 0x3) << 4) | \
			   (((b) & 0x3) << 6) | \
			   (((c) & 0x3) << 8) | \
			   (((d) & 0x3) << 10) | \
			   (((e) & 0x3) << 12) | \
			   (((f) & 0x3) << 14) | \
			   (((g) & 0x3) << 16) | \
			   (((h) & 0x3) << 18) | \
			   (((i) & 0x3) << 20) | \
			   (((j) & 0x3) << 22) | \
			   ((num) & 0xf))

#define QCOM_SCM_ARGS(...) QCOM_SCM_ARGS_IMPL(__VA_ARGS__, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)

/**
 * struct qcom_scm_desc
 * @arginfo:	Metadata describing the arguments in args[]
 * @args:	The array of arguments for the secure syscall
 */
struct qcom_scm_desc {
	u32 svc;
	u32 cmd;
	u32 arginfo;
	u64 args[MAX_QCOM_SCM_ARGS];
	u32 owner;
};

/**
 * struct qcom_scm_res
 * @result:	The values returned by the secure syscall
 */
struct qcom_scm_res {
	u64 result[MAX_QCOM_SCM_RETS];
};

/**
 * struct arm_smccc_args
 * @args:	The array of values used in registers in smc instruction
 */
struct arm_smccc_args {
	unsigned long args[8];
};

#define SCM_LEGACY_FNID(s, c)	(((s) << 10) | ((c) & 0x3ff))

/**
 * struct scm_legacy_command - one SCM command buffer
 * @len: total available memory for command and response
 * @buf_offset: start of command buffer
 * @resp_hdr_offset: start of response buffer
 * @id: command to be executed
 * @buf: buffer returned from scm_legacy_get_command_buffer()
 *
 * An SCM command is laid out in memory as follows:
 *
 *	------------------- <--- struct scm_legacy_command
 *	| command header  |
 *	------------------- <--- scm_legacy_get_command_buffer()
 *	| command buffer  |
 *	------------------- <--- struct scm_legacy_response and
 *	| response header |      scm_legacy_command_to_response()
 *	------------------- <--- scm_legacy_get_response_buffer()
 *	| response buffer |
 *	-------------------
 *
 * There can be arbitrary padding between the headers and buffers so
 * you should always use the appropriate scm_legacy_get_*_buffer() routines
 * to access the buffers in a safe manner.
 */
struct scm_legacy_command {
	__le32 len;
	__le32 buf_offset;
	__le32 resp_hdr_offset;
	__le32 id;
	__le32 buf[0];
};

/**
 * struct scm_legacy_response - one SCM response buffer
 * @len: total available memory for response
 * @buf_offset: start of response data relative to start of scm_legacy_response
 * @is_complete: indicates if the command has finished processing
 */
struct scm_legacy_response {
	__le32 len;
	__le32 buf_offset;
	__le32 is_complete;
};

/**
 * scm_legacy_command_to_response() - Get a pointer to a scm_legacy_response
 * @cmd: command
 *
 * Returns a pointer to a response for a command.
 */
static inline struct scm_legacy_response *scm_legacy_command_to_response(
		const struct scm_legacy_command *cmd)
{
	return (void *)cmd + le32_to_cpu(cmd->resp_hdr_offset);
}

/**
 * scm_legacy_get_command_buffer() - Get a pointer to a command buffer
 * @cmd: command
 *
 * Returns a pointer to the command buffer of a command.
 */
static inline void *scm_legacy_get_command_buffer(
		const struct scm_legacy_command *cmd)
{
	return (void *)cmd->buf;
}

/**
 * scm_legacy_get_response_buffer() - Get a pointer to a response buffer
 * @rsp: response
 *
 * Returns a pointer to a response buffer of a response.
 */
static inline void *scm_legacy_get_response_buffer(
		const struct scm_legacy_response *rsp)
{
	return (void *)rsp + le32_to_cpu(rsp->buf_offset);
}

static void __scm_legacy_do(const struct arm_smccc_args *smc,
			    struct arm_smccc_res *res)
{
	do {
		arm_smccc_smc(smc->args[0], smc->args[1], smc->args[2],
			      smc->args[3], smc->args[4], smc->args[5],
			      smc->args[6], smc->args[7], res);
	} while (res->a0 == QCOM_SCM_INTERRUPTED);
}

/**
 * qcom_scm_call() - Sends a command to the SCM and waits for the command to
 * finish processing.
 *
 * A note on cache maintenance:
 * Note that any buffers that are expected to be accessed by the secure world
 * must be flushed before invoking qcom_scm_call and invalidated in the cache
 * immediately after qcom_scm_call returns. Cache maintenance on the command
 * and response buffers is taken care of by qcom_scm_call; however, callers are
 * responsible for any other cached buffers passed over to the secure world.
 */
static int qcom_scm_call(struct device *dev, const struct qcom_scm_desc *desc,
			 struct qcom_scm_res *res)
{
	u8 arglen = desc->arginfo & 0xf;
	int ret = 0, context_id;
	unsigned int i;
	struct scm_legacy_command *cmd;
	struct scm_legacy_response *rsp;
	struct arm_smccc_args smc = {0};
	struct arm_smccc_res smc_res;
	const size_t cmd_len = arglen * sizeof(__le32);
	const size_t resp_len = MAX_QCOM_SCM_RETS * sizeof(__le32);
	size_t alloc_len = sizeof(*cmd) + cmd_len + sizeof(*rsp) + resp_len;
	dma_addr_t cmd_phys;
	__le32 *arg_buf;
	const __le32 *res_buf;

	cmd = kzalloc(PAGE_ALIGN(alloc_len), GFP_KERNEL);
	if (!cmd)
		return -ENOMEM;

	cmd->len = cpu_to_le32(alloc_len);
	cmd->buf_offset = cpu_to_le32(sizeof(*cmd));
	cmd->resp_hdr_offset = cpu_to_le32(sizeof(*cmd) + cmd_len);
	cmd->id = cpu_to_le32(SCM_LEGACY_FNID(desc->svc, desc->cmd));

	arg_buf = scm_legacy_get_command_buffer(cmd);
	for (i = 0; i < arglen; i++)
		arg_buf[i] = cpu_to_le32(desc->args[i]);

	rsp = scm_legacy_command_to_response(cmd);

	cmd_phys = dma_map_single(dev, cmd, alloc_len, DMA_TO_DEVICE);
	if (dma_mapping_error(dev, cmd_phys)) {
		kfree(cmd);
		return -ENOMEM;
	}

	smc.args[0] = 1;
	smc.args[1] = (unsigned long)&context_id;
	smc.args[2] = cmd_phys;

	mutex_lock(&qcom_scm_lock);
	__scm_legacy_do(&smc, &smc_res);
	if (smc_res.a0)
		ret = qcom_scm_remap_error(smc_res.a0);
	mutex_unlock(&qcom_scm_lock);
	if (ret)
		goto out;

	do {
		dma_sync_single_for_cpu(dev, cmd_phys + sizeof(*cmd) + cmd_len,
					sizeof(*rsp), DMA_FROM_DEVICE);
	} while (!rsp->is_complete);

	dma_sync_single_for_cpu(dev, cmd_phys + sizeof(*cmd) + cmd_len +
				le32_to_cpu(rsp->buf_offset),
				resp_len, DMA_FROM_DEVICE);

	if (res) {
		res_buf = scm_legacy_get_response_buffer(rsp);
		for (i = 0; i < MAX_QCOM_SCM_RETS; i++)
			res->result[i] = le32_to_cpu(res_buf[i]);
	}
out:
	dma_unmap_single(dev, cmd_phys, alloc_len, DMA_TO_DEVICE);
	kfree(cmd);
	return ret;
}

#define SCM_LEGACY_CLASS_REGISTER		(0x2 << 8)
#define SCM_LEGACY_MASK_IRQS		BIT(5)
#define SCM_LEGACY_ATOMIC_ID(svc, cmd, n) \
				((SCM_LEGACY_FNID(svc, cmd) << 12) | \
				SCM_LEGACY_CLASS_REGISTER | \
				SCM_LEGACY_MASK_IRQS | \
				(n & 0xf))

/**
 * qcom_scm_call_atomic1() - Send an atomic SCM command with one argument
 * @svc_id: service identifier
 * @cmd_id: command identifier
 * @arg1: first argument
 *
 * This shall only be used with commands that are guaranteed to be
 * uninterruptable, atomic and SMP safe.
 */
static s32 qcom_scm_call_atomic1(u32 svc, u32 cmd, u32 arg1)
{
	int context_id;
	struct arm_smccc_res res;

	arm_smccc_smc(SCM_LEGACY_ATOMIC_ID(svc, cmd, 1),
		      (unsigned long)&context_id, arg1, 0, 0, 0, 0, 0, &res);

	return res.a0;
}

/**
 * qcom_scm_call_atomic2() - Send an atomic SCM command with two arguments
 * @svc_id:	service identifier
 * @cmd_id:	command identifier
 * @arg1:	first argument
 * @arg2:	second argument
 *
 * This shall only be used with commands that are guaranteed to be
 * uninterruptable, atomic and SMP safe.
 */
static s32 qcom_scm_call_atomic2(u32 svc, u32 cmd, u32 arg1, u32 arg2)
{
	int context_id;
	struct arm_smccc_res res;

	arm_smccc_smc(SCM_LEGACY_ATOMIC_ID(svc, cmd, 2),
		      (unsigned long)&context_id, arg1, 0, 0, 0, 0, 0, &res);

	return res.a0;
}

/**
 * qcom_scm_set_cold_boot_addr() - Set the cold boot address for cpus
 * @entry: Entry point function for the cpus
 * @cpus: The cpumask of cpus that will use the entry point
 *
 * Set the cold boot address of the cpus. Any cpu outside the supported
 * range would be removed from the cpu present mask.
 */
int __qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus)
{
	int flags = 0;
	int cpu;
	int scm_cb_flags[] = {
		QCOM_SCM_FLAG_COLDBOOT_CPU0,
		QCOM_SCM_FLAG_COLDBOOT_CPU1,
		QCOM_SCM_FLAG_COLDBOOT_CPU2,
		QCOM_SCM_FLAG_COLDBOOT_CPU3,
	};

	if (!cpus || (cpus && cpumask_empty(cpus)))
		return -EINVAL;

	for_each_cpu(cpu, cpus) {
		if (cpu < ARRAY_SIZE(scm_cb_flags))
			flags |= scm_cb_flags[cpu];
		else
			set_cpu_present(cpu, false);
	}

	return qcom_scm_call_atomic2(QCOM_SCM_SVC_BOOT, QCOM_SCM_BOOT_SET_ADDR,
				    flags, virt_to_phys(entry));
}

/**
 * qcom_scm_set_warm_boot_addr() - Set the warm boot address for cpus
 * @entry: Entry point function for the cpus
 * @cpus: The cpumask of cpus that will use the entry point
 *
 * Set the Linux entry point for the SCM to transfer control to when coming
 * out of a power down. CPU power down may be executed on cpuidle or hotplug.
 */
int __qcom_scm_set_warm_boot_addr(struct device *dev, void *entry,
				  const cpumask_t *cpus)
{
	int ret;
	int flags = 0;
	int cpu;
	struct qcom_scm_desc desc = {
		.svc = QCOM_SCM_SVC_BOOT,
		.cmd = QCOM_SCM_BOOT_SET_ADDR,
	};

	/*
	 * Reassign only if we are switching from hotplug entry point
	 * to cpuidle entry point or vice versa.
	 */
	for_each_cpu(cpu, cpus) {
		if (entry == qcom_scm_wb[cpu].entry)
			continue;
		flags |= qcom_scm_wb[cpu].flag;
	}

	/* No change in entry function */
	if (!flags)
		return 0;

	desc.args[0] = flags;
	desc.args[1] = virt_to_phys(entry);
	desc.arginfo = QCOM_SCM_ARGS(2);

	ret = qcom_scm_call(dev, &desc, NULL);
	if (!ret) {
		for_each_cpu(cpu, cpus)
			qcom_scm_wb[cpu].entry = entry;
	}

	return ret;
}

/**
 * qcom_scm_cpu_power_down() - Power down the cpu
 * @flags - Flags to flush cache
 *
 * This is an end point to power down cpu. If there was a pending interrupt,
 * the control would return from this function, otherwise, the cpu jumps to the
 * warm boot entry point set for this cpu upon reset.
 */
void __qcom_scm_cpu_power_down(u32 flags)
{
	qcom_scm_call_atomic1(QCOM_SCM_SVC_BOOT, QCOM_SCM_BOOT_TERMINATE_PC,
			flags & QCOM_SCM_FLUSH_FLAG_MASK);
}

int __qcom_scm_is_call_available(struct device *dev, u32 svc_id, u32 cmd_id)
{
	int ret;
	struct qcom_scm_desc desc = {
		.svc = QCOM_SCM_SVC_INFO,
		.cmd = QCOM_SCM_INFO_IS_CALL_AVAIL,
		.args[0] = SCM_LEGACY_FNID(svc_id, cmd_id),
		.arginfo = QCOM_SCM_ARGS(1),
	};
	struct qcom_scm_res res;

	ret = qcom_scm_call(dev, &desc, &res);

	return ret ? : res.result[0];
}

int __qcom_scm_hdcp_req(struct device *dev, struct qcom_scm_hdcp_req *req,
			u32 req_cnt, u32 *resp)
{
	int ret;
	struct qcom_scm_desc desc = {
		.svc = QCOM_SCM_SVC_HDCP,
		.cmd = QCOM_SCM_HDCP_INVOKE,
	};
	struct qcom_scm_res res;

	if (req_cnt > QCOM_SCM_HDCP_MAX_REQ_CNT)
		return -ERANGE;

	desc.args[0] = req[0].addr;
	desc.args[1] = req[0].val;
	desc.args[2] = req[1].addr;
	desc.args[3] = req[1].val;
	desc.args[4] = req[2].addr;
	desc.args[5] = req[2].val;
	desc.args[6] = req[3].addr;
	desc.args[7] = req[3].val;
	desc.args[8] = req[4].addr;
	desc.args[9] = req[4].val;
	desc.arginfo = QCOM_SCM_ARGS(10);

	ret = qcom_scm_call(dev, &desc, &res);
	*resp = res.result[0];

	return ret;
}

int __qcom_scm_ocmem_lock(struct device *dev, u32 id, u32 offset, u32 size,
			  u32 mode)
{
	struct qcom_scm_desc desc = {
		.svc = QCOM_SCM_SVC_OCMEM,
		.cmd = QCOM_SCM_OCMEM_LOCK_CMD,
	};

	desc.args[0] = id;
	desc.args[1] = offset;
	desc.args[2] = size;
	desc.args[3] = mode;
	desc.arginfo = QCOM_SCM_ARGS(4);

	return qcom_scm_call(dev, &desc, NULL);
}

int __qcom_scm_ocmem_unlock(struct device *dev, u32 id, u32 offset, u32 size)
{
	struct qcom_scm_desc desc = {
		.svc = QCOM_SCM_SVC_OCMEM,
		.cmd = QCOM_SCM_OCMEM_UNLOCK_CMD,
	};

	desc.args[0] = id;
	desc.args[1] = offset;
	desc.args[2] = size;
	desc.arginfo = QCOM_SCM_ARGS(3);

	return qcom_scm_call(dev, &desc, NULL);
}

void __qcom_scm_init(void)
{
}

bool __qcom_scm_pas_supported(struct device *dev, u32 peripheral)
{
	int ret;
	struct qcom_scm_desc desc = {
		.svc = QCOM_SCM_SVC_PIL,
		.cmd = QCOM_SCM_PIL_PAS_IS_SUPPORTED,
	};
	struct qcom_scm_res res;

	desc.args[0] = peripheral;
	desc.arginfo = QCOM_SCM_ARGS(1);

	ret = qcom_scm_call(dev, &desc, &res);

	return ret ? false : !!res.result[0];
}

int __qcom_scm_pas_init_image(struct device *dev, u32 peripheral,
			      dma_addr_t metadata_phys)
{
	int ret;
	struct qcom_scm_desc desc = {
		.svc = QCOM_SCM_SVC_PIL,
		.cmd = QCOM_SCM_PIL_PAS_INIT_IMAGE,
	};
	struct qcom_scm_res res;

	desc.args[0] = peripheral;
	desc.args[1] = metadata_phys;
	desc.arginfo = QCOM_SCM_ARGS(2, QCOM_SCM_VAL, QCOM_SCM_RW);

	ret = qcom_scm_call(dev, &desc, &res);

	return ret ? : res.result[0];
}

int __qcom_scm_pas_mem_setup(struct device *dev, u32 peripheral,
			      phys_addr_t addr, phys_addr_t size)
{
	int ret;
	struct qcom_scm_desc desc = {
		.svc = QCOM_SCM_SVC_PIL,
		.cmd = QCOM_SCM_PIL_PAS_MEM_SETUP,
	};
	struct qcom_scm_res res;

	desc.args[0] = peripheral;
	desc.args[1] = addr;
	desc.args[2] = size;
	desc.arginfo = QCOM_SCM_ARGS(3);

	ret = qcom_scm_call(dev, &desc, &res);

	return ret ? : res.result[0];
}

int __qcom_scm_pas_auth_and_reset(struct device *dev, u32 peripheral)
{
	int ret;
	struct qcom_scm_desc desc = {
		.svc = QCOM_SCM_SVC_PIL,
		.cmd = QCOM_SCM_PIL_PAS_AUTH_AND_RESET,
	};
	struct qcom_scm_res res;

	desc.args[0] = peripheral;
	desc.arginfo = QCOM_SCM_ARGS(1);

	ret = qcom_scm_call(dev, &desc, &res);

	return ret ? : res.result[0];
}

int __qcom_scm_pas_shutdown(struct device *dev, u32 peripheral)
{
	int ret;
	struct qcom_scm_desc desc = {
		.svc = QCOM_SCM_SVC_PIL,
		.cmd = QCOM_SCM_PIL_PAS_SHUTDOWN,
	};
	struct qcom_scm_res res;

	desc.args[0] = peripheral;
	desc.arginfo = QCOM_SCM_ARGS(1);

	ret = qcom_scm_call(dev, &desc, &res);

	return ret ? : res.result[0];
}

int __qcom_scm_pas_mss_reset(struct device *dev, bool reset)
{
	struct qcom_scm_desc desc = {
		.svc = QCOM_SCM_SVC_PIL,
		.cmd = QCOM_SCM_PIL_PAS_MSS_RESET,
	};
	struct qcom_scm_res res;
	int ret;

	desc.args[0] = reset;
	desc.args[1] = 0;
	desc.arginfo = QCOM_SCM_ARGS(2);

	ret = qcom_scm_call(dev, &desc, &res);

	return ret ? : res.result[0];
}

int __qcom_scm_set_dload_mode(struct device *dev, bool enable)
{
	return qcom_scm_call_atomic2(QCOM_SCM_SVC_BOOT, QCOM_SCM_BOOT_SET_DLOAD_MODE,
				     enable ? QCOM_SCM_BOOT_SET_DLOAD_MODE : 0, 0);
}

int __qcom_scm_set_remote_state(struct device *dev, u32 state, u32 id)
{
	struct qcom_scm_desc desc = {
		.svc = QCOM_SCM_SVC_BOOT,
		.cmd = QCOM_SCM_BOOT_SET_REMOTE_STATE,
	};
	struct qcom_scm_res res;
	int ret;

	desc.args[0] = state;
	desc.args[1] = id;

	ret = qcom_scm_call(dev, &desc, &res);

	return ret ? : res.result[0];
}

int __qcom_scm_assign_mem(struct device *dev, phys_addr_t mem_region,
			  size_t mem_sz, phys_addr_t src, size_t src_sz,
			  phys_addr_t dest, size_t dest_sz)
{
	return -ENODEV;
}

int __qcom_scm_restore_sec_cfg(struct device *dev, u32 device_id,
			       u32 spare)
{
	struct qcom_scm_desc desc = {
		.svc = QCOM_SCM_SVC_MP,
		.cmd = QCOM_SCM_MP_RESTORE_SEC_CFG,
	};
	struct qcom_scm_res res;
	int ret;

	desc.args[0] = device_id;
	desc.args[1] = spare;
	desc.arginfo = QCOM_SCM_ARGS(2);

	ret = qcom_scm_call(dev, &desc, &res);

	return ret ? : res.result[0];
}

int __qcom_scm_iommu_secure_ptbl_size(struct device *dev, u32 spare,
				      size_t *size)
{
	return -ENODEV;
}

int __qcom_scm_iommu_secure_ptbl_init(struct device *dev, u64 addr, u32 size,
				      u32 spare)
{
	return -ENODEV;
}

int __qcom_scm_io_readl(struct device *dev, phys_addr_t addr,
			unsigned int *val)
{
	int ret;

	ret = qcom_scm_call_atomic1(QCOM_SCM_SVC_IO, QCOM_SCM_IO_READ, addr);
	if (ret >= 0)
		*val = ret;

	return ret < 0 ? ret : 0;
}

int __qcom_scm_io_writel(struct device *dev, phys_addr_t addr, unsigned int val)
{
	return qcom_scm_call_atomic2(QCOM_SCM_SVC_IO, QCOM_SCM_IO_WRITE,
				     addr, val);
}

int __qcom_scm_qsmmu500_wait_safe_toggle(struct device *dev, bool enable)
{
	return -ENODEV;
}
Commit	Line	Data
08dbd0f8	1	// SPDX-License-Identifier: GPL-2.0-only
e0aa1539	2	/* Copyright (c) 2010,2015,2019 The Linux Foundation. All rights reserved.
b6a1dfbc	3	* Copyright (C) 2015 Linaro Ltd.
b6a1dfbc KG	4	*/
	5
	6	#include <linux/slab.h>
	7	#include <linux/io.h>
	8	#include <linux/module.h>
	9	#include <linux/mutex.h>
	10	#include <linux/errno.h>
	11	#include <linux/err.h>
	12	#include <linux/qcom_scm.h>
02248981	13	#include <linux/arm-smccc.h>
16e59467	14	#include <linux/dma-mapping.h>
b6a1dfbc KG	15
	16	#include "qcom_scm.h"
	17
	18	#define QCOM_SCM_FLAG_COLDBOOT_CPU0 0x00
	19	#define QCOM_SCM_FLAG_COLDBOOT_CPU1 0x01
	20	#define QCOM_SCM_FLAG_COLDBOOT_CPU2 0x08
	21	#define QCOM_SCM_FLAG_COLDBOOT_CPU3 0x20
	22
	23	#define QCOM_SCM_FLAG_WARMBOOT_CPU0 0x04
	24	#define QCOM_SCM_FLAG_WARMBOOT_CPU1 0x02
	25	#define QCOM_SCM_FLAG_WARMBOOT_CPU2 0x10
	26	#define QCOM_SCM_FLAG_WARMBOOT_CPU3 0x40
	27
	28	struct qcom_scm_entry {
	29	int flag;
	30	void *entry;
	31	};
	32
	33	static struct qcom_scm_entry qcom_scm_wb[] = {
	34	{ .flag = QCOM_SCM_FLAG_WARMBOOT_CPU0 },
	35	{ .flag = QCOM_SCM_FLAG_WARMBOOT_CPU1 },
	36	{ .flag = QCOM_SCM_FLAG_WARMBOOT_CPU2 },
	37	{ .flag = QCOM_SCM_FLAG_WARMBOOT_CPU3 },
	38	};
	39
	40	static DEFINE_MUTEX(qcom_scm_lock);
	41
efd2b15c EB	42	#define MAX_QCOM_SCM_ARGS 10
	43	#define MAX_QCOM_SCM_RETS 3
	44
	45	enum qcom_scm_arg_types {
	46	QCOM_SCM_VAL,
	47	QCOM_SCM_RO,
	48	QCOM_SCM_RW,
	49	QCOM_SCM_BUFVAL,
	50	};
	51
	52	#define QCOM_SCM_ARGS_IMPL(num, a, b, c, d, e, f, g, h, i, j, ...) (\
	53	(((a) & 0x3) << 4) \| \
	54	(((b) & 0x3) << 6) \| \
	55	(((c) & 0x3) << 8) \| \
	56	(((d) & 0x3) << 10) \| \
	57	(((e) & 0x3) << 12) \| \
	58	(((f) & 0x3) << 14) \| \
	59	(((g) & 0x3) << 16) \| \
	60	(((h) & 0x3) << 18) \| \
	61	(((i) & 0x3) << 20) \| \
	62	(((j) & 0x3) << 22) \| \
	63	((num) & 0xf))
	64
	65	#define QCOM_SCM_ARGS(...) QCOM_SCM_ARGS_IMPL(__VA_ARGS__, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)
	66
	67	/**
	68	* struct qcom_scm_desc
	69	* @arginfo: Metadata describing the arguments in args[]
	70	* @args: The array of arguments for the secure syscall
	71	*/
	72	struct qcom_scm_desc {
	73	u32 svc;
	74	u32 cmd;
	75	u32 arginfo;
	76	u64 args[MAX_QCOM_SCM_ARGS];
	77	u32 owner;
	78	};
	79
	80	/**
	81	* struct qcom_scm_res
	82	* @result: The values returned by the secure syscall
	83	*/
	84	struct qcom_scm_res {
	85	u64 result[MAX_QCOM_SCM_RETS];
	86	};
	87
590e9280 EB	88	/**
	89	* struct arm_smccc_args
	90	* @args: The array of values used in registers in smc instruction
	91	*/
	92	struct arm_smccc_args {
	93	unsigned long args[8];
	94	};
	95
fd62c30b EB	96	#define SCM_LEGACY_FNID(s, c) (((s) << 10) \| ((c) & 0x3ff))
fd62c30b EB	97
b6a1dfbc	98	/**
e0aa1539	99	* struct scm_legacy_command - one SCM command buffer
b6a1dfbc KG	100	* @len: total available memory for command and response
	101	* @buf_offset: start of command buffer
	102	* @resp_hdr_offset: start of response buffer
	103	* @id: command to be executed
e0aa1539	104	* @buf: buffer returned from scm_legacy_get_command_buffer()
b6a1dfbc KG	105	*
	106	* An SCM command is laid out in memory as follows:
	107	*
e0aa1539	108	* ------------------- <--- struct scm_legacy_command
b6a1dfbc	109	* \| command header \|
e0aa1539	110	* ------------------- <--- scm_legacy_get_command_buffer()
b6a1dfbc	111	* \| command buffer \|
e0aa1539 EB	112	* ------------------- <--- struct scm_legacy_response and
	113	* \| response header \| scm_legacy_command_to_response()
	114	* ------------------- <--- scm_legacy_get_response_buffer()
b6a1dfbc KG	115	* \| response buffer \|
	116	* -------------------
	117	*
	118	* There can be arbitrary padding between the headers and buffers so
e0aa1539	119	* you should always use the appropriate scm_legacy_get_*_buffer() routines
b6a1dfbc KG	120	* to access the buffers in a safe manner.
b6a1dfbc KG	121	*/
e0aa1539	122	struct scm_legacy_command {
b6a1dfbc KG	123	__le32 len;
	124	__le32 buf_offset;
	125	__le32 resp_hdr_offset;
	126	__le32 id;
	127	__le32 buf[0];
	128	};
	129
	130	/**
e0aa1539	131	* struct scm_legacy_response - one SCM response buffer
b6a1dfbc	132	* @len: total available memory for response
e0aa1539	133	* @buf_offset: start of response data relative to start of scm_legacy_response
b6a1dfbc KG	134	* @is_complete: indicates if the command has finished processing
b6a1dfbc KG	135	*/
e0aa1539	136	struct scm_legacy_response {
b6a1dfbc KG	137	__le32 len;
	138	__le32 buf_offset;
	139	__le32 is_complete;
	140	};
	141
b6a1dfbc	142	/**
e0aa1539	143	* scm_legacy_command_to_response() - Get a pointer to a scm_legacy_response
b6a1dfbc KG	144	* @cmd: command
	145	*
	146	* Returns a pointer to a response for a command.
	147	*/
e0aa1539 EB	148	static inline struct scm_legacy_response *scm_legacy_command_to_response(
e0aa1539 EB	149	const struct scm_legacy_command *cmd)
b6a1dfbc KG	150	{
	151	return (void *)cmd + le32_to_cpu(cmd->resp_hdr_offset);
	152	}
	153
	154	/**
e0aa1539	155	* scm_legacy_get_command_buffer() - Get a pointer to a command buffer
b6a1dfbc KG	156	* @cmd: command
	157	*
	158	* Returns a pointer to the command buffer of a command.
	159	*/
e0aa1539 EB	160	static inline void *scm_legacy_get_command_buffer(
e0aa1539 EB	161	const struct scm_legacy_command *cmd)
b6a1dfbc KG	162	{
	163	return (void *)cmd->buf;
	164	}
	165
	166	/**
e0aa1539	167	* scm_legacy_get_response_buffer() - Get a pointer to a response buffer
b6a1dfbc KG	168	* @rsp: response
	169	*
	170	* Returns a pointer to a response buffer of a response.
	171	*/
e0aa1539 EB	172	static inline void *scm_legacy_get_response_buffer(
e0aa1539 EB	173	const struct scm_legacy_response *rsp)
b6a1dfbc KG	174	{
	175	return (void *)rsp + le32_to_cpu(rsp->buf_offset);
	176	}
	177
590e9280 EB	178	static void __scm_legacy_do(const struct arm_smccc_args *smc,
590e9280 EB	179	struct arm_smccc_res *res)
b6a1dfbc	180	{
b6a1dfbc	181	do {
590e9280 EB	182	arm_smccc_smc(smc->args[0], smc->args[1], smc->args[2],
	183	smc->args[3], smc->args[4], smc->args[5],
	184	smc->args[6], smc->args[7], res);
	185	} while (res->a0 == QCOM_SCM_INTERRUPTED);
b6a1dfbc KG	186	}
b6a1dfbc KG	187
b6a1dfbc	188	/**
efd2b15c EB	189	* qcom_scm_call() - Sends a command to the SCM and waits for the command to
efd2b15c EB	190	* finish processing.
b6a1dfbc KG	191	*
	192	* A note on cache maintenance:
	193	* Note that any buffers that are expected to be accessed by the secure world
	194	* must be flushed before invoking qcom_scm_call and invalidated in the cache
	195	* immediately after qcom_scm_call returns. Cache maintenance on the command
	196	* and response buffers is taken care of by qcom_scm_call; however, callers are
	197	* responsible for any other cached buffers passed over to the secure world.
	198	*/
efd2b15c EB	199	static int qcom_scm_call(struct device dev, const struct qcom_scm_desc desc,
efd2b15c EB	200	struct qcom_scm_res *res)
b6a1dfbc	201	{
efd2b15c	202	u8 arglen = desc->arginfo & 0xf;
590e9280	203	int ret = 0, context_id;
efd2b15c	204	unsigned int i;
e0aa1539 EB	205	struct scm_legacy_command *cmd;
e0aa1539 EB	206	struct scm_legacy_response *rsp;
590e9280 EB	207	struct arm_smccc_args smc = {0};
590e9280 EB	208	struct arm_smccc_res smc_res;
efd2b15c EB	209	const size_t cmd_len = arglen * sizeof(__le32);
efd2b15c EB	210	const size_t resp_len = MAX_QCOM_SCM_RETS * sizeof(__le32);
16e59467 AG	211	size_t alloc_len = sizeof(cmd) + cmd_len + sizeof(rsp) + resp_len;
16e59467 AG	212	dma_addr_t cmd_phys;
efd2b15c EB	213	__le32 *arg_buf;
efd2b15c EB	214	const __le32 *res_buf;
b6a1dfbc	215
16e59467	216	cmd = kzalloc(PAGE_ALIGN(alloc_len), GFP_KERNEL);
b6a1dfbc KG	217	if (!cmd)
	218	return -ENOMEM;
	219
16e59467 AG	220	cmd->len = cpu_to_le32(alloc_len);
	221	cmd->buf_offset = cpu_to_le32(sizeof(*cmd));
	222	cmd->resp_hdr_offset = cpu_to_le32(sizeof(*cmd) + cmd_len);
efd2b15c	223	cmd->id = cpu_to_le32(SCM_LEGACY_FNID(desc->svc, desc->cmd));
16e59467	224
efd2b15c EB	225	arg_buf = scm_legacy_get_command_buffer(cmd);
	226	for (i = 0; i < arglen; i++)
	227	arg_buf[i] = cpu_to_le32(desc->args[i]);
b6a1dfbc	228
e0aa1539	229	rsp = scm_legacy_command_to_response(cmd);
16e59467 AG	230
	231	cmd_phys = dma_map_single(dev, cmd, alloc_len, DMA_TO_DEVICE);
	232	if (dma_mapping_error(dev, cmd_phys)) {
	233	kfree(cmd);
	234	return -ENOMEM;
	235	}
	236
590e9280 EB	237	smc.args[0] = 1;
	238	smc.args[1] = (unsigned long)&context_id;
	239	smc.args[2] = cmd_phys;
	240
b6a1dfbc	241	mutex_lock(&qcom_scm_lock);
590e9280 EB	242	__scm_legacy_do(&smc, &smc_res);
	243	if (smc_res.a0)
	244	ret = qcom_scm_remap_error(smc_res.a0);
b6a1dfbc KG	245	mutex_unlock(&qcom_scm_lock);
	246	if (ret)
	247	goto out;
	248
b6a1dfbc	249	do {
16e59467 AG	250	dma_sync_single_for_cpu(dev, cmd_phys + sizeof(*cmd) + cmd_len,
16e59467 AG	251	sizeof(*rsp), DMA_FROM_DEVICE);
b6a1dfbc KG	252	} while (!rsp->is_complete);
b6a1dfbc KG	253
efd2b15c EB	254	dma_sync_single_for_cpu(dev, cmd_phys + sizeof(*cmd) + cmd_len +
	255	le32_to_cpu(rsp->buf_offset),
	256	resp_len, DMA_FROM_DEVICE);
	257
	258	if (res) {
	259	res_buf = scm_legacy_get_response_buffer(rsp);
	260	for (i = 0; i < MAX_QCOM_SCM_RETS; i++)
	261	res->result[i] = le32_to_cpu(res_buf[i]);
16e59467	262	}
b6a1dfbc	263	out:
16e59467 AG	264	dma_unmap_single(dev, cmd_phys, alloc_len, DMA_TO_DEVICE);
16e59467 AG	265	kfree(cmd);
b6a1dfbc KG	266	return ret;
	267	}
	268
e0aa1539 EB	269	#define SCM_LEGACY_CLASS_REGISTER (0x2 << 8)
	270	#define SCM_LEGACY_MASK_IRQS BIT(5)
	271	#define SCM_LEGACY_ATOMIC_ID(svc, cmd, n) \
fd62c30b	272	((SCM_LEGACY_FNID(svc, cmd) << 12) \| \
e0aa1539 EB	273	SCM_LEGACY_CLASS_REGISTER \| \
e0aa1539 EB	274	SCM_LEGACY_MASK_IRQS \| \
b6a1dfbc KG	275	(n & 0xf))
	276
	277	/**
	278	* qcom_scm_call_atomic1() - Send an atomic SCM command with one argument
	279	* @svc_id: service identifier
	280	* @cmd_id: command identifier
	281	* @arg1: first argument
	282	*
	283	* This shall only be used with commands that are guaranteed to be
	284	* uninterruptable, atomic and SMP safe.
	285	*/
	286	static s32 qcom_scm_call_atomic1(u32 svc, u32 cmd, u32 arg1)
	287	{
	288	int context_id;
02248981 EB	289	struct arm_smccc_res res;
	290
	291	arm_smccc_smc(SCM_LEGACY_ATOMIC_ID(svc, cmd, 1),
	292	(unsigned long)&context_id, arg1, 0, 0, 0, 0, 0, &res);
b6a1dfbc	293
02248981	294	return res.a0;
b6a1dfbc KG	295	}
b6a1dfbc KG	296
13e77747 AG	297	/**
	298	* qcom_scm_call_atomic2() - Send an atomic SCM command with two arguments
	299	* @svc_id: service identifier
	300	* @cmd_id: command identifier
	301	* @arg1: first argument
	302	* @arg2: second argument
	303	*
	304	* This shall only be used with commands that are guaranteed to be
	305	* uninterruptable, atomic and SMP safe.
	306	*/
	307	static s32 qcom_scm_call_atomic2(u32 svc, u32 cmd, u32 arg1, u32 arg2)
	308	{
	309	int context_id;
02248981 EB	310	struct arm_smccc_res res;
	311
	312	arm_smccc_smc(SCM_LEGACY_ATOMIC_ID(svc, cmd, 2),
	313	(unsigned long)&context_id, arg1, 0, 0, 0, 0, 0, &res);
13e77747	314
02248981	315	return res.a0;
13e77747 AG	316	}
13e77747 AG	317
b6a1dfbc KG	318	/**
	319	* qcom_scm_set_cold_boot_addr() - Set the cold boot address for cpus
	320	* @entry: Entry point function for the cpus
	321	* @cpus: The cpumask of cpus that will use the entry point
	322	*
	323	* Set the cold boot address of the cpus. Any cpu outside the supported
	324	* range would be removed from the cpu present mask.
	325	*/
	326	int __qcom_scm_set_cold_boot_addr(void entry, const cpumask_t cpus)
	327	{
	328	int flags = 0;
	329	int cpu;
	330	int scm_cb_flags[] = {
	331	QCOM_SCM_FLAG_COLDBOOT_CPU0,
	332	QCOM_SCM_FLAG_COLDBOOT_CPU1,
	333	QCOM_SCM_FLAG_COLDBOOT_CPU2,
	334	QCOM_SCM_FLAG_COLDBOOT_CPU3,
	335	};
	336
	337	if (!cpus \|\| (cpus && cpumask_empty(cpus)))
	338	return -EINVAL;
	339
	340	for_each_cpu(cpu, cpus) {
	341	if (cpu < ARRAY_SIZE(scm_cb_flags))
	342	flags \|= scm_cb_flags[cpu];
	343	else
	344	set_cpu_present(cpu, false);
	345	}
	346
5443cc5f	347	return qcom_scm_call_atomic2(QCOM_SCM_SVC_BOOT, QCOM_SCM_BOOT_SET_ADDR,
13e77747	348	flags, virt_to_phys(entry));
b6a1dfbc KG	349	}
	350
	351	/**
	352	* qcom_scm_set_warm_boot_addr() - Set the warm boot address for cpus
	353	* @entry: Entry point function for the cpus
	354	* @cpus: The cpumask of cpus that will use the entry point
	355	*
	356	* Set the Linux entry point for the SCM to transfer control to when coming
	357	* out of a power down. CPU power down may be executed on cpuidle or hotplug.
	358	*/
16e59467 AG	359	int __qcom_scm_set_warm_boot_addr(struct device dev, void entry,
16e59467 AG	360	const cpumask_t *cpus)
b6a1dfbc KG	361	{
	362	int ret;
	363	int flags = 0;
	364	int cpu;
efd2b15c EB	365	struct qcom_scm_desc desc = {
	366	.svc = QCOM_SCM_SVC_BOOT,
	367	.cmd = QCOM_SCM_BOOT_SET_ADDR,
	368	};
b6a1dfbc KG	369
	370	/*
	371	* Reassign only if we are switching from hotplug entry point
	372	* to cpuidle entry point or vice versa.
	373	*/
	374	for_each_cpu(cpu, cpus) {
	375	if (entry == qcom_scm_wb[cpu].entry)
	376	continue;
	377	flags \|= qcom_scm_wb[cpu].flag;
	378	}
	379
	380	/* No change in entry function */
	381	if (!flags)
	382	return 0;
	383
efd2b15c EB	384	desc.args[0] = flags;
	385	desc.args[1] = virt_to_phys(entry);
	386	desc.arginfo = QCOM_SCM_ARGS(2);
	387
	388	ret = qcom_scm_call(dev, &desc, NULL);
b6a1dfbc KG	389	if (!ret) {
	390	for_each_cpu(cpu, cpus)
	391	qcom_scm_wb[cpu].entry = entry;
	392	}
	393
	394	return ret;
	395	}
	396
	397	/**
	398	* qcom_scm_cpu_power_down() - Power down the cpu
	399	* @flags - Flags to flush cache
	400	*
	401	* This is an end point to power down cpu. If there was a pending interrupt,
	402	* the control would return from this function, otherwise, the cpu jumps to the
	403	* warm boot entry point set for this cpu upon reset.
	404	*/
	405	void __qcom_scm_cpu_power_down(u32 flags)
	406	{
5443cc5f	407	qcom_scm_call_atomic1(QCOM_SCM_SVC_BOOT, QCOM_SCM_BOOT_TERMINATE_PC,
b6a1dfbc KG	408	flags & QCOM_SCM_FLUSH_FLAG_MASK);
b6a1dfbc KG	409	}
9626b699	410
16e59467	411	int __qcom_scm_is_call_available(struct device *dev, u32 svc_id, u32 cmd_id)
9626b699	412	{
9626b699	413	int ret;
efd2b15c EB	414	struct qcom_scm_desc desc = {
	415	.svc = QCOM_SCM_SVC_INFO,
	416	.cmd = QCOM_SCM_INFO_IS_CALL_AVAIL,
	417	.args[0] = SCM_LEGACY_FNID(svc_id, cmd_id),
	418	.arginfo = QCOM_SCM_ARGS(1),
	419	};
	420	struct qcom_scm_res res;
9626b699	421
efd2b15c	422	ret = qcom_scm_call(dev, &desc, &res);
9626b699	423
efd2b15c	424	return ret ? : res.result[0];
9626b699	425	}
9626b699	426
16e59467 AG	427	int __qcom_scm_hdcp_req(struct device dev, struct qcom_scm_hdcp_req req,
16e59467 AG	428	u32 req_cnt, u32 *resp)
9626b699	429	{
efd2b15c EB	430	int ret;
	431	struct qcom_scm_desc desc = {
	432	.svc = QCOM_SCM_SVC_HDCP,
	433	.cmd = QCOM_SCM_HDCP_INVOKE,
	434	};
	435	struct qcom_scm_res res;
	436
9626b699	437	if (req_cnt > QCOM_SCM_HDCP_MAX_REQ_CNT)
	438	return -ERANGE;
	439
efd2b15c EB	440	desc.args[0] = req[0].addr;
	441	desc.args[1] = req[0].val;
	442	desc.args[2] = req[1].addr;
	443	desc.args[3] = req[1].val;
	444	desc.args[4] = req[2].addr;
	445	desc.args[5] = req[2].val;
	446	desc.args[6] = req[3].addr;
	447	desc.args[7] = req[3].val;
	448	desc.args[8] = req[4].addr;
	449	desc.args[9] = req[4].val;
	450	desc.arginfo = QCOM_SCM_ARGS(10);
	451
	452	ret = qcom_scm_call(dev, &desc, &res);
	453	*resp = res.result[0];
	454
	455	return ret;
9626b699	456	}
6b1751a8	457
b0a1614f RC	458	int __qcom_scm_ocmem_lock(struct device *dev, u32 id, u32 offset, u32 size,
	459	u32 mode)
	460	{
efd2b15c EB	461	struct qcom_scm_desc desc = {
	462	.svc = QCOM_SCM_SVC_OCMEM,
	463	.cmd = QCOM_SCM_OCMEM_LOCK_CMD,
	464	};
	465
	466	desc.args[0] = id;
	467	desc.args[1] = offset;
	468	desc.args[2] = size;
	469	desc.args[3] = mode;
	470	desc.arginfo = QCOM_SCM_ARGS(4);
	471
	472	return qcom_scm_call(dev, &desc, NULL);
b0a1614f RC	473	}
	474
	475	int __qcom_scm_ocmem_unlock(struct device *dev, u32 id, u32 offset, u32 size)
	476	{
efd2b15c EB	477	struct qcom_scm_desc desc = {
	478	.svc = QCOM_SCM_SVC_OCMEM,
	479	.cmd = QCOM_SCM_OCMEM_UNLOCK_CMD,
	480	};
	481
	482	desc.args[0] = id;
	483	desc.args[1] = offset;
	484	desc.args[2] = size;
	485	desc.arginfo = QCOM_SCM_ARGS(3);
	486
	487	return qcom_scm_call(dev, &desc, NULL);
b0a1614f RC	488	}
b0a1614f RC	489
6b1751a8 KG	490	void __qcom_scm_init(void)
	491	{
	492	}
f01e90fe BA	493
	494	bool __qcom_scm_pas_supported(struct device *dev, u32 peripheral)
	495	{
f01e90fe	496	int ret;
efd2b15c EB	497	struct qcom_scm_desc desc = {
	498	.svc = QCOM_SCM_SVC_PIL,
	499	.cmd = QCOM_SCM_PIL_PAS_IS_SUPPORTED,
	500	};
	501	struct qcom_scm_res res;
	502
	503	desc.args[0] = peripheral;
	504	desc.arginfo = QCOM_SCM_ARGS(1);
f01e90fe	505
efd2b15c	506	ret = qcom_scm_call(dev, &desc, &res);
f01e90fe	507
efd2b15c	508	return ret ? false : !!res.result[0];
f01e90fe BA	509	}
	510
	511	int __qcom_scm_pas_init_image(struct device *dev, u32 peripheral,
	512	dma_addr_t metadata_phys)
	513	{
f01e90fe	514	int ret;
efd2b15c EB	515	struct qcom_scm_desc desc = {
	516	.svc = QCOM_SCM_SVC_PIL,
	517	.cmd = QCOM_SCM_PIL_PAS_INIT_IMAGE,
	518	};
	519	struct qcom_scm_res res;
f01e90fe	520
efd2b15c EB	521	desc.args[0] = peripheral;
	522	desc.args[1] = metadata_phys;
	523	desc.arginfo = QCOM_SCM_ARGS(2, QCOM_SCM_VAL, QCOM_SCM_RW);
f01e90fe	524
efd2b15c	525	ret = qcom_scm_call(dev, &desc, &res);
f01e90fe	526
efd2b15c	527	return ret ? : res.result[0];
f01e90fe BA	528	}
	529
	530	int __qcom_scm_pas_mem_setup(struct device *dev, u32 peripheral,
efd2b15c	531	phys_addr_t addr, phys_addr_t size)
f01e90fe	532	{
f01e90fe	533	int ret;
efd2b15c EB	534	struct qcom_scm_desc desc = {
	535	.svc = QCOM_SCM_SVC_PIL,
	536	.cmd = QCOM_SCM_PIL_PAS_MEM_SETUP,
	537	};
	538	struct qcom_scm_res res;
	539
	540	desc.args[0] = peripheral;
	541	desc.args[1] = addr;
	542	desc.args[2] = size;
	543	desc.arginfo = QCOM_SCM_ARGS(3);
	544
	545	ret = qcom_scm_call(dev, &desc, &res);
	546
	547	return ret ? : res.result[0];
f01e90fe BA	548	}
	549
	550	int __qcom_scm_pas_auth_and_reset(struct device *dev, u32 peripheral)
	551	{
f01e90fe	552	int ret;
efd2b15c EB	553	struct qcom_scm_desc desc = {
	554	.svc = QCOM_SCM_SVC_PIL,
	555	.cmd = QCOM_SCM_PIL_PAS_AUTH_AND_RESET,
	556	};
	557	struct qcom_scm_res res;
	558
	559	desc.args[0] = peripheral;
	560	desc.arginfo = QCOM_SCM_ARGS(1);
f01e90fe	561
efd2b15c	562	ret = qcom_scm_call(dev, &desc, &res);
f01e90fe	563
efd2b15c	564	return ret ? : res.result[0];
f01e90fe BA	565	}
	566
	567	int __qcom_scm_pas_shutdown(struct device *dev, u32 peripheral)
	568	{
f01e90fe	569	int ret;
efd2b15c EB	570	struct qcom_scm_desc desc = {
	571	.svc = QCOM_SCM_SVC_PIL,
	572	.cmd = QCOM_SCM_PIL_PAS_SHUTDOWN,
	573	};
	574	struct qcom_scm_res res;
	575
	576	desc.args[0] = peripheral;
	577	desc.arginfo = QCOM_SCM_ARGS(1);
f01e90fe	578
efd2b15c	579	ret = qcom_scm_call(dev, &desc, &res);
f01e90fe	580
efd2b15c	581	return ret ? : res.result[0];
f01e90fe	582	}
dd4fe5b2 BA	583
	584	int __qcom_scm_pas_mss_reset(struct device *dev, bool reset)
	585	{
efd2b15c EB	586	struct qcom_scm_desc desc = {
	587	.svc = QCOM_SCM_SVC_PIL,
	588	.cmd = QCOM_SCM_PIL_PAS_MSS_RESET,
	589	};
	590	struct qcom_scm_res res;
dd4fe5b2 BA	591	int ret;
dd4fe5b2 BA	592
efd2b15c EB	593	desc.args[0] = reset;
	594	desc.args[1] = 0;
	595	desc.arginfo = QCOM_SCM_ARGS(2);
dd4fe5b2	596
efd2b15c EB	597	ret = qcom_scm_call(dev, &desc, &res);
	598
	599	return ret ? : res.result[0];
dd4fe5b2	600	}
a811b420	601
8c1b7dc9 BA	602	int __qcom_scm_set_dload_mode(struct device *dev, bool enable)
8c1b7dc9 BA	603	{
5443cc5f EB	604	return qcom_scm_call_atomic2(QCOM_SCM_SVC_BOOT, QCOM_SCM_BOOT_SET_DLOAD_MODE,
5443cc5f EB	605	enable ? QCOM_SCM_BOOT_SET_DLOAD_MODE : 0, 0);
8c1b7dc9 BA	606	}
8c1b7dc9 BA	607
a811b420 AG	608	int __qcom_scm_set_remote_state(struct device *dev, u32 state, u32 id)
a811b420 AG	609	{
efd2b15c EB	610	struct qcom_scm_desc desc = {
	611	.svc = QCOM_SCM_SVC_BOOT,
	612	.cmd = QCOM_SCM_BOOT_SET_REMOTE_STATE,
	613	};
	614	struct qcom_scm_res res;
a811b420 AG	615	int ret;
a811b420 AG	616
efd2b15c EB	617	desc.args[0] = state;
efd2b15c EB	618	desc.args[1] = id;
a811b420	619
efd2b15c	620	ret = qcom_scm_call(dev, &desc, &res);
a811b420	621
efd2b15c	622	return ret ? : res.result[0];
a811b420	623	}
a2c680c6	624
d82bd359 AKD	625	int __qcom_scm_assign_mem(struct device *dev, phys_addr_t mem_region,
	626	size_t mem_sz, phys_addr_t src, size_t src_sz,
	627	phys_addr_t dest, size_t dest_sz)
	628	{
	629	return -ENODEV;
	630	}
	631
a2c680c6 RC	632	int __qcom_scm_restore_sec_cfg(struct device *dev, u32 device_id,
	633	u32 spare)
	634	{
efd2b15c EB	635	struct qcom_scm_desc desc = {
	636	.svc = QCOM_SCM_SVC_MP,
	637	.cmd = QCOM_SCM_MP_RESTORE_SEC_CFG,
	638	};
	639	struct qcom_scm_res res;
	640	int ret;
0434a406	641
efd2b15c EB	642	desc.args[0] = device_id;
	643	desc.args[1] = spare;
	644	desc.arginfo = QCOM_SCM_ARGS(2);
0434a406	645
efd2b15c	646	ret = qcom_scm_call(dev, &desc, &res);
0434a406	647
efd2b15c	648	return ret ? : res.result[0];
a2c680c6	649	}
b182cc4d SV	650
	651	int __qcom_scm_iommu_secure_ptbl_size(struct device *dev, u32 spare,
	652	size_t *size)
	653	{
	654	return -ENODEV;
	655	}
	656
	657	int __qcom_scm_iommu_secure_ptbl_init(struct device *dev, u64 addr, u32 size,
	658	u32 spare)
	659	{
	660	return -ENODEV;
	661	}
4e659dbe BA	662
	663	int __qcom_scm_io_readl(struct device *dev, phys_addr_t addr,
	664	unsigned int *val)
	665	{
	666	int ret;
	667
	668	ret = qcom_scm_call_atomic1(QCOM_SCM_SVC_IO, QCOM_SCM_IO_READ, addr);
	669	if (ret >= 0)
	670	*val = ret;
	671
	672	return ret < 0 ? ret : 0;
	673	}
	674
	675	int __qcom_scm_io_writel(struct device *dev, phys_addr_t addr, unsigned int val)
	676	{
	677	return qcom_scm_call_atomic2(QCOM_SCM_SVC_IO, QCOM_SCM_IO_WRITE,
	678	addr, val);
	679	}
5eb0e0e4 VG	680
	681	int __qcom_scm_qsmmu500_wait_safe_toggle(struct device *dev, bool enable)
	682	{
	683	return -ENODEV;
	684	}