[mirror_ubuntu-jammy-kernel.git] / drivers / firmware / qcom_scm-smc.c

// SPDX-License-Identifier: GPL-2.0-only
/* Copyright (c) 2015,2019 The Linux Foundation. All rights reserved.
 */

#include <linux/io.h>
#include <linux/errno.h>
#include <linux/delay.h>
#include <linux/mutex.h>
#include <linux/slab.h>
#include <linux/types.h>
#include <linux/qcom_scm.h>
#include <linux/arm-smccc.h>
#include <linux/dma-mapping.h>

#include "qcom_scm.h"

/**
 * struct arm_smccc_args
 * @args:	The array of values used in registers in smc instruction
 */
struct arm_smccc_args {
	unsigned long args[8];
};

static DEFINE_MUTEX(qcom_scm_lock);

#define QCOM_SCM_EBUSY_WAIT_MS 30
#define QCOM_SCM_EBUSY_MAX_RETRY 20

#define SCM_SMC_N_REG_ARGS	4
#define SCM_SMC_FIRST_EXT_IDX	(SCM_SMC_N_REG_ARGS - 1)
#define SCM_SMC_N_EXT_ARGS	(MAX_QCOM_SCM_ARGS - SCM_SMC_N_REG_ARGS + 1)
#define SCM_SMC_FIRST_REG_IDX	2
#define SCM_SMC_LAST_REG_IDX	(SCM_SMC_FIRST_REG_IDX + SCM_SMC_N_REG_ARGS - 1)

static void __scm_smc_do_quirk(const struct arm_smccc_args *smc,
			       struct arm_smccc_res *res)
{
	unsigned long a0 = smc->args[0];
	struct arm_smccc_quirk quirk = { .id = ARM_SMCCC_QUIRK_QCOM_A6 };

	quirk.state.a6 = 0;

	do {
		arm_smccc_smc_quirk(a0, smc->args[1], smc->args[2],
				    smc->args[3], smc->args[4], smc->args[5],
				    quirk.state.a6, smc->args[7], res, &quirk);

		if (res->a0 == QCOM_SCM_INTERRUPTED)
			a0 = res->a0;

	} while (res->a0 == QCOM_SCM_INTERRUPTED);
}

static void __scm_smc_do(const struct arm_smccc_args *smc,
			 struct arm_smccc_res *res, bool atomic)
{
	int retry_count = 0;

	if (atomic) {
		__scm_smc_do_quirk(smc, res);
		return;
	}

	do {
		mutex_lock(&qcom_scm_lock);

		__scm_smc_do_quirk(smc, res);

		mutex_unlock(&qcom_scm_lock);

		if (res->a0 == QCOM_SCM_V2_EBUSY) {
			if (retry_count++ > QCOM_SCM_EBUSY_MAX_RETRY)
				break;
			msleep(QCOM_SCM_EBUSY_WAIT_MS);
		}
	}  while (res->a0 == QCOM_SCM_V2_EBUSY);
}


int __scm_smc_call(struct device *dev, const struct qcom_scm_desc *desc,
		   enum qcom_scm_convention qcom_convention,
		   struct qcom_scm_res *res, bool atomic)
{
	int arglen = desc->arginfo & 0xf;
	int i;
	dma_addr_t args_phys = 0;
	void *args_virt = NULL;
	size_t alloc_len;
	gfp_t flag = atomic ? GFP_ATOMIC : GFP_KERNEL;
	u32 smccc_call_type = atomic ? ARM_SMCCC_FAST_CALL : ARM_SMCCC_STD_CALL;
	u32 qcom_smccc_convention = (qcom_convention == SMC_CONVENTION_ARM_32) ?
				    ARM_SMCCC_SMC_32 : ARM_SMCCC_SMC_64;
	struct arm_smccc_res smc_res;
	struct arm_smccc_args smc = {0};

	smc.args[0] = ARM_SMCCC_CALL_VAL(
		smccc_call_type,
		qcom_smccc_convention,
		desc->owner,
		SCM_SMC_FNID(desc->svc, desc->cmd));
	smc.args[1] = desc->arginfo;
	for (i = 0; i < SCM_SMC_N_REG_ARGS; i++)
		smc.args[i + SCM_SMC_FIRST_REG_IDX] = desc->args[i];

	if (unlikely(arglen > SCM_SMC_N_REG_ARGS)) {
		alloc_len = SCM_SMC_N_EXT_ARGS * sizeof(u64);
		args_virt = kzalloc(PAGE_ALIGN(alloc_len), flag);

		if (!args_virt)
			return -ENOMEM;

		if (qcom_smccc_convention == ARM_SMCCC_SMC_32) {
			__le32 *args = args_virt;

			for (i = 0; i < SCM_SMC_N_EXT_ARGS; i++)
				args[i] = cpu_to_le32(desc->args[i +
						      SCM_SMC_FIRST_EXT_IDX]);
		} else {
			__le64 *args = args_virt;

			for (i = 0; i < SCM_SMC_N_EXT_ARGS; i++)
				args[i] = cpu_to_le64(desc->args[i +
						      SCM_SMC_FIRST_EXT_IDX]);
		}

		args_phys = dma_map_single(dev, args_virt, alloc_len,
					   DMA_TO_DEVICE);

		if (dma_mapping_error(dev, args_phys)) {
			kfree(args_virt);
			return -ENOMEM;
		}

		smc.args[SCM_SMC_LAST_REG_IDX] = args_phys;
	}

	__scm_smc_do(&smc, &smc_res, atomic);

	if (args_virt) {
		dma_unmap_single(dev, args_phys, alloc_len, DMA_TO_DEVICE);
		kfree(args_virt);
	}

	if (res) {
		res->result[0] = smc_res.a1;
		res->result[1] = smc_res.a2;
		res->result[2] = smc_res.a3;
	}

	return (long)smc_res.a0 ? qcom_scm_remap_error(smc_res.a0) : 0;

}
Commit	Line	Data
97fb5e8d	1	// SPDX-License-Identifier: GPL-2.0-only
e0aa1539	2	/* Copyright (c) 2015,2019 The Linux Foundation. All rights reserved.
50b956f3 AG	3	*/
	4
	5	#include <linux/io.h>
	6	#include <linux/errno.h>
6b1751a8 KG	7	#include <linux/delay.h>
	8	#include <linux/mutex.h>
	9	#include <linux/slab.h>
	10	#include <linux/types.h>
50b956f3	11	#include <linux/qcom_scm.h>
6b1751a8 KG	12	#include <linux/arm-smccc.h>
	13	#include <linux/dma-mapping.h>
	14
	15	#include "qcom_scm.h"
	16
3f951ea6 EB	17	/**
	18	* struct arm_smccc_args
	19	* @args: The array of values used in registers in smc instruction
	20	*/
	21	struct arm_smccc_args {
	22	unsigned long args[8];
	23	};
	24
6b1751a8 KG	25	static DEFINE_MUTEX(qcom_scm_lock);
	26
	27	#define QCOM_SCM_EBUSY_WAIT_MS 30
	28	#define QCOM_SCM_EBUSY_MAX_RETRY 20
	29
4a9f1e13 EB	30	#define SCM_SMC_N_REG_ARGS 4
	31	#define SCM_SMC_FIRST_EXT_IDX (SCM_SMC_N_REG_ARGS - 1)
	32	#define SCM_SMC_N_EXT_ARGS (MAX_QCOM_SCM_ARGS - SCM_SMC_N_REG_ARGS + 1)
3f951ea6 EB	33	#define SCM_SMC_FIRST_REG_IDX 2
3f951ea6 EB	34	#define SCM_SMC_LAST_REG_IDX (SCM_SMC_FIRST_REG_IDX + SCM_SMC_N_REG_ARGS - 1)
6b1751a8	35
3f951ea6 EB	36	static void __scm_smc_do_quirk(const struct arm_smccc_args *smc,
3f951ea6 EB	37	struct arm_smccc_res *res)
1a5ea3b7	38	{
3f951ea6	39	unsigned long a0 = smc->args[0];
1a5ea3b7 VG	40	struct arm_smccc_quirk quirk = { .id = ARM_SMCCC_QUIRK_QCOM_A6 };
1a5ea3b7 VG	41
1a5ea3b7 VG	42	quirk.state.a6 = 0;
	43
	44	do {
3f951ea6 EB	45	arm_smccc_smc_quirk(a0, smc->args[1], smc->args[2],
	46	smc->args[3], smc->args[4], smc->args[5],
	47	quirk.state.a6, smc->args[7], res, &quirk);
1a5ea3b7 VG	48
1a5ea3b7 VG	49	if (res->a0 == QCOM_SCM_INTERRUPTED)
3f951ea6	50	a0 = res->a0;
1a5ea3b7 VG	51
	52	} while (res->a0 == QCOM_SCM_INTERRUPTED);
	53	}
	54
3f951ea6 EB	55	static void __scm_smc_do(const struct arm_smccc_args *smc,
3f951ea6 EB	56	struct arm_smccc_res *res, bool atomic)
1a5ea3b7 VG	57	{
	58	int retry_count = 0;
	59
	60	if (atomic) {
3f951ea6	61	__scm_smc_do_quirk(smc, res);
1a5ea3b7 VG	62	return;
	63	}
	64
	65	do {
	66	mutex_lock(&qcom_scm_lock);
	67
3f951ea6	68	__scm_smc_do_quirk(smc, res);
1a5ea3b7 VG	69
	70	mutex_unlock(&qcom_scm_lock);
	71
	72	if (res->a0 == QCOM_SCM_V2_EBUSY) {
	73	if (retry_count++ > QCOM_SCM_EBUSY_MAX_RETRY)
	74	break;
	75	msleep(QCOM_SCM_EBUSY_WAIT_MS);
	76	}
	77	} while (res->a0 == QCOM_SCM_V2_EBUSY);
	78	}
	79
f6ea568f SB	80
	81	int __scm_smc_call(struct device dev, const struct qcom_scm_desc desc,
	82	enum qcom_scm_convention qcom_convention,
	83	struct qcom_scm_res *res, bool atomic)
6b1751a8 KG	84	{
6b1751a8 KG	85	int arglen = desc->arginfo & 0xf;
1a5ea3b7	86	int i;
6b1751a8 KG	87	dma_addr_t args_phys = 0;
	88	void *args_virt = NULL;
	89	size_t alloc_len;
1a5ea3b7	90	gfp_t flag = atomic ? GFP_ATOMIC : GFP_KERNEL;
3f951ea6	91	u32 smccc_call_type = atomic ? ARM_SMCCC_FAST_CALL : ARM_SMCCC_STD_CALL;
f6ea568f SB	92	u32 qcom_smccc_convention = (qcom_convention == SMC_CONVENTION_ARM_32) ?
f6ea568f SB	93	ARM_SMCCC_SMC_32 : ARM_SMCCC_SMC_64;
1f7166fd	94	struct arm_smccc_res smc_res;
3f951ea6 EB	95	struct arm_smccc_args smc = {0};
	96
	97	smc.args[0] = ARM_SMCCC_CALL_VAL(
	98	smccc_call_type,
	99	qcom_smccc_convention,
	100	desc->owner,
	101	SCM_SMC_FNID(desc->svc, desc->cmd));
	102	smc.args[1] = desc->arginfo;
	103	for (i = 0; i < SCM_SMC_N_REG_ARGS; i++)
	104	smc.args[i + SCM_SMC_FIRST_REG_IDX] = desc->args[i];
6b1751a8	105
e0aa1539 EB	106	if (unlikely(arglen > SCM_SMC_N_REG_ARGS)) {
e0aa1539 EB	107	alloc_len = SCM_SMC_N_EXT_ARGS * sizeof(u64);
1a5ea3b7	108	args_virt = kzalloc(PAGE_ALIGN(alloc_len), flag);
6b1751a8 KG	109
	110	if (!args_virt)
	111	return -ENOMEM;
	112
	113	if (qcom_smccc_convention == ARM_SMCCC_SMC_32) {
	114	__le32 *args = args_virt;
	115
e0aa1539	116	for (i = 0; i < SCM_SMC_N_EXT_ARGS; i++)
6b1751a8	117	args[i] = cpu_to_le32(desc->args[i +
e0aa1539	118	SCM_SMC_FIRST_EXT_IDX]);
6b1751a8 KG	119	} else {
	120	__le64 *args = args_virt;
	121
e0aa1539	122	for (i = 0; i < SCM_SMC_N_EXT_ARGS; i++)
6b1751a8	123	args[i] = cpu_to_le64(desc->args[i +
e0aa1539	124	SCM_SMC_FIRST_EXT_IDX]);
6b1751a8 KG	125	}
	126
	127	args_phys = dma_map_single(dev, args_virt, alloc_len,
	128	DMA_TO_DEVICE);
	129
	130	if (dma_mapping_error(dev, args_phys)) {
	131	kfree(args_virt);
	132	return -ENOMEM;
	133	}
	134
3f951ea6	135	smc.args[SCM_SMC_LAST_REG_IDX] = args_phys;
6b1751a8 KG	136	}
6b1751a8 KG	137
3f951ea6	138	__scm_smc_do(&smc, &smc_res, atomic);
6b1751a8 KG	139
	140	if (args_virt) {
	141	dma_unmap_single(dev, args_phys, alloc_len, DMA_TO_DEVICE);
	142	kfree(args_virt);
	143	}
	144
1f7166fd EB	145	if (res) {
	146	res->result[0] = smc_res.a1;
	147	res->result[1] = smc_res.a2;
	148	res->result[2] = smc_res.a3;
	149	}
6b1751a8	150
1f7166fd	151	return (long)smc_res.a0 ? qcom_scm_remap_error(smc_res.a0) : 0;
f6ea568f	152
6b1751a8	153	}