projects / mirror_ubuntu-artful-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| 9626b699 | 1 | /* Copyright (c) 2010-2015, The Linux Foundation. All rights reserved. |
| b6a1dfbc KG |
2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify | |
| 4 | * it under the terms of the GNU General Public License version 2 and | |
| 5 | * only version 2 as published by the Free Software Foundation. | |
| 6 | * | |
| 7 | * This program is distributed in the hope that it will be useful, | |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 10 | * GNU General Public License for more details. | |
| 11 | */ | |
| 12 | #ifndef __QCOM_SCM_INT_H | |
| 13 | #define __QCOM_SCM_INT_H | |
| 14 | ||
| 15 | #define QCOM_SCM_SVC_BOOT 0x1 | |
| 16 | #define QCOM_SCM_BOOT_ADDR 0x1 | |
| 17 | #define QCOM_SCM_BOOT_ADDR_MC 0x11 | |
| 18 | ||
| 19 | #define QCOM_SCM_FLAG_HLOS 0x01 | |
| 20 | #define QCOM_SCM_FLAG_COLDBOOT_MC 0x02 | |
| 21 | #define QCOM_SCM_FLAG_WARMBOOT_MC 0x04 | |
| 16e59467 AG |
22 | extern int __qcom_scm_set_warm_boot_addr(struct device *dev, void *entry, |
| 23 | const cpumask_t *cpus); | |
| b6a1dfbc KG |
24 | extern int __qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus); |
| 25 | ||
| 26 | #define QCOM_SCM_CMD_TERMINATE_PC 0x2 | |
| 27 | #define QCOM_SCM_FLUSH_FLAG_MASK 0x3 | |
| 28 | #define QCOM_SCM_CMD_CORE_HOTPLUGGED 0x10 | |
| 29 | extern void __qcom_scm_cpu_power_down(u32 flags); | |
| 30 | ||
| 9626b699 | 31 | #define QCOM_SCM_SVC_INFO 0x6 |
| 32 | #define QCOM_IS_CALL_AVAIL_CMD 0x1 | |
| 16e59467 AG |
33 | extern int __qcom_scm_is_call_available(struct device *dev, u32 svc_id, |
| 34 | u32 cmd_id); | |
| 9626b699 | 35 | |
| 36 | #define QCOM_SCM_SVC_HDCP 0x11 | |
| 37 | #define QCOM_SCM_CMD_HDCP 0x01 | |
| 16e59467 AG |
38 | extern int __qcom_scm_hdcp_req(struct device *dev, |
| 39 | struct qcom_scm_hdcp_req *req, u32 req_cnt, u32 *resp); | |
| 9626b699 | 40 | |
| 6b1751a8 KG |
41 | extern void __qcom_scm_init(void); |
| 42 | ||
| f01e90fe BA |
43 | #define QCOM_SCM_SVC_PIL 0x2 |
| 44 | #define QCOM_SCM_PAS_INIT_IMAGE_CMD 0x1 | |
| 45 | #define QCOM_SCM_PAS_MEM_SETUP_CMD 0x2 | |
| 46 | #define QCOM_SCM_PAS_AUTH_AND_RESET_CMD 0x5 | |
| 47 | #define QCOM_SCM_PAS_SHUTDOWN_CMD 0x6 | |
| 48 | #define QCOM_SCM_PAS_IS_SUPPORTED_CMD 0x7 | |
| dd4fe5b2 | 49 | #define QCOM_SCM_PAS_MSS_RESET 0xa |
| f01e90fe BA |
50 | extern bool __qcom_scm_pas_supported(struct device *dev, u32 peripheral); |
| 51 | extern int __qcom_scm_pas_init_image(struct device *dev, u32 peripheral, | |
| 52 | dma_addr_t metadata_phys); | |
| 53 | extern int __qcom_scm_pas_mem_setup(struct device *dev, u32 peripheral, | |
| 54 | phys_addr_t addr, phys_addr_t size); | |
| 55 | extern int __qcom_scm_pas_auth_and_reset(struct device *dev, u32 peripheral); | |
| 56 | extern int __qcom_scm_pas_shutdown(struct device *dev, u32 peripheral); | |
| dd4fe5b2 | 57 | extern int __qcom_scm_pas_mss_reset(struct device *dev, bool reset); |
| f01e90fe | 58 | |
| b6a1dfbc | 59 | /* common error codes */ |
| 6b1751a8 | 60 | #define QCOM_SCM_V2_EBUSY -12 |
| b6a1dfbc KG |
61 | #define QCOM_SCM_ENOMEM -5 |
| 62 | #define QCOM_SCM_EOPNOTSUPP -4 | |
| 63 | #define QCOM_SCM_EINVAL_ADDR -3 | |
| 64 | #define QCOM_SCM_EINVAL_ARG -2 | |
| 65 | #define QCOM_SCM_ERROR -1 | |
| 66 | #define QCOM_SCM_INTERRUPTED 1 | |
| 67 | ||
| 11bdcee4 AG |
68 | static inline int qcom_scm_remap_error(int err) |
| 69 | { | |
| 70 | switch (err) { | |
| 71 | case QCOM_SCM_ERROR: | |
| 72 | return -EIO; | |
| 73 | case QCOM_SCM_EINVAL_ADDR: | |
| 74 | case QCOM_SCM_EINVAL_ARG: | |
| 75 | return -EINVAL; | |
| 76 | case QCOM_SCM_EOPNOTSUPP: | |
| 77 | return -EOPNOTSUPP; | |
| 78 | case QCOM_SCM_ENOMEM: | |
| 79 | return -ENOMEM; | |
| 6b1751a8 KG |
80 | case QCOM_SCM_V2_EBUSY: |
| 81 | return -EBUSY; | |
| 11bdcee4 AG |
82 | } |
| 83 | return -EINVAL; | |
| 84 | } | |
| 85 | ||
| b6a1dfbc | 86 | #endif |