[mirror_ubuntu-hirsute-kernel.git] / drivers / firmware / trusted_foundations.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Trusted Foundations support for ARM CPUs
 *
 * Copyright (c) 2013, NVIDIA Corporation.
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/of.h>

#include <linux/firmware/trusted_foundations.h>

#include <asm/firmware.h>
#include <asm/hardware/cache-l2x0.h>
#include <asm/outercache.h>

#define TF_CACHE_MAINT		0xfffff100

#define TF_CACHE_ENABLE		1
#define TF_CACHE_DISABLE	2
#define TF_CACHE_REENABLE	4

#define TF_SET_CPU_BOOT_ADDR_SMC 0xfffff200

#define TF_CPU_PM		0xfffffffc
#define TF_CPU_PM_S3		0xffffffe3
#define TF_CPU_PM_S2		0xffffffe6
#define TF_CPU_PM_S2_NO_MC_CLK	0xffffffe5
#define TF_CPU_PM_S1		0xffffffe4
#define TF_CPU_PM_S1_NOFLUSH_L2	0xffffffe7

static unsigned long tf_idle_mode = TF_PM_MODE_NONE;
static unsigned long cpu_boot_addr;

static void tf_generic_smc(u32 type, u32 arg1, u32 arg2)
{
	register u32 r0 asm("r0") = type;
	register u32 r1 asm("r1") = arg1;
	register u32 r2 asm("r2") = arg2;

	asm volatile(
		".arch_extension	sec\n\t"
		"stmfd	sp!, {r4 - r11}\n\t"
		__asmeq("%0", "r0")
		__asmeq("%1", "r1")
		__asmeq("%2", "r2")
		"mov	r3, #0\n\t"
		"mov	r4, #0\n\t"
		"smc	#0\n\t"
		"ldmfd	sp!, {r4 - r11}\n\t"
		:
		: "r" (r0), "r" (r1), "r" (r2)
		: "memory", "r3", "r12", "lr");
}

static int tf_set_cpu_boot_addr(int cpu, unsigned long boot_addr)
{
	cpu_boot_addr = boot_addr;
	tf_generic_smc(TF_SET_CPU_BOOT_ADDR_SMC, cpu_boot_addr, 0);

	return 0;
}

static int tf_prepare_idle(unsigned long mode)
{
	switch (mode) {
	case TF_PM_MODE_LP0:
		tf_generic_smc(TF_CPU_PM, TF_CPU_PM_S3, cpu_boot_addr);
		break;

	case TF_PM_MODE_LP1:
		tf_generic_smc(TF_CPU_PM, TF_CPU_PM_S2, cpu_boot_addr);
		break;

	case TF_PM_MODE_LP1_NO_MC_CLK:
		tf_generic_smc(TF_CPU_PM, TF_CPU_PM_S2_NO_MC_CLK,
			       cpu_boot_addr);
		break;

	case TF_PM_MODE_LP2:
		tf_generic_smc(TF_CPU_PM, TF_CPU_PM_S1, cpu_boot_addr);
		break;

	case TF_PM_MODE_LP2_NOFLUSH_L2:
		tf_generic_smc(TF_CPU_PM, TF_CPU_PM_S1_NOFLUSH_L2,
			       cpu_boot_addr);
		break;

	case TF_PM_MODE_NONE:
		break;

	default:
		return -EINVAL;
	}

	tf_idle_mode = mode;

	return 0;
}

#ifdef CONFIG_CACHE_L2X0
static void tf_cache_write_sec(unsigned long val, unsigned int reg)
{
	u32 enable_op, l2x0_way_mask = 0xff;

	switch (reg) {
	case L2X0_CTRL:
		if (l2x0_saved_regs.aux_ctrl & L310_AUX_CTRL_ASSOCIATIVITY_16)
			l2x0_way_mask = 0xffff;

		switch (tf_idle_mode) {
		case TF_PM_MODE_LP2:
			enable_op = TF_CACHE_REENABLE;
			break;

		default:
			enable_op = TF_CACHE_ENABLE;
			break;
		}

		if (val == L2X0_CTRL_EN)
			tf_generic_smc(TF_CACHE_MAINT, enable_op,
				       l2x0_saved_regs.aux_ctrl);
		else
			tf_generic_smc(TF_CACHE_MAINT, TF_CACHE_DISABLE,
				       l2x0_way_mask);
		break;

	default:
		break;
	}
}

static int tf_init_cache(void)
{
	outer_cache.write_sec = tf_cache_write_sec;

	return 0;
}
#endif /* CONFIG_CACHE_L2X0 */

static const struct firmware_ops trusted_foundations_ops = {
	.set_cpu_boot_addr = tf_set_cpu_boot_addr,
	.prepare_idle = tf_prepare_idle,
#ifdef CONFIG_CACHE_L2X0
	.l2x0_init = tf_init_cache,
#endif
};

void register_trusted_foundations(struct trusted_foundations_platform_data *pd)
{
	/*
	 * we are not using version information for now since currently
	 * supported SMCs are compatible with all TF releases
	 */
	register_firmware_ops(&trusted_foundations_ops);
}

void of_register_trusted_foundations(void)
{
	struct device_node *node;
	struct trusted_foundations_platform_data pdata;
	int err;

	node = of_find_compatible_node(NULL, NULL, "tlm,trusted-foundations");
	if (!node)
		return;

	err = of_property_read_u32(node, "tlm,version-major",
				   &pdata.version_major);
	if (err != 0)
		panic("Trusted Foundation: missing version-major property\n");
	err = of_property_read_u32(node, "tlm,version-minor",
				   &pdata.version_minor);
	if (err != 0)
		panic("Trusted Foundation: missing version-minor property\n");
	register_trusted_foundations(&pdata);
}

bool trusted_foundations_registered(void)
{
	return firmware_ops == &trusted_foundations_ops;
}
Commit	Line	Data
c942fddf	1	// SPDX-License-Identifier: GPL-2.0-or-later
d9a1beaa AC	2	/*
	3	* Trusted Foundations support for ARM CPUs
	4	*
	5	* Copyright (c) 2013, NVIDIA Corporation.
d9a1beaa AC	6	*/
	7
	8	#include <linux/kernel.h>
	9	#include <linux/init.h>
	10	#include <linux/of.h>
4cb5d9ec TR	11
	12	#include <linux/firmware/trusted_foundations.h>
	13
d9a1beaa	14	#include <asm/firmware.h>
ebca2a6e DO	15	#include <asm/hardware/cache-l2x0.h>
ebca2a6e DO	16	#include <asm/outercache.h>
d9a1beaa	17
ebca2a6e DO	18	#define TF_CACHE_MAINT 0xfffff100
	19
	20	#define TF_CACHE_ENABLE 1
	21	#define TF_CACHE_DISABLE 2
b720aaa3	22	#define TF_CACHE_REENABLE 4
ebca2a6e	23
d9a1beaa AC	24	#define TF_SET_CPU_BOOT_ADDR_SMC 0xfffff200
d9a1beaa AC	25
b77b6e88 AC	26	#define TF_CPU_PM 0xfffffffc
	27	#define TF_CPU_PM_S3 0xffffffe3
	28	#define TF_CPU_PM_S2 0xffffffe6
	29	#define TF_CPU_PM_S2_NO_MC_CLK 0xffffffe5
	30	#define TF_CPU_PM_S1 0xffffffe4
	31	#define TF_CPU_PM_S1_NOFLUSH_L2 0xffffffe7
	32
b720aaa3	33	static unsigned long tf_idle_mode = TF_PM_MODE_NONE;
b77b6e88 AC	34	static unsigned long cpu_boot_addr;
b77b6e88 AC	35
4ea7bdc6	36	static void tf_generic_smc(u32 type, u32 arg1, u32 arg2)
d9a1beaa	37	{
4ea7bdc6 SA	38	register u32 r0 asm("r0") = type;
	39	register u32 r1 asm("r1") = arg1;
	40	register u32 r2 asm("r2") = arg2;
	41
d9a1beaa AC	42	asm volatile(
d9a1beaa AC	43	".arch_extension sec\n\t"
4ea7bdc6	44	"stmfd sp!, {r4 - r11}\n\t"
d9a1beaa AC	45	__asmeq("%0", "r0")
	46	__asmeq("%1", "r1")
	47	__asmeq("%2", "r2")
	48	"mov r3, #0\n\t"
	49	"mov r4, #0\n\t"
	50	"smc #0\n\t"
4ea7bdc6	51	"ldmfd sp!, {r4 - r11}\n\t"
d9a1beaa	52	:
4ea7bdc6 SA	53	: "r" (r0), "r" (r1), "r" (r2)
4ea7bdc6 SA	54	: "memory", "r3", "r12", "lr");
d9a1beaa AC	55	}
	56
	57	static int tf_set_cpu_boot_addr(int cpu, unsigned long boot_addr)
	58	{
b77b6e88 AC	59	cpu_boot_addr = boot_addr;
	60	tf_generic_smc(TF_SET_CPU_BOOT_ADDR_SMC, cpu_boot_addr, 0);
	61
	62	return 0;
	63	}
	64
96446e21	65	static int tf_prepare_idle(unsigned long mode)
b77b6e88	66	{
96446e21 DO	67	switch (mode) {
	68	case TF_PM_MODE_LP0:
	69	tf_generic_smc(TF_CPU_PM, TF_CPU_PM_S3, cpu_boot_addr);
	70	break;
	71
	72	case TF_PM_MODE_LP1:
	73	tf_generic_smc(TF_CPU_PM, TF_CPU_PM_S2, cpu_boot_addr);
	74	break;
	75
	76	case TF_PM_MODE_LP1_NO_MC_CLK:
	77	tf_generic_smc(TF_CPU_PM, TF_CPU_PM_S2_NO_MC_CLK,
	78	cpu_boot_addr);
	79	break;
	80
	81	case TF_PM_MODE_LP2:
	82	tf_generic_smc(TF_CPU_PM, TF_CPU_PM_S1, cpu_boot_addr);
	83	break;
	84
	85	case TF_PM_MODE_LP2_NOFLUSH_L2:
	86	tf_generic_smc(TF_CPU_PM, TF_CPU_PM_S1_NOFLUSH_L2,
	87	cpu_boot_addr);
	88	break;
	89
b720aaa3 DO	90	case TF_PM_MODE_NONE:
	91	break;
	92
96446e21 DO	93	default:
	94	return -EINVAL;
	95	}
d9a1beaa	96
b720aaa3 DO	97	tf_idle_mode = mode;
b720aaa3 DO	98
d9a1beaa AC	99	return 0;
	100	}
	101
ebca2a6e DO	102	#ifdef CONFIG_CACHE_L2X0
	103	static void tf_cache_write_sec(unsigned long val, unsigned int reg)
	104	{
b720aaa3	105	u32 enable_op, l2x0_way_mask = 0xff;
ebca2a6e DO	106
	107	switch (reg) {
	108	case L2X0_CTRL:
	109	if (l2x0_saved_regs.aux_ctrl & L310_AUX_CTRL_ASSOCIATIVITY_16)
	110	l2x0_way_mask = 0xffff;
	111
b720aaa3 DO	112	switch (tf_idle_mode) {
	113	case TF_PM_MODE_LP2:
	114	enable_op = TF_CACHE_REENABLE;
	115	break;
	116
	117	default:
	118	enable_op = TF_CACHE_ENABLE;
	119	break;
	120	}
	121
ebca2a6e	122	if (val == L2X0_CTRL_EN)
b720aaa3	123	tf_generic_smc(TF_CACHE_MAINT, enable_op,
ebca2a6e DO	124	l2x0_saved_regs.aux_ctrl);
	125	else
	126	tf_generic_smc(TF_CACHE_MAINT, TF_CACHE_DISABLE,
	127	l2x0_way_mask);
	128	break;
	129
	130	default:
	131	break;
	132	}
	133	}
	134
	135	static int tf_init_cache(void)
	136	{
	137	outer_cache.write_sec = tf_cache_write_sec;
	138
	139	return 0;
	140	}
	141	#endif /* CONFIG_CACHE_L2X0 */
	142
d9a1beaa AC	143	static const struct firmware_ops trusted_foundations_ops = {
d9a1beaa AC	144	.set_cpu_boot_addr = tf_set_cpu_boot_addr,
b77b6e88	145	.prepare_idle = tf_prepare_idle,
ebca2a6e DO	146	#ifdef CONFIG_CACHE_L2X0
	147	.l2x0_init = tf_init_cache,
	148	#endif
d9a1beaa AC	149	};
	150
	151	void register_trusted_foundations(struct trusted_foundations_platform_data *pd)
	152	{
	153	/*
	154	* we are not using version information for now since currently
	155	* supported SMCs are compatible with all TF releases
	156	*/
	157	register_firmware_ops(&trusted_foundations_ops);
	158	}
	159
	160	void of_register_trusted_foundations(void)
	161	{
	162	struct device_node *node;
	163	struct trusted_foundations_platform_data pdata;
	164	int err;
	165
	166	node = of_find_compatible_node(NULL, NULL, "tlm,trusted-foundations");
	167	if (!node)
	168	return;
	169
	170	err = of_property_read_u32(node, "tlm,version-major",
	171	&pdata.version_major);
	172	if (err != 0)
	173	panic("Trusted Foundation: missing version-major property\n");
	174	err = of_property_read_u32(node, "tlm,version-minor",
	175	&pdata.version_minor);
	176	if (err != 0)
	177	panic("Trusted Foundation: missing version-minor property\n");
	178	register_trusted_foundations(&pdata);
	179	}
ebc7c1a2 DO	180
	181	bool trusted_foundations_registered(void)
	182	{
	183	return firmware_ops == &trusted_foundations_ops;
	184	}