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Commit | Line | Data |
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ec8f24b7 | 1 | # SPDX-License-Identifier: GPL-2.0-only |
6a8c3be7 AT |
2 | # |
3 | # FPGA framework configuration | |
4 | # | |
5 | ||
50fa0285 | 6 | menuconfig FPGA |
6a8c3be7 AT |
7 | tristate "FPGA Configuration Framework" |
8 | help | |
9 | Say Y here if you want support for configuring FPGAs from the | |
10 | kernel. The FPGA framework adds a FPGA manager class and FPGA | |
11 | manager drivers. | |
12 | ||
fab6266e AT |
13 | if FPGA |
14 | ||
84e93f1d AT |
15 | config FPGA_MGR_SOCFPGA |
16 | tristate "Altera SOCFPGA FPGA Manager" | |
17 | depends on ARCH_SOCFPGA || COMPILE_TEST | |
0fa20cdf | 18 | help |
84e93f1d | 19 | FPGA manager driver support for Altera SOCFPGA. |
ef3acdd8 | 20 | |
84e93f1d AT |
21 | config FPGA_MGR_SOCFPGA_A10 |
22 | tristate "Altera SoCFPGA Arria10" | |
23 | depends on ARCH_SOCFPGA || COMPILE_TEST | |
24 | select REGMAP_MMIO | |
ef3acdd8 | 25 | help |
84e93f1d | 26 | FPGA manager driver support for Altera Arria10 SoCFPGA. |
0fa20cdf | 27 | |
84e93f1d | 28 | config ALTERA_PR_IP_CORE |
786285f5 EW |
29 | tristate "Altera Partial Reconfiguration IP Core" |
30 | help | |
31 | Core driver support for Altera Partial Reconfiguration IP component | |
21f8ba2e | 32 | |
84e93f1d AT |
33 | config ALTERA_PR_IP_CORE_PLAT |
34 | tristate "Platform support of Altera Partial Reconfiguration IP Core" | |
35 | depends on ALTERA_PR_IP_CORE && OF && HAS_IOMEM | |
34d1dc17 | 36 | help |
84e93f1d AT |
37 | Platform driver support for Altera Partial Reconfiguration IP |
38 | component | |
34d1dc17 | 39 | |
5692fae0 JC |
40 | config FPGA_MGR_ALTERA_PS_SPI |
41 | tristate "Altera FPGA Passive Serial over SPI" | |
42 | depends on SPI | |
3d139703 | 43 | select BITREVERSE |
5692fae0 JC |
44 | help |
45 | FPGA manager driver support for Altera Arria/Cyclone/Stratix | |
46 | using the passive serial interface over SPI. | |
47 | ||
84e93f1d | 48 | config FPGA_MGR_ALTERA_CVP |
e5891517 | 49 | tristate "Altera CvP FPGA Manager" |
84e93f1d | 50 | depends on PCI |
acbb910a | 51 | help |
e5891517 TT |
52 | FPGA manager driver support for Arria-V, Cyclone-V, Stratix-V, |
53 | Arria 10 and Stratix10 Altera FPGAs using the CvP interface over PCIe. | |
acbb910a | 54 | |
84e93f1d AT |
55 | config FPGA_MGR_ZYNQ_FPGA |
56 | tristate "Xilinx Zynq FPGA" | |
57 | depends on ARCH_ZYNQ || COMPILE_TEST | |
4348f7e2 | 58 | help |
84e93f1d | 59 | FPGA manager driver support for Xilinx Zynq FPGAs. |
4348f7e2 | 60 | |
e7eef1d7 AT |
61 | config FPGA_MGR_STRATIX10_SOC |
62 | tristate "Intel Stratix10 SoC FPGA Manager" | |
63 | depends on (ARCH_STRATIX10 && INTEL_STRATIX10_SERVICE) | |
64 | help | |
65 | FPGA manager driver support for the Intel Stratix10 SoC. | |
66 | ||
061c97d1 AG |
67 | config FPGA_MGR_XILINX_SPI |
68 | tristate "Xilinx Configuration over Slave Serial (SPI)" | |
69 | depends on SPI | |
70 | help | |
71 | FPGA manager driver support for Xilinx FPGA configuration | |
72 | over slave serial interface. | |
73 | ||
84e93f1d AT |
74 | config FPGA_MGR_ICE40_SPI |
75 | tristate "Lattice iCE40 SPI" | |
76 | depends on OF && SPI | |
37784706 | 77 | help |
84e93f1d AT |
78 | FPGA manager driver support for Lattice iCE40 FPGAs over SPI. |
79 | ||
88fb3a00 PP |
80 | config FPGA_MGR_MACHXO2_SPI |
81 | tristate "Lattice MachXO2 SPI" | |
82 | depends on SPI | |
83 | help | |
84 | FPGA manager driver support for Lattice MachXO2 configuration | |
85 | over slave SPI interface. | |
86 | ||
84e93f1d AT |
87 | config FPGA_MGR_TS73XX |
88 | tristate "Technologic Systems TS-73xx SBC FPGA Manager" | |
89 | depends on ARCH_EP93XX && MACH_TS72XX | |
90 | help | |
91 | FPGA manager driver support for the Altera Cyclone II FPGA | |
92 | present on the TS-73xx SBC boards. | |
37784706 | 93 | |
21aeda95 AT |
94 | config FPGA_BRIDGE |
95 | tristate "FPGA Bridge Framework" | |
21aeda95 AT |
96 | help |
97 | Say Y here if you want to support bridges connected between host | |
98 | processors and FPGAs or between FPGAs. | |
99 | ||
e5f8efa5 AT |
100 | config SOCFPGA_FPGA_BRIDGE |
101 | tristate "Altera SoCFPGA FPGA Bridges" | |
102 | depends on ARCH_SOCFPGA && FPGA_BRIDGE | |
103 | help | |
104 | Say Y to enable drivers for FPGA bridges for Altera SOCFPGA | |
105 | devices. | |
106 | ||
ca24a648 AT |
107 | config ALTERA_FREEZE_BRIDGE |
108 | tristate "Altera FPGA Freeze Bridge" | |
38cd7ad5 | 109 | depends on FPGA_BRIDGE && HAS_IOMEM |
ca24a648 AT |
110 | help |
111 | Say Y to enable drivers for Altera FPGA Freeze bridges. A | |
112 | freeze bridge is a bridge that exists in the FPGA fabric to | |
113 | isolate one region of the FPGA from the busses while that | |
114 | region is being reprogrammed. | |
115 | ||
7e961c12 MF |
116 | config XILINX_PR_DECOUPLER |
117 | tristate "Xilinx LogiCORE PR Decoupler" | |
118 | depends on FPGA_BRIDGE | |
119 | depends on HAS_IOMEM | |
120 | help | |
121 | Say Y to enable drivers for Xilinx LogiCORE PR Decoupler. | |
122 | The PR Decoupler exists in the FPGA fabric to isolate one | |
123 | region of the FPGA from the busses while that region is | |
124 | being reprogrammed during partial reconfig. | |
125 | ||
84e93f1d AT |
126 | config FPGA_REGION |
127 | tristate "FPGA Region" | |
128 | depends on FPGA_BRIDGE | |
129 | help | |
130 | FPGA Region common code. A FPGA Region controls a FPGA Manager | |
131 | and the FPGA Bridges associated with either a reconfigurable | |
132 | region of an FPGA or a whole FPGA. | |
133 | ||
134 | config OF_FPGA_REGION | |
135 | tristate "FPGA Region Device Tree Overlay Support" | |
136 | depends on OF && FPGA_REGION | |
137 | help | |
138 | Support for loading FPGA images by applying a Device Tree | |
139 | overlay. | |
140 | ||
543be3d8 WH |
141 | config FPGA_DFL |
142 | tristate "FPGA Device Feature List (DFL) support" | |
143 | select FPGA_BRIDGE | |
144 | select FPGA_REGION | |
1a16af33 | 145 | depends on HAS_IOMEM |
543be3d8 WH |
146 | help |
147 | Device Feature List (DFL) defines a feature list structure that | |
148 | creates a linked list of feature headers within the MMIO space | |
149 | to provide an extensible way of adding features for FPGA. | |
150 | Driver can walk through the feature headers to enumerate feature | |
151 | devices (e.g. FPGA Management Engine, Port and Accelerator | |
152 | Function Unit) and their private features for target FPGA devices. | |
153 | ||
154 | Select this option to enable common support for Field-Programmable | |
155 | Gate Array (FPGA) solutions which implement Device Feature List. | |
156 | It provides enumeration APIs and feature device infrastructure. | |
157 | ||
322ddebe KL |
158 | config FPGA_DFL_FME |
159 | tristate "FPGA DFL FME Driver" | |
724142f8 | 160 | depends on FPGA_DFL && HWMON && PERF_EVENTS |
322ddebe KL |
161 | help |
162 | The FPGA Management Engine (FME) is a feature device implemented | |
163 | under Device Feature List (DFL) framework. Select this option to | |
164 | enable the platform device driver for FME which implements all | |
165 | FPGA platform level management features. There shall be one FME | |
166 | per DFL based FPGA device. | |
167 | ||
af275ec6 WH |
168 | config FPGA_DFL_FME_MGR |
169 | tristate "FPGA DFL FME Manager Driver" | |
170 | depends on FPGA_DFL_FME && HAS_IOMEM | |
171 | help | |
172 | Say Y to enable FPGA Manager driver for FPGA Management Engine. | |
173 | ||
de892dff WH |
174 | config FPGA_DFL_FME_BRIDGE |
175 | tristate "FPGA DFL FME Bridge Driver" | |
176 | depends on FPGA_DFL_FME && HAS_IOMEM | |
177 | help | |
178 | Say Y to enable FPGA Bridge driver for FPGA Management Engine. | |
179 | ||
bb61b9be WH |
180 | config FPGA_DFL_FME_REGION |
181 | tristate "FPGA DFL FME Region Driver" | |
182 | depends on FPGA_DFL_FME && HAS_IOMEM | |
183 | help | |
184 | Say Y to enable FPGA Region driver for FPGA Management Engine. | |
185 | ||
1a1527cf WH |
186 | config FPGA_DFL_AFU |
187 | tristate "FPGA DFL AFU Driver" | |
188 | depends on FPGA_DFL | |
189 | help | |
190 | This is the driver for FPGA Accelerated Function Unit (AFU) which | |
191 | implements AFU and Port management features. A User AFU connects | |
192 | to the FPGA infrastructure via a Port. There may be more than one | |
193 | Port/AFU per DFL based FPGA device. | |
194 | ||
72ddd9f3 ZY |
195 | config FPGA_DFL_PCI |
196 | tristate "FPGA DFL PCIe Device Driver" | |
197 | depends on PCI && FPGA_DFL | |
198 | help | |
199 | Select this option to enable PCIe driver for PCIe-based | |
200 | Field-Programmable Gate Array (FPGA) solutions which implement | |
201 | the Device Feature List (DFL). This driver provides interfaces | |
202 | for userspace applications to configure, enumerate, open and access | |
203 | FPGA accelerators on the FPGA DFL devices, enables system level | |
204 | management functions such as FPGA partial reconfiguration, power | |
205 | management and virtualization with DFL framework and DFL feature | |
206 | device drivers. | |
207 | ||
208 | To compile this as a module, choose M here. | |
209 | ||
c09f7471 NM |
210 | config FPGA_MGR_ZYNQMP_FPGA |
211 | tristate "Xilinx ZynqMP FPGA" | |
6a47d6ef | 212 | depends on ZYNQMP_FIRMWARE || (!ZYNQMP_FIRMWARE && COMPILE_TEST) |
c09f7471 NM |
213 | help |
214 | FPGA manager driver support for Xilinx ZynqMP FPGAs. | |
215 | This driver uses the processor configuration port(PCAP) | |
216 | to configure the programmable logic(PL) through PS | |
217 | on ZynqMP SoC. | |
218 | ||
fab6266e | 219 | endif # FPGA |