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Commit | Line | Data |
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6a8c3be7 AT |
1 | # |
2 | # FPGA framework configuration | |
3 | # | |
4 | ||
50fa0285 | 5 | menuconfig FPGA |
6a8c3be7 AT |
6 | tristate "FPGA Configuration Framework" |
7 | help | |
8 | Say Y here if you want support for configuring FPGAs from the | |
9 | kernel. The FPGA framework adds a FPGA manager class and FPGA | |
10 | manager drivers. | |
11 | ||
fab6266e AT |
12 | if FPGA |
13 | ||
0fa20cdf AT |
14 | config FPGA_REGION |
15 | tristate "FPGA Region" | |
16 | depends on OF && FPGA_BRIDGE | |
17 | help | |
18 | FPGA Regions allow loading FPGA images under control of | |
19 | the Device Tree. | |
20 | ||
21f8ba2e JH |
21 | config FPGA_MGR_ICE40_SPI |
22 | tristate "Lattice iCE40 SPI" | |
23 | depends on OF && SPI | |
24 | help | |
25 | FPGA manager driver support for Lattice iCE40 FPGAs over SPI. | |
26 | ||
34d1dc17 AG |
27 | config FPGA_MGR_ALTERA_CVP |
28 | tristate "Altera Arria-V/Cyclone-V/Stratix-V CvP FPGA Manager" | |
29 | depends on PCI | |
30 | help | |
31 | FPGA manager driver support for Arria-V, Cyclone-V, Stratix-V | |
32 | and Arria 10 Altera FPGAs using the CvP interface over PCIe. | |
33 | ||
5692fae0 JC |
34 | config FPGA_MGR_ALTERA_PS_SPI |
35 | tristate "Altera FPGA Passive Serial over SPI" | |
36 | depends on SPI | |
064e8a1b | 37 | select BITREVERSE |
5692fae0 JC |
38 | help |
39 | FPGA manager driver support for Altera Arria/Cyclone/Stratix | |
40 | using the passive serial interface over SPI. | |
41 | ||
fab6266e AT |
42 | config FPGA_MGR_SOCFPGA |
43 | tristate "Altera SOCFPGA FPGA Manager" | |
a0e1b618 | 44 | depends on ARCH_SOCFPGA || COMPILE_TEST |
fab6266e AT |
45 | help |
46 | FPGA manager driver support for Altera SOCFPGA. | |
47 | ||
acbb910a AT |
48 | config FPGA_MGR_SOCFPGA_A10 |
49 | tristate "Altera SoCFPGA Arria10" | |
a0e1b618 JG |
50 | depends on ARCH_SOCFPGA || COMPILE_TEST |
51 | select REGMAP_MMIO | |
acbb910a AT |
52 | help |
53 | FPGA manager driver support for Altera Arria10 SoCFPGA. | |
54 | ||
4348f7e2 FF |
55 | config FPGA_MGR_TS73XX |
56 | tristate "Technologic Systems TS-73xx SBC FPGA Manager" | |
57 | depends on ARCH_EP93XX && MACH_TS72XX | |
58 | help | |
59 | FPGA manager driver support for the Altera Cyclone II FPGA | |
60 | present on the TS-73xx SBC boards. | |
61 | ||
061c97d1 AG |
62 | config FPGA_MGR_XILINX_SPI |
63 | tristate "Xilinx Configuration over Slave Serial (SPI)" | |
64 | depends on SPI | |
65 | help | |
66 | FPGA manager driver support for Xilinx FPGA configuration | |
67 | over slave serial interface. | |
68 | ||
37784706 MF |
69 | config FPGA_MGR_ZYNQ_FPGA |
70 | tristate "Xilinx Zynq FPGA" | |
54e9b099 | 71 | depends on ARCH_ZYNQ || COMPILE_TEST |
1c8cb409 | 72 | depends on HAS_DMA |
37784706 MF |
73 | help |
74 | FPGA manager driver support for Xilinx Zynq FPGAs. | |
75 | ||
21aeda95 AT |
76 | config FPGA_BRIDGE |
77 | tristate "FPGA Bridge Framework" | |
78 | depends on OF | |
79 | help | |
80 | Say Y here if you want to support bridges connected between host | |
81 | processors and FPGAs or between FPGAs. | |
82 | ||
e5f8efa5 AT |
83 | config SOCFPGA_FPGA_BRIDGE |
84 | tristate "Altera SoCFPGA FPGA Bridges" | |
85 | depends on ARCH_SOCFPGA && FPGA_BRIDGE | |
86 | help | |
87 | Say Y to enable drivers for FPGA bridges for Altera SOCFPGA | |
88 | devices. | |
89 | ||
ca24a648 AT |
90 | config ALTERA_FREEZE_BRIDGE |
91 | tristate "Altera FPGA Freeze Bridge" | |
92 | depends on ARCH_SOCFPGA && FPGA_BRIDGE | |
93 | help | |
94 | Say Y to enable drivers for Altera FPGA Freeze bridges. A | |
95 | freeze bridge is a bridge that exists in the FPGA fabric to | |
96 | isolate one region of the FPGA from the busses while that | |
97 | region is being reprogrammed. | |
98 | ||
d201cc17 MG |
99 | config ALTERA_PR_IP_CORE |
100 | tristate "Altera Partial Reconfiguration IP Core" | |
101 | help | |
102 | Core driver support for Altera Partial Reconfiguration IP component | |
103 | ||
5b73cb5b MG |
104 | config ALTERA_PR_IP_CORE_PLAT |
105 | tristate "Platform support of Altera Partial Reconfiguration IP Core" | |
106 | depends on ALTERA_PR_IP_CORE && OF && HAS_IOMEM | |
107 | help | |
108 | Platform driver support for Altera Partial Reconfiguration IP | |
109 | component | |
110 | ||
7e961c12 MF |
111 | config XILINX_PR_DECOUPLER |
112 | tristate "Xilinx LogiCORE PR Decoupler" | |
113 | depends on FPGA_BRIDGE | |
114 | depends on HAS_IOMEM | |
115 | help | |
116 | Say Y to enable drivers for Xilinx LogiCORE PR Decoupler. | |
117 | The PR Decoupler exists in the FPGA fabric to isolate one | |
118 | region of the FPGA from the busses while that region is | |
119 | being reprogrammed during partial reconfig. | |
120 | ||
fab6266e | 121 | endif # FPGA |