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Commit | Line | Data |
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6a8c3be7 AT |
1 | # |
2 | # FPGA framework configuration | |
3 | # | |
4 | ||
5 | menu "FPGA Configuration Support" | |
6 | ||
7 | config FPGA | |
8 | tristate "FPGA Configuration Framework" | |
9 | help | |
10 | Say Y here if you want support for configuring FPGAs from the | |
11 | kernel. The FPGA framework adds a FPGA manager class and FPGA | |
12 | manager drivers. | |
13 | ||
fab6266e AT |
14 | if FPGA |
15 | ||
0fa20cdf AT |
16 | config FPGA_REGION |
17 | tristate "FPGA Region" | |
18 | depends on OF && FPGA_BRIDGE | |
19 | help | |
20 | FPGA Regions allow loading FPGA images under control of | |
21 | the Device Tree. | |
22 | ||
21f8ba2e JH |
23 | config FPGA_MGR_ICE40_SPI |
24 | tristate "Lattice iCE40 SPI" | |
25 | depends on OF && SPI | |
26 | help | |
27 | FPGA manager driver support for Lattice iCE40 FPGAs over SPI. | |
28 | ||
fab6266e AT |
29 | config FPGA_MGR_SOCFPGA |
30 | tristate "Altera SOCFPGA FPGA Manager" | |
a0e1b618 | 31 | depends on ARCH_SOCFPGA || COMPILE_TEST |
fab6266e AT |
32 | help |
33 | FPGA manager driver support for Altera SOCFPGA. | |
34 | ||
acbb910a AT |
35 | config FPGA_MGR_SOCFPGA_A10 |
36 | tristate "Altera SoCFPGA Arria10" | |
a0e1b618 JG |
37 | depends on ARCH_SOCFPGA || COMPILE_TEST |
38 | select REGMAP_MMIO | |
acbb910a AT |
39 | help |
40 | FPGA manager driver support for Altera Arria10 SoCFPGA. | |
41 | ||
4348f7e2 FF |
42 | config FPGA_MGR_TS73XX |
43 | tristate "Technologic Systems TS-73xx SBC FPGA Manager" | |
44 | depends on ARCH_EP93XX && MACH_TS72XX | |
45 | help | |
46 | FPGA manager driver support for the Altera Cyclone II FPGA | |
47 | present on the TS-73xx SBC boards. | |
48 | ||
061c97d1 AG |
49 | config FPGA_MGR_XILINX_SPI |
50 | tristate "Xilinx Configuration over Slave Serial (SPI)" | |
51 | depends on SPI | |
52 | help | |
53 | FPGA manager driver support for Xilinx FPGA configuration | |
54 | over slave serial interface. | |
55 | ||
37784706 MF |
56 | config FPGA_MGR_ZYNQ_FPGA |
57 | tristate "Xilinx Zynq FPGA" | |
54e9b099 | 58 | depends on ARCH_ZYNQ || COMPILE_TEST |
1c8cb409 | 59 | depends on HAS_DMA |
37784706 MF |
60 | help |
61 | FPGA manager driver support for Xilinx Zynq FPGAs. | |
62 | ||
21aeda95 AT |
63 | config FPGA_BRIDGE |
64 | tristate "FPGA Bridge Framework" | |
65 | depends on OF | |
66 | help | |
67 | Say Y here if you want to support bridges connected between host | |
68 | processors and FPGAs or between FPGAs. | |
69 | ||
e5f8efa5 AT |
70 | config SOCFPGA_FPGA_BRIDGE |
71 | tristate "Altera SoCFPGA FPGA Bridges" | |
72 | depends on ARCH_SOCFPGA && FPGA_BRIDGE | |
73 | help | |
74 | Say Y to enable drivers for FPGA bridges for Altera SOCFPGA | |
75 | devices. | |
76 | ||
ca24a648 AT |
77 | config ALTERA_FREEZE_BRIDGE |
78 | tristate "Altera FPGA Freeze Bridge" | |
79 | depends on ARCH_SOCFPGA && FPGA_BRIDGE | |
80 | help | |
81 | Say Y to enable drivers for Altera FPGA Freeze bridges. A | |
82 | freeze bridge is a bridge that exists in the FPGA fabric to | |
83 | isolate one region of the FPGA from the busses while that | |
84 | region is being reprogrammed. | |
85 | ||
d201cc17 MG |
86 | config ALTERA_PR_IP_CORE |
87 | tristate "Altera Partial Reconfiguration IP Core" | |
88 | help | |
89 | Core driver support for Altera Partial Reconfiguration IP component | |
90 | ||
5b73cb5b MG |
91 | config ALTERA_PR_IP_CORE_PLAT |
92 | tristate "Platform support of Altera Partial Reconfiguration IP Core" | |
93 | depends on ALTERA_PR_IP_CORE && OF && HAS_IOMEM | |
94 | help | |
95 | Platform driver support for Altera Partial Reconfiguration IP | |
96 | component | |
97 | ||
7e961c12 MF |
98 | config XILINX_PR_DECOUPLER |
99 | tristate "Xilinx LogiCORE PR Decoupler" | |
100 | depends on FPGA_BRIDGE | |
101 | depends on HAS_IOMEM | |
102 | help | |
103 | Say Y to enable drivers for Xilinx LogiCORE PR Decoupler. | |
104 | The PR Decoupler exists in the FPGA fabric to isolate one | |
105 | region of the FPGA from the busses while that region is | |
106 | being reprogrammed during partial reconfig. | |
107 | ||
fab6266e AT |
108 | endif # FPGA |
109 | ||
6a8c3be7 | 110 | endmenu |