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1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | /* | |
3 | * Driver Header File for FPGA Device Feature List (DFL) Support | |
4 | * | |
5 | * Copyright (C) 2017-2018 Intel Corporation, Inc. | |
6 | * | |
7 | * Authors: | |
8 | * Kang Luwei <luwei.kang@intel.com> | |
9 | * Zhang Yi <yi.z.zhang@intel.com> | |
10 | * Wu Hao <hao.wu@intel.com> | |
11 | * Xiao Guangrong <guangrong.xiao@linux.intel.com> | |
12 | */ | |
13 | ||
14 | #ifndef __FPGA_DFL_H | |
15 | #define __FPGA_DFL_H | |
16 | ||
17 | #include <linux/bitfield.h> | |
b16c5147 | 18 | #include <linux/cdev.h> |
543be3d8 WH |
19 | #include <linux/delay.h> |
20 | #include <linux/fs.h> | |
21 | #include <linux/iopoll.h> | |
22 | #include <linux/io-64-nonatomic-lo-hi.h> | |
23 | #include <linux/platform_device.h> | |
24 | #include <linux/slab.h> | |
25 | #include <linux/uuid.h> | |
26 | #include <linux/fpga/fpga-region.h> | |
27 | ||
28 | /* maximum supported number of ports */ | |
29 | #define MAX_DFL_FPGA_PORT_NUM 4 | |
30 | /* plus one for fme device */ | |
31 | #define MAX_DFL_FEATURE_DEV_NUM (MAX_DFL_FPGA_PORT_NUM + 1) | |
32 | ||
33 | /* Reserved 0x0 for Header Group Register and 0xff for AFU */ | |
34 | #define FEATURE_ID_FIU_HEADER 0x0 | |
35 | #define FEATURE_ID_AFU 0xff | |
36 | ||
37 | #define FME_FEATURE_ID_HEADER FEATURE_ID_FIU_HEADER | |
38 | #define FME_FEATURE_ID_THERMAL_MGMT 0x1 | |
39 | #define FME_FEATURE_ID_POWER_MGMT 0x2 | |
40 | #define FME_FEATURE_ID_GLOBAL_IPERF 0x3 | |
41 | #define FME_FEATURE_ID_GLOBAL_ERR 0x4 | |
42 | #define FME_FEATURE_ID_PR_MGMT 0x5 | |
43 | #define FME_FEATURE_ID_HSSI 0x6 | |
44 | #define FME_FEATURE_ID_GLOBAL_DPERF 0x7 | |
45 | ||
46 | #define PORT_FEATURE_ID_HEADER FEATURE_ID_FIU_HEADER | |
47 | #define PORT_FEATURE_ID_AFU FEATURE_ID_AFU | |
48 | #define PORT_FEATURE_ID_ERROR 0x10 | |
49 | #define PORT_FEATURE_ID_UMSG 0x11 | |
50 | #define PORT_FEATURE_ID_UINT 0x12 | |
51 | #define PORT_FEATURE_ID_STP 0x13 | |
52 | ||
53 | /* | |
54 | * Device Feature Header Register Set | |
55 | * | |
56 | * For FIUs, they all have DFH + GUID + NEXT_AFU as common header registers. | |
57 | * For AFUs, they have DFH + GUID as common header registers. | |
58 | * For private features, they only have DFH register as common header. | |
59 | */ | |
60 | #define DFH 0x0 | |
61 | #define GUID_L 0x8 | |
62 | #define GUID_H 0x10 | |
63 | #define NEXT_AFU 0x18 | |
64 | ||
65 | #define DFH_SIZE 0x8 | |
66 | ||
67 | /* Device Feature Header Register Bitfield */ | |
68 | #define DFH_ID GENMASK_ULL(11, 0) /* Feature ID */ | |
69 | #define DFH_ID_FIU_FME 0 | |
70 | #define DFH_ID_FIU_PORT 1 | |
71 | #define DFH_REVISION GENMASK_ULL(15, 12) /* Feature revision */ | |
72 | #define DFH_NEXT_HDR_OFST GENMASK_ULL(39, 16) /* Offset to next DFH */ | |
73 | #define DFH_EOL BIT_ULL(40) /* End of list */ | |
74 | #define DFH_TYPE GENMASK_ULL(63, 60) /* Feature type */ | |
75 | #define DFH_TYPE_AFU 1 | |
76 | #define DFH_TYPE_PRIVATE 3 | |
77 | #define DFH_TYPE_FIU 4 | |
78 | ||
79 | /* Next AFU Register Bitfield */ | |
80 | #define NEXT_AFU_NEXT_DFH_OFST GENMASK_ULL(23, 0) /* Offset to next AFU */ | |
81 | ||
82 | /* FME Header Register Set */ | |
83 | #define FME_HDR_DFH DFH | |
84 | #define FME_HDR_GUID_L GUID_L | |
85 | #define FME_HDR_GUID_H GUID_H | |
86 | #define FME_HDR_NEXT_AFU NEXT_AFU | |
87 | #define FME_HDR_CAP 0x30 | |
88 | #define FME_HDR_PORT_OFST(n) (0x38 + ((n) * 0x8)) | |
89 | #define FME_HDR_BITSTREAM_ID 0x60 | |
90 | #define FME_HDR_BITSTREAM_MD 0x68 | |
91 | ||
92 | /* FME Fab Capability Register Bitfield */ | |
93 | #define FME_CAP_FABRIC_VERID GENMASK_ULL(7, 0) /* Fabric version ID */ | |
94 | #define FME_CAP_SOCKET_ID BIT_ULL(8) /* Socket ID */ | |
95 | #define FME_CAP_PCIE0_LINK_AVL BIT_ULL(12) /* PCIE0 Link */ | |
96 | #define FME_CAP_PCIE1_LINK_AVL BIT_ULL(13) /* PCIE1 Link */ | |
97 | #define FME_CAP_COHR_LINK_AVL BIT_ULL(14) /* Coherent Link */ | |
98 | #define FME_CAP_IOMMU_AVL BIT_ULL(16) /* IOMMU available */ | |
99 | #define FME_CAP_NUM_PORTS GENMASK_ULL(19, 17) /* Number of ports */ | |
100 | #define FME_CAP_ADDR_WIDTH GENMASK_ULL(29, 24) /* Address bus width */ | |
101 | #define FME_CAP_CACHE_SIZE GENMASK_ULL(43, 32) /* cache size in KB */ | |
102 | #define FME_CAP_CACHE_ASSOC GENMASK_ULL(47, 44) /* Associativity */ | |
103 | ||
104 | /* FME Port Offset Register Bitfield */ | |
105 | /* Offset to port device feature header */ | |
106 | #define FME_PORT_OFST_DFH_OFST GENMASK_ULL(23, 0) | |
107 | /* PCI Bar ID for this port */ | |
108 | #define FME_PORT_OFST_BAR_ID GENMASK_ULL(34, 32) | |
109 | /* AFU MMIO access permission. 1 - VF, 0 - PF. */ | |
110 | #define FME_PORT_OFST_ACC_CTRL BIT_ULL(55) | |
111 | #define FME_PORT_OFST_ACC_PF 0 | |
112 | #define FME_PORT_OFST_ACC_VF 1 | |
113 | #define FME_PORT_OFST_IMP BIT_ULL(60) | |
114 | ||
115 | /* PORT Header Register Set */ | |
116 | #define PORT_HDR_DFH DFH | |
117 | #define PORT_HDR_GUID_L GUID_L | |
118 | #define PORT_HDR_GUID_H GUID_H | |
119 | #define PORT_HDR_NEXT_AFU NEXT_AFU | |
120 | #define PORT_HDR_CAP 0x30 | |
121 | #define PORT_HDR_CTRL 0x38 | |
122 | ||
123 | /* Port Capability Register Bitfield */ | |
124 | #define PORT_CAP_PORT_NUM GENMASK_ULL(1, 0) /* ID of this port */ | |
125 | #define PORT_CAP_MMIO_SIZE GENMASK_ULL(23, 8) /* MMIO size in KB */ | |
126 | #define PORT_CAP_SUPP_INT_NUM GENMASK_ULL(35, 32) /* Interrupts num */ | |
127 | ||
128 | /* Port Control Register Bitfield */ | |
129 | #define PORT_CTRL_SFTRST BIT_ULL(0) /* Port soft reset */ | |
130 | /* Latency tolerance reporting. '1' >= 40us, '0' < 40us.*/ | |
131 | #define PORT_CTRL_LATENCY BIT_ULL(2) | |
132 | #define PORT_CTRL_SFTRST_ACK BIT_ULL(4) /* HW ack for reset */ | |
133 | ||
134 | /** | |
135 | * struct dfl_feature - sub feature of the feature devices | |
136 | * | |
137 | * @id: sub feature id. | |
138 | * @resource_index: each sub feature has one mmio resource for its registers. | |
139 | * this index is used to find its mmio resource from the | |
140 | * feature dev (platform device)'s reources. | |
141 | * @ioaddr: mapped mmio resource address. | |
142 | */ | |
143 | struct dfl_feature { | |
144 | u64 id; | |
145 | int resource_index; | |
146 | void __iomem *ioaddr; | |
147 | }; | |
148 | ||
149 | /** | |
150 | * struct dfl_feature_platform_data - platform data for feature devices | |
151 | * | |
152 | * @node: node to link feature devs to container device's port_dev_list. | |
153 | * @lock: mutex to protect platform data. | |
b16c5147 | 154 | * @cdev: cdev of feature dev. |
543be3d8 WH |
155 | * @dev: ptr to platform device linked with this platform data. |
156 | * @dfl_cdev: ptr to container device. | |
157 | * @disable_count: count for port disable. | |
158 | * @num: number for sub features. | |
159 | * @features: sub features of this feature dev. | |
160 | */ | |
161 | struct dfl_feature_platform_data { | |
162 | struct list_head node; | |
163 | struct mutex lock; | |
b16c5147 | 164 | struct cdev cdev; |
543be3d8 WH |
165 | struct platform_device *dev; |
166 | struct dfl_fpga_cdev *dfl_cdev; | |
167 | unsigned int disable_count; | |
168 | ||
169 | int num; | |
170 | struct dfl_feature features[0]; | |
171 | }; | |
172 | ||
173 | #define DFL_FPGA_FEATURE_DEV_FME "dfl-fme" | |
174 | #define DFL_FPGA_FEATURE_DEV_PORT "dfl-port" | |
175 | ||
176 | static inline int dfl_feature_platform_data_size(const int num) | |
177 | { | |
178 | return sizeof(struct dfl_feature_platform_data) + | |
179 | num * sizeof(struct dfl_feature); | |
180 | } | |
181 | ||
b16c5147 WH |
182 | int dfl_fpga_dev_ops_register(struct platform_device *pdev, |
183 | const struct file_operations *fops, | |
184 | struct module *owner); | |
185 | void dfl_fpga_dev_ops_unregister(struct platform_device *pdev); | |
186 | ||
543be3d8 WH |
187 | #define dfl_fpga_dev_for_each_feature(pdata, feature) \ |
188 | for ((feature) = (pdata)->features; \ | |
189 | (feature) < (pdata)->features + (pdata)->num; (feature)++) | |
190 | ||
191 | static inline | |
192 | struct dfl_feature *dfl_get_feature_by_id(struct device *dev, u64 id) | |
193 | { | |
194 | struct dfl_feature_platform_data *pdata = dev_get_platdata(dev); | |
195 | struct dfl_feature *feature; | |
196 | ||
197 | dfl_fpga_dev_for_each_feature(pdata, feature) | |
198 | if (feature->id == id) | |
199 | return feature; | |
200 | ||
201 | return NULL; | |
202 | } | |
203 | ||
204 | static inline | |
205 | void __iomem *dfl_get_feature_ioaddr_by_id(struct device *dev, u64 id) | |
206 | { | |
207 | struct dfl_feature *feature = dfl_get_feature_by_id(dev, id); | |
208 | ||
209 | if (feature && feature->ioaddr) | |
210 | return feature->ioaddr; | |
211 | ||
212 | WARN_ON(1); | |
213 | return NULL; | |
214 | } | |
215 | ||
216 | static inline bool dfl_feature_is_fme(void __iomem *base) | |
217 | { | |
218 | u64 v = readq(base + DFH); | |
219 | ||
220 | return (FIELD_GET(DFH_TYPE, v) == DFH_TYPE_FIU) && | |
221 | (FIELD_GET(DFH_ID, v) == DFH_ID_FIU_FME); | |
222 | } | |
223 | ||
224 | static inline bool dfl_feature_is_port(void __iomem *base) | |
225 | { | |
226 | u64 v = readq(base + DFH); | |
227 | ||
228 | return (FIELD_GET(DFH_TYPE, v) == DFH_TYPE_FIU) && | |
229 | (FIELD_GET(DFH_ID, v) == DFH_ID_FIU_PORT); | |
230 | } | |
231 | ||
232 | /** | |
233 | * struct dfl_fpga_enum_info - DFL FPGA enumeration information | |
234 | * | |
235 | * @dev: parent device. | |
236 | * @dfls: list of device feature lists. | |
237 | */ | |
238 | struct dfl_fpga_enum_info { | |
239 | struct device *dev; | |
240 | struct list_head dfls; | |
241 | }; | |
242 | ||
243 | /** | |
244 | * struct dfl_fpga_enum_dfl - DFL FPGA enumeration device feature list info | |
245 | * | |
246 | * @start: base address of this device feature list. | |
247 | * @len: size of this device feature list. | |
248 | * @ioaddr: mapped base address of this device feature list. | |
249 | * @node: node in list of device feature lists. | |
250 | */ | |
251 | struct dfl_fpga_enum_dfl { | |
252 | resource_size_t start; | |
253 | resource_size_t len; | |
254 | ||
255 | void __iomem *ioaddr; | |
256 | ||
257 | struct list_head node; | |
258 | }; | |
259 | ||
260 | struct dfl_fpga_enum_info *dfl_fpga_enum_info_alloc(struct device *dev); | |
261 | int dfl_fpga_enum_info_add_dfl(struct dfl_fpga_enum_info *info, | |
262 | resource_size_t start, resource_size_t len, | |
263 | void __iomem *ioaddr); | |
264 | void dfl_fpga_enum_info_free(struct dfl_fpga_enum_info *info); | |
265 | ||
266 | /** | |
267 | * struct dfl_fpga_cdev - container device of DFL based FPGA | |
268 | * | |
269 | * @parent: parent device of this container device. | |
270 | * @region: base fpga region. | |
271 | * @fme_dev: FME feature device under this container device. | |
272 | * @lock: mutex lock to protect the port device list. | |
273 | * @port_dev_list: list of all port feature devices under this container device. | |
274 | */ | |
275 | struct dfl_fpga_cdev { | |
276 | struct device *parent; | |
277 | struct fpga_region *region; | |
278 | struct device *fme_dev; | |
279 | struct mutex lock; | |
280 | struct list_head port_dev_list; | |
281 | }; | |
282 | ||
283 | struct dfl_fpga_cdev * | |
284 | dfl_fpga_feature_devs_enumerate(struct dfl_fpga_enum_info *info); | |
285 | void dfl_fpga_feature_devs_remove(struct dfl_fpga_cdev *cdev); | |
286 | ||
5d56e117 WH |
287 | /* |
288 | * need to drop the device reference with put_device() after use port platform | |
289 | * device returned by __dfl_fpga_cdev_find_port and dfl_fpga_cdev_find_port | |
290 | * functions. | |
291 | */ | |
292 | struct platform_device * | |
293 | __dfl_fpga_cdev_find_port(struct dfl_fpga_cdev *cdev, void *data, | |
294 | int (*match)(struct platform_device *, void *)); | |
295 | ||
296 | static inline struct platform_device * | |
297 | dfl_fpga_cdev_find_port(struct dfl_fpga_cdev *cdev, void *data, | |
298 | int (*match)(struct platform_device *, void *)) | |
299 | { | |
300 | struct platform_device *pdev; | |
301 | ||
302 | mutex_lock(&cdev->lock); | |
303 | pdev = __dfl_fpga_cdev_find_port(cdev, data, match); | |
304 | mutex_unlock(&cdev->lock); | |
305 | ||
306 | return pdev; | |
307 | } | |
543be3d8 | 308 | #endif /* __FPGA_DFL_H */ |