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6a8c3be7 AT |
1 | /* |
2 | * FPGA Manager Core | |
3 | * | |
4 | * Copyright (C) 2013-2015 Altera Corporation | |
5cf0c7f6 | 5 | * Copyright (C) 2017 Intel Corporation |
6a8c3be7 AT |
6 | * |
7 | * With code from the mailing list: | |
8 | * Copyright (C) 2013 Xilinx, Inc. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify it | |
11 | * under the terms and conditions of the GNU General Public License, | |
12 | * version 2, as published by the Free Software Foundation. | |
13 | * | |
14 | * This program is distributed in the hope it will be useful, but WITHOUT | |
15 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
16 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
17 | * more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License along with | |
20 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
21 | */ | |
22 | #include <linux/firmware.h> | |
23 | #include <linux/fpga/fpga-mgr.h> | |
24 | #include <linux/idr.h> | |
25 | #include <linux/module.h> | |
26 | #include <linux/of.h> | |
27 | #include <linux/mutex.h> | |
28 | #include <linux/slab.h> | |
baa6d396 JG |
29 | #include <linux/scatterlist.h> |
30 | #include <linux/highmem.h> | |
6a8c3be7 AT |
31 | |
32 | static DEFINE_IDA(fpga_mgr_ida); | |
33 | static struct class *fpga_mgr_class; | |
34 | ||
5cf0c7f6 AT |
35 | struct fpga_image_info *fpga_image_info_alloc(struct device *dev) |
36 | { | |
37 | struct fpga_image_info *info; | |
38 | ||
39 | get_device(dev); | |
40 | ||
41 | info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL); | |
42 | if (!info) { | |
43 | put_device(dev); | |
44 | return NULL; | |
45 | } | |
46 | ||
47 | info->dev = dev; | |
48 | ||
49 | return info; | |
50 | } | |
51 | EXPORT_SYMBOL_GPL(fpga_image_info_alloc); | |
52 | ||
53 | void fpga_image_info_free(struct fpga_image_info *info) | |
54 | { | |
55 | struct device *dev; | |
56 | ||
57 | if (!info) | |
58 | return; | |
59 | ||
60 | dev = info->dev; | |
61 | if (info->firmware_name) | |
62 | devm_kfree(dev, info->firmware_name); | |
63 | ||
64 | devm_kfree(dev, info); | |
65 | put_device(dev); | |
66 | } | |
67 | EXPORT_SYMBOL_GPL(fpga_image_info_free); | |
68 | ||
baa6d396 JG |
69 | /* |
70 | * Call the low level driver's write_init function. This will do the | |
71 | * device-specific things to get the FPGA into the state where it is ready to | |
72 | * receive an FPGA image. The low level driver only gets to see the first | |
73 | * initial_header_size bytes in the buffer. | |
74 | */ | |
75 | static int fpga_mgr_write_init_buf(struct fpga_manager *mgr, | |
76 | struct fpga_image_info *info, | |
77 | const char *buf, size_t count) | |
78 | { | |
79 | int ret; | |
80 | ||
81 | mgr->state = FPGA_MGR_STATE_WRITE_INIT; | |
82 | if (!mgr->mops->initial_header_size) | |
83 | ret = mgr->mops->write_init(mgr, info, NULL, 0); | |
84 | else | |
85 | ret = mgr->mops->write_init( | |
86 | mgr, info, buf, min(mgr->mops->initial_header_size, count)); | |
87 | ||
88 | if (ret) { | |
89 | dev_err(&mgr->dev, "Error preparing FPGA for writing\n"); | |
90 | mgr->state = FPGA_MGR_STATE_WRITE_INIT_ERR; | |
91 | return ret; | |
92 | } | |
93 | ||
94 | return 0; | |
95 | } | |
96 | ||
97 | static int fpga_mgr_write_init_sg(struct fpga_manager *mgr, | |
98 | struct fpga_image_info *info, | |
99 | struct sg_table *sgt) | |
100 | { | |
101 | struct sg_mapping_iter miter; | |
102 | size_t len; | |
103 | char *buf; | |
104 | int ret; | |
105 | ||
106 | if (!mgr->mops->initial_header_size) | |
107 | return fpga_mgr_write_init_buf(mgr, info, NULL, 0); | |
108 | ||
109 | /* | |
110 | * First try to use miter to map the first fragment to access the | |
111 | * header, this is the typical path. | |
112 | */ | |
113 | sg_miter_start(&miter, sgt->sgl, sgt->nents, SG_MITER_FROM_SG); | |
114 | if (sg_miter_next(&miter) && | |
115 | miter.length >= mgr->mops->initial_header_size) { | |
116 | ret = fpga_mgr_write_init_buf(mgr, info, miter.addr, | |
117 | miter.length); | |
118 | sg_miter_stop(&miter); | |
119 | return ret; | |
120 | } | |
121 | sg_miter_stop(&miter); | |
122 | ||
123 | /* Otherwise copy the fragments into temporary memory. */ | |
124 | buf = kmalloc(mgr->mops->initial_header_size, GFP_KERNEL); | |
125 | if (!buf) | |
126 | return -ENOMEM; | |
127 | ||
128 | len = sg_copy_to_buffer(sgt->sgl, sgt->nents, buf, | |
129 | mgr->mops->initial_header_size); | |
130 | ret = fpga_mgr_write_init_buf(mgr, info, buf, len); | |
131 | ||
132 | kfree(buf); | |
133 | ||
134 | return ret; | |
135 | } | |
136 | ||
137 | /* | |
138 | * After all the FPGA image has been written, do the device specific steps to | |
139 | * finish and set the FPGA into operating mode. | |
140 | */ | |
141 | static int fpga_mgr_write_complete(struct fpga_manager *mgr, | |
142 | struct fpga_image_info *info) | |
143 | { | |
144 | int ret; | |
145 | ||
146 | mgr->state = FPGA_MGR_STATE_WRITE_COMPLETE; | |
147 | ret = mgr->mops->write_complete(mgr, info); | |
148 | if (ret) { | |
149 | dev_err(&mgr->dev, "Error after writing image data to FPGA\n"); | |
150 | mgr->state = FPGA_MGR_STATE_WRITE_COMPLETE_ERR; | |
151 | return ret; | |
152 | } | |
153 | mgr->state = FPGA_MGR_STATE_OPERATING; | |
154 | ||
155 | return 0; | |
156 | } | |
157 | ||
6a8c3be7 | 158 | /** |
baa6d396 | 159 | * fpga_mgr_buf_load_sg - load fpga from image in buffer from a scatter list |
6a8c3be7 | 160 | * @mgr: fpga manager |
1df2865f | 161 | * @info: fpga image specific information |
baa6d396 | 162 | * @sgt: scatterlist table |
6a8c3be7 AT |
163 | * |
164 | * Step the low level fpga manager through the device-specific steps of getting | |
165 | * an FPGA ready to be configured, writing the image to it, then doing whatever | |
92d94a7e | 166 | * post-configuration steps necessary. This code assumes the caller got the |
9dce0287 AT |
167 | * mgr pointer from of_fpga_mgr_get() or fpga_mgr_get() and checked that it is |
168 | * not an error code. | |
6a8c3be7 | 169 | * |
baa6d396 JG |
170 | * This is the preferred entry point for FPGA programming, it does not require |
171 | * any contiguous kernel memory. | |
172 | * | |
6a8c3be7 AT |
173 | * Return: 0 on success, negative error code otherwise. |
174 | */ | |
5cf0c7f6 AT |
175 | static int fpga_mgr_buf_load_sg(struct fpga_manager *mgr, |
176 | struct fpga_image_info *info, | |
177 | struct sg_table *sgt) | |
6a8c3be7 | 178 | { |
6a8c3be7 AT |
179 | int ret; |
180 | ||
baa6d396 JG |
181 | ret = fpga_mgr_write_init_sg(mgr, info, sgt); |
182 | if (ret) | |
183 | return ret; | |
184 | ||
185 | /* Write the FPGA image to the FPGA. */ | |
186 | mgr->state = FPGA_MGR_STATE_WRITE; | |
187 | if (mgr->mops->write_sg) { | |
188 | ret = mgr->mops->write_sg(mgr, sgt); | |
189 | } else { | |
190 | struct sg_mapping_iter miter; | |
191 | ||
192 | sg_miter_start(&miter, sgt->sgl, sgt->nents, SG_MITER_FROM_SG); | |
193 | while (sg_miter_next(&miter)) { | |
194 | ret = mgr->mops->write(mgr, miter.addr, miter.length); | |
195 | if (ret) | |
196 | break; | |
197 | } | |
198 | sg_miter_stop(&miter); | |
199 | } | |
200 | ||
6a8c3be7 | 201 | if (ret) { |
baa6d396 JG |
202 | dev_err(&mgr->dev, "Error while writing image data to FPGA\n"); |
203 | mgr->state = FPGA_MGR_STATE_WRITE_ERR; | |
6a8c3be7 AT |
204 | return ret; |
205 | } | |
206 | ||
baa6d396 JG |
207 | return fpga_mgr_write_complete(mgr, info); |
208 | } | |
baa6d396 JG |
209 | |
210 | static int fpga_mgr_buf_load_mapped(struct fpga_manager *mgr, | |
211 | struct fpga_image_info *info, | |
212 | const char *buf, size_t count) | |
213 | { | |
214 | int ret; | |
215 | ||
216 | ret = fpga_mgr_write_init_buf(mgr, info, buf, count); | |
217 | if (ret) | |
218 | return ret; | |
219 | ||
6a8c3be7 AT |
220 | /* |
221 | * Write the FPGA image to the FPGA. | |
222 | */ | |
223 | mgr->state = FPGA_MGR_STATE_WRITE; | |
224 | ret = mgr->mops->write(mgr, buf, count); | |
225 | if (ret) { | |
baa6d396 | 226 | dev_err(&mgr->dev, "Error while writing image data to FPGA\n"); |
6a8c3be7 AT |
227 | mgr->state = FPGA_MGR_STATE_WRITE_ERR; |
228 | return ret; | |
229 | } | |
230 | ||
baa6d396 JG |
231 | return fpga_mgr_write_complete(mgr, info); |
232 | } | |
233 | ||
234 | /** | |
235 | * fpga_mgr_buf_load - load fpga from image in buffer | |
236 | * @mgr: fpga manager | |
237 | * @flags: flags setting fpga confuration modes | |
238 | * @buf: buffer contain fpga image | |
239 | * @count: byte count of buf | |
240 | * | |
241 | * Step the low level fpga manager through the device-specific steps of getting | |
242 | * an FPGA ready to be configured, writing the image to it, then doing whatever | |
243 | * post-configuration steps necessary. This code assumes the caller got the | |
244 | * mgr pointer from of_fpga_mgr_get() and checked that it is not an error code. | |
245 | * | |
246 | * Return: 0 on success, negative error code otherwise. | |
247 | */ | |
5cf0c7f6 AT |
248 | static int fpga_mgr_buf_load(struct fpga_manager *mgr, |
249 | struct fpga_image_info *info, | |
250 | const char *buf, size_t count) | |
baa6d396 JG |
251 | { |
252 | struct page **pages; | |
253 | struct sg_table sgt; | |
254 | const void *p; | |
255 | int nr_pages; | |
256 | int index; | |
257 | int rc; | |
258 | ||
6a8c3be7 | 259 | /* |
baa6d396 JG |
260 | * This is just a fast path if the caller has already created a |
261 | * contiguous kernel buffer and the driver doesn't require SG, non-SG | |
262 | * drivers will still work on the slow path. | |
6a8c3be7 | 263 | */ |
baa6d396 JG |
264 | if (mgr->mops->write) |
265 | return fpga_mgr_buf_load_mapped(mgr, info, buf, count); | |
266 | ||
267 | /* | |
268 | * Convert the linear kernel pointer into a sg_table of pages for use | |
269 | * by the driver. | |
270 | */ | |
271 | nr_pages = DIV_ROUND_UP((unsigned long)buf + count, PAGE_SIZE) - | |
272 | (unsigned long)buf / PAGE_SIZE; | |
273 | pages = kmalloc_array(nr_pages, sizeof(struct page *), GFP_KERNEL); | |
274 | if (!pages) | |
275 | return -ENOMEM; | |
276 | ||
277 | p = buf - offset_in_page(buf); | |
278 | for (index = 0; index < nr_pages; index++) { | |
279 | if (is_vmalloc_addr(p)) | |
280 | pages[index] = vmalloc_to_page(p); | |
281 | else | |
282 | pages[index] = kmap_to_page((void *)p); | |
283 | if (!pages[index]) { | |
284 | kfree(pages); | |
285 | return -EFAULT; | |
286 | } | |
287 | p += PAGE_SIZE; | |
6a8c3be7 | 288 | } |
6a8c3be7 | 289 | |
baa6d396 JG |
290 | /* |
291 | * The temporary pages list is used to code share the merging algorithm | |
292 | * in sg_alloc_table_from_pages | |
293 | */ | |
294 | rc = sg_alloc_table_from_pages(&sgt, pages, index, offset_in_page(buf), | |
295 | count, GFP_KERNEL); | |
296 | kfree(pages); | |
297 | if (rc) | |
298 | return rc; | |
299 | ||
300 | rc = fpga_mgr_buf_load_sg(mgr, info, &sgt); | |
301 | sg_free_table(&sgt); | |
302 | ||
303 | return rc; | |
6a8c3be7 | 304 | } |
6a8c3be7 AT |
305 | |
306 | /** | |
307 | * fpga_mgr_firmware_load - request firmware and load to fpga | |
308 | * @mgr: fpga manager | |
1df2865f | 309 | * @info: fpga image specific information |
6a8c3be7 AT |
310 | * @image_name: name of image file on the firmware search path |
311 | * | |
312 | * Request an FPGA image using the firmware class, then write out to the FPGA. | |
313 | * Update the state before each step to provide info on what step failed if | |
92d94a7e | 314 | * there is a failure. This code assumes the caller got the mgr pointer |
9dce0287 AT |
315 | * from of_fpga_mgr_get() or fpga_mgr_get() and checked that it is not an error |
316 | * code. | |
6a8c3be7 AT |
317 | * |
318 | * Return: 0 on success, negative error code otherwise. | |
319 | */ | |
5cf0c7f6 AT |
320 | static int fpga_mgr_firmware_load(struct fpga_manager *mgr, |
321 | struct fpga_image_info *info, | |
322 | const char *image_name) | |
6a8c3be7 AT |
323 | { |
324 | struct device *dev = &mgr->dev; | |
325 | const struct firmware *fw; | |
326 | int ret; | |
327 | ||
6a8c3be7 AT |
328 | dev_info(dev, "writing %s to %s\n", image_name, mgr->name); |
329 | ||
330 | mgr->state = FPGA_MGR_STATE_FIRMWARE_REQ; | |
331 | ||
332 | ret = request_firmware(&fw, image_name, dev); | |
333 | if (ret) { | |
334 | mgr->state = FPGA_MGR_STATE_FIRMWARE_REQ_ERR; | |
335 | dev_err(dev, "Error requesting firmware %s\n", image_name); | |
336 | return ret; | |
337 | } | |
338 | ||
1df2865f | 339 | ret = fpga_mgr_buf_load(mgr, info, fw->data, fw->size); |
6a8c3be7 AT |
340 | |
341 | release_firmware(fw); | |
342 | ||
e8c77bda | 343 | return ret; |
6a8c3be7 | 344 | } |
5cf0c7f6 AT |
345 | |
346 | int fpga_mgr_load(struct fpga_manager *mgr, struct fpga_image_info *info) | |
347 | { | |
348 | if (info->sgt) | |
349 | return fpga_mgr_buf_load_sg(mgr, info, info->sgt); | |
350 | if (info->buf && info->count) | |
351 | return fpga_mgr_buf_load(mgr, info, info->buf, info->count); | |
352 | if (info->firmware_name) | |
353 | return fpga_mgr_firmware_load(mgr, info, info->firmware_name); | |
354 | return -EINVAL; | |
355 | } | |
356 | EXPORT_SYMBOL_GPL(fpga_mgr_load); | |
6a8c3be7 AT |
357 | |
358 | static const char * const state_str[] = { | |
359 | [FPGA_MGR_STATE_UNKNOWN] = "unknown", | |
360 | [FPGA_MGR_STATE_POWER_OFF] = "power off", | |
361 | [FPGA_MGR_STATE_POWER_UP] = "power up", | |
362 | [FPGA_MGR_STATE_RESET] = "reset", | |
363 | ||
364 | /* requesting FPGA image from firmware */ | |
365 | [FPGA_MGR_STATE_FIRMWARE_REQ] = "firmware request", | |
366 | [FPGA_MGR_STATE_FIRMWARE_REQ_ERR] = "firmware request error", | |
367 | ||
368 | /* Preparing FPGA to receive image */ | |
369 | [FPGA_MGR_STATE_WRITE_INIT] = "write init", | |
370 | [FPGA_MGR_STATE_WRITE_INIT_ERR] = "write init error", | |
371 | ||
372 | /* Writing image to FPGA */ | |
373 | [FPGA_MGR_STATE_WRITE] = "write", | |
374 | [FPGA_MGR_STATE_WRITE_ERR] = "write error", | |
375 | ||
376 | /* Finishing configuration after image has been written */ | |
377 | [FPGA_MGR_STATE_WRITE_COMPLETE] = "write complete", | |
378 | [FPGA_MGR_STATE_WRITE_COMPLETE_ERR] = "write complete error", | |
379 | ||
380 | /* FPGA reports to be in normal operating mode */ | |
381 | [FPGA_MGR_STATE_OPERATING] = "operating", | |
382 | }; | |
383 | ||
384 | static ssize_t name_show(struct device *dev, | |
385 | struct device_attribute *attr, char *buf) | |
386 | { | |
387 | struct fpga_manager *mgr = to_fpga_manager(dev); | |
388 | ||
389 | return sprintf(buf, "%s\n", mgr->name); | |
390 | } | |
391 | ||
392 | static ssize_t state_show(struct device *dev, | |
393 | struct device_attribute *attr, char *buf) | |
394 | { | |
395 | struct fpga_manager *mgr = to_fpga_manager(dev); | |
396 | ||
397 | return sprintf(buf, "%s\n", state_str[mgr->state]); | |
398 | } | |
399 | ||
400 | static DEVICE_ATTR_RO(name); | |
401 | static DEVICE_ATTR_RO(state); | |
402 | ||
403 | static struct attribute *fpga_mgr_attrs[] = { | |
404 | &dev_attr_name.attr, | |
405 | &dev_attr_state.attr, | |
406 | NULL, | |
407 | }; | |
408 | ATTRIBUTE_GROUPS(fpga_mgr); | |
409 | ||
47910a49 | 410 | static struct fpga_manager *__fpga_mgr_get(struct device *dev) |
6a8c3be7 AT |
411 | { |
412 | struct fpga_manager *mgr; | |
654ba4cc | 413 | int ret = -ENODEV; |
6a8c3be7 | 414 | |
6a8c3be7 | 415 | mgr = to_fpga_manager(dev); |
6a8c3be7 | 416 | if (!mgr) |
654ba4cc | 417 | goto err_dev; |
6a8c3be7 AT |
418 | |
419 | /* Get exclusive use of fpga manager */ | |
654ba4cc AT |
420 | if (!mutex_trylock(&mgr->ref_mutex)) { |
421 | ret = -EBUSY; | |
422 | goto err_dev; | |
6a8c3be7 AT |
423 | } |
424 | ||
654ba4cc AT |
425 | if (!try_module_get(dev->parent->driver->owner)) |
426 | goto err_ll_mod; | |
427 | ||
6a8c3be7 | 428 | return mgr; |
654ba4cc AT |
429 | |
430 | err_ll_mod: | |
431 | mutex_unlock(&mgr->ref_mutex); | |
432 | err_dev: | |
433 | put_device(dev); | |
434 | return ERR_PTR(ret); | |
6a8c3be7 | 435 | } |
9dce0287 AT |
436 | |
437 | static int fpga_mgr_dev_match(struct device *dev, const void *data) | |
438 | { | |
439 | return dev->parent == data; | |
440 | } | |
441 | ||
442 | /** | |
443 | * fpga_mgr_get - get an exclusive reference to a fpga mgr | |
444 | * @dev: parent device that fpga mgr was registered with | |
445 | * | |
446 | * Given a device, get an exclusive reference to a fpga mgr. | |
447 | * | |
448 | * Return: fpga manager struct or IS_ERR() condition containing error code. | |
449 | */ | |
450 | struct fpga_manager *fpga_mgr_get(struct device *dev) | |
451 | { | |
452 | struct device *mgr_dev = class_find_device(fpga_mgr_class, NULL, dev, | |
453 | fpga_mgr_dev_match); | |
454 | if (!mgr_dev) | |
455 | return ERR_PTR(-ENODEV); | |
456 | ||
457 | return __fpga_mgr_get(mgr_dev); | |
458 | } | |
459 | EXPORT_SYMBOL_GPL(fpga_mgr_get); | |
460 | ||
461 | static int fpga_mgr_of_node_match(struct device *dev, const void *data) | |
462 | { | |
463 | return dev->of_node == data; | |
464 | } | |
465 | ||
466 | /** | |
467 | * of_fpga_mgr_get - get an exclusive reference to a fpga mgr | |
468 | * @node: device node | |
469 | * | |
470 | * Given a device node, get an exclusive reference to a fpga mgr. | |
471 | * | |
472 | * Return: fpga manager struct or IS_ERR() condition containing error code. | |
473 | */ | |
474 | struct fpga_manager *of_fpga_mgr_get(struct device_node *node) | |
475 | { | |
476 | struct device *dev; | |
477 | ||
478 | dev = class_find_device(fpga_mgr_class, NULL, node, | |
479 | fpga_mgr_of_node_match); | |
480 | if (!dev) | |
481 | return ERR_PTR(-ENODEV); | |
482 | ||
483 | return __fpga_mgr_get(dev); | |
484 | } | |
6a8c3be7 AT |
485 | EXPORT_SYMBOL_GPL(of_fpga_mgr_get); |
486 | ||
487 | /** | |
488 | * fpga_mgr_put - release a reference to a fpga manager | |
489 | * @mgr: fpga manager structure | |
490 | */ | |
491 | void fpga_mgr_put(struct fpga_manager *mgr) | |
492 | { | |
654ba4cc AT |
493 | module_put(mgr->dev.parent->driver->owner); |
494 | mutex_unlock(&mgr->ref_mutex); | |
495 | put_device(&mgr->dev); | |
6a8c3be7 AT |
496 | } |
497 | EXPORT_SYMBOL_GPL(fpga_mgr_put); | |
498 | ||
499 | /** | |
500 | * fpga_mgr_register - register a low level fpga manager driver | |
501 | * @dev: fpga manager device from pdev | |
502 | * @name: fpga manager name | |
503 | * @mops: pointer to structure of fpga manager ops | |
504 | * @priv: fpga manager private data | |
505 | * | |
506 | * Return: 0 on success, negative error code otherwise. | |
507 | */ | |
508 | int fpga_mgr_register(struct device *dev, const char *name, | |
509 | const struct fpga_manager_ops *mops, | |
510 | void *priv) | |
511 | { | |
512 | struct fpga_manager *mgr; | |
6a8c3be7 AT |
513 | int id, ret; |
514 | ||
baa6d396 JG |
515 | if (!mops || !mops->write_complete || !mops->state || |
516 | !mops->write_init || (!mops->write && !mops->write_sg) || | |
517 | (mops->write && mops->write_sg)) { | |
6a8c3be7 AT |
518 | dev_err(dev, "Attempt to register without fpga_manager_ops\n"); |
519 | return -EINVAL; | |
520 | } | |
521 | ||
522 | if (!name || !strlen(name)) { | |
523 | dev_err(dev, "Attempt to register with no name!\n"); | |
524 | return -EINVAL; | |
525 | } | |
526 | ||
527 | mgr = kzalloc(sizeof(*mgr), GFP_KERNEL); | |
528 | if (!mgr) | |
529 | return -ENOMEM; | |
530 | ||
531 | id = ida_simple_get(&fpga_mgr_ida, 0, 0, GFP_KERNEL); | |
532 | if (id < 0) { | |
533 | ret = id; | |
534 | goto error_kfree; | |
535 | } | |
536 | ||
537 | mutex_init(&mgr->ref_mutex); | |
538 | ||
539 | mgr->name = name; | |
540 | mgr->mops = mops; | |
541 | mgr->priv = priv; | |
542 | ||
543 | /* | |
544 | * Initialize framework state by requesting low level driver read state | |
545 | * from device. FPGA may be in reset mode or may have been programmed | |
546 | * by bootloader or EEPROM. | |
547 | */ | |
548 | mgr->state = mgr->mops->state(mgr); | |
549 | ||
550 | device_initialize(&mgr->dev); | |
551 | mgr->dev.class = fpga_mgr_class; | |
552 | mgr->dev.parent = dev; | |
553 | mgr->dev.of_node = dev->of_node; | |
554 | mgr->dev.id = id; | |
555 | dev_set_drvdata(dev, mgr); | |
556 | ||
07687c03 AT |
557 | ret = dev_set_name(&mgr->dev, "fpga%d", id); |
558 | if (ret) | |
559 | goto error_device; | |
6a8c3be7 AT |
560 | |
561 | ret = device_add(&mgr->dev); | |
562 | if (ret) | |
563 | goto error_device; | |
564 | ||
565 | dev_info(&mgr->dev, "%s registered\n", mgr->name); | |
566 | ||
567 | return 0; | |
568 | ||
569 | error_device: | |
570 | ida_simple_remove(&fpga_mgr_ida, id); | |
571 | error_kfree: | |
572 | kfree(mgr); | |
573 | ||
574 | return ret; | |
575 | } | |
576 | EXPORT_SYMBOL_GPL(fpga_mgr_register); | |
577 | ||
578 | /** | |
579 | * fpga_mgr_unregister - unregister a low level fpga manager driver | |
580 | * @dev: fpga manager device from pdev | |
581 | */ | |
582 | void fpga_mgr_unregister(struct device *dev) | |
583 | { | |
584 | struct fpga_manager *mgr = dev_get_drvdata(dev); | |
585 | ||
586 | dev_info(&mgr->dev, "%s %s\n", __func__, mgr->name); | |
587 | ||
588 | /* | |
589 | * If the low level driver provides a method for putting fpga into | |
590 | * a desired state upon unregister, do it. | |
591 | */ | |
592 | if (mgr->mops->fpga_remove) | |
593 | mgr->mops->fpga_remove(mgr); | |
594 | ||
595 | device_unregister(&mgr->dev); | |
596 | } | |
597 | EXPORT_SYMBOL_GPL(fpga_mgr_unregister); | |
598 | ||
599 | static void fpga_mgr_dev_release(struct device *dev) | |
600 | { | |
601 | struct fpga_manager *mgr = to_fpga_manager(dev); | |
602 | ||
603 | ida_simple_remove(&fpga_mgr_ida, mgr->dev.id); | |
604 | kfree(mgr); | |
605 | } | |
606 | ||
607 | static int __init fpga_mgr_class_init(void) | |
608 | { | |
609 | pr_info("FPGA manager framework\n"); | |
610 | ||
611 | fpga_mgr_class = class_create(THIS_MODULE, "fpga_manager"); | |
612 | if (IS_ERR(fpga_mgr_class)) | |
613 | return PTR_ERR(fpga_mgr_class); | |
614 | ||
615 | fpga_mgr_class->dev_groups = fpga_mgr_groups; | |
616 | fpga_mgr_class->dev_release = fpga_mgr_dev_release; | |
617 | ||
618 | return 0; | |
619 | } | |
620 | ||
621 | static void __exit fpga_mgr_class_exit(void) | |
622 | { | |
623 | class_destroy(fpga_mgr_class); | |
624 | ida_destroy(&fpga_mgr_ida); | |
625 | } | |
626 | ||
5cf0c7f6 | 627 | MODULE_AUTHOR("Alan Tull <atull@kernel.org>"); |
6a8c3be7 AT |
628 | MODULE_DESCRIPTION("FPGA manager framework"); |
629 | MODULE_LICENSE("GPL v2"); | |
630 | ||
631 | subsys_initcall(fpga_mgr_class_init); | |
632 | module_exit(fpga_mgr_class_exit); |