[mirror_ubuntu-hirsute-kernel.git] / drivers / fpga / xilinx-pr-decoupler.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (c) 2017, National Instruments Corp.
 * Copyright (c) 2017, Xilix Inc
 *
 * FPGA Bridge Driver for the Xilinx LogiCORE Partial Reconfiguration
 * Decoupler IP Core.
 */

#include <linux/clk.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/of_device.h>
#include <linux/module.h>
#include <linux/fpga/fpga-bridge.h>

#define CTRL_CMD_DECOUPLE	BIT(0)
#define CTRL_CMD_COUPLE		0
#define CTRL_OFFSET		0

struct xlnx_pr_decoupler_data {
	void __iomem *io_base;
	struct clk *clk;
};

static inline void xlnx_pr_decoupler_write(struct xlnx_pr_decoupler_data *d,
					   u32 offset, u32 val)
{
	writel(val, d->io_base + offset);
}

static inline u32 xlnx_pr_decouple_read(const struct xlnx_pr_decoupler_data *d,
					u32 offset)
{
	return readl(d->io_base + offset);
}

static int xlnx_pr_decoupler_enable_set(struct fpga_bridge *bridge, bool enable)
{
	int err;
	struct xlnx_pr_decoupler_data *priv = bridge->priv;

	err = clk_enable(priv->clk);
	if (err)
		return err;

	if (enable)
		xlnx_pr_decoupler_write(priv, CTRL_OFFSET, CTRL_CMD_COUPLE);
	else
		xlnx_pr_decoupler_write(priv, CTRL_OFFSET, CTRL_CMD_DECOUPLE);

	clk_disable(priv->clk);

	return 0;
}

static int xlnx_pr_decoupler_enable_show(struct fpga_bridge *bridge)
{
	const struct xlnx_pr_decoupler_data *priv = bridge->priv;
	u32 status;
	int err;

	err = clk_enable(priv->clk);
	if (err)
		return err;

	status = readl(priv->io_base);

	clk_disable(priv->clk);

	return !status;
}

static const struct fpga_bridge_ops xlnx_pr_decoupler_br_ops = {
	.enable_set = xlnx_pr_decoupler_enable_set,
	.enable_show = xlnx_pr_decoupler_enable_show,
};

static const struct of_device_id xlnx_pr_decoupler_of_match[] = {
	{ .compatible = "xlnx,pr-decoupler-1.00", },
	{ .compatible = "xlnx,pr-decoupler", },
	{},
};
MODULE_DEVICE_TABLE(of, xlnx_pr_decoupler_of_match);

static int xlnx_pr_decoupler_probe(struct platform_device *pdev)
{
	struct xlnx_pr_decoupler_data *priv;
	struct fpga_bridge *br;
	int err;
	struct resource *res;

	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
	if (!priv)
		return -ENOMEM;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	priv->io_base = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(priv->io_base))
		return PTR_ERR(priv->io_base);

	priv->clk = devm_clk_get(&pdev->dev, "aclk");
	if (IS_ERR(priv->clk)) {
		if (PTR_ERR(priv->clk) != -EPROBE_DEFER)
			dev_err(&pdev->dev, "input clock not found\n");
		return PTR_ERR(priv->clk);
	}

	err = clk_prepare_enable(priv->clk);
	if (err) {
		dev_err(&pdev->dev, "unable to enable clock\n");
		return err;
	}

	clk_disable(priv->clk);

	br = devm_fpga_bridge_create(&pdev->dev, "Xilinx PR Decoupler",
				     &xlnx_pr_decoupler_br_ops, priv);
	if (!br) {
		err = -ENOMEM;
		goto err_clk;
	}

	platform_set_drvdata(pdev, br);

	err = fpga_bridge_register(br);
	if (err) {
		dev_err(&pdev->dev, "unable to register Xilinx PR Decoupler");
		goto err_clk;
	}

	return 0;

err_clk:
	clk_unprepare(priv->clk);

	return err;
}

static int xlnx_pr_decoupler_remove(struct platform_device *pdev)
{
	struct fpga_bridge *bridge = platform_get_drvdata(pdev);
	struct xlnx_pr_decoupler_data *p = bridge->priv;

	fpga_bridge_unregister(bridge);

	clk_unprepare(p->clk);

	return 0;
}

static struct platform_driver xlnx_pr_decoupler_driver = {
	.probe = xlnx_pr_decoupler_probe,
	.remove = xlnx_pr_decoupler_remove,
	.driver = {
		.name = "xlnx_pr_decoupler",
		.of_match_table = of_match_ptr(xlnx_pr_decoupler_of_match),
	},
};

module_platform_driver(xlnx_pr_decoupler_driver);

MODULE_DESCRIPTION("Xilinx Partial Reconfiguration Decoupler");
MODULE_AUTHOR("Moritz Fischer <mdf@kernel.org>");
MODULE_AUTHOR("Michal Simek <michal.simek@xilinx.com>");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
8e8e69d6	1	// SPDX-License-Identifier: GPL-2.0-only
7e961c12 MF	2	/*
	3	* Copyright (c) 2017, National Instruments Corp.
	4	* Copyright (c) 2017, Xilix Inc
	5	*
	6	* FPGA Bridge Driver for the Xilinx LogiCORE Partial Reconfiguration
	7	* Decoupler IP Core.
7e961c12 MF	8	*/
	9
	10	#include <linux/clk.h>
	11	#include <linux/io.h>
	12	#include <linux/kernel.h>
	13	#include <linux/of_device.h>
	14	#include <linux/module.h>
	15	#include <linux/fpga/fpga-bridge.h>
	16
	17	#define CTRL_CMD_DECOUPLE BIT(0)
	18	#define CTRL_CMD_COUPLE 0
	19	#define CTRL_OFFSET 0
	20
	21	struct xlnx_pr_decoupler_data {
	22	void __iomem *io_base;
	23	struct clk *clk;
	24	};
	25
	26	static inline void xlnx_pr_decoupler_write(struct xlnx_pr_decoupler_data *d,
	27	u32 offset, u32 val)
	28	{
	29	writel(val, d->io_base + offset);
	30	}
	31
	32	static inline u32 xlnx_pr_decouple_read(const struct xlnx_pr_decoupler_data *d,
	33	u32 offset)
	34	{
	35	return readl(d->io_base + offset);
	36	}
	37
	38	static int xlnx_pr_decoupler_enable_set(struct fpga_bridge *bridge, bool enable)
	39	{
	40	int err;
	41	struct xlnx_pr_decoupler_data *priv = bridge->priv;
	42
	43	err = clk_enable(priv->clk);
	44	if (err)
	45	return err;
	46
	47	if (enable)
	48	xlnx_pr_decoupler_write(priv, CTRL_OFFSET, CTRL_CMD_COUPLE);
	49	else
	50	xlnx_pr_decoupler_write(priv, CTRL_OFFSET, CTRL_CMD_DECOUPLE);
	51
	52	clk_disable(priv->clk);
	53
	54	return 0;
	55	}
	56
	57	static int xlnx_pr_decoupler_enable_show(struct fpga_bridge *bridge)
	58	{
	59	const struct xlnx_pr_decoupler_data *priv = bridge->priv;
	60	u32 status;
	61	int err;
	62
	63	err = clk_enable(priv->clk);
	64	if (err)
	65	return err;
	66
	67	status = readl(priv->io_base);
	68
	69	clk_disable(priv->clk);
	70
	71	return !status;
72	}
73
d8d9d936	74	static const struct fpga_bridge_ops xlnx_pr_decoupler_br_ops = {
7e961c12 MF	75	.enable_set = xlnx_pr_decoupler_enable_set,
	76	.enable_show = xlnx_pr_decoupler_enable_show,
	77	};
	78
	79	static const struct of_device_id xlnx_pr_decoupler_of_match[] = {
	80	{ .compatible = "xlnx,pr-decoupler-1.00", },
	81	{ .compatible = "xlnx,pr-decoupler", },
	82	{},
	83	};
	84	MODULE_DEVICE_TABLE(of, xlnx_pr_decoupler_of_match);
	85
	86	static int xlnx_pr_decoupler_probe(struct platform_device *pdev)
	87	{
	88	struct xlnx_pr_decoupler_data *priv;
371cd1b1	89	struct fpga_bridge *br;
7e961c12 MF	90	int err;
	91	struct resource *res;
	92
	93	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
	94	if (!priv)
	95	return -ENOMEM;
	96
	97	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	98	priv->io_base = devm_ioremap_resource(&pdev->dev, res);
	99	if (IS_ERR(priv->io_base))
	100	return PTR_ERR(priv->io_base);
	101
	102	priv->clk = devm_clk_get(&pdev->dev, "aclk");
	103	if (IS_ERR(priv->clk)) {
28910cee SD	104	if (PTR_ERR(priv->clk) != -EPROBE_DEFER)
28910cee SD	105	dev_err(&pdev->dev, "input clock not found\n");
7e961c12 MF	106	return PTR_ERR(priv->clk);
	107	}
	108
	109	err = clk_prepare_enable(priv->clk);
	110	if (err) {
	111	dev_err(&pdev->dev, "unable to enable clock\n");
	112	return err;
	113	}
	114
	115	clk_disable(priv->clk);
	116
213befe0 AT	117	br = devm_fpga_bridge_create(&pdev->dev, "Xilinx PR Decoupler",
213befe0 AT	118	&xlnx_pr_decoupler_br_ops, priv);
371cd1b1 AT	119	if (!br) {
	120	err = -ENOMEM;
	121	goto err_clk;
	122	}
	123
	124	platform_set_drvdata(pdev, br);
7e961c12	125
371cd1b1	126	err = fpga_bridge_register(br);
7e961c12 MF	127	if (err) {
7e961c12 MF	128	dev_err(&pdev->dev, "unable to register Xilinx PR Decoupler");
371cd1b1	129	goto err_clk;
7e961c12 MF	130	}
	131
	132	return 0;
371cd1b1 AT	133
	134	err_clk:
	135	clk_unprepare(priv->clk);
	136
	137	return err;
7e961c12 MF	138	}
	139
	140	static int xlnx_pr_decoupler_remove(struct platform_device *pdev)
	141	{
	142	struct fpga_bridge *bridge = platform_get_drvdata(pdev);
	143	struct xlnx_pr_decoupler_data *p = bridge->priv;
	144
371cd1b1	145	fpga_bridge_unregister(bridge);
7e961c12 MF	146
	147	clk_unprepare(p->clk);
	148
	149	return 0;
	150	}
	151
	152	static struct platform_driver xlnx_pr_decoupler_driver = {
	153	.probe = xlnx_pr_decoupler_probe,
	154	.remove = xlnx_pr_decoupler_remove,
	155	.driver = {
	156	.name = "xlnx_pr_decoupler",
	157	.of_match_table = of_match_ptr(xlnx_pr_decoupler_of_match),
	158	},
	159	};
	160
	161	module_platform_driver(xlnx_pr_decoupler_driver);
	162
	163	MODULE_DESCRIPTION("Xilinx Partial Reconfiguration Decoupler");
	164	MODULE_AUTHOR("Moritz Fischer <mdf@kernel.org>");
	165	MODULE_AUTHOR("Michal Simek <michal.simek@xilinx.com>");
	166	MODULE_LICENSE("GPL v2");