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37784706 MF |
1 | /* |
2 | * Copyright (c) 2011-2015 Xilinx Inc. | |
3 | * Copyright (c) 2015, National Instruments Corp. | |
4 | * | |
5 | * FPGA Manager Driver for Xilinx Zynq, heavily based on xdevcfg driver | |
6 | * in their vendor tree. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; version 2 of the License. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | */ | |
17 | ||
18 | #include <linux/clk.h> | |
19 | #include <linux/completion.h> | |
20 | #include <linux/delay.h> | |
21 | #include <linux/dma-mapping.h> | |
22 | #include <linux/fpga/fpga-mgr.h> | |
23 | #include <linux/interrupt.h> | |
24 | #include <linux/io.h> | |
25 | #include <linux/iopoll.h> | |
26 | #include <linux/module.h> | |
27 | #include <linux/mfd/syscon.h> | |
28 | #include <linux/of_address.h> | |
29 | #include <linux/of_irq.h> | |
30 | #include <linux/pm.h> | |
31 | #include <linux/regmap.h> | |
32 | #include <linux/string.h> | |
33 | ||
34 | /* Offsets into SLCR regmap */ | |
35 | ||
36 | /* FPGA Software Reset Control */ | |
37 | #define SLCR_FPGA_RST_CTRL_OFFSET 0x240 | |
38 | /* Level Shifters Enable */ | |
39 | #define SLCR_LVL_SHFTR_EN_OFFSET 0x900 | |
40 | ||
41 | /* Constant Definitions */ | |
42 | ||
43 | /* Control Register */ | |
44 | #define CTRL_OFFSET 0x00 | |
45 | /* Lock Register */ | |
46 | #define LOCK_OFFSET 0x04 | |
47 | /* Interrupt Status Register */ | |
48 | #define INT_STS_OFFSET 0x0c | |
49 | /* Interrupt Mask Register */ | |
50 | #define INT_MASK_OFFSET 0x10 | |
51 | /* Status Register */ | |
52 | #define STATUS_OFFSET 0x14 | |
53 | /* DMA Source Address Register */ | |
54 | #define DMA_SRC_ADDR_OFFSET 0x18 | |
55 | /* DMA Destination Address Reg */ | |
56 | #define DMA_DST_ADDR_OFFSET 0x1c | |
57 | /* DMA Source Transfer Length */ | |
58 | #define DMA_SRC_LEN_OFFSET 0x20 | |
59 | /* DMA Destination Transfer */ | |
60 | #define DMA_DEST_LEN_OFFSET 0x24 | |
61 | /* Unlock Register */ | |
62 | #define UNLOCK_OFFSET 0x34 | |
63 | /* Misc. Control Register */ | |
64 | #define MCTRL_OFFSET 0x80 | |
65 | ||
66 | /* Control Register Bit definitions */ | |
67 | ||
68 | /* Signal to reset FPGA */ | |
69 | #define CTRL_PCFG_PROG_B_MASK BIT(30) | |
70 | /* Enable PCAP for PR */ | |
71 | #define CTRL_PCAP_PR_MASK BIT(27) | |
72 | /* Enable PCAP */ | |
73 | #define CTRL_PCAP_MODE_MASK BIT(26) | |
74 | ||
75 | /* Miscellaneous Control Register bit definitions */ | |
76 | /* Internal PCAP loopback */ | |
77 | #define MCTRL_PCAP_LPBK_MASK BIT(4) | |
78 | ||
79 | /* Status register bit definitions */ | |
80 | ||
81 | /* FPGA init status */ | |
82 | #define STATUS_DMA_Q_F BIT(31) | |
83 | #define STATUS_PCFG_INIT_MASK BIT(4) | |
84 | ||
85 | /* Interrupt Status/Mask Register Bit definitions */ | |
86 | /* DMA command done */ | |
87 | #define IXR_DMA_DONE_MASK BIT(13) | |
88 | /* DMA and PCAP cmd done */ | |
89 | #define IXR_D_P_DONE_MASK BIT(12) | |
90 | /* FPGA programmed */ | |
91 | #define IXR_PCFG_DONE_MASK BIT(2) | |
92 | #define IXR_ERROR_FLAGS_MASK 0x00F0F860 | |
93 | #define IXR_ALL_MASK 0xF8F7F87F | |
94 | ||
95 | /* Miscellaneous constant values */ | |
96 | ||
97 | /* Invalid DMA addr */ | |
98 | #define DMA_INVALID_ADDRESS GENMASK(31, 0) | |
99 | /* Used to unlock the dev */ | |
100 | #define UNLOCK_MASK 0x757bdf0d | |
101 | /* Timeout for DMA to complete */ | |
102 | #define DMA_DONE_TIMEOUT msecs_to_jiffies(1000) | |
103 | /* Timeout for polling reset bits */ | |
104 | #define INIT_POLL_TIMEOUT 2500000 | |
105 | /* Delay for polling reset bits */ | |
106 | #define INIT_POLL_DELAY 20 | |
107 | ||
108 | /* Masks for controlling stuff in SLCR */ | |
109 | /* Disable all Level shifters */ | |
110 | #define LVL_SHFTR_DISABLE_ALL_MASK 0x0 | |
111 | /* Enable Level shifters from PS to PL */ | |
112 | #define LVL_SHFTR_ENABLE_PS_TO_PL 0xa | |
113 | /* Enable Level shifters from PL to PS */ | |
114 | #define LVL_SHFTR_ENABLE_PL_TO_PS 0xf | |
115 | /* Enable global resets */ | |
116 | #define FPGA_RST_ALL_MASK 0xf | |
117 | /* Disable global resets */ | |
118 | #define FPGA_RST_NONE_MASK 0x0 | |
119 | ||
120 | struct zynq_fpga_priv { | |
121 | struct device *dev; | |
122 | int irq; | |
123 | struct clk *clk; | |
124 | ||
125 | void __iomem *io_base; | |
126 | struct regmap *slcr; | |
127 | ||
128 | struct completion dma_done; | |
129 | }; | |
130 | ||
131 | static inline void zynq_fpga_write(struct zynq_fpga_priv *priv, u32 offset, | |
132 | u32 val) | |
133 | { | |
134 | writel(val, priv->io_base + offset); | |
135 | } | |
136 | ||
137 | static inline u32 zynq_fpga_read(const struct zynq_fpga_priv *priv, | |
138 | u32 offset) | |
139 | { | |
140 | return readl(priv->io_base + offset); | |
141 | } | |
142 | ||
143 | #define zynq_fpga_poll_timeout(priv, addr, val, cond, sleep_us, timeout_us) \ | |
144 | readl_poll_timeout(priv->io_base + addr, val, cond, sleep_us, \ | |
145 | timeout_us) | |
146 | ||
147 | static void zynq_fpga_mask_irqs(struct zynq_fpga_priv *priv) | |
148 | { | |
149 | u32 intr_mask; | |
150 | ||
151 | intr_mask = zynq_fpga_read(priv, INT_MASK_OFFSET); | |
152 | zynq_fpga_write(priv, INT_MASK_OFFSET, | |
153 | intr_mask | IXR_DMA_DONE_MASK | IXR_ERROR_FLAGS_MASK); | |
154 | } | |
155 | ||
156 | static void zynq_fpga_unmask_irqs(struct zynq_fpga_priv *priv) | |
157 | { | |
158 | u32 intr_mask; | |
159 | ||
160 | intr_mask = zynq_fpga_read(priv, INT_MASK_OFFSET); | |
161 | zynq_fpga_write(priv, INT_MASK_OFFSET, | |
162 | intr_mask | |
163 | & ~(IXR_D_P_DONE_MASK | IXR_ERROR_FLAGS_MASK)); | |
164 | } | |
165 | ||
166 | static irqreturn_t zynq_fpga_isr(int irq, void *data) | |
167 | { | |
168 | struct zynq_fpga_priv *priv = data; | |
169 | ||
170 | /* disable DMA and error IRQs */ | |
171 | zynq_fpga_mask_irqs(priv); | |
172 | ||
173 | complete(&priv->dma_done); | |
174 | ||
175 | return IRQ_HANDLED; | |
176 | } | |
177 | ||
1df2865f AT |
178 | static int zynq_fpga_ops_write_init(struct fpga_manager *mgr, |
179 | struct fpga_image_info *info, | |
37784706 MF |
180 | const char *buf, size_t count) |
181 | { | |
182 | struct zynq_fpga_priv *priv; | |
183 | u32 ctrl, status; | |
184 | int err; | |
185 | ||
186 | priv = mgr->priv; | |
187 | ||
188 | err = clk_enable(priv->clk); | |
189 | if (err) | |
190 | return err; | |
191 | ||
192 | /* don't globally reset PL if we're doing partial reconfig */ | |
1df2865f | 193 | if (!(info->flags & FPGA_MGR_PARTIAL_RECONFIG)) { |
37784706 MF |
194 | /* assert AXI interface resets */ |
195 | regmap_write(priv->slcr, SLCR_FPGA_RST_CTRL_OFFSET, | |
196 | FPGA_RST_ALL_MASK); | |
197 | ||
198 | /* disable all level shifters */ | |
199 | regmap_write(priv->slcr, SLCR_LVL_SHFTR_EN_OFFSET, | |
200 | LVL_SHFTR_DISABLE_ALL_MASK); | |
201 | /* enable level shifters from PS to PL */ | |
202 | regmap_write(priv->slcr, SLCR_LVL_SHFTR_EN_OFFSET, | |
203 | LVL_SHFTR_ENABLE_PS_TO_PL); | |
204 | ||
205 | /* create a rising edge on PCFG_INIT. PCFG_INIT follows | |
206 | * PCFG_PROG_B, so we need to poll it after setting PCFG_PROG_B | |
207 | * to make sure the rising edge actually happens. | |
208 | * Note: PCFG_PROG_B is low active, sequence as described in | |
209 | * UG585 v1.10 page 211 | |
210 | */ | |
211 | ctrl = zynq_fpga_read(priv, CTRL_OFFSET); | |
212 | ctrl |= CTRL_PCFG_PROG_B_MASK; | |
213 | ||
214 | zynq_fpga_write(priv, CTRL_OFFSET, ctrl); | |
215 | ||
216 | err = zynq_fpga_poll_timeout(priv, STATUS_OFFSET, status, | |
217 | status & STATUS_PCFG_INIT_MASK, | |
218 | INIT_POLL_DELAY, | |
219 | INIT_POLL_TIMEOUT); | |
220 | if (err) { | |
221 | dev_err(priv->dev, "Timeout waiting for PCFG_INIT"); | |
222 | goto out_err; | |
223 | } | |
224 | ||
225 | ctrl = zynq_fpga_read(priv, CTRL_OFFSET); | |
226 | ctrl &= ~CTRL_PCFG_PROG_B_MASK; | |
227 | ||
228 | zynq_fpga_write(priv, CTRL_OFFSET, ctrl); | |
229 | ||
230 | err = zynq_fpga_poll_timeout(priv, STATUS_OFFSET, status, | |
231 | !(status & STATUS_PCFG_INIT_MASK), | |
232 | INIT_POLL_DELAY, | |
233 | INIT_POLL_TIMEOUT); | |
234 | if (err) { | |
235 | dev_err(priv->dev, "Timeout waiting for !PCFG_INIT"); | |
236 | goto out_err; | |
237 | } | |
238 | ||
239 | ctrl = zynq_fpga_read(priv, CTRL_OFFSET); | |
240 | ctrl |= CTRL_PCFG_PROG_B_MASK; | |
241 | ||
242 | zynq_fpga_write(priv, CTRL_OFFSET, ctrl); | |
243 | ||
244 | err = zynq_fpga_poll_timeout(priv, STATUS_OFFSET, status, | |
245 | status & STATUS_PCFG_INIT_MASK, | |
246 | INIT_POLL_DELAY, | |
247 | INIT_POLL_TIMEOUT); | |
248 | if (err) { | |
249 | dev_err(priv->dev, "Timeout waiting for PCFG_INIT"); | |
250 | goto out_err; | |
251 | } | |
252 | } | |
253 | ||
254 | /* set configuration register with following options: | |
255 | * - enable PCAP interface | |
256 | * - set throughput for maximum speed | |
257 | * - set CPU in user mode | |
258 | */ | |
259 | ctrl = zynq_fpga_read(priv, CTRL_OFFSET); | |
260 | zynq_fpga_write(priv, CTRL_OFFSET, | |
261 | (CTRL_PCAP_PR_MASK | CTRL_PCAP_MODE_MASK | ctrl)); | |
262 | ||
263 | /* check that we have room in the command queue */ | |
264 | status = zynq_fpga_read(priv, STATUS_OFFSET); | |
265 | if (status & STATUS_DMA_Q_F) { | |
266 | dev_err(priv->dev, "DMA command queue full"); | |
267 | err = -EBUSY; | |
268 | goto out_err; | |
269 | } | |
270 | ||
271 | /* ensure internal PCAP loopback is disabled */ | |
272 | ctrl = zynq_fpga_read(priv, MCTRL_OFFSET); | |
273 | zynq_fpga_write(priv, MCTRL_OFFSET, (~MCTRL_PCAP_LPBK_MASK & ctrl)); | |
274 | ||
275 | clk_disable(priv->clk); | |
276 | ||
277 | return 0; | |
278 | ||
279 | out_err: | |
280 | clk_disable(priv->clk); | |
281 | ||
282 | return err; | |
283 | } | |
284 | ||
285 | static int zynq_fpga_ops_write(struct fpga_manager *mgr, | |
286 | const char *buf, size_t count) | |
287 | { | |
288 | struct zynq_fpga_priv *priv; | |
289 | int err; | |
290 | char *kbuf; | |
4d10eaff | 291 | size_t in_count; |
37784706 | 292 | dma_addr_t dma_addr; |
4d10eaff | 293 | u32 transfer_length; |
37784706 MF |
294 | u32 intr_status; |
295 | ||
296 | in_count = count; | |
297 | priv = mgr->priv; | |
298 | ||
299 | kbuf = dma_alloc_coherent(priv->dev, count, &dma_addr, GFP_KERNEL); | |
300 | if (!kbuf) | |
301 | return -ENOMEM; | |
302 | ||
303 | memcpy(kbuf, buf, count); | |
304 | ||
37784706 MF |
305 | /* enable clock */ |
306 | err = clk_enable(priv->clk); | |
307 | if (err) | |
308 | goto out_free; | |
309 | ||
310 | zynq_fpga_write(priv, INT_STS_OFFSET, IXR_ALL_MASK); | |
311 | ||
312 | reinit_completion(&priv->dma_done); | |
313 | ||
314 | /* enable DMA and error IRQs */ | |
315 | zynq_fpga_unmask_irqs(priv); | |
316 | ||
317 | /* the +1 in the src addr is used to hold off on DMA_DONE IRQ | |
318 | * until both AXI and PCAP are done ... | |
319 | */ | |
320 | zynq_fpga_write(priv, DMA_SRC_ADDR_OFFSET, (u32)(dma_addr) + 1); | |
321 | zynq_fpga_write(priv, DMA_DST_ADDR_OFFSET, (u32)DMA_INVALID_ADDRESS); | |
322 | ||
323 | /* convert #bytes to #words */ | |
324 | transfer_length = (count + 3) / 4; | |
325 | ||
326 | zynq_fpga_write(priv, DMA_SRC_LEN_OFFSET, transfer_length); | |
327 | zynq_fpga_write(priv, DMA_DEST_LEN_OFFSET, 0); | |
328 | ||
329 | wait_for_completion(&priv->dma_done); | |
330 | ||
331 | intr_status = zynq_fpga_read(priv, INT_STS_OFFSET); | |
332 | zynq_fpga_write(priv, INT_STS_OFFSET, intr_status); | |
333 | ||
334 | if (!((intr_status & IXR_D_P_DONE_MASK) == IXR_D_P_DONE_MASK)) { | |
335 | dev_err(priv->dev, "Error configuring FPGA"); | |
336 | err = -EFAULT; | |
337 | } | |
338 | ||
339 | clk_disable(priv->clk); | |
340 | ||
341 | out_free: | |
342 | dma_free_coherent(priv->dev, in_count, kbuf, dma_addr); | |
343 | ||
344 | return err; | |
345 | } | |
346 | ||
1df2865f AT |
347 | static int zynq_fpga_ops_write_complete(struct fpga_manager *mgr, |
348 | struct fpga_image_info *info) | |
37784706 MF |
349 | { |
350 | struct zynq_fpga_priv *priv = mgr->priv; | |
351 | int err; | |
352 | u32 intr_status; | |
353 | ||
354 | err = clk_enable(priv->clk); | |
355 | if (err) | |
356 | return err; | |
357 | ||
358 | err = zynq_fpga_poll_timeout(priv, INT_STS_OFFSET, intr_status, | |
359 | intr_status & IXR_PCFG_DONE_MASK, | |
360 | INIT_POLL_DELAY, | |
361 | INIT_POLL_TIMEOUT); | |
362 | ||
363 | clk_disable(priv->clk); | |
364 | ||
365 | if (err) | |
366 | return err; | |
367 | ||
368 | /* for the partial reconfig case we didn't touch the level shifters */ | |
1df2865f | 369 | if (!(info->flags & FPGA_MGR_PARTIAL_RECONFIG)) { |
37784706 MF |
370 | /* enable level shifters from PL to PS */ |
371 | regmap_write(priv->slcr, SLCR_LVL_SHFTR_EN_OFFSET, | |
372 | LVL_SHFTR_ENABLE_PL_TO_PS); | |
373 | ||
374 | /* deassert AXI interface resets */ | |
375 | regmap_write(priv->slcr, SLCR_FPGA_RST_CTRL_OFFSET, | |
376 | FPGA_RST_NONE_MASK); | |
377 | } | |
378 | ||
379 | return 0; | |
380 | } | |
381 | ||
382 | static enum fpga_mgr_states zynq_fpga_ops_state(struct fpga_manager *mgr) | |
383 | { | |
384 | int err; | |
385 | u32 intr_status; | |
386 | struct zynq_fpga_priv *priv; | |
387 | ||
388 | priv = mgr->priv; | |
389 | ||
390 | err = clk_enable(priv->clk); | |
391 | if (err) | |
392 | return FPGA_MGR_STATE_UNKNOWN; | |
393 | ||
394 | intr_status = zynq_fpga_read(priv, INT_STS_OFFSET); | |
395 | clk_disable(priv->clk); | |
396 | ||
397 | if (intr_status & IXR_PCFG_DONE_MASK) | |
398 | return FPGA_MGR_STATE_OPERATING; | |
399 | ||
400 | return FPGA_MGR_STATE_UNKNOWN; | |
401 | } | |
402 | ||
403 | static const struct fpga_manager_ops zynq_fpga_ops = { | |
404 | .state = zynq_fpga_ops_state, | |
405 | .write_init = zynq_fpga_ops_write_init, | |
406 | .write = zynq_fpga_ops_write, | |
407 | .write_complete = zynq_fpga_ops_write_complete, | |
408 | }; | |
409 | ||
410 | static int zynq_fpga_probe(struct platform_device *pdev) | |
411 | { | |
412 | struct device *dev = &pdev->dev; | |
413 | struct zynq_fpga_priv *priv; | |
414 | struct resource *res; | |
415 | int err; | |
416 | ||
417 | priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); | |
418 | if (!priv) | |
419 | return -ENOMEM; | |
420 | ||
37784706 MF |
421 | priv->dev = dev; |
422 | ||
423 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
424 | priv->io_base = devm_ioremap_resource(dev, res); | |
425 | if (IS_ERR(priv->io_base)) | |
426 | return PTR_ERR(priv->io_base); | |
427 | ||
428 | priv->slcr = syscon_regmap_lookup_by_phandle(dev->of_node, | |
429 | "syscon"); | |
430 | if (IS_ERR(priv->slcr)) { | |
431 | dev_err(dev, "unable to get zynq-slcr regmap"); | |
432 | return PTR_ERR(priv->slcr); | |
433 | } | |
434 | ||
435 | init_completion(&priv->dma_done); | |
436 | ||
437 | priv->irq = platform_get_irq(pdev, 0); | |
438 | if (priv->irq < 0) { | |
439 | dev_err(dev, "No IRQ available"); | |
440 | return priv->irq; | |
441 | } | |
442 | ||
443 | err = devm_request_irq(dev, priv->irq, zynq_fpga_isr, 0, | |
444 | dev_name(dev), priv); | |
445 | if (err) { | |
446 | dev_err(dev, "unable to request IRQ"); | |
447 | return err; | |
448 | } | |
449 | ||
450 | priv->clk = devm_clk_get(dev, "ref_clk"); | |
451 | if (IS_ERR(priv->clk)) { | |
452 | dev_err(dev, "input clock not found"); | |
453 | return PTR_ERR(priv->clk); | |
454 | } | |
455 | ||
456 | err = clk_prepare_enable(priv->clk); | |
457 | if (err) { | |
458 | dev_err(dev, "unable to enable clock"); | |
459 | return err; | |
460 | } | |
461 | ||
462 | /* unlock the device */ | |
463 | zynq_fpga_write(priv, UNLOCK_OFFSET, UNLOCK_MASK); | |
464 | ||
465 | clk_disable(priv->clk); | |
466 | ||
467 | err = fpga_mgr_register(dev, "Xilinx Zynq FPGA Manager", | |
468 | &zynq_fpga_ops, priv); | |
469 | if (err) { | |
470 | dev_err(dev, "unable to register FPGA manager"); | |
6376931b | 471 | clk_unprepare(priv->clk); |
37784706 MF |
472 | return err; |
473 | } | |
474 | ||
475 | return 0; | |
476 | } | |
477 | ||
478 | static int zynq_fpga_remove(struct platform_device *pdev) | |
479 | { | |
480 | struct zynq_fpga_priv *priv; | |
28f98a12 | 481 | struct fpga_manager *mgr; |
37784706 | 482 | |
28f98a12 MF |
483 | mgr = platform_get_drvdata(pdev); |
484 | priv = mgr->priv; | |
37784706 | 485 | |
28f98a12 | 486 | fpga_mgr_unregister(&pdev->dev); |
37784706 | 487 | |
6376931b | 488 | clk_unprepare(priv->clk); |
37784706 MF |
489 | |
490 | return 0; | |
491 | } | |
492 | ||
493 | #ifdef CONFIG_OF | |
494 | static const struct of_device_id zynq_fpga_of_match[] = { | |
495 | { .compatible = "xlnx,zynq-devcfg-1.0", }, | |
496 | {}, | |
497 | }; | |
498 | ||
499 | MODULE_DEVICE_TABLE(of, zynq_fpga_of_match); | |
500 | #endif | |
501 | ||
502 | static struct platform_driver zynq_fpga_driver = { | |
503 | .probe = zynq_fpga_probe, | |
504 | .remove = zynq_fpga_remove, | |
505 | .driver = { | |
506 | .name = "zynq_fpga_manager", | |
507 | .of_match_table = of_match_ptr(zynq_fpga_of_match), | |
508 | }, | |
509 | }; | |
510 | ||
511 | module_platform_driver(zynq_fpga_driver); | |
512 | ||
513 | MODULE_AUTHOR("Moritz Fischer <moritz.fischer@ettus.com>"); | |
514 | MODULE_AUTHOR("Michal Simek <michal.simek@xilinx.com>"); | |
515 | MODULE_DESCRIPTION("Xilinx Zynq FPGA Manager"); | |
516 | MODULE_LICENSE("GPL v2"); |