[mirror_ubuntu-hirsute-kernel.git] / drivers / gpio / gpio-74x164.c

/*
 *  74Hx164 - Generic serial-in/parallel-out 8-bits shift register GPIO driver
 *
 *  Copyright (C) 2010 Gabor Juhos <juhosg@openwrt.org>
 *  Copyright (C) 2010 Miguel Gaio <miguel.gaio@efixo.com>
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License version 2 as
 *  published by the Free Software Foundation.
 */

#include <linux/init.h>
#include <linux/mutex.h>
#include <linux/spi/spi.h>
#include <linux/gpio.h>
#include <linux/of_gpio.h>
#include <linux/slab.h>
#include <linux/module.h>

#define GEN_74X164_NUMBER_GPIOS	8

struct gen_74x164_chip {
	struct gpio_chip	gpio_chip;
	struct mutex		lock;
	u32			registers;
	u8			buffer[0];
};

static struct gen_74x164_chip *gpio_to_74x164_chip(struct gpio_chip *gc)
{
	return container_of(gc, struct gen_74x164_chip, gpio_chip);
}

static int __gen_74x164_write_config(struct gen_74x164_chip *chip)
{
	struct spi_device *spi = to_spi_device(chip->gpio_chip.parent);
	struct spi_message message;
	struct spi_transfer *msg_buf;
	int i, ret = 0;

	msg_buf = kzalloc(chip->registers * sizeof(struct spi_transfer),
			GFP_KERNEL);
	if (!msg_buf)
		return -ENOMEM;

	spi_message_init(&message);

	/*
	 * Since the registers are chained, every byte sent will make
	 * the previous byte shift to the next register in the
	 * chain. Thus, the first byte send will end up in the last
	 * register at the end of the transfer. So, to have a logical
	 * numbering, send the bytes in reverse order so that the last
	 * byte of the buffer will end up in the last register.
	 */
	for (i = chip->registers - 1; i >= 0; i--) {
		msg_buf[i].tx_buf = chip->buffer + i;
		msg_buf[i].len = sizeof(u8);
		spi_message_add_tail(msg_buf + i, &message);
	}

	ret = spi_sync(spi, &message);

	kfree(msg_buf);

	return ret;
}

static int gen_74x164_get_value(struct gpio_chip *gc, unsigned offset)
{
	struct gen_74x164_chip *chip = gpio_to_74x164_chip(gc);
	u8 bank = offset / 8;
	u8 pin = offset % 8;
	int ret;

	mutex_lock(&chip->lock);
	ret = (chip->buffer[bank] >> pin) & 0x1;
	mutex_unlock(&chip->lock);

	return ret;
}

static void gen_74x164_set_value(struct gpio_chip *gc,
		unsigned offset, int val)
{
	struct gen_74x164_chip *chip = gpio_to_74x164_chip(gc);
	u8 bank = offset / 8;
	u8 pin = offset % 8;

	mutex_lock(&chip->lock);
	if (val)
		chip->buffer[bank] |= (1 << pin);
	else
		chip->buffer[bank] &= ~(1 << pin);

	__gen_74x164_write_config(chip);
	mutex_unlock(&chip->lock);
}

static int gen_74x164_direction_output(struct gpio_chip *gc,
		unsigned offset, int val)
{
	gen_74x164_set_value(gc, offset, val);
	return 0;
}

static int gen_74x164_probe(struct spi_device *spi)
{
	struct gen_74x164_chip *chip;
	u32 nregs;
	int ret;

	/*
	 * bits_per_word cannot be configured in platform data
	 */
	spi->bits_per_word = 8;

	ret = spi_setup(spi);
	if (ret < 0)
		return ret;

	if (of_property_read_u32(spi->dev.of_node, "registers-number",
				 &nregs)) {
		dev_err(&spi->dev,
			"Missing registers-number property in the DT.\n");
		return -EINVAL;
	}

	chip = devm_kzalloc(&spi->dev, sizeof(*chip) + nregs, GFP_KERNEL);
	if (!chip)
		return -ENOMEM;

	spi_set_drvdata(spi, chip);

	chip->gpio_chip.label = spi->modalias;
	chip->gpio_chip.direction_output = gen_74x164_direction_output;
	chip->gpio_chip.get = gen_74x164_get_value;
	chip->gpio_chip.set = gen_74x164_set_value;
	chip->gpio_chip.base = -1;

	chip->registers = nregs;
	chip->gpio_chip.ngpio = GEN_74X164_NUMBER_GPIOS * chip->registers;

	chip->gpio_chip.can_sleep = true;
	chip->gpio_chip.parent = &spi->dev;
	chip->gpio_chip.owner = THIS_MODULE;

	mutex_init(&chip->lock);

	ret = __gen_74x164_write_config(chip);
	if (ret) {
		dev_err(&spi->dev, "Failed writing: %d\n", ret);
		goto exit_destroy;
	}

	ret = gpiochip_add(&chip->gpio_chip);
	if (!ret)
		return 0;

exit_destroy:
	mutex_destroy(&chip->lock);

	return ret;
}

static int gen_74x164_remove(struct spi_device *spi)
{
	struct gen_74x164_chip *chip = spi_get_drvdata(spi);

	gpiochip_remove(&chip->gpio_chip);
	mutex_destroy(&chip->lock);

	return 0;
}

static const struct of_device_id gen_74x164_dt_ids[] = {
	{ .compatible = "fairchild,74hc595" },
	{},
};
MODULE_DEVICE_TABLE(of, gen_74x164_dt_ids);

static struct spi_driver gen_74x164_driver = {
	.driver = {
		.name		= "74x164",
		.of_match_table	= gen_74x164_dt_ids,
	},
	.probe		= gen_74x164_probe,
	.remove		= gen_74x164_remove,
};
module_spi_driver(gen_74x164_driver);

MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
MODULE_AUTHOR("Miguel Gaio <miguel.gaio@efixo.com>");
MODULE_DESCRIPTION("GPIO expander driver for 74X164 8-bits shift register");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
ead6db08 MG	1	/*
	2	* 74Hx164 - Generic serial-in/parallel-out 8-bits shift register GPIO driver
	3	*
	4	* Copyright (C) 2010 Gabor Juhos <juhosg@openwrt.org>
	5	* Copyright (C) 2010 Miguel Gaio <miguel.gaio@efixo.com>
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*/
	11
	12	#include <linux/init.h>
	13	#include <linux/mutex.h>
	14	#include <linux/spi/spi.h>
ead6db08	15	#include <linux/gpio.h>
20bc4d5d	16	#include <linux/of_gpio.h>
ead6db08	17	#include <linux/slab.h>
bb207ef1	18	#include <linux/module.h>
ead6db08	19
20bc4d5d MR	20	#define GEN_74X164_NUMBER_GPIOS 8
20bc4d5d MR	21
ead6db08	22	struct gen_74x164_chip {
ead6db08 MG	23	struct gpio_chip gpio_chip;
ead6db08 MG	24	struct mutex lock;
20bc4d5d	25	u32 registers;
410f4574	26	u8 buffer[0];
ead6db08 MG	27	};
ead6db08 MG	28
12610be3	29	static struct gen_74x164_chip gpio_to_74x164_chip(struct gpio_chip gc)
ead6db08 MG	30	{
	31	return container_of(gc, struct gen_74x164_chip, gpio_chip);
	32	}
	33
	34	static int __gen_74x164_write_config(struct gen_74x164_chip *chip)
	35	{
58383c78	36	struct spi_device *spi = to_spi_device(chip->gpio_chip.parent);
20bc4d5d MR	37	struct spi_message message;
	38	struct spi_transfer *msg_buf;
	39	int i, ret = 0;
	40
	41	msg_buf = kzalloc(chip->registers * sizeof(struct spi_transfer),
	42	GFP_KERNEL);
	43	if (!msg_buf)
	44	return -ENOMEM;
	45
	46	spi_message_init(&message);
	47
	48	/*
	49	* Since the registers are chained, every byte sent will make
	50	* the previous byte shift to the next register in the
	51	* chain. Thus, the first byte send will end up in the last
	52	* register at the end of the transfer. So, to have a logical
	53	* numbering, send the bytes in reverse order so that the last
	54	* byte of the buffer will end up in the last register.
	55	*/
	56	for (i = chip->registers - 1; i >= 0; i--) {
bcc0562c	57	msg_buf[i].tx_buf = chip->buffer + i;
20bc4d5d MR	58	msg_buf[i].len = sizeof(u8);
	59	spi_message_add_tail(msg_buf + i, &message);
	60	}
	61
bcc0562c	62	ret = spi_sync(spi, &message);
20bc4d5d MR	63
	64	kfree(msg_buf);
	65
	66	return ret;
ead6db08 MG	67	}
ead6db08 MG	68
ead6db08 MG	69	static int gen_74x164_get_value(struct gpio_chip *gc, unsigned offset)
ead6db08 MG	70	{
12610be3	71	struct gen_74x164_chip *chip = gpio_to_74x164_chip(gc);
20bc4d5d MR	72	u8 bank = offset / 8;
20bc4d5d MR	73	u8 pin = offset % 8;
ead6db08 MG	74	int ret;
	75
	76	mutex_lock(&chip->lock);
20bc4d5d	77	ret = (chip->buffer[bank] >> pin) & 0x1;
ead6db08 MG	78	mutex_unlock(&chip->lock);
	79
	80	return ret;
	81	}
	82
	83	static void gen_74x164_set_value(struct gpio_chip *gc,
	84	unsigned offset, int val)
	85	{
12610be3	86	struct gen_74x164_chip *chip = gpio_to_74x164_chip(gc);
20bc4d5d MR	87	u8 bank = offset / 8;
20bc4d5d MR	88	u8 pin = offset % 8;
ead6db08 MG	89
	90	mutex_lock(&chip->lock);
	91	if (val)
20bc4d5d	92	chip->buffer[bank] \|= (1 << pin);
ead6db08	93	else
20bc4d5d	94	chip->buffer[bank] &= ~(1 << pin);
ead6db08 MG	95
	96	__gen_74x164_write_config(chip);
	97	mutex_unlock(&chip->lock);
	98	}
	99
a3cc68c3 HS	100	static int gen_74x164_direction_output(struct gpio_chip *gc,
	101	unsigned offset, int val)
	102	{
	103	gen_74x164_set_value(gc, offset, val);
	104	return 0;
	105	}
	106
3836309d	107	static int gen_74x164_probe(struct spi_device *spi)
ead6db08 MG	108	{
ead6db08 MG	109	struct gen_74x164_chip *chip;
410f4574	110	u32 nregs;
ead6db08 MG	111	int ret;
ead6db08 MG	112
ead6db08 MG	113	/*
	114	* bits_per_word cannot be configured in platform data
	115	*/
	116	spi->bits_per_word = 8;
	117
	118	ret = spi_setup(spi);
	119	if (ret < 0)
	120	return ret;
	121
410f4574 GU	122	if (of_property_read_u32(spi->dev.of_node, "registers-number",
	123	&nregs)) {
	124	dev_err(&spi->dev,
	125	"Missing registers-number property in the DT.\n");
	126	return -EINVAL;
	127	}
	128
	129	chip = devm_kzalloc(&spi->dev, sizeof(*chip) + nregs, GFP_KERNEL);
ead6db08 MG	130	if (!chip)
	131	return -ENOMEM;
	132
6c0cf42b	133	spi_set_drvdata(spi, chip);
ead6db08	134
a3cc68c3 HS	135	chip->gpio_chip.label = spi->modalias;
a3cc68c3 HS	136	chip->gpio_chip.direction_output = gen_74x164_direction_output;
ead6db08 MG	137	chip->gpio_chip.get = gen_74x164_get_value;
ead6db08 MG	138	chip->gpio_chip.set = gen_74x164_set_value;
61e73804	139	chip->gpio_chip.base = -1;
20bc4d5d	140
410f4574	141	chip->registers = nregs;
20bc4d5d	142	chip->gpio_chip.ngpio = GEN_74X164_NUMBER_GPIOS * chip->registers;
20bc4d5d	143
9fb1f39e	144	chip->gpio_chip.can_sleep = true;
58383c78	145	chip->gpio_chip.parent = &spi->dev;
ead6db08 MG	146	chip->gpio_chip.owner = THIS_MODULE;
ead6db08 MG	147
bcc0562c AS	148	mutex_init(&chip->lock);
bcc0562c AS	149
ead6db08 MG	150	ret = __gen_74x164_write_config(chip);
	151	if (ret) {
	152	dev_err(&spi->dev, "Failed writing: %d\n", ret);
	153	goto exit_destroy;
	154	}
	155
	156	ret = gpiochip_add(&chip->gpio_chip);
bcc0562c AS	157	if (!ret)
bcc0562c AS	158	return 0;
ead6db08 MG	159
ead6db08 MG	160	exit_destroy:
ead6db08	161	mutex_destroy(&chip->lock);
bcc0562c	162
ead6db08 MG	163	return ret;
	164	}
	165
206210ce	166	static int gen_74x164_remove(struct spi_device *spi)
ead6db08	167	{
bcc0562c	168	struct gen_74x164_chip *chip = spi_get_drvdata(spi);
ead6db08	169
9f5132ae	170	gpiochip_remove(&chip->gpio_chip);
9f5132ae	171	mutex_destroy(&chip->lock);
ead6db08	172
9f5132ae	173	return 0;
ead6db08 MG	174	}
ead6db08 MG	175
0a90a9fb MR	176	static const struct of_device_id gen_74x164_dt_ids[] = {
	177	{ .compatible = "fairchild,74hc595" },
	178	{},
	179	};
	180	MODULE_DEVICE_TABLE(of, gen_74x164_dt_ids);
	181
ead6db08 MG	182	static struct spi_driver gen_74x164_driver = {
ead6db08 MG	183	.driver = {
a3cc68c3	184	.name = "74x164",
187a53a5	185	.of_match_table = gen_74x164_dt_ids,
ead6db08 MG	186	},
ead6db08 MG	187	.probe = gen_74x164_probe,
8283c4ff	188	.remove = gen_74x164_remove,
ead6db08	189	};
ab3b8782	190	module_spi_driver(gen_74x164_driver);
ead6db08 MG	191
	192	MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
	193	MODULE_AUTHOR("Miguel Gaio <miguel.gaio@efixo.com>");
	194	MODULE_DESCRIPTION("GPIO expander driver for 74X164 8-bits shift register");
	195	MODULE_LICENSE("GPL v2");