[mirror_ubuntu-focal-kernel.git] / drivers / gpio / gpio-altera.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Copyright (C) 2013 Altera Corporation
 * Based on gpio-mpc8xxx.c
 */

#include <linux/io.h>
#include <linux/module.h>
#include <linux/gpio/driver.h>
#include <linux/of_gpio.h> /* For of_mm_gpio_chip */
#include <linux/platform_device.h>

#define ALTERA_GPIO_MAX_NGPIO		32
#define ALTERA_GPIO_DATA		0x0
#define ALTERA_GPIO_DIR			0x4
#define ALTERA_GPIO_IRQ_MASK		0x8
#define ALTERA_GPIO_EDGE_CAP		0xc

/**
* struct altera_gpio_chip
* @mmchip		: memory mapped chip structure.
* @gpio_lock		: synchronization lock so that new irq/set/get requests
*			  will be blocked until the current one completes.
* @interrupt_trigger	: specifies the hardware configured IRQ trigger type
*			  (rising, falling, both, high)
* @mapped_irq		: kernel mapped irq number.
*/
struct altera_gpio_chip {
	struct of_mm_gpio_chip mmchip;
	raw_spinlock_t gpio_lock;
	int interrupt_trigger;
	int mapped_irq;
	struct irq_chip irq_chip;
};

static void altera_gpio_irq_unmask(struct irq_data *d)
{
	struct altera_gpio_chip *altera_gc;
	struct of_mm_gpio_chip *mm_gc;
	unsigned long flags;
	u32 intmask;

	altera_gc = gpiochip_get_data(irq_data_get_irq_chip_data(d));
	mm_gc = &altera_gc->mmchip;

	raw_spin_lock_irqsave(&altera_gc->gpio_lock, flags);
	intmask = readl(mm_gc->regs + ALTERA_GPIO_IRQ_MASK);
	/* Set ALTERA_GPIO_IRQ_MASK bit to unmask */
	intmask |= BIT(irqd_to_hwirq(d));
	writel(intmask, mm_gc->regs + ALTERA_GPIO_IRQ_MASK);
	raw_spin_unlock_irqrestore(&altera_gc->gpio_lock, flags);
}

static void altera_gpio_irq_mask(struct irq_data *d)
{
	struct altera_gpio_chip *altera_gc;
	struct of_mm_gpio_chip *mm_gc;
	unsigned long flags;
	u32 intmask;

	altera_gc = gpiochip_get_data(irq_data_get_irq_chip_data(d));
	mm_gc = &altera_gc->mmchip;

	raw_spin_lock_irqsave(&altera_gc->gpio_lock, flags);
	intmask = readl(mm_gc->regs + ALTERA_GPIO_IRQ_MASK);
	/* Clear ALTERA_GPIO_IRQ_MASK bit to mask */
	intmask &= ~BIT(irqd_to_hwirq(d));
	writel(intmask, mm_gc->regs + ALTERA_GPIO_IRQ_MASK);
	raw_spin_unlock_irqrestore(&altera_gc->gpio_lock, flags);
}

/**
 * This controller's IRQ type is synthesized in hardware, so this function
 * just checks if the requested set_type matches the synthesized IRQ type
 */
static int altera_gpio_irq_set_type(struct irq_data *d,
				   unsigned int type)
{
	struct altera_gpio_chip *altera_gc;

	altera_gc = gpiochip_get_data(irq_data_get_irq_chip_data(d));

	if (type == IRQ_TYPE_NONE) {
		irq_set_handler_locked(d, handle_bad_irq);
		return 0;
	}
	if (type == altera_gc->interrupt_trigger) {
		if (type == IRQ_TYPE_LEVEL_HIGH)
			irq_set_handler_locked(d, handle_level_irq);
		else
			irq_set_handler_locked(d, handle_simple_irq);
		return 0;
	}
	irq_set_handler_locked(d, handle_bad_irq);
	return -EINVAL;
}

static unsigned int altera_gpio_irq_startup(struct irq_data *d)
{
	altera_gpio_irq_unmask(d);

	return 0;
}

static int altera_gpio_get(struct gpio_chip *gc, unsigned offset)
{
	struct of_mm_gpio_chip *mm_gc;

	mm_gc = to_of_mm_gpio_chip(gc);

	return !!(readl(mm_gc->regs + ALTERA_GPIO_DATA) & BIT(offset));
}

static void altera_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
{
	struct of_mm_gpio_chip *mm_gc;
	struct altera_gpio_chip *chip;
	unsigned long flags;
	unsigned int data_reg;

	mm_gc = to_of_mm_gpio_chip(gc);
	chip = gpiochip_get_data(gc);

	raw_spin_lock_irqsave(&chip->gpio_lock, flags);
	data_reg = readl(mm_gc->regs + ALTERA_GPIO_DATA);
	if (value)
		data_reg |= BIT(offset);
	else
		data_reg &= ~BIT(offset);
	writel(data_reg, mm_gc->regs + ALTERA_GPIO_DATA);
	raw_spin_unlock_irqrestore(&chip->gpio_lock, flags);
}

static int altera_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
{
	struct of_mm_gpio_chip *mm_gc;
	struct altera_gpio_chip *chip;
	unsigned long flags;
	unsigned int gpio_ddr;

	mm_gc = to_of_mm_gpio_chip(gc);
	chip = gpiochip_get_data(gc);

	raw_spin_lock_irqsave(&chip->gpio_lock, flags);
	/* Set pin as input, assumes software controlled IP */
	gpio_ddr = readl(mm_gc->regs + ALTERA_GPIO_DIR);
	gpio_ddr &= ~BIT(offset);
	writel(gpio_ddr, mm_gc->regs + ALTERA_GPIO_DIR);
	raw_spin_unlock_irqrestore(&chip->gpio_lock, flags);

	return 0;
}

static int altera_gpio_direction_output(struct gpio_chip *gc,
		unsigned offset, int value)
{
	struct of_mm_gpio_chip *mm_gc;
	struct altera_gpio_chip *chip;
	unsigned long flags;
	unsigned int data_reg, gpio_ddr;

	mm_gc = to_of_mm_gpio_chip(gc);
	chip = gpiochip_get_data(gc);

	raw_spin_lock_irqsave(&chip->gpio_lock, flags);
	/* Sets the GPIO value */
	data_reg = readl(mm_gc->regs + ALTERA_GPIO_DATA);
	if (value)
		data_reg |= BIT(offset);
	else
		data_reg &= ~BIT(offset);
	writel(data_reg, mm_gc->regs + ALTERA_GPIO_DATA);

	/* Set pin as output, assumes software controlled IP */
	gpio_ddr = readl(mm_gc->regs + ALTERA_GPIO_DIR);
	gpio_ddr |= BIT(offset);
	writel(gpio_ddr, mm_gc->regs + ALTERA_GPIO_DIR);
	raw_spin_unlock_irqrestore(&chip->gpio_lock, flags);

	return 0;
}

static void altera_gpio_irq_edge_handler(struct irq_desc *desc)
{
	struct altera_gpio_chip *altera_gc;
	struct irq_chip *chip;
	struct of_mm_gpio_chip *mm_gc;
	struct irq_domain *irqdomain;
	unsigned long status;
	int i;

	altera_gc = gpiochip_get_data(irq_desc_get_handler_data(desc));
	chip = irq_desc_get_chip(desc);
	mm_gc = &altera_gc->mmchip;
	irqdomain = altera_gc->mmchip.gc.irq.domain;

	chained_irq_enter(chip, desc);

	while ((status =
	      (readl(mm_gc->regs + ALTERA_GPIO_EDGE_CAP) &
	      readl(mm_gc->regs + ALTERA_GPIO_IRQ_MASK)))) {
		writel(status, mm_gc->regs + ALTERA_GPIO_EDGE_CAP);
		for_each_set_bit(i, &status, mm_gc->gc.ngpio) {
			generic_handle_irq(irq_find_mapping(irqdomain, i));
		}
	}

	chained_irq_exit(chip, desc);
}

static void altera_gpio_irq_leveL_high_handler(struct irq_desc *desc)
{
	struct altera_gpio_chip *altera_gc;
	struct irq_chip *chip;
	struct of_mm_gpio_chip *mm_gc;
	struct irq_domain *irqdomain;
	unsigned long status;
	int i;

	altera_gc = gpiochip_get_data(irq_desc_get_handler_data(desc));
	chip = irq_desc_get_chip(desc);
	mm_gc = &altera_gc->mmchip;
	irqdomain = altera_gc->mmchip.gc.irq.domain;

	chained_irq_enter(chip, desc);

	status = readl(mm_gc->regs + ALTERA_GPIO_DATA);
	status &= readl(mm_gc->regs + ALTERA_GPIO_IRQ_MASK);

	for_each_set_bit(i, &status, mm_gc->gc.ngpio) {
		generic_handle_irq(irq_find_mapping(irqdomain, i));
	}
	chained_irq_exit(chip, desc);
}

static int altera_gpio_probe(struct platform_device *pdev)
{
	struct device_node *node = pdev->dev.of_node;
	int reg, ret;
	struct altera_gpio_chip *altera_gc;
	struct gpio_irq_chip *girq;

	altera_gc = devm_kzalloc(&pdev->dev, sizeof(*altera_gc), GFP_KERNEL);
	if (!altera_gc)
		return -ENOMEM;

	raw_spin_lock_init(&altera_gc->gpio_lock);

	if (of_property_read_u32(node, "altr,ngpio", &reg))
		/* By default assume maximum ngpio */
		altera_gc->mmchip.gc.ngpio = ALTERA_GPIO_MAX_NGPIO;
	else
		altera_gc->mmchip.gc.ngpio = reg;

	if (altera_gc->mmchip.gc.ngpio > ALTERA_GPIO_MAX_NGPIO) {
		dev_warn(&pdev->dev,
			"ngpio is greater than %d, defaulting to %d\n",
			ALTERA_GPIO_MAX_NGPIO, ALTERA_GPIO_MAX_NGPIO);
		altera_gc->mmchip.gc.ngpio = ALTERA_GPIO_MAX_NGPIO;
	}

	altera_gc->mmchip.gc.direction_input	= altera_gpio_direction_input;
	altera_gc->mmchip.gc.direction_output	= altera_gpio_direction_output;
	altera_gc->mmchip.gc.get		= altera_gpio_get;
	altera_gc->mmchip.gc.set		= altera_gpio_set;
	altera_gc->mmchip.gc.owner		= THIS_MODULE;
	altera_gc->mmchip.gc.parent		= &pdev->dev;

	altera_gc->mapped_irq = platform_get_irq(pdev, 0);

	if (altera_gc->mapped_irq < 0)
		goto skip_irq;

	if (of_property_read_u32(node, "altr,interrupt-type", &reg)) {
		dev_err(&pdev->dev,
			"altr,interrupt-type value not set in device tree\n");
		return -EINVAL;
	}
	altera_gc->interrupt_trigger = reg;

	altera_gc->irq_chip.name = "altera-gpio";
	altera_gc->irq_chip.irq_mask     = altera_gpio_irq_mask;
	altera_gc->irq_chip.irq_unmask   = altera_gpio_irq_unmask;
	altera_gc->irq_chip.irq_set_type = altera_gpio_irq_set_type;
	altera_gc->irq_chip.irq_startup  = altera_gpio_irq_startup;
	altera_gc->irq_chip.irq_shutdown = altera_gpio_irq_mask;

	girq = &altera_gc->mmchip.gc.irq;
	girq->chip = &altera_gc->irq_chip;
	if (altera_gc->interrupt_trigger == IRQ_TYPE_LEVEL_HIGH)
		girq->parent_handler = altera_gpio_irq_leveL_high_handler;
	else
		girq->parent_handler = altera_gpio_irq_edge_handler;
	girq->num_parents = 1;
	girq->parents = devm_kcalloc(&pdev->dev, 1, sizeof(*girq->parents),
				     GFP_KERNEL);
	if (!girq->parents)
		return -ENOMEM;
	girq->default_type = IRQ_TYPE_NONE;
	girq->handler = handle_bad_irq;
	girq->parents[0] = altera_gc->mapped_irq;

skip_irq:
	ret = of_mm_gpiochip_add_data(node, &altera_gc->mmchip, altera_gc);
	if (ret) {
		dev_err(&pdev->dev, "Failed adding memory mapped gpiochip\n");
		return ret;
	}

	platform_set_drvdata(pdev, altera_gc);

	return 0;
}

static int altera_gpio_remove(struct platform_device *pdev)
{
	struct altera_gpio_chip *altera_gc = platform_get_drvdata(pdev);

	of_mm_gpiochip_remove(&altera_gc->mmchip);

	return 0;
}

static const struct of_device_id altera_gpio_of_match[] = {
	{ .compatible = "altr,pio-1.0", },
	{},
};
MODULE_DEVICE_TABLE(of, altera_gpio_of_match);

static struct platform_driver altera_gpio_driver = {
	.driver = {
		.name	= "altera_gpio",
		.of_match_table = of_match_ptr(altera_gpio_of_match),
	},
	.probe		= altera_gpio_probe,
	.remove		= altera_gpio_remove,
};

static int __init altera_gpio_init(void)
{
	return platform_driver_register(&altera_gpio_driver);
}
subsys_initcall(altera_gpio_init);

static void __exit altera_gpio_exit(void)
{
	platform_driver_unregister(&altera_gpio_driver);
}
module_exit(altera_gpio_exit);

MODULE_AUTHOR("Tien Hock Loh <thloh@altera.com>");
MODULE_DESCRIPTION("Altera GPIO driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
1ccea77e	1	// SPDX-License-Identifier: GPL-2.0-or-later
c5abbba9 THL	2	/*
	3	* Copyright (C) 2013 Altera Corporation
	4	* Based on gpio-mpc8xxx.c
c5abbba9 THL	5	*/
	6
	7	#include <linux/io.h>
7b5409ee	8	#include <linux/module.h>
40a1f9b2 LW	9	#include <linux/gpio/driver.h>
40a1f9b2 LW	10	#include <linux/of_gpio.h> /* For of_mm_gpio_chip */
c5abbba9 THL	11	#include <linux/platform_device.h>
	12
	13	#define ALTERA_GPIO_MAX_NGPIO 32
	14	#define ALTERA_GPIO_DATA 0x0
	15	#define ALTERA_GPIO_DIR 0x4
	16	#define ALTERA_GPIO_IRQ_MASK 0x8
	17	#define ALTERA_GPIO_EDGE_CAP 0xc
	18
	19	/**
	20	* struct altera_gpio_chip
	21	* @mmchip : memory mapped chip structure.
	22	* @gpio_lock : synchronization lock so that new irq/set/get requests
9ce01efe	23	* will be blocked until the current one completes.
c5abbba9	24	* @interrupt_trigger : specifies the hardware configured IRQ trigger type
9ce01efe	25	* (rising, falling, both, high)
c5abbba9 THL	26	* @mapped_irq : kernel mapped irq number.
	27	*/
	28	struct altera_gpio_chip {
	29	struct of_mm_gpio_chip mmchip;
21d01c9c	30	raw_spinlock_t gpio_lock;
c5abbba9 THL	31	int interrupt_trigger;
c5abbba9 THL	32	int mapped_irq;
9d373aca	33	struct irq_chip irq_chip;
c5abbba9 THL	34	};
	35
	36	static void altera_gpio_irq_unmask(struct irq_data *d)
	37	{
	38	struct altera_gpio_chip *altera_gc;
	39	struct of_mm_gpio_chip *mm_gc;
	40	unsigned long flags;
	41	u32 intmask;
	42
397d0773	43	altera_gc = gpiochip_get_data(irq_data_get_irq_chip_data(d));
c5abbba9 THL	44	mm_gc = &altera_gc->mmchip;
c5abbba9 THL	45
21d01c9c	46	raw_spin_lock_irqsave(&altera_gc->gpio_lock, flags);
c5abbba9 THL	47	intmask = readl(mm_gc->regs + ALTERA_GPIO_IRQ_MASK);
	48	/* Set ALTERA_GPIO_IRQ_MASK bit to unmask */
	49	intmask \|= BIT(irqd_to_hwirq(d));
	50	writel(intmask, mm_gc->regs + ALTERA_GPIO_IRQ_MASK);
21d01c9c	51	raw_spin_unlock_irqrestore(&altera_gc->gpio_lock, flags);
c5abbba9 THL	52	}
	53
	54	static void altera_gpio_irq_mask(struct irq_data *d)
	55	{
	56	struct altera_gpio_chip *altera_gc;
	57	struct of_mm_gpio_chip *mm_gc;
	58	unsigned long flags;
	59	u32 intmask;
	60
397d0773	61	altera_gc = gpiochip_get_data(irq_data_get_irq_chip_data(d));
c5abbba9 THL	62	mm_gc = &altera_gc->mmchip;
c5abbba9 THL	63
21d01c9c	64	raw_spin_lock_irqsave(&altera_gc->gpio_lock, flags);
c5abbba9 THL	65	intmask = readl(mm_gc->regs + ALTERA_GPIO_IRQ_MASK);
	66	/* Clear ALTERA_GPIO_IRQ_MASK bit to mask */
	67	intmask &= ~BIT(irqd_to_hwirq(d));
	68	writel(intmask, mm_gc->regs + ALTERA_GPIO_IRQ_MASK);
21d01c9c	69	raw_spin_unlock_irqrestore(&altera_gc->gpio_lock, flags);
c5abbba9 THL	70	}
	71
	72	/**
	73	* This controller's IRQ type is synthesized in hardware, so this function
	74	* just checks if the requested set_type matches the synthesized IRQ type
	75	*/
	76	static int altera_gpio_irq_set_type(struct irq_data *d,
	77	unsigned int type)
	78	{
	79	struct altera_gpio_chip *altera_gc;
	80
397d0773	81	altera_gc = gpiochip_get_data(irq_data_get_irq_chip_data(d));
c5abbba9	82
f759921c PR	83	if (type == IRQ_TYPE_NONE) {
f759921c PR	84	irq_set_handler_locked(d, handle_bad_irq);
c5abbba9	85	return 0;
f759921c PR	86	}
	87	if (type == altera_gc->interrupt_trigger) {
	88	if (type == IRQ_TYPE_LEVEL_HIGH)
	89	irq_set_handler_locked(d, handle_level_irq);
	90	else
	91	irq_set_handler_locked(d, handle_simple_irq);
c5abbba9	92	return 0;
f759921c PR	93	}
f759921c PR	94	irq_set_handler_locked(d, handle_bad_irq);
c5abbba9 THL	95	return -EINVAL;
	96	}
	97
38e003f4 DL	98	static unsigned int altera_gpio_irq_startup(struct irq_data *d)
38e003f4 DL	99	{
c5abbba9 THL	100	altera_gpio_irq_unmask(d);
	101
	102	return 0;
	103	}
	104
c5abbba9 THL	105	static int altera_gpio_get(struct gpio_chip *gc, unsigned offset)
	106	{
	107	struct of_mm_gpio_chip *mm_gc;
	108
	109	mm_gc = to_of_mm_gpio_chip(gc);
	110
	111	return !!(readl(mm_gc->regs + ALTERA_GPIO_DATA) & BIT(offset));
	112	}
	113
	114	static void altera_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
	115	{
	116	struct of_mm_gpio_chip *mm_gc;
	117	struct altera_gpio_chip *chip;
	118	unsigned long flags;
	119	unsigned int data_reg;
	120
	121	mm_gc = to_of_mm_gpio_chip(gc);
397d0773	122	chip = gpiochip_get_data(gc);
c5abbba9	123
21d01c9c	124	raw_spin_lock_irqsave(&chip->gpio_lock, flags);
c5abbba9 THL	125	data_reg = readl(mm_gc->regs + ALTERA_GPIO_DATA);
	126	if (value)
	127	data_reg \|= BIT(offset);
	128	else
	129	data_reg &= ~BIT(offset);
	130	writel(data_reg, mm_gc->regs + ALTERA_GPIO_DATA);
21d01c9c	131	raw_spin_unlock_irqrestore(&chip->gpio_lock, flags);
c5abbba9 THL	132	}
	133
	134	static int altera_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
	135	{
	136	struct of_mm_gpio_chip *mm_gc;
	137	struct altera_gpio_chip *chip;
	138	unsigned long flags;
	139	unsigned int gpio_ddr;
	140
	141	mm_gc = to_of_mm_gpio_chip(gc);
397d0773	142	chip = gpiochip_get_data(gc);
c5abbba9	143
21d01c9c	144	raw_spin_lock_irqsave(&chip->gpio_lock, flags);
c5abbba9 THL	145	/* Set pin as input, assumes software controlled IP */
	146	gpio_ddr = readl(mm_gc->regs + ALTERA_GPIO_DIR);
	147	gpio_ddr &= ~BIT(offset);
	148	writel(gpio_ddr, mm_gc->regs + ALTERA_GPIO_DIR);
21d01c9c	149	raw_spin_unlock_irqrestore(&chip->gpio_lock, flags);
c5abbba9 THL	150
	151	return 0;
	152	}
	153
	154	static int altera_gpio_direction_output(struct gpio_chip *gc,
	155	unsigned offset, int value)
	156	{
	157	struct of_mm_gpio_chip *mm_gc;
	158	struct altera_gpio_chip *chip;
	159	unsigned long flags;
	160	unsigned int data_reg, gpio_ddr;
	161
	162	mm_gc = to_of_mm_gpio_chip(gc);
397d0773	163	chip = gpiochip_get_data(gc);
c5abbba9	164
21d01c9c	165	raw_spin_lock_irqsave(&chip->gpio_lock, flags);
c5abbba9 THL	166	/* Sets the GPIO value */
	167	data_reg = readl(mm_gc->regs + ALTERA_GPIO_DATA);
	168	if (value)
	169	data_reg \|= BIT(offset);
	170	else
	171	data_reg &= ~BIT(offset);
	172	writel(data_reg, mm_gc->regs + ALTERA_GPIO_DATA);
	173
	174	/* Set pin as output, assumes software controlled IP */
	175	gpio_ddr = readl(mm_gc->regs + ALTERA_GPIO_DIR);
	176	gpio_ddr \|= BIT(offset);
	177	writel(gpio_ddr, mm_gc->regs + ALTERA_GPIO_DIR);
21d01c9c	178	raw_spin_unlock_irqrestore(&chip->gpio_lock, flags);
c5abbba9 THL	179
	180	return 0;
	181	}
	182
bd0b9ac4	183	static void altera_gpio_irq_edge_handler(struct irq_desc *desc)
c5abbba9 THL	184	{
	185	struct altera_gpio_chip *altera_gc;
	186	struct irq_chip *chip;
	187	struct of_mm_gpio_chip *mm_gc;
	188	struct irq_domain *irqdomain;
	189	unsigned long status;
	190	int i;
	191
397d0773	192	altera_gc = gpiochip_get_data(irq_desc_get_handler_data(desc));
c5abbba9 THL	193	chip = irq_desc_get_chip(desc);
c5abbba9 THL	194	mm_gc = &altera_gc->mmchip;
f0fbe7bc	195	irqdomain = altera_gc->mmchip.gc.irq.domain;
c5abbba9 THL	196
	197	chained_irq_enter(chip, desc);
	198
	199	while ((status =
	200	(readl(mm_gc->regs + ALTERA_GPIO_EDGE_CAP) &
	201	readl(mm_gc->regs + ALTERA_GPIO_IRQ_MASK)))) {
	202	writel(status, mm_gc->regs + ALTERA_GPIO_EDGE_CAP);
	203	for_each_set_bit(i, &status, mm_gc->gc.ngpio) {
	204	generic_handle_irq(irq_find_mapping(irqdomain, i));
	205	}
	206	}
	207
	208	chained_irq_exit(chip, desc);
	209	}
	210
bd0b9ac4	211	static void altera_gpio_irq_leveL_high_handler(struct irq_desc *desc)
c5abbba9 THL	212	{
	213	struct altera_gpio_chip *altera_gc;
	214	struct irq_chip *chip;
	215	struct of_mm_gpio_chip *mm_gc;
	216	struct irq_domain *irqdomain;
	217	unsigned long status;
	218	int i;
	219
397d0773	220	altera_gc = gpiochip_get_data(irq_desc_get_handler_data(desc));
c5abbba9 THL	221	chip = irq_desc_get_chip(desc);
c5abbba9 THL	222	mm_gc = &altera_gc->mmchip;
f0fbe7bc	223	irqdomain = altera_gc->mmchip.gc.irq.domain;
c5abbba9 THL	224
	225	chained_irq_enter(chip, desc);
	226
	227	status = readl(mm_gc->regs + ALTERA_GPIO_DATA);
	228	status &= readl(mm_gc->regs + ALTERA_GPIO_IRQ_MASK);
	229
	230	for_each_set_bit(i, &status, mm_gc->gc.ngpio) {
	231	generic_handle_irq(irq_find_mapping(irqdomain, i));
	232	}
	233	chained_irq_exit(chip, desc);
	234	}
	235
c4b40493	236	static int altera_gpio_probe(struct platform_device *pdev)
c5abbba9 THL	237	{
	238	struct device_node *node = pdev->dev.of_node;
	239	int reg, ret;
	240	struct altera_gpio_chip *altera_gc;
2617790f	241	struct gpio_irq_chip *girq;
c5abbba9 THL	242
	243	altera_gc = devm_kzalloc(&pdev->dev, sizeof(*altera_gc), GFP_KERNEL);
	244	if (!altera_gc)
	245	return -ENOMEM;
	246
21d01c9c	247	raw_spin_lock_init(&altera_gc->gpio_lock);
c5abbba9 THL	248
	249	if (of_property_read_u32(node, "altr,ngpio", &reg))
	250	/* By default assume maximum ngpio */
	251	altera_gc->mmchip.gc.ngpio = ALTERA_GPIO_MAX_NGPIO;
	252	else
	253	altera_gc->mmchip.gc.ngpio = reg;
	254
	255	if (altera_gc->mmchip.gc.ngpio > ALTERA_GPIO_MAX_NGPIO) {
	256	dev_warn(&pdev->dev,
	257	"ngpio is greater than %d, defaulting to %d\n",
	258	ALTERA_GPIO_MAX_NGPIO, ALTERA_GPIO_MAX_NGPIO);
	259	altera_gc->mmchip.gc.ngpio = ALTERA_GPIO_MAX_NGPIO;
	260	}
	261
	262	altera_gc->mmchip.gc.direction_input = altera_gpio_direction_input;
	263	altera_gc->mmchip.gc.direction_output = altera_gpio_direction_output;
	264	altera_gc->mmchip.gc.get = altera_gpio_get;
	265	altera_gc->mmchip.gc.set = altera_gpio_set;
	266	altera_gc->mmchip.gc.owner = THIS_MODULE;
58383c78	267	altera_gc->mmchip.gc.parent = &pdev->dev;
c5abbba9	268
c5abbba9 THL	269	altera_gc->mapped_irq = platform_get_irq(pdev, 0);
	270
	271	if (altera_gc->mapped_irq < 0)
	272	goto skip_irq;
	273
	274	if (of_property_read_u32(node, "altr,interrupt-type", &reg)) {
c5abbba9 THL	275	dev_err(&pdev->dev,
c5abbba9 THL	276	"altr,interrupt-type value not set in device tree\n");
2617790f	277	return -EINVAL;
c5abbba9 THL	278	}
	279	altera_gc->interrupt_trigger = reg;
	280
9d373aca PR	281	altera_gc->irq_chip.name = "altera-gpio";
	282	altera_gc->irq_chip.irq_mask = altera_gpio_irq_mask;
	283	altera_gc->irq_chip.irq_unmask = altera_gpio_irq_unmask;
	284	altera_gc->irq_chip.irq_set_type = altera_gpio_irq_set_type;
	285	altera_gc->irq_chip.irq_startup = altera_gpio_irq_startup;
	286	altera_gc->irq_chip.irq_shutdown = altera_gpio_irq_mask;
	287
2617790f LW	288	girq = &altera_gc->mmchip.gc.irq;
	289	girq->chip = &altera_gc->irq_chip;
	290	if (altera_gc->interrupt_trigger == IRQ_TYPE_LEVEL_HIGH)
	291	girq->parent_handler = altera_gpio_irq_leveL_high_handler;
	292	else
	293	girq->parent_handler = altera_gpio_irq_edge_handler;
	294	girq->num_parents = 1;
	295	girq->parents = devm_kcalloc(&pdev->dev, 1, sizeof(*girq->parents),
	296	GFP_KERNEL);
	297	if (!girq->parents)
	298	return -ENOMEM;
	299	girq->default_type = IRQ_TYPE_NONE;
	300	girq->handler = handle_bad_irq;
	301	girq->parents[0] = altera_gc->mapped_irq;
c5abbba9	302
2617790f LW	303	skip_irq:
2617790f LW	304	ret = of_mm_gpiochip_add_data(node, &altera_gc->mmchip, altera_gc);
c5abbba9	305	if (ret) {
2617790f LW	306	dev_err(&pdev->dev, "Failed adding memory mapped gpiochip\n");
2617790f LW	307	return ret;
c5abbba9 THL	308	}
c5abbba9 THL	309
2617790f	310	platform_set_drvdata(pdev, altera_gc);
c5abbba9	311
c5abbba9	312	return 0;
c5abbba9 THL	313	}
	314
	315	static int altera_gpio_remove(struct platform_device *pdev)
	316	{
	317	struct altera_gpio_chip *altera_gc = platform_get_drvdata(pdev);
	318
41ec66c9	319	of_mm_gpiochip_remove(&altera_gc->mmchip);
c5abbba9	320
1c8b5d68	321	return 0;
c5abbba9 THL	322	}
	323
	324	static const struct of_device_id altera_gpio_of_match[] = {
	325	{ .compatible = "altr,pio-1.0", },
	326	{},
	327	};
	328	MODULE_DEVICE_TABLE(of, altera_gpio_of_match);
	329
	330	static struct platform_driver altera_gpio_driver = {
	331	.driver = {
	332	.name = "altera_gpio",
	333	.of_match_table = of_match_ptr(altera_gpio_of_match),
	334	},
	335	.probe = altera_gpio_probe,
	336	.remove = altera_gpio_remove,
	337	};
	338
	339	static int __init altera_gpio_init(void)
	340	{
	341	return platform_driver_register(&altera_gpio_driver);
	342	}
	343	subsys_initcall(altera_gpio_init);
	344
	345	static void __exit altera_gpio_exit(void)
	346	{
	347	platform_driver_unregister(&altera_gpio_driver);
	348	}
	349	module_exit(altera_gpio_exit);
	350
	351	MODULE_AUTHOR("Tien Hock Loh <thloh@altera.com>");
	352	MODULE_DESCRIPTION("Altera GPIO driver");
	353	MODULE_LICENSE("GPL");