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361b7911 JS |
1 | /* |
2 | * Copyright 2015 IBM Corp. | |
3 | * | |
4 | * Joel Stanley <joel@jms.id.au> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version | |
9 | * 2 of the License, or (at your option) any later version. | |
10 | */ | |
11 | ||
5ae4cb94 AJ |
12 | #include <asm/div64.h> |
13 | #include <linux/clk.h> | |
14 | #include <linux/gpio/driver.h> | |
15 | #include <linux/hashtable.h> | |
361b7911 JS |
16 | #include <linux/init.h> |
17 | #include <linux/io.h> | |
5ae4cb94 AJ |
18 | #include <linux/kernel.h> |
19 | #include <linux/module.h> | |
361b7911 | 20 | #include <linux/pinctrl/consumer.h> |
5ae4cb94 AJ |
21 | #include <linux/platform_device.h> |
22 | #include <linux/spinlock.h> | |
23 | #include <linux/string.h> | |
361b7911 | 24 | |
1736f75d AJ |
25 | struct aspeed_bank_props { |
26 | unsigned int bank; | |
27 | u32 input; | |
28 | u32 output; | |
29 | }; | |
30 | ||
31 | struct aspeed_gpio_config { | |
32 | unsigned int nr_gpios; | |
33 | const struct aspeed_bank_props *props; | |
34 | }; | |
35 | ||
5ae4cb94 AJ |
36 | /* |
37 | * @offset_timer: Maps an offset to an @timer_users index, or zero if disabled | |
38 | * @timer_users: Tracks the number of users for each timer | |
39 | * | |
40 | * The @timer_users has four elements but the first element is unused. This is | |
41 | * to simplify accounting and indexing, as a zero value in @offset_timer | |
42 | * represents disabled debouncing for the GPIO. Any other value for an element | |
43 | * of @offset_timer is used as an index into @timer_users. This behaviour of | |
44 | * the zero value aligns with the behaviour of zero built from the timer | |
45 | * configuration registers (i.e. debouncing is disabled). | |
46 | */ | |
361b7911 JS |
47 | struct aspeed_gpio { |
48 | struct gpio_chip chip; | |
49 | spinlock_t lock; | |
50 | void __iomem *base; | |
51 | int irq; | |
1736f75d | 52 | const struct aspeed_gpio_config *config; |
5ae4cb94 AJ |
53 | |
54 | u8 *offset_timer; | |
55 | unsigned int timer_users[4]; | |
56 | struct clk *clk; | |
361b7911 JS |
57 | }; |
58 | ||
59 | struct aspeed_gpio_bank { | |
60 | uint16_t val_regs; | |
61 | uint16_t irq_regs; | |
5ae4cb94 | 62 | uint16_t debounce_regs; |
7153f8ef | 63 | const char names[4][3]; |
361b7911 JS |
64 | }; |
65 | ||
5ae4cb94 AJ |
66 | static const int debounce_timers[4] = { 0x00, 0x50, 0x54, 0x58 }; |
67 | ||
361b7911 JS |
68 | static const struct aspeed_gpio_bank aspeed_gpio_banks[] = { |
69 | { | |
70 | .val_regs = 0x0000, | |
71 | .irq_regs = 0x0008, | |
5ae4cb94 | 72 | .debounce_regs = 0x0040, |
7153f8ef | 73 | .names = { "A", "B", "C", "D" }, |
361b7911 JS |
74 | }, |
75 | { | |
76 | .val_regs = 0x0020, | |
77 | .irq_regs = 0x0028, | |
5ae4cb94 | 78 | .debounce_regs = 0x0048, |
7153f8ef | 79 | .names = { "E", "F", "G", "H" }, |
361b7911 JS |
80 | }, |
81 | { | |
82 | .val_regs = 0x0070, | |
83 | .irq_regs = 0x0098, | |
5ae4cb94 | 84 | .debounce_regs = 0x00b0, |
7153f8ef | 85 | .names = { "I", "J", "K", "L" }, |
361b7911 JS |
86 | }, |
87 | { | |
88 | .val_regs = 0x0078, | |
89 | .irq_regs = 0x00e8, | |
5ae4cb94 | 90 | .debounce_regs = 0x0100, |
7153f8ef | 91 | .names = { "M", "N", "O", "P" }, |
361b7911 JS |
92 | }, |
93 | { | |
94 | .val_regs = 0x0080, | |
95 | .irq_regs = 0x0118, | |
5ae4cb94 | 96 | .debounce_regs = 0x0130, |
7153f8ef | 97 | .names = { "Q", "R", "S", "T" }, |
361b7911 JS |
98 | }, |
99 | { | |
100 | .val_regs = 0x0088, | |
101 | .irq_regs = 0x0148, | |
5ae4cb94 | 102 | .debounce_regs = 0x0160, |
7153f8ef | 103 | .names = { "U", "V", "W", "X" }, |
361b7911 | 104 | }, |
1736f75d AJ |
105 | { |
106 | .val_regs = 0x01E0, | |
107 | .irq_regs = 0x0178, | |
5ae4cb94 | 108 | .debounce_regs = 0x0190, |
1736f75d AJ |
109 | .names = { "Y", "Z", "AA", "AB" }, |
110 | }, | |
111 | { | |
112 | .val_regs = 0x01E8, | |
113 | .irq_regs = 0x01A8, | |
5ae4cb94 | 114 | .debounce_regs = 0x01c0, |
1736f75d AJ |
115 | .names = { "AC", "", "", "" }, |
116 | }, | |
361b7911 JS |
117 | }; |
118 | ||
119 | #define GPIO_BANK(x) ((x) >> 5) | |
120 | #define GPIO_OFFSET(x) ((x) & 0x1f) | |
121 | #define GPIO_BIT(x) BIT(GPIO_OFFSET(x)) | |
122 | ||
123 | #define GPIO_DATA 0x00 | |
124 | #define GPIO_DIR 0x04 | |
125 | ||
126 | #define GPIO_IRQ_ENABLE 0x00 | |
127 | #define GPIO_IRQ_TYPE0 0x04 | |
128 | #define GPIO_IRQ_TYPE1 0x08 | |
129 | #define GPIO_IRQ_TYPE2 0x0c | |
130 | #define GPIO_IRQ_STATUS 0x10 | |
131 | ||
5ae4cb94 AJ |
132 | #define GPIO_DEBOUNCE_SEL1 0x00 |
133 | #define GPIO_DEBOUNCE_SEL2 0x04 | |
134 | ||
135 | #define _GPIO_SET_DEBOUNCE(t, o, i) ((!!((t) & BIT(i))) << GPIO_OFFSET(o)) | |
136 | #define GPIO_SET_DEBOUNCE1(t, o) _GPIO_SET_DEBOUNCE(t, o, 1) | |
137 | #define GPIO_SET_DEBOUNCE2(t, o) _GPIO_SET_DEBOUNCE(t, o, 0) | |
138 | ||
361b7911 JS |
139 | static const struct aspeed_gpio_bank *to_bank(unsigned int offset) |
140 | { | |
141 | unsigned int bank = GPIO_BANK(offset); | |
142 | ||
143 | WARN_ON(bank > ARRAY_SIZE(aspeed_gpio_banks)); | |
144 | return &aspeed_gpio_banks[bank]; | |
145 | } | |
146 | ||
1736f75d AJ |
147 | static inline bool is_bank_props_sentinel(const struct aspeed_bank_props *props) |
148 | { | |
149 | return !(props->input || props->output); | |
150 | } | |
151 | ||
152 | static inline const struct aspeed_bank_props *find_bank_props( | |
153 | struct aspeed_gpio *gpio, unsigned int offset) | |
154 | { | |
155 | const struct aspeed_bank_props *props = gpio->config->props; | |
156 | ||
157 | while (!is_bank_props_sentinel(props)) { | |
158 | if (props->bank == GPIO_BANK(offset)) | |
159 | return props; | |
160 | props++; | |
161 | } | |
162 | ||
163 | return NULL; | |
164 | } | |
165 | ||
166 | static inline bool have_gpio(struct aspeed_gpio *gpio, unsigned int offset) | |
167 | { | |
168 | const struct aspeed_bank_props *props = find_bank_props(gpio, offset); | |
169 | const struct aspeed_gpio_bank *bank = to_bank(offset); | |
170 | unsigned int group = GPIO_OFFSET(offset) / 8; | |
171 | ||
172 | return bank->names[group][0] != '\0' && | |
173 | (!props || ((props->input | props->output) & GPIO_BIT(offset))); | |
174 | } | |
175 | ||
176 | static inline bool have_input(struct aspeed_gpio *gpio, unsigned int offset) | |
177 | { | |
178 | const struct aspeed_bank_props *props = find_bank_props(gpio, offset); | |
179 | ||
180 | return !props || (props->input & GPIO_BIT(offset)); | |
181 | } | |
182 | ||
183 | #define have_irq(g, o) have_input((g), (o)) | |
5ae4cb94 | 184 | #define have_debounce(g, o) have_input((g), (o)) |
1736f75d AJ |
185 | |
186 | static inline bool have_output(struct aspeed_gpio *gpio, unsigned int offset) | |
187 | { | |
188 | const struct aspeed_bank_props *props = find_bank_props(gpio, offset); | |
189 | ||
190 | return !props || (props->output & GPIO_BIT(offset)); | |
191 | } | |
192 | ||
361b7911 JS |
193 | static void __iomem *bank_val_reg(struct aspeed_gpio *gpio, |
194 | const struct aspeed_gpio_bank *bank, | |
195 | unsigned int reg) | |
196 | { | |
197 | return gpio->base + bank->val_regs + reg; | |
198 | } | |
199 | ||
200 | static void __iomem *bank_irq_reg(struct aspeed_gpio *gpio, | |
201 | const struct aspeed_gpio_bank *bank, | |
202 | unsigned int reg) | |
203 | { | |
204 | return gpio->base + bank->irq_regs + reg; | |
205 | } | |
206 | ||
207 | static int aspeed_gpio_get(struct gpio_chip *gc, unsigned int offset) | |
208 | { | |
209 | struct aspeed_gpio *gpio = gpiochip_get_data(gc); | |
210 | const struct aspeed_gpio_bank *bank = to_bank(offset); | |
211 | ||
212 | return !!(ioread32(bank_val_reg(gpio, bank, GPIO_DATA)) | |
213 | & GPIO_BIT(offset)); | |
214 | } | |
215 | ||
216 | static void __aspeed_gpio_set(struct gpio_chip *gc, unsigned int offset, | |
217 | int val) | |
218 | { | |
219 | struct aspeed_gpio *gpio = gpiochip_get_data(gc); | |
220 | const struct aspeed_gpio_bank *bank = to_bank(offset); | |
221 | void __iomem *addr; | |
222 | u32 reg; | |
223 | ||
224 | addr = bank_val_reg(gpio, bank, GPIO_DATA); | |
225 | reg = ioread32(addr); | |
226 | ||
227 | if (val) | |
228 | reg |= GPIO_BIT(offset); | |
229 | else | |
230 | reg &= ~GPIO_BIT(offset); | |
231 | ||
232 | iowrite32(reg, addr); | |
233 | } | |
234 | ||
235 | static void aspeed_gpio_set(struct gpio_chip *gc, unsigned int offset, | |
236 | int val) | |
237 | { | |
238 | struct aspeed_gpio *gpio = gpiochip_get_data(gc); | |
239 | unsigned long flags; | |
240 | ||
241 | spin_lock_irqsave(&gpio->lock, flags); | |
242 | ||
243 | __aspeed_gpio_set(gc, offset, val); | |
244 | ||
245 | spin_unlock_irqrestore(&gpio->lock, flags); | |
246 | } | |
247 | ||
248 | static int aspeed_gpio_dir_in(struct gpio_chip *gc, unsigned int offset) | |
249 | { | |
250 | struct aspeed_gpio *gpio = gpiochip_get_data(gc); | |
251 | const struct aspeed_gpio_bank *bank = to_bank(offset); | |
252 | unsigned long flags; | |
253 | u32 reg; | |
254 | ||
1736f75d AJ |
255 | if (!have_input(gpio, offset)) |
256 | return -ENOTSUPP; | |
257 | ||
361b7911 JS |
258 | spin_lock_irqsave(&gpio->lock, flags); |
259 | ||
260 | reg = ioread32(bank_val_reg(gpio, bank, GPIO_DIR)); | |
261 | iowrite32(reg & ~GPIO_BIT(offset), bank_val_reg(gpio, bank, GPIO_DIR)); | |
262 | ||
263 | spin_unlock_irqrestore(&gpio->lock, flags); | |
264 | ||
265 | return 0; | |
266 | } | |
267 | ||
268 | static int aspeed_gpio_dir_out(struct gpio_chip *gc, | |
269 | unsigned int offset, int val) | |
270 | { | |
271 | struct aspeed_gpio *gpio = gpiochip_get_data(gc); | |
272 | const struct aspeed_gpio_bank *bank = to_bank(offset); | |
273 | unsigned long flags; | |
274 | u32 reg; | |
275 | ||
1736f75d AJ |
276 | if (!have_output(gpio, offset)) |
277 | return -ENOTSUPP; | |
278 | ||
361b7911 JS |
279 | spin_lock_irqsave(&gpio->lock, flags); |
280 | ||
281 | reg = ioread32(bank_val_reg(gpio, bank, GPIO_DIR)); | |
282 | iowrite32(reg | GPIO_BIT(offset), bank_val_reg(gpio, bank, GPIO_DIR)); | |
283 | ||
284 | __aspeed_gpio_set(gc, offset, val); | |
285 | ||
286 | spin_unlock_irqrestore(&gpio->lock, flags); | |
287 | ||
288 | return 0; | |
289 | } | |
290 | ||
291 | static int aspeed_gpio_get_direction(struct gpio_chip *gc, unsigned int offset) | |
292 | { | |
293 | struct aspeed_gpio *gpio = gpiochip_get_data(gc); | |
294 | const struct aspeed_gpio_bank *bank = to_bank(offset); | |
295 | unsigned long flags; | |
296 | u32 val; | |
297 | ||
1736f75d | 298 | if (!have_input(gpio, offset)) |
619e96f4 | 299 | return 0; |
1736f75d AJ |
300 | |
301 | if (!have_output(gpio, offset)) | |
619e96f4 | 302 | return 1; |
1736f75d | 303 | |
361b7911 JS |
304 | spin_lock_irqsave(&gpio->lock, flags); |
305 | ||
306 | val = ioread32(bank_val_reg(gpio, bank, GPIO_DIR)) & GPIO_BIT(offset); | |
307 | ||
308 | spin_unlock_irqrestore(&gpio->lock, flags); | |
309 | ||
310 | return !val; | |
311 | ||
312 | } | |
313 | ||
314 | static inline int irqd_to_aspeed_gpio_data(struct irq_data *d, | |
315 | struct aspeed_gpio **gpio, | |
316 | const struct aspeed_gpio_bank **bank, | |
317 | u32 *bit) | |
318 | { | |
319 | int offset; | |
1736f75d | 320 | struct aspeed_gpio *internal; |
361b7911 JS |
321 | |
322 | offset = irqd_to_hwirq(d); | |
323 | ||
1736f75d AJ |
324 | internal = irq_data_get_irq_chip_data(d); |
325 | ||
326 | /* This might be a bit of a questionable place to check */ | |
327 | if (!have_irq(internal, offset)) | |
328 | return -ENOTSUPP; | |
329 | ||
330 | *gpio = internal; | |
361b7911 JS |
331 | *bank = to_bank(offset); |
332 | *bit = GPIO_BIT(offset); | |
333 | ||
334 | return 0; | |
335 | } | |
336 | ||
337 | static void aspeed_gpio_irq_ack(struct irq_data *d) | |
338 | { | |
339 | const struct aspeed_gpio_bank *bank; | |
340 | struct aspeed_gpio *gpio; | |
341 | unsigned long flags; | |
342 | void __iomem *status_addr; | |
343 | u32 bit; | |
344 | int rc; | |
345 | ||
346 | rc = irqd_to_aspeed_gpio_data(d, &gpio, &bank, &bit); | |
347 | if (rc) | |
348 | return; | |
349 | ||
350 | status_addr = bank_irq_reg(gpio, bank, GPIO_IRQ_STATUS); | |
351 | ||
352 | spin_lock_irqsave(&gpio->lock, flags); | |
353 | iowrite32(bit, status_addr); | |
354 | spin_unlock_irqrestore(&gpio->lock, flags); | |
355 | } | |
356 | ||
357 | static void aspeed_gpio_irq_set_mask(struct irq_data *d, bool set) | |
358 | { | |
359 | const struct aspeed_gpio_bank *bank; | |
360 | struct aspeed_gpio *gpio; | |
361 | unsigned long flags; | |
362 | u32 reg, bit; | |
363 | void __iomem *addr; | |
364 | int rc; | |
365 | ||
366 | rc = irqd_to_aspeed_gpio_data(d, &gpio, &bank, &bit); | |
367 | if (rc) | |
368 | return; | |
369 | ||
370 | addr = bank_irq_reg(gpio, bank, GPIO_IRQ_ENABLE); | |
371 | ||
372 | spin_lock_irqsave(&gpio->lock, flags); | |
373 | ||
374 | reg = ioread32(addr); | |
375 | if (set) | |
376 | reg |= bit; | |
377 | else | |
378 | reg &= bit; | |
379 | iowrite32(reg, addr); | |
380 | ||
381 | spin_unlock_irqrestore(&gpio->lock, flags); | |
382 | } | |
383 | ||
384 | static void aspeed_gpio_irq_mask(struct irq_data *d) | |
385 | { | |
386 | aspeed_gpio_irq_set_mask(d, false); | |
387 | } | |
388 | ||
389 | static void aspeed_gpio_irq_unmask(struct irq_data *d) | |
390 | { | |
391 | aspeed_gpio_irq_set_mask(d, true); | |
392 | } | |
393 | ||
394 | static int aspeed_gpio_set_type(struct irq_data *d, unsigned int type) | |
395 | { | |
396 | u32 type0 = 0; | |
397 | u32 type1 = 0; | |
398 | u32 type2 = 0; | |
399 | u32 bit, reg; | |
400 | const struct aspeed_gpio_bank *bank; | |
401 | irq_flow_handler_t handler; | |
402 | struct aspeed_gpio *gpio; | |
403 | unsigned long flags; | |
404 | void __iomem *addr; | |
405 | int rc; | |
406 | ||
407 | rc = irqd_to_aspeed_gpio_data(d, &gpio, &bank, &bit); | |
408 | if (rc) | |
409 | return -EINVAL; | |
410 | ||
411 | switch (type & IRQ_TYPE_SENSE_MASK) { | |
412 | case IRQ_TYPE_EDGE_BOTH: | |
413 | type2 |= bit; | |
e80df7b8 | 414 | /* fall through */ |
361b7911 JS |
415 | case IRQ_TYPE_EDGE_RISING: |
416 | type0 |= bit; | |
e80df7b8 | 417 | /* fall through */ |
361b7911 JS |
418 | case IRQ_TYPE_EDGE_FALLING: |
419 | handler = handle_edge_irq; | |
420 | break; | |
421 | case IRQ_TYPE_LEVEL_HIGH: | |
422 | type0 |= bit; | |
e80df7b8 | 423 | /* fall through */ |
361b7911 JS |
424 | case IRQ_TYPE_LEVEL_LOW: |
425 | type1 |= bit; | |
426 | handler = handle_level_irq; | |
427 | break; | |
428 | default: | |
429 | return -EINVAL; | |
430 | } | |
431 | ||
432 | spin_lock_irqsave(&gpio->lock, flags); | |
433 | ||
434 | addr = bank_irq_reg(gpio, bank, GPIO_IRQ_TYPE0); | |
435 | reg = ioread32(addr); | |
436 | reg = (reg & ~bit) | type0; | |
437 | iowrite32(reg, addr); | |
438 | ||
439 | addr = bank_irq_reg(gpio, bank, GPIO_IRQ_TYPE1); | |
440 | reg = ioread32(addr); | |
441 | reg = (reg & ~bit) | type1; | |
442 | iowrite32(reg, addr); | |
443 | ||
444 | addr = bank_irq_reg(gpio, bank, GPIO_IRQ_TYPE2); | |
445 | reg = ioread32(addr); | |
446 | reg = (reg & ~bit) | type2; | |
447 | iowrite32(reg, addr); | |
448 | ||
449 | spin_unlock_irqrestore(&gpio->lock, flags); | |
450 | ||
451 | irq_set_handler_locked(d, handler); | |
452 | ||
453 | return 0; | |
454 | } | |
455 | ||
456 | static void aspeed_gpio_irq_handler(struct irq_desc *desc) | |
457 | { | |
458 | struct gpio_chip *gc = irq_desc_get_handler_data(desc); | |
459 | struct irq_chip *ic = irq_desc_get_chip(desc); | |
460 | struct aspeed_gpio *data = gpiochip_get_data(gc); | |
461 | unsigned int i, p, girq; | |
462 | unsigned long reg; | |
463 | ||
464 | chained_irq_enter(ic, desc); | |
465 | ||
466 | for (i = 0; i < ARRAY_SIZE(aspeed_gpio_banks); i++) { | |
467 | const struct aspeed_gpio_bank *bank = &aspeed_gpio_banks[i]; | |
468 | ||
469 | reg = ioread32(bank_irq_reg(data, bank, GPIO_IRQ_STATUS)); | |
470 | ||
471 | for_each_set_bit(p, ®, 32) { | |
f0fbe7bc | 472 | girq = irq_find_mapping(gc->irq.domain, i * 32 + p); |
361b7911 JS |
473 | generic_handle_irq(girq); |
474 | } | |
475 | ||
476 | } | |
477 | ||
478 | chained_irq_exit(ic, desc); | |
479 | } | |
480 | ||
481 | static struct irq_chip aspeed_gpio_irqchip = { | |
482 | .name = "aspeed-gpio", | |
483 | .irq_ack = aspeed_gpio_irq_ack, | |
484 | .irq_mask = aspeed_gpio_irq_mask, | |
485 | .irq_unmask = aspeed_gpio_irq_unmask, | |
486 | .irq_set_type = aspeed_gpio_set_type, | |
487 | }; | |
488 | ||
1736f75d AJ |
489 | static void set_irq_valid_mask(struct aspeed_gpio *gpio) |
490 | { | |
491 | const struct aspeed_bank_props *props = gpio->config->props; | |
492 | ||
493 | while (!is_bank_props_sentinel(props)) { | |
494 | unsigned int offset; | |
495 | const unsigned long int input = props->input; | |
496 | ||
497 | /* Pretty crummy approach, but similar to GPIO core */ | |
498 | for_each_clear_bit(offset, &input, 32) { | |
499 | unsigned int i = props->bank * 32 + offset; | |
500 | ||
501 | if (i >= gpio->config->nr_gpios) | |
502 | break; | |
503 | ||
504 | clear_bit(i, gpio->chip.irq_valid_mask); | |
505 | } | |
506 | ||
507 | props++; | |
508 | } | |
509 | } | |
510 | ||
361b7911 JS |
511 | static int aspeed_gpio_setup_irqs(struct aspeed_gpio *gpio, |
512 | struct platform_device *pdev) | |
513 | { | |
514 | int rc; | |
515 | ||
516 | rc = platform_get_irq(pdev, 0); | |
517 | if (rc < 0) | |
518 | return rc; | |
519 | ||
520 | gpio->irq = rc; | |
521 | ||
1736f75d AJ |
522 | set_irq_valid_mask(gpio); |
523 | ||
361b7911 JS |
524 | rc = gpiochip_irqchip_add(&gpio->chip, &aspeed_gpio_irqchip, |
525 | 0, handle_bad_irq, IRQ_TYPE_NONE); | |
526 | if (rc) { | |
527 | dev_info(&pdev->dev, "Could not add irqchip\n"); | |
528 | return rc; | |
529 | } | |
530 | ||
531 | gpiochip_set_chained_irqchip(&gpio->chip, &aspeed_gpio_irqchip, | |
532 | gpio->irq, aspeed_gpio_irq_handler); | |
533 | ||
534 | return 0; | |
535 | } | |
536 | ||
537 | static int aspeed_gpio_request(struct gpio_chip *chip, unsigned int offset) | |
538 | { | |
1736f75d AJ |
539 | if (!have_gpio(gpiochip_get_data(chip), offset)) |
540 | return -ENODEV; | |
541 | ||
361b7911 JS |
542 | return pinctrl_request_gpio(chip->base + offset); |
543 | } | |
544 | ||
545 | static void aspeed_gpio_free(struct gpio_chip *chip, unsigned int offset) | |
546 | { | |
547 | pinctrl_free_gpio(chip->base + offset); | |
548 | } | |
549 | ||
5ae4cb94 AJ |
550 | static inline void __iomem *bank_debounce_reg(struct aspeed_gpio *gpio, |
551 | const struct aspeed_gpio_bank *bank, | |
552 | unsigned int reg) | |
553 | { | |
554 | return gpio->base + bank->debounce_regs + reg; | |
555 | } | |
556 | ||
557 | static int usecs_to_cycles(struct aspeed_gpio *gpio, unsigned long usecs, | |
558 | u32 *cycles) | |
559 | { | |
560 | u64 rate; | |
561 | u64 n; | |
562 | u32 r; | |
563 | ||
564 | rate = clk_get_rate(gpio->clk); | |
565 | if (!rate) | |
566 | return -ENOTSUPP; | |
567 | ||
568 | n = rate * usecs; | |
569 | r = do_div(n, 1000000); | |
570 | ||
571 | if (n >= U32_MAX) | |
572 | return -ERANGE; | |
573 | ||
574 | /* At least as long as the requested time */ | |
575 | *cycles = n + (!!r); | |
576 | ||
577 | return 0; | |
578 | } | |
579 | ||
580 | /* Call under gpio->lock */ | |
581 | static int register_allocated_timer(struct aspeed_gpio *gpio, | |
582 | unsigned int offset, unsigned int timer) | |
583 | { | |
584 | if (WARN(gpio->offset_timer[offset] != 0, | |
585 | "Offset %d already allocated timer %d\n", | |
586 | offset, gpio->offset_timer[offset])) | |
587 | return -EINVAL; | |
588 | ||
589 | if (WARN(gpio->timer_users[timer] == UINT_MAX, | |
590 | "Timer user count would overflow\n")) | |
591 | return -EPERM; | |
592 | ||
593 | gpio->offset_timer[offset] = timer; | |
594 | gpio->timer_users[timer]++; | |
595 | ||
596 | return 0; | |
597 | } | |
598 | ||
599 | /* Call under gpio->lock */ | |
600 | static int unregister_allocated_timer(struct aspeed_gpio *gpio, | |
601 | unsigned int offset) | |
602 | { | |
603 | if (WARN(gpio->offset_timer[offset] == 0, | |
604 | "No timer allocated to offset %d\n", offset)) | |
605 | return -EINVAL; | |
606 | ||
607 | if (WARN(gpio->timer_users[gpio->offset_timer[offset]] == 0, | |
608 | "No users recorded for timer %d\n", | |
609 | gpio->offset_timer[offset])) | |
610 | return -EINVAL; | |
611 | ||
612 | gpio->timer_users[gpio->offset_timer[offset]]--; | |
613 | gpio->offset_timer[offset] = 0; | |
614 | ||
615 | return 0; | |
616 | } | |
617 | ||
618 | /* Call under gpio->lock */ | |
619 | static inline bool timer_allocation_registered(struct aspeed_gpio *gpio, | |
620 | unsigned int offset) | |
621 | { | |
622 | return gpio->offset_timer[offset] > 0; | |
623 | } | |
624 | ||
625 | /* Call under gpio->lock */ | |
626 | static void configure_timer(struct aspeed_gpio *gpio, unsigned int offset, | |
627 | unsigned int timer) | |
628 | { | |
629 | const struct aspeed_gpio_bank *bank = to_bank(offset); | |
630 | const u32 mask = GPIO_BIT(offset); | |
631 | void __iomem *addr; | |
632 | u32 val; | |
633 | ||
634 | addr = bank_debounce_reg(gpio, bank, GPIO_DEBOUNCE_SEL1); | |
635 | val = ioread32(addr); | |
636 | iowrite32((val & ~mask) | GPIO_SET_DEBOUNCE1(timer, offset), addr); | |
637 | ||
638 | addr = bank_debounce_reg(gpio, bank, GPIO_DEBOUNCE_SEL2); | |
639 | val = ioread32(addr); | |
640 | iowrite32((val & ~mask) | GPIO_SET_DEBOUNCE2(timer, offset), addr); | |
641 | } | |
642 | ||
643 | static int enable_debounce(struct gpio_chip *chip, unsigned int offset, | |
644 | unsigned long usecs) | |
645 | { | |
646 | struct aspeed_gpio *gpio = gpiochip_get_data(chip); | |
647 | u32 requested_cycles; | |
648 | unsigned long flags; | |
649 | int rc; | |
650 | int i; | |
651 | ||
df563c85 JS |
652 | if (!gpio->clk) |
653 | return -EINVAL; | |
654 | ||
5ae4cb94 AJ |
655 | rc = usecs_to_cycles(gpio, usecs, &requested_cycles); |
656 | if (rc < 0) { | |
657 | dev_warn(chip->parent, "Failed to convert %luus to cycles at %luHz: %d\n", | |
658 | usecs, clk_get_rate(gpio->clk), rc); | |
659 | return rc; | |
660 | } | |
661 | ||
662 | spin_lock_irqsave(&gpio->lock, flags); | |
663 | ||
664 | if (timer_allocation_registered(gpio, offset)) { | |
665 | rc = unregister_allocated_timer(gpio, offset); | |
666 | if (rc < 0) | |
667 | goto out; | |
668 | } | |
669 | ||
670 | /* Try to find a timer already configured for the debounce period */ | |
671 | for (i = 1; i < ARRAY_SIZE(debounce_timers); i++) { | |
672 | u32 cycles; | |
673 | ||
674 | cycles = ioread32(gpio->base + debounce_timers[i]); | |
675 | if (requested_cycles == cycles) | |
676 | break; | |
677 | } | |
678 | ||
679 | if (i == ARRAY_SIZE(debounce_timers)) { | |
680 | int j; | |
681 | ||
682 | /* | |
683 | * As there are no timers configured for the requested debounce | |
684 | * period, find an unused timer instead | |
685 | */ | |
686 | for (j = 1; j < ARRAY_SIZE(gpio->timer_users); j++) { | |
687 | if (gpio->timer_users[j] == 0) | |
688 | break; | |
689 | } | |
690 | ||
691 | if (j == ARRAY_SIZE(gpio->timer_users)) { | |
692 | dev_warn(chip->parent, | |
693 | "Debounce timers exhausted, cannot debounce for period %luus\n", | |
694 | usecs); | |
695 | ||
696 | rc = -EPERM; | |
697 | ||
698 | /* | |
699 | * We already adjusted the accounting to remove @offset | |
700 | * as a user of its previous timer, so also configure | |
701 | * the hardware so @offset has timers disabled for | |
702 | * consistency. | |
703 | */ | |
704 | configure_timer(gpio, offset, 0); | |
705 | goto out; | |
706 | } | |
707 | ||
708 | i = j; | |
709 | ||
710 | iowrite32(requested_cycles, gpio->base + debounce_timers[i]); | |
711 | } | |
712 | ||
713 | if (WARN(i == 0, "Cannot register index of disabled timer\n")) { | |
714 | rc = -EINVAL; | |
715 | goto out; | |
716 | } | |
717 | ||
718 | register_allocated_timer(gpio, offset, i); | |
719 | configure_timer(gpio, offset, i); | |
720 | ||
721 | out: | |
722 | spin_unlock_irqrestore(&gpio->lock, flags); | |
723 | ||
724 | return rc; | |
725 | } | |
726 | ||
727 | static int disable_debounce(struct gpio_chip *chip, unsigned int offset) | |
728 | { | |
729 | struct aspeed_gpio *gpio = gpiochip_get_data(chip); | |
730 | unsigned long flags; | |
731 | int rc; | |
732 | ||
733 | spin_lock_irqsave(&gpio->lock, flags); | |
734 | ||
735 | rc = unregister_allocated_timer(gpio, offset); | |
736 | if (!rc) | |
737 | configure_timer(gpio, offset, 0); | |
738 | ||
739 | spin_unlock_irqrestore(&gpio->lock, flags); | |
740 | ||
741 | return rc; | |
742 | } | |
743 | ||
744 | static int set_debounce(struct gpio_chip *chip, unsigned int offset, | |
745 | unsigned long usecs) | |
746 | { | |
747 | struct aspeed_gpio *gpio = gpiochip_get_data(chip); | |
748 | ||
749 | if (!have_debounce(gpio, offset)) | |
750 | return -ENOTSUPP; | |
751 | ||
752 | if (usecs) | |
753 | return enable_debounce(chip, offset, usecs); | |
754 | ||
755 | return disable_debounce(chip, offset); | |
756 | } | |
757 | ||
758 | static int aspeed_gpio_set_config(struct gpio_chip *chip, unsigned int offset, | |
759 | unsigned long config) | |
760 | { | |
761 | unsigned long param = pinconf_to_config_param(config); | |
762 | u32 arg = pinconf_to_config_argument(config); | |
763 | ||
764 | if (param == PIN_CONFIG_INPUT_DEBOUNCE) | |
765 | return set_debounce(chip, offset, arg); | |
766 | else if (param == PIN_CONFIG_BIAS_DISABLE || | |
767 | param == PIN_CONFIG_BIAS_PULL_DOWN || | |
768 | param == PIN_CONFIG_DRIVE_STRENGTH) | |
769 | return pinctrl_gpio_set_config(offset, config); | |
c3bafe01 AJ |
770 | else if (param == PIN_CONFIG_DRIVE_OPEN_DRAIN || |
771 | param == PIN_CONFIG_DRIVE_OPEN_SOURCE) | |
772 | /* Return -ENOTSUPP to trigger emulation, as per datasheet */ | |
773 | return -ENOTSUPP; | |
5ae4cb94 AJ |
774 | |
775 | return -ENOTSUPP; | |
776 | } | |
777 | ||
1736f75d AJ |
778 | /* |
779 | * Any banks not specified in a struct aspeed_bank_props array are assumed to | |
780 | * have the properties: | |
781 | * | |
782 | * { .input = 0xffffffff, .output = 0xffffffff } | |
783 | */ | |
784 | ||
785 | static const struct aspeed_bank_props ast2400_bank_props[] = { | |
786 | /* input output */ | |
787 | { 5, 0xffffffff, 0x0000ffff }, /* U/V/W/X */ | |
788 | { 6, 0x0000000f, 0x0fffff0f }, /* Y/Z/AA/AB, two 4-GPIO holes */ | |
789 | { }, | |
790 | }; | |
791 | ||
792 | static const struct aspeed_gpio_config ast2400_config = | |
793 | /* 220 for simplicity, really 216 with two 4-GPIO holes, four at end */ | |
794 | { .nr_gpios = 220, .props = ast2400_bank_props, }; | |
795 | ||
796 | static const struct aspeed_bank_props ast2500_bank_props[] = { | |
797 | /* input output */ | |
798 | { 5, 0xffffffff, 0x0000ffff }, /* U/V/W/X */ | |
799 | { 6, 0x0fffffff, 0x0fffffff }, /* Y/Z/AA/AB, 4-GPIO hole */ | |
800 | { 7, 0x000000ff, 0x000000ff }, /* AC */ | |
801 | { }, | |
802 | }; | |
803 | ||
804 | static const struct aspeed_gpio_config ast2500_config = | |
805 | /* 232 for simplicity, actual number is 228 (4-GPIO hole in GPIOAB) */ | |
806 | { .nr_gpios = 232, .props = ast2500_bank_props, }; | |
807 | ||
808 | static const struct of_device_id aspeed_gpio_of_table[] = { | |
809 | { .compatible = "aspeed,ast2400-gpio", .data = &ast2400_config, }, | |
810 | { .compatible = "aspeed,ast2500-gpio", .data = &ast2500_config, }, | |
811 | {} | |
812 | }; | |
813 | MODULE_DEVICE_TABLE(of, aspeed_gpio_of_table); | |
814 | ||
361b7911 JS |
815 | static int __init aspeed_gpio_probe(struct platform_device *pdev) |
816 | { | |
1736f75d | 817 | const struct of_device_id *gpio_id; |
361b7911 JS |
818 | struct aspeed_gpio *gpio; |
819 | struct resource *res; | |
820 | int rc; | |
821 | ||
822 | gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL); | |
823 | if (!gpio) | |
824 | return -ENOMEM; | |
825 | ||
826 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
361b7911 | 827 | gpio->base = devm_ioremap_resource(&pdev->dev, res); |
7f8b9657 WY |
828 | if (IS_ERR(gpio->base)) |
829 | return PTR_ERR(gpio->base); | |
361b7911 JS |
830 | |
831 | spin_lock_init(&gpio->lock); | |
832 | ||
1736f75d AJ |
833 | gpio_id = of_match_node(aspeed_gpio_of_table, pdev->dev.of_node); |
834 | if (!gpio_id) | |
835 | return -EINVAL; | |
836 | ||
5ae4cb94 AJ |
837 | gpio->clk = of_clk_get(pdev->dev.of_node, 0); |
838 | if (IS_ERR(gpio->clk)) { | |
839 | dev_warn(&pdev->dev, | |
754c0458 | 840 | "Failed to get clock from devicetree, debouncing disabled\n"); |
5ae4cb94 AJ |
841 | gpio->clk = NULL; |
842 | } | |
843 | ||
1736f75d | 844 | gpio->config = gpio_id->data; |
361b7911 | 845 | |
5ae4cb94 | 846 | gpio->chip.parent = &pdev->dev; |
1736f75d | 847 | gpio->chip.ngpio = gpio->config->nr_gpios; |
361b7911 JS |
848 | gpio->chip.parent = &pdev->dev; |
849 | gpio->chip.direction_input = aspeed_gpio_dir_in; | |
850 | gpio->chip.direction_output = aspeed_gpio_dir_out; | |
851 | gpio->chip.get_direction = aspeed_gpio_get_direction; | |
852 | gpio->chip.request = aspeed_gpio_request; | |
853 | gpio->chip.free = aspeed_gpio_free; | |
854 | gpio->chip.get = aspeed_gpio_get; | |
855 | gpio->chip.set = aspeed_gpio_set; | |
5ae4cb94 | 856 | gpio->chip.set_config = aspeed_gpio_set_config; |
361b7911 JS |
857 | gpio->chip.label = dev_name(&pdev->dev); |
858 | gpio->chip.base = -1; | |
1736f75d | 859 | gpio->chip.irq_need_valid_mask = true; |
361b7911 JS |
860 | |
861 | rc = devm_gpiochip_add_data(&pdev->dev, &gpio->chip, gpio); | |
862 | if (rc < 0) | |
863 | return rc; | |
864 | ||
5ae4cb94 AJ |
865 | gpio->offset_timer = |
866 | devm_kzalloc(&pdev->dev, gpio->chip.ngpio, GFP_KERNEL); | |
867 | ||
361b7911 JS |
868 | return aspeed_gpio_setup_irqs(gpio, pdev); |
869 | } | |
870 | ||
361b7911 JS |
871 | static struct platform_driver aspeed_gpio_driver = { |
872 | .driver = { | |
873 | .name = KBUILD_MODNAME, | |
874 | .of_match_table = aspeed_gpio_of_table, | |
875 | }, | |
876 | }; | |
877 | ||
878 | module_platform_driver_probe(aspeed_gpio_driver, aspeed_gpio_probe); | |
879 | ||
880 | MODULE_DESCRIPTION("Aspeed GPIO Driver"); | |
e50237c7 | 881 | MODULE_LICENSE("GPL"); |