[mirror_ubuntu-bionic-kernel.git] / drivers / gpio / gpio-ath79.c

/*
 *  Atheros AR71XX/AR724X/AR913X GPIO API support
 *
 *  Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
 *  Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
 *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
 *
 *  Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
 *
 *  This program is free software; you can redistribute it and/or modify it
 *  under the terms of the GNU General Public License version 2 as published
 *  by the Free Software Foundation.
 */

#include <linux/gpio/driver.h>
#include <linux/platform_data/gpio-ath79.h>
#include <linux/of_device.h>

#include <asm/mach-ath79/ar71xx_regs.h>

struct ath79_gpio_ctrl {
	struct gpio_chip chip;
	void __iomem *base;
	spinlock_t lock;
};

static void ath79_gpio_set_value(struct gpio_chip *chip,
				unsigned gpio, int value)
{
	struct ath79_gpio_ctrl *ctrl = gpiochip_get_data(chip);

	if (value)
		__raw_writel(BIT(gpio), ctrl->base + AR71XX_GPIO_REG_SET);
	else
		__raw_writel(BIT(gpio), ctrl->base + AR71XX_GPIO_REG_CLEAR);
}

static int ath79_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
{
	struct ath79_gpio_ctrl *ctrl = gpiochip_get_data(chip);

	return (__raw_readl(ctrl->base + AR71XX_GPIO_REG_IN) >> gpio) & 1;
}

static int ath79_gpio_direction_input(struct gpio_chip *chip,
				       unsigned offset)
{
	struct ath79_gpio_ctrl *ctrl = gpiochip_get_data(chip);
	unsigned long flags;

	spin_lock_irqsave(&ctrl->lock, flags);

	__raw_writel(
		__raw_readl(ctrl->base + AR71XX_GPIO_REG_OE) & ~BIT(offset),
		ctrl->base + AR71XX_GPIO_REG_OE);

	spin_unlock_irqrestore(&ctrl->lock, flags);

	return 0;
}

static int ath79_gpio_direction_output(struct gpio_chip *chip,
					unsigned offset, int value)
{
	struct ath79_gpio_ctrl *ctrl = gpiochip_get_data(chip);
	unsigned long flags;

	spin_lock_irqsave(&ctrl->lock, flags);

	if (value)
		__raw_writel(BIT(offset), ctrl->base + AR71XX_GPIO_REG_SET);
	else
		__raw_writel(BIT(offset), ctrl->base + AR71XX_GPIO_REG_CLEAR);

	__raw_writel(
		__raw_readl(ctrl->base + AR71XX_GPIO_REG_OE) | BIT(offset),
		ctrl->base + AR71XX_GPIO_REG_OE);

	spin_unlock_irqrestore(&ctrl->lock, flags);

	return 0;
}

static int ar934x_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
{
	struct ath79_gpio_ctrl *ctrl = gpiochip_get_data(chip);
	unsigned long flags;

	spin_lock_irqsave(&ctrl->lock, flags);

	__raw_writel(
		__raw_readl(ctrl->base + AR71XX_GPIO_REG_OE) | BIT(offset),
		ctrl->base + AR71XX_GPIO_REG_OE);

	spin_unlock_irqrestore(&ctrl->lock, flags);

	return 0;
}

static int ar934x_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
					int value)
{
	struct ath79_gpio_ctrl *ctrl = gpiochip_get_data(chip);
	unsigned long flags;

	spin_lock_irqsave(&ctrl->lock, flags);

	if (value)
		__raw_writel(BIT(offset), ctrl->base + AR71XX_GPIO_REG_SET);
	else
		__raw_writel(BIT(offset), ctrl->base + AR71XX_GPIO_REG_CLEAR);

	__raw_writel(
		__raw_readl(ctrl->base + AR71XX_GPIO_REG_OE) & ~BIT(offset),
		ctrl->base + AR71XX_GPIO_REG_OE);

	spin_unlock_irqrestore(&ctrl->lock, flags);

	return 0;
}

static const struct gpio_chip ath79_gpio_chip = {
	.label			= "ath79",
	.get			= ath79_gpio_get_value,
	.set			= ath79_gpio_set_value,
	.direction_input	= ath79_gpio_direction_input,
	.direction_output	= ath79_gpio_direction_output,
	.base			= 0,
};

static const struct of_device_id ath79_gpio_of_match[] = {
	{ .compatible = "qca,ar7100-gpio" },
	{ .compatible = "qca,ar9340-gpio" },
	{},
};

static int ath79_gpio_probe(struct platform_device *pdev)
{
	struct ath79_gpio_platform_data *pdata = dev_get_platdata(&pdev->dev);
	struct device_node *np = pdev->dev.of_node;
	struct ath79_gpio_ctrl *ctrl;
	struct resource *res;
	u32 ath79_gpio_count;
	bool oe_inverted;
	int err;

	ctrl = devm_kzalloc(&pdev->dev, sizeof(*ctrl), GFP_KERNEL);
	if (!ctrl)
		return -ENOMEM;

	if (np) {
		err = of_property_read_u32(np, "ngpios", &ath79_gpio_count);
		if (err) {
			dev_err(&pdev->dev, "ngpios property is not valid\n");
			return err;
		}
		if (ath79_gpio_count >= 32) {
			dev_err(&pdev->dev, "ngpios must be less than 32\n");
			return -EINVAL;
		}
		oe_inverted = of_device_is_compatible(np, "qca,ar9340-gpio");
	} else if (pdata) {
		ath79_gpio_count = pdata->ngpios;
		oe_inverted = pdata->oe_inverted;
	} else {
		dev_err(&pdev->dev, "No DT node or platform data found\n");
		return -EINVAL;
	}

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	ctrl->base = devm_ioremap_nocache(
		&pdev->dev, res->start, resource_size(res));
	if (!ctrl->base)
		return -ENOMEM;

	spin_lock_init(&ctrl->lock);
	memcpy(&ctrl->chip, &ath79_gpio_chip, sizeof(ctrl->chip));
	ctrl->chip.parent = &pdev->dev;
	ctrl->chip.ngpio = ath79_gpio_count;
	if (oe_inverted) {
		ctrl->chip.direction_input = ar934x_gpio_direction_input;
		ctrl->chip.direction_output = ar934x_gpio_direction_output;
	}

	err = gpiochip_add_data(&ctrl->chip, ctrl);
	if (err) {
		dev_err(&pdev->dev,
			"cannot add AR71xx GPIO chip, error=%d", err);
		return err;
	}

	return 0;
}

static struct platform_driver ath79_gpio_driver = {
	.driver = {
		.name = "ath79-gpio",
		.of_match_table	= ath79_gpio_of_match,
	},
	.probe = ath79_gpio_probe,
};

module_platform_driver(ath79_gpio_driver);
Commit	Line	Data
6eae43c5 GJ	1	/*
	2	* Atheros AR71XX/AR724X/AR913X GPIO API support
	3	*
5b5b544e GJ	4	* Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
5b5b544e GJ	5	* Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
6eae43c5 GJ	6	* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6eae43c5 GJ	7	*
5b5b544e GJ	8	* Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
5b5b544e GJ	9	*
6eae43c5 GJ	10	* This program is free software; you can redistribute it and/or modify it
	11	* under the terms of the GNU General Public License version 2 as published
	12	* by the Free Software Foundation.
	13	*/
	14
49a5bd88	15	#include <linux/gpio/driver.h>
2ddf3a79 AB	16	#include <linux/platform_data/gpio-ath79.h>
2ddf3a79 AB	17	#include <linux/of_device.h>
6eae43c5 GJ	18
6eae43c5 GJ	19	#include <asm/mach-ath79/ar71xx_regs.h>
6eae43c5	20
49a5bd88 AB	21	struct ath79_gpio_ctrl {
	22	struct gpio_chip chip;
	23	void __iomem *base;
	24	spinlock_t lock;
	25	};
	26
49a5bd88 AB	27	static void ath79_gpio_set_value(struct gpio_chip *chip,
49a5bd88 AB	28	unsigned gpio, int value)
6eae43c5	29	{
b4e97a61	30	struct ath79_gpio_ctrl *ctrl = gpiochip_get_data(chip);
6eae43c5 GJ	31
6eae43c5 GJ	32	if (value)
49a5bd88	33	__raw_writel(BIT(gpio), ctrl->base + AR71XX_GPIO_REG_SET);
6eae43c5	34	else
49a5bd88	35	__raw_writel(BIT(gpio), ctrl->base + AR71XX_GPIO_REG_CLEAR);
6eae43c5 GJ	36	}
6eae43c5 GJ	37
49a5bd88	38	static int ath79_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
6eae43c5	39	{
b4e97a61	40	struct ath79_gpio_ctrl *ctrl = gpiochip_get_data(chip);
6eae43c5	41
49a5bd88	42	return (__raw_readl(ctrl->base + AR71XX_GPIO_REG_IN) >> gpio) & 1;
6eae43c5 GJ	43	}
	44
	45	static int ath79_gpio_direction_input(struct gpio_chip *chip,
	46	unsigned offset)
	47	{
b4e97a61	48	struct ath79_gpio_ctrl *ctrl = gpiochip_get_data(chip);
6eae43c5 GJ	49	unsigned long flags;
6eae43c5 GJ	50
49a5bd88	51	spin_lock_irqsave(&ctrl->lock, flags);
6eae43c5	52
49a5bd88 AB	53	__raw_writel(
	54	__raw_readl(ctrl->base + AR71XX_GPIO_REG_OE) & ~BIT(offset),
	55	ctrl->base + AR71XX_GPIO_REG_OE);
6eae43c5	56
49a5bd88	57	spin_unlock_irqrestore(&ctrl->lock, flags);
6eae43c5 GJ	58
	59	return 0;
	60	}
	61
	62	static int ath79_gpio_direction_output(struct gpio_chip *chip,
	63	unsigned offset, int value)
	64	{
b4e97a61	65	struct ath79_gpio_ctrl *ctrl = gpiochip_get_data(chip);
6eae43c5 GJ	66	unsigned long flags;
6eae43c5 GJ	67
49a5bd88	68	spin_lock_irqsave(&ctrl->lock, flags);
6eae43c5 GJ	69
6eae43c5 GJ	70	if (value)
49a5bd88	71	__raw_writel(BIT(offset), ctrl->base + AR71XX_GPIO_REG_SET);
6eae43c5	72	else
49a5bd88	73	__raw_writel(BIT(offset), ctrl->base + AR71XX_GPIO_REG_CLEAR);
6eae43c5	74
49a5bd88 AB	75	__raw_writel(
	76	__raw_readl(ctrl->base + AR71XX_GPIO_REG_OE) \| BIT(offset),
	77	ctrl->base + AR71XX_GPIO_REG_OE);
6eae43c5	78
49a5bd88	79	spin_unlock_irqrestore(&ctrl->lock, flags);
6eae43c5 GJ	80
	81	return 0;
	82	}
	83
5b5b544e GJ	84	static int ar934x_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
5b5b544e GJ	85	{
b4e97a61	86	struct ath79_gpio_ctrl *ctrl = gpiochip_get_data(chip);
5b5b544e GJ	87	unsigned long flags;
5b5b544e GJ	88
49a5bd88	89	spin_lock_irqsave(&ctrl->lock, flags);
5b5b544e	90
49a5bd88 AB	91	__raw_writel(
	92	__raw_readl(ctrl->base + AR71XX_GPIO_REG_OE) \| BIT(offset),
	93	ctrl->base + AR71XX_GPIO_REG_OE);
5b5b544e	94
49a5bd88	95	spin_unlock_irqrestore(&ctrl->lock, flags);
5b5b544e GJ	96
	97	return 0;
	98	}
	99
	100	static int ar934x_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
	101	int value)
	102	{
b4e97a61	103	struct ath79_gpio_ctrl *ctrl = gpiochip_get_data(chip);
5b5b544e GJ	104	unsigned long flags;
5b5b544e GJ	105
49a5bd88	106	spin_lock_irqsave(&ctrl->lock, flags);
5b5b544e GJ	107
5b5b544e GJ	108	if (value)
49a5bd88	109	__raw_writel(BIT(offset), ctrl->base + AR71XX_GPIO_REG_SET);
5b5b544e	110	else
49a5bd88	111	__raw_writel(BIT(offset), ctrl->base + AR71XX_GPIO_REG_CLEAR);
5b5b544e	112
49a5bd88	113	__raw_writel(
3a57e741	114	__raw_readl(ctrl->base + AR71XX_GPIO_REG_OE) & ~BIT(offset),
49a5bd88	115	ctrl->base + AR71XX_GPIO_REG_OE);
5b5b544e	116
49a5bd88	117	spin_unlock_irqrestore(&ctrl->lock, flags);
5b5b544e GJ	118
	119	return 0;
	120	}
	121
49a5bd88	122	static const struct gpio_chip ath79_gpio_chip = {
6eae43c5 GJ	123	.label = "ath79",
	124	.get = ath79_gpio_get_value,
	125	.set = ath79_gpio_set_value,
	126	.direction_input = ath79_gpio_direction_input,
	127	.direction_output = ath79_gpio_direction_output,
	128	.base = 0,
	129	};
	130
2ddf3a79 AB	131	static const struct of_device_id ath79_gpio_of_match[] = {
	132	{ .compatible = "qca,ar7100-gpio" },
	133	{ .compatible = "qca,ar9340-gpio" },
	134	{},
	135	};
	136
	137	static int ath79_gpio_probe(struct platform_device *pdev)
6eae43c5	138	{
ab128afc	139	struct ath79_gpio_platform_data *pdata = dev_get_platdata(&pdev->dev);
2ddf3a79	140	struct device_node *np = pdev->dev.of_node;
49a5bd88	141	struct ath79_gpio_ctrl *ctrl;
2ddf3a79	142	struct resource *res;
49a5bd88	143	u32 ath79_gpio_count;
2ddf3a79	144	bool oe_inverted;
6eae43c5 GJ	145	int err;
6eae43c5 GJ	146
49a5bd88 AB	147	ctrl = devm_kzalloc(&pdev->dev, sizeof(*ctrl), GFP_KERNEL);
	148	if (!ctrl)
	149	return -ENOMEM;
	150
2ddf3a79 AB	151	if (np) {
	152	err = of_property_read_u32(np, "ngpios", &ath79_gpio_count);
	153	if (err) {
	154	dev_err(&pdev->dev, "ngpios property is not valid\n");
	155	return err;
	156	}
	157	if (ath79_gpio_count >= 32) {
	158	dev_err(&pdev->dev, "ngpios must be less than 32\n");
	159	return -EINVAL;
	160	}
	161	oe_inverted = of_device_is_compatible(np, "qca,ar9340-gpio");
	162	} else if (pdata) {
	163	ath79_gpio_count = pdata->ngpios;
	164	oe_inverted = pdata->oe_inverted;
	165	} else {
	166	dev_err(&pdev->dev, "No DT node or platform data found\n");
	167	return -EINVAL;
	168	}
	169
	170	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
49a5bd88	171	ctrl->base = devm_ioremap_nocache(
2ddf3a79	172	&pdev->dev, res->start, resource_size(res));
49a5bd88	173	if (!ctrl->base)
2ddf3a79	174	return -ENOMEM;
6eae43c5	175
49a5bd88 AB	176	spin_lock_init(&ctrl->lock);
49a5bd88 AB	177	memcpy(&ctrl->chip, &ath79_gpio_chip, sizeof(ctrl->chip));
58383c78	178	ctrl->chip.parent = &pdev->dev;
49a5bd88	179	ctrl->chip.ngpio = ath79_gpio_count;
2ddf3a79	180	if (oe_inverted) {
49a5bd88 AB	181	ctrl->chip.direction_input = ar934x_gpio_direction_input;
49a5bd88 AB	182	ctrl->chip.direction_output = ar934x_gpio_direction_output;
5b5b544e	183	}
6eae43c5	184
b4e97a61	185	err = gpiochip_add_data(&ctrl->chip, ctrl);
2ddf3a79 AB	186	if (err) {
	187	dev_err(&pdev->dev,
	188	"cannot add AR71xx GPIO chip, error=%d", err);
	189	return err;
	190	}
	191
	192	return 0;
6eae43c5 GJ	193	}
6eae43c5 GJ	194
2ddf3a79 AB	195	static struct platform_driver ath79_gpio_driver = {
	196	.driver = {
	197	.name = "ath79-gpio",
	198	.of_match_table = ath79_gpio_of_match,
	199	},
	200	.probe = ath79_gpio_probe,
	201	};
	202
	203	module_platform_driver(ath79_gpio_driver);