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757651e3 | 1 | /* |
8f3e19fa PG |
2 | * Broadcom Kona GPIO Driver |
3 | * | |
4 | * Author: Broadcom Corporation <bcm-kernel-feedback-list@broadcom.com> | |
6f587c9f | 5 | * Copyright (C) 2012-2014 Broadcom Corporation |
757651e3 MM |
6 | * |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License as | |
9 | * published by the Free Software Foundation version 2. | |
10 | * | |
11 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any | |
12 | * kind, whether express or implied; without even the implied warranty | |
13 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | */ | |
16 | ||
17 | #include <linux/bitops.h> | |
18 | #include <linux/err.h> | |
19 | #include <linux/io.h> | |
14ec018e | 20 | #include <linux/gpio/driver.h> |
757651e3 MM |
21 | #include <linux/of_device.h> |
22 | #include <linux/of_irq.h> | |
8f3e19fa | 23 | #include <linux/init.h> |
757651e3 MM |
24 | #include <linux/irqdomain.h> |
25 | #include <linux/irqchip/chained_irq.h> | |
26 | ||
27 | #define BCM_GPIO_PASSWD 0x00a5a501 | |
28 | #define GPIO_PER_BANK 32 | |
29 | #define GPIO_MAX_BANK_NUM 8 | |
30 | ||
31 | #define GPIO_BANK(gpio) ((gpio) >> 5) | |
32 | #define GPIO_BIT(gpio) ((gpio) & (GPIO_PER_BANK - 1)) | |
33 | ||
d762bae4 MM |
34 | /* There is a GPIO control register for each GPIO */ |
35 | #define GPIO_CONTROL(gpio) (0x00000100 + ((gpio) << 2)) | |
36 | ||
37 | /* The remaining registers are per GPIO bank */ | |
757651e3 MM |
38 | #define GPIO_OUT_STATUS(bank) (0x00000000 + ((bank) << 2)) |
39 | #define GPIO_IN_STATUS(bank) (0x00000020 + ((bank) << 2)) | |
40 | #define GPIO_OUT_SET(bank) (0x00000040 + ((bank) << 2)) | |
41 | #define GPIO_OUT_CLEAR(bank) (0x00000060 + ((bank) << 2)) | |
42 | #define GPIO_INT_STATUS(bank) (0x00000080 + ((bank) << 2)) | |
43 | #define GPIO_INT_MASK(bank) (0x000000a0 + ((bank) << 2)) | |
44 | #define GPIO_INT_MSKCLR(bank) (0x000000c0 + ((bank) << 2)) | |
757651e3 MM |
45 | #define GPIO_PWD_STATUS(bank) (0x00000500 + ((bank) << 2)) |
46 | ||
47 | #define GPIO_GPPWR_OFFSET 0x00000520 | |
48 | ||
49 | #define GPIO_GPCTR0_DBR_SHIFT 5 | |
50 | #define GPIO_GPCTR0_DBR_MASK 0x000001e0 | |
51 | ||
52 | #define GPIO_GPCTR0_ITR_SHIFT 3 | |
53 | #define GPIO_GPCTR0_ITR_MASK 0x00000018 | |
54 | #define GPIO_GPCTR0_ITR_CMD_RISING_EDGE 0x00000001 | |
55 | #define GPIO_GPCTR0_ITR_CMD_FALLING_EDGE 0x00000002 | |
56 | #define GPIO_GPCTR0_ITR_CMD_BOTH_EDGE 0x00000003 | |
57 | ||
58 | #define GPIO_GPCTR0_IOTR_MASK 0x00000001 | |
59 | #define GPIO_GPCTR0_IOTR_CMD_0UTPUT 0x00000000 | |
60 | #define GPIO_GPCTR0_IOTR_CMD_INPUT 0x00000001 | |
61 | ||
62 | #define GPIO_GPCTR0_DB_ENABLE_MASK 0x00000100 | |
63 | ||
64 | #define LOCK_CODE 0xffffffff | |
65 | #define UNLOCK_CODE 0x00000000 | |
66 | ||
67 | struct bcm_kona_gpio { | |
68 | void __iomem *reg_base; | |
69 | int num_bank; | |
c69fcea5 | 70 | raw_spinlock_t lock; |
757651e3 MM |
71 | struct gpio_chip gpio_chip; |
72 | struct irq_domain *irq_domain; | |
73 | struct bcm_kona_gpio_bank *banks; | |
74 | struct platform_device *pdev; | |
75 | }; | |
76 | ||
77 | struct bcm_kona_gpio_bank { | |
78 | int id; | |
79 | int irq; | |
80 | /* Used in the interrupt handler */ | |
81 | struct bcm_kona_gpio *kona_gpio; | |
82 | }; | |
83 | ||
bdb93c03 MM |
84 | static inline void bcm_kona_gpio_write_lock_regs(void __iomem *reg_base, |
85 | int bank_id, u32 lockcode) | |
757651e3 MM |
86 | { |
87 | writel(BCM_GPIO_PASSWD, reg_base + GPIO_GPPWR_OFFSET); | |
88 | writel(lockcode, reg_base + GPIO_PWD_STATUS(bank_id)); | |
89 | } | |
90 | ||
bdb93c03 MM |
91 | static void bcm_kona_gpio_lock_gpio(struct bcm_kona_gpio *kona_gpio, |
92 | unsigned gpio) | |
757651e3 | 93 | { |
bdb93c03 MM |
94 | u32 val; |
95 | unsigned long flags; | |
96 | int bank_id = GPIO_BANK(gpio); | |
97 | ||
c69fcea5 | 98 | raw_spin_lock_irqsave(&kona_gpio->lock, flags); |
bdb93c03 MM |
99 | |
100 | val = readl(kona_gpio->reg_base + GPIO_PWD_STATUS(bank_id)); | |
101 | val |= BIT(gpio); | |
102 | bcm_kona_gpio_write_lock_regs(kona_gpio->reg_base, bank_id, val); | |
103 | ||
c69fcea5 | 104 | raw_spin_unlock_irqrestore(&kona_gpio->lock, flags); |
757651e3 MM |
105 | } |
106 | ||
bdb93c03 MM |
107 | static void bcm_kona_gpio_unlock_gpio(struct bcm_kona_gpio *kona_gpio, |
108 | unsigned gpio) | |
757651e3 | 109 | { |
bdb93c03 MM |
110 | u32 val; |
111 | unsigned long flags; | |
112 | int bank_id = GPIO_BANK(gpio); | |
113 | ||
c69fcea5 | 114 | raw_spin_lock_irqsave(&kona_gpio->lock, flags); |
bdb93c03 MM |
115 | |
116 | val = readl(kona_gpio->reg_base + GPIO_PWD_STATUS(bank_id)); | |
117 | val &= ~BIT(gpio); | |
118 | bcm_kona_gpio_write_lock_regs(kona_gpio->reg_base, bank_id, val); | |
119 | ||
c69fcea5 | 120 | raw_spin_unlock_irqrestore(&kona_gpio->lock, flags); |
757651e3 MM |
121 | } |
122 | ||
0218d5a8 AL |
123 | static int bcm_kona_gpio_get_dir(struct gpio_chip *chip, unsigned gpio) |
124 | { | |
ba4a7448 | 125 | struct bcm_kona_gpio *kona_gpio = gpiochip_get_data(chip); |
0218d5a8 AL |
126 | void __iomem *reg_base = kona_gpio->reg_base; |
127 | u32 val; | |
128 | ||
129 | val = readl(reg_base + GPIO_CONTROL(gpio)) & GPIO_GPCTR0_IOTR_MASK; | |
14ec018e | 130 | return !!val; |
0218d5a8 AL |
131 | } |
132 | ||
757651e3 MM |
133 | static void bcm_kona_gpio_set(struct gpio_chip *chip, unsigned gpio, int value) |
134 | { | |
135 | struct bcm_kona_gpio *kona_gpio; | |
136 | void __iomem *reg_base; | |
137 | int bank_id = GPIO_BANK(gpio); | |
138 | int bit = GPIO_BIT(gpio); | |
139 | u32 val, reg_offset; | |
140 | unsigned long flags; | |
141 | ||
ba4a7448 | 142 | kona_gpio = gpiochip_get_data(chip); |
757651e3 | 143 | reg_base = kona_gpio->reg_base; |
c69fcea5 | 144 | raw_spin_lock_irqsave(&kona_gpio->lock, flags); |
757651e3 | 145 | |
757651e3 | 146 | /* this function only applies to output pin */ |
14ec018e | 147 | if (bcm_kona_gpio_get_dir(chip, gpio) == 1) |
757651e3 MM |
148 | goto out; |
149 | ||
150 | reg_offset = value ? GPIO_OUT_SET(bank_id) : GPIO_OUT_CLEAR(bank_id); | |
151 | ||
152 | val = readl(reg_base + reg_offset); | |
153 | val |= BIT(bit); | |
154 | writel(val, reg_base + reg_offset); | |
155 | ||
156 | out: | |
c69fcea5 | 157 | raw_spin_unlock_irqrestore(&kona_gpio->lock, flags); |
757651e3 MM |
158 | } |
159 | ||
160 | static int bcm_kona_gpio_get(struct gpio_chip *chip, unsigned gpio) | |
161 | { | |
162 | struct bcm_kona_gpio *kona_gpio; | |
163 | void __iomem *reg_base; | |
164 | int bank_id = GPIO_BANK(gpio); | |
165 | int bit = GPIO_BIT(gpio); | |
166 | u32 val, reg_offset; | |
167 | unsigned long flags; | |
168 | ||
ba4a7448 | 169 | kona_gpio = gpiochip_get_data(chip); |
757651e3 | 170 | reg_base = kona_gpio->reg_base; |
c69fcea5 | 171 | raw_spin_lock_irqsave(&kona_gpio->lock, flags); |
757651e3 | 172 | |
14ec018e | 173 | if (bcm_kona_gpio_get_dir(chip, gpio) == 1) |
0218d5a8 AL |
174 | reg_offset = GPIO_IN_STATUS(bank_id); |
175 | else | |
176 | reg_offset = GPIO_OUT_STATUS(bank_id); | |
757651e3 MM |
177 | |
178 | /* read the GPIO bank status */ | |
757651e3 MM |
179 | val = readl(reg_base + reg_offset); |
180 | ||
c69fcea5 | 181 | raw_spin_unlock_irqrestore(&kona_gpio->lock, flags); |
757651e3 MM |
182 | |
183 | /* return the specified bit status */ | |
e2f0b005 | 184 | return !!(val & BIT(bit)); |
757651e3 MM |
185 | } |
186 | ||
bdb93c03 MM |
187 | static int bcm_kona_gpio_request(struct gpio_chip *chip, unsigned gpio) |
188 | { | |
ba4a7448 | 189 | struct bcm_kona_gpio *kona_gpio = gpiochip_get_data(chip); |
bdb93c03 MM |
190 | |
191 | bcm_kona_gpio_unlock_gpio(kona_gpio, gpio); | |
192 | return 0; | |
193 | } | |
194 | ||
195 | static void bcm_kona_gpio_free(struct gpio_chip *chip, unsigned gpio) | |
196 | { | |
ba4a7448 | 197 | struct bcm_kona_gpio *kona_gpio = gpiochip_get_data(chip); |
bdb93c03 MM |
198 | |
199 | bcm_kona_gpio_lock_gpio(kona_gpio, gpio); | |
200 | } | |
201 | ||
757651e3 MM |
202 | static int bcm_kona_gpio_direction_input(struct gpio_chip *chip, unsigned gpio) |
203 | { | |
204 | struct bcm_kona_gpio *kona_gpio; | |
205 | void __iomem *reg_base; | |
206 | u32 val; | |
207 | unsigned long flags; | |
757651e3 | 208 | |
ba4a7448 | 209 | kona_gpio = gpiochip_get_data(chip); |
757651e3 | 210 | reg_base = kona_gpio->reg_base; |
c69fcea5 | 211 | raw_spin_lock_irqsave(&kona_gpio->lock, flags); |
757651e3 MM |
212 | |
213 | val = readl(reg_base + GPIO_CONTROL(gpio)); | |
214 | val &= ~GPIO_GPCTR0_IOTR_MASK; | |
215 | val |= GPIO_GPCTR0_IOTR_CMD_INPUT; | |
216 | writel(val, reg_base + GPIO_CONTROL(gpio)); | |
217 | ||
c69fcea5 | 218 | raw_spin_unlock_irqrestore(&kona_gpio->lock, flags); |
757651e3 MM |
219 | |
220 | return 0; | |
221 | } | |
222 | ||
223 | static int bcm_kona_gpio_direction_output(struct gpio_chip *chip, | |
224 | unsigned gpio, int value) | |
225 | { | |
226 | struct bcm_kona_gpio *kona_gpio; | |
227 | void __iomem *reg_base; | |
228 | int bank_id = GPIO_BANK(gpio); | |
229 | int bit = GPIO_BIT(gpio); | |
230 | u32 val, reg_offset; | |
231 | unsigned long flags; | |
232 | ||
ba4a7448 | 233 | kona_gpio = gpiochip_get_data(chip); |
757651e3 | 234 | reg_base = kona_gpio->reg_base; |
c69fcea5 | 235 | raw_spin_lock_irqsave(&kona_gpio->lock, flags); |
757651e3 MM |
236 | |
237 | val = readl(reg_base + GPIO_CONTROL(gpio)); | |
238 | val &= ~GPIO_GPCTR0_IOTR_MASK; | |
239 | val |= GPIO_GPCTR0_IOTR_CMD_0UTPUT; | |
240 | writel(val, reg_base + GPIO_CONTROL(gpio)); | |
241 | reg_offset = value ? GPIO_OUT_SET(bank_id) : GPIO_OUT_CLEAR(bank_id); | |
242 | ||
243 | val = readl(reg_base + reg_offset); | |
244 | val |= BIT(bit); | |
245 | writel(val, reg_base + reg_offset); | |
246 | ||
c69fcea5 | 247 | raw_spin_unlock_irqrestore(&kona_gpio->lock, flags); |
757651e3 MM |
248 | |
249 | return 0; | |
250 | } | |
251 | ||
252 | static int bcm_kona_gpio_to_irq(struct gpio_chip *chip, unsigned gpio) | |
253 | { | |
254 | struct bcm_kona_gpio *kona_gpio; | |
255 | ||
ba4a7448 | 256 | kona_gpio = gpiochip_get_data(chip); |
757651e3 MM |
257 | if (gpio >= kona_gpio->gpio_chip.ngpio) |
258 | return -ENXIO; | |
259 | return irq_create_mapping(kona_gpio->irq_domain, gpio); | |
260 | } | |
261 | ||
262 | static int bcm_kona_gpio_set_debounce(struct gpio_chip *chip, unsigned gpio, | |
263 | unsigned debounce) | |
264 | { | |
265 | struct bcm_kona_gpio *kona_gpio; | |
266 | void __iomem *reg_base; | |
267 | u32 val, res; | |
268 | unsigned long flags; | |
757651e3 | 269 | |
ba4a7448 | 270 | kona_gpio = gpiochip_get_data(chip); |
757651e3 MM |
271 | reg_base = kona_gpio->reg_base; |
272 | /* debounce must be 1-128ms (or 0) */ | |
273 | if ((debounce > 0 && debounce < 1000) || debounce > 128000) { | |
58383c78 | 274 | dev_err(chip->parent, "Debounce value %u not in range\n", |
757651e3 MM |
275 | debounce); |
276 | return -EINVAL; | |
277 | } | |
278 | ||
279 | /* calculate debounce bit value */ | |
280 | if (debounce != 0) { | |
281 | /* Convert to ms */ | |
282 | debounce /= 1000; | |
283 | /* find the MSB */ | |
284 | res = fls(debounce) - 1; | |
285 | /* Check if MSB-1 is set (round up or down) */ | |
286 | if (res > 0 && (debounce & BIT(res - 1))) | |
287 | res++; | |
288 | } | |
289 | ||
290 | /* spin lock for read-modify-write of the GPIO register */ | |
c69fcea5 | 291 | raw_spin_lock_irqsave(&kona_gpio->lock, flags); |
757651e3 MM |
292 | |
293 | val = readl(reg_base + GPIO_CONTROL(gpio)); | |
294 | val &= ~GPIO_GPCTR0_DBR_MASK; | |
295 | ||
296 | if (debounce == 0) { | |
297 | /* disable debounce */ | |
298 | val &= ~GPIO_GPCTR0_DB_ENABLE_MASK; | |
299 | } else { | |
300 | val |= GPIO_GPCTR0_DB_ENABLE_MASK | | |
301 | (res << GPIO_GPCTR0_DBR_SHIFT); | |
302 | } | |
303 | ||
304 | writel(val, reg_base + GPIO_CONTROL(gpio)); | |
305 | ||
c69fcea5 | 306 | raw_spin_unlock_irqrestore(&kona_gpio->lock, flags); |
757651e3 MM |
307 | |
308 | return 0; | |
309 | } | |
310 | ||
2956b5d9 MW |
311 | static int bcm_kona_gpio_set_config(struct gpio_chip *chip, unsigned gpio, |
312 | unsigned long config) | |
313 | { | |
314 | u32 debounce; | |
315 | ||
316 | if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE) | |
317 | return -ENOTSUPP; | |
318 | ||
319 | debounce = pinconf_to_config_argument(config); | |
320 | return bcm_kona_gpio_set_debounce(chip, gpio, debounce); | |
321 | } | |
322 | ||
e35b5ab0 | 323 | static const struct gpio_chip template_chip = { |
757651e3 | 324 | .label = "bcm-kona-gpio", |
afb3690c | 325 | .owner = THIS_MODULE, |
bdb93c03 MM |
326 | .request = bcm_kona_gpio_request, |
327 | .free = bcm_kona_gpio_free, | |
0218d5a8 | 328 | .get_direction = bcm_kona_gpio_get_dir, |
757651e3 MM |
329 | .direction_input = bcm_kona_gpio_direction_input, |
330 | .get = bcm_kona_gpio_get, | |
331 | .direction_output = bcm_kona_gpio_direction_output, | |
332 | .set = bcm_kona_gpio_set, | |
2956b5d9 | 333 | .set_config = bcm_kona_gpio_set_config, |
757651e3 MM |
334 | .to_irq = bcm_kona_gpio_to_irq, |
335 | .base = 0, | |
336 | }; | |
337 | ||
338 | static void bcm_kona_gpio_irq_ack(struct irq_data *d) | |
339 | { | |
340 | struct bcm_kona_gpio *kona_gpio; | |
341 | void __iomem *reg_base; | |
b7ab6973 | 342 | unsigned gpio = d->hwirq; |
757651e3 MM |
343 | int bank_id = GPIO_BANK(gpio); |
344 | int bit = GPIO_BIT(gpio); | |
345 | u32 val; | |
346 | unsigned long flags; | |
347 | ||
348 | kona_gpio = irq_data_get_irq_chip_data(d); | |
349 | reg_base = kona_gpio->reg_base; | |
c69fcea5 | 350 | raw_spin_lock_irqsave(&kona_gpio->lock, flags); |
757651e3 MM |
351 | |
352 | val = readl(reg_base + GPIO_INT_STATUS(bank_id)); | |
353 | val |= BIT(bit); | |
354 | writel(val, reg_base + GPIO_INT_STATUS(bank_id)); | |
355 | ||
c69fcea5 | 356 | raw_spin_unlock_irqrestore(&kona_gpio->lock, flags); |
757651e3 MM |
357 | } |
358 | ||
359 | static void bcm_kona_gpio_irq_mask(struct irq_data *d) | |
360 | { | |
361 | struct bcm_kona_gpio *kona_gpio; | |
362 | void __iomem *reg_base; | |
b7ab6973 | 363 | unsigned gpio = d->hwirq; |
757651e3 MM |
364 | int bank_id = GPIO_BANK(gpio); |
365 | int bit = GPIO_BIT(gpio); | |
366 | u32 val; | |
367 | unsigned long flags; | |
368 | ||
369 | kona_gpio = irq_data_get_irq_chip_data(d); | |
370 | reg_base = kona_gpio->reg_base; | |
c69fcea5 | 371 | raw_spin_lock_irqsave(&kona_gpio->lock, flags); |
757651e3 MM |
372 | |
373 | val = readl(reg_base + GPIO_INT_MASK(bank_id)); | |
374 | val |= BIT(bit); | |
375 | writel(val, reg_base + GPIO_INT_MASK(bank_id)); | |
376 | ||
c69fcea5 | 377 | raw_spin_unlock_irqrestore(&kona_gpio->lock, flags); |
757651e3 MM |
378 | } |
379 | ||
380 | static void bcm_kona_gpio_irq_unmask(struct irq_data *d) | |
381 | { | |
382 | struct bcm_kona_gpio *kona_gpio; | |
383 | void __iomem *reg_base; | |
b7ab6973 | 384 | unsigned gpio = d->hwirq; |
757651e3 MM |
385 | int bank_id = GPIO_BANK(gpio); |
386 | int bit = GPIO_BIT(gpio); | |
387 | u32 val; | |
388 | unsigned long flags; | |
389 | ||
390 | kona_gpio = irq_data_get_irq_chip_data(d); | |
391 | reg_base = kona_gpio->reg_base; | |
c69fcea5 | 392 | raw_spin_lock_irqsave(&kona_gpio->lock, flags); |
757651e3 MM |
393 | |
394 | val = readl(reg_base + GPIO_INT_MSKCLR(bank_id)); | |
395 | val |= BIT(bit); | |
396 | writel(val, reg_base + GPIO_INT_MSKCLR(bank_id)); | |
397 | ||
c69fcea5 | 398 | raw_spin_unlock_irqrestore(&kona_gpio->lock, flags); |
757651e3 MM |
399 | } |
400 | ||
401 | static int bcm_kona_gpio_irq_set_type(struct irq_data *d, unsigned int type) | |
402 | { | |
403 | struct bcm_kona_gpio *kona_gpio; | |
404 | void __iomem *reg_base; | |
b7ab6973 | 405 | unsigned gpio = d->hwirq; |
757651e3 MM |
406 | u32 lvl_type; |
407 | u32 val; | |
408 | unsigned long flags; | |
757651e3 MM |
409 | |
410 | kona_gpio = irq_data_get_irq_chip_data(d); | |
411 | reg_base = kona_gpio->reg_base; | |
412 | switch (type & IRQ_TYPE_SENSE_MASK) { | |
413 | case IRQ_TYPE_EDGE_RISING: | |
414 | lvl_type = GPIO_GPCTR0_ITR_CMD_RISING_EDGE; | |
415 | break; | |
416 | ||
417 | case IRQ_TYPE_EDGE_FALLING: | |
418 | lvl_type = GPIO_GPCTR0_ITR_CMD_FALLING_EDGE; | |
419 | break; | |
420 | ||
421 | case IRQ_TYPE_EDGE_BOTH: | |
422 | lvl_type = GPIO_GPCTR0_ITR_CMD_BOTH_EDGE; | |
423 | break; | |
424 | ||
425 | case IRQ_TYPE_LEVEL_HIGH: | |
426 | case IRQ_TYPE_LEVEL_LOW: | |
427 | /* BCM GPIO doesn't support level triggering */ | |
428 | default: | |
58383c78 | 429 | dev_err(kona_gpio->gpio_chip.parent, |
757651e3 MM |
430 | "Invalid BCM GPIO irq type 0x%x\n", type); |
431 | return -EINVAL; | |
432 | } | |
433 | ||
c69fcea5 | 434 | raw_spin_lock_irqsave(&kona_gpio->lock, flags); |
757651e3 MM |
435 | |
436 | val = readl(reg_base + GPIO_CONTROL(gpio)); | |
437 | val &= ~GPIO_GPCTR0_ITR_MASK; | |
438 | val |= lvl_type << GPIO_GPCTR0_ITR_SHIFT; | |
439 | writel(val, reg_base + GPIO_CONTROL(gpio)); | |
440 | ||
c69fcea5 | 441 | raw_spin_unlock_irqrestore(&kona_gpio->lock, flags); |
757651e3 MM |
442 | |
443 | return 0; | |
444 | } | |
445 | ||
bd0b9ac4 | 446 | static void bcm_kona_gpio_irq_handler(struct irq_desc *desc) |
757651e3 MM |
447 | { |
448 | void __iomem *reg_base; | |
449 | int bit, bank_id; | |
450 | unsigned long sta; | |
476f8b4c | 451 | struct bcm_kona_gpio_bank *bank = irq_desc_get_handler_data(desc); |
757651e3 MM |
452 | struct irq_chip *chip = irq_desc_get_chip(desc); |
453 | ||
454 | chained_irq_enter(chip, desc); | |
455 | ||
456 | /* | |
457 | * For bank interrupts, we can't use chip_data to store the kona_gpio | |
458 | * pointer, since GIC needs it for its own purposes. Therefore, we get | |
459 | * our pointer from the bank structure. | |
460 | */ | |
461 | reg_base = bank->kona_gpio->reg_base; | |
462 | bank_id = bank->id; | |
757651e3 MM |
463 | |
464 | while ((sta = readl(reg_base + GPIO_INT_STATUS(bank_id)) & | |
465 | (~(readl(reg_base + GPIO_INT_MASK(bank_id)))))) { | |
466 | for_each_set_bit(bit, &sta, 32) { | |
d933cc61 LW |
467 | int hwirq = GPIO_PER_BANK * bank_id + bit; |
468 | int child_irq = | |
469 | irq_find_mapping(bank->kona_gpio->irq_domain, | |
470 | hwirq); | |
757651e3 MM |
471 | /* |
472 | * Clear interrupt before handler is called so we don't | |
473 | * miss any interrupt occurred during executing them. | |
474 | */ | |
475 | writel(readl(reg_base + GPIO_INT_STATUS(bank_id)) | | |
476 | BIT(bit), reg_base + GPIO_INT_STATUS(bank_id)); | |
477 | /* Invoke interrupt handler */ | |
d933cc61 | 478 | generic_handle_irq(child_irq); |
757651e3 MM |
479 | } |
480 | } | |
481 | ||
757651e3 MM |
482 | chained_irq_exit(chip, desc); |
483 | } | |
484 | ||
57ef0428 | 485 | static int bcm_kona_gpio_irq_reqres(struct irq_data *d) |
db6b3ad1 LW |
486 | { |
487 | struct bcm_kona_gpio *kona_gpio = irq_data_get_irq_chip_data(d); | |
488 | ||
e3a2e878 | 489 | if (gpiochip_lock_as_irq(&kona_gpio->gpio_chip, d->hwirq)) { |
58383c78 | 490 | dev_err(kona_gpio->gpio_chip.parent, |
db6b3ad1 LW |
491 | "unable to lock HW IRQ %lu for IRQ\n", |
492 | d->hwirq); | |
57ef0428 LW |
493 | return -EINVAL; |
494 | } | |
db6b3ad1 LW |
495 | return 0; |
496 | } | |
497 | ||
57ef0428 | 498 | static void bcm_kona_gpio_irq_relres(struct irq_data *d) |
db6b3ad1 LW |
499 | { |
500 | struct bcm_kona_gpio *kona_gpio = irq_data_get_irq_chip_data(d); | |
501 | ||
e3a2e878 | 502 | gpiochip_unlock_as_irq(&kona_gpio->gpio_chip, d->hwirq); |
db6b3ad1 LW |
503 | } |
504 | ||
757651e3 MM |
505 | static struct irq_chip bcm_gpio_irq_chip = { |
506 | .name = "bcm-kona-gpio", | |
507 | .irq_ack = bcm_kona_gpio_irq_ack, | |
508 | .irq_mask = bcm_kona_gpio_irq_mask, | |
509 | .irq_unmask = bcm_kona_gpio_irq_unmask, | |
510 | .irq_set_type = bcm_kona_gpio_irq_set_type, | |
57ef0428 LW |
511 | .irq_request_resources = bcm_kona_gpio_irq_reqres, |
512 | .irq_release_resources = bcm_kona_gpio_irq_relres, | |
757651e3 MM |
513 | }; |
514 | ||
37781292 | 515 | static struct of_device_id const bcm_kona_gpio_of_match[] = { |
757651e3 MM |
516 | { .compatible = "brcm,kona-gpio" }, |
517 | {} | |
518 | }; | |
519 | ||
757651e3 MM |
520 | /* |
521 | * This lock class tells lockdep that GPIO irqs are in a different | |
522 | * category than their parents, so it won't report false recursion. | |
523 | */ | |
524 | static struct lock_class_key gpio_lock_class; | |
39c3fd58 | 525 | static struct lock_class_key gpio_request_class; |
757651e3 | 526 | |
1dc94272 | 527 | static int bcm_kona_gpio_irq_map(struct irq_domain *d, unsigned int irq, |
757651e3 MM |
528 | irq_hw_number_t hwirq) |
529 | { | |
530 | int ret; | |
531 | ||
1dc94272 | 532 | ret = irq_set_chip_data(irq, d->host_data); |
757651e3 MM |
533 | if (ret < 0) |
534 | return ret; | |
39c3fd58 | 535 | irq_set_lockdep_class(irq, &gpio_lock_class, &gpio_request_class); |
1dc94272 | 536 | irq_set_chip_and_handler(irq, &bcm_gpio_irq_chip, handle_simple_irq); |
1dc94272 | 537 | irq_set_noprobe(irq); |
757651e3 MM |
538 | |
539 | return 0; | |
540 | } | |
541 | ||
d933cc61 | 542 | static void bcm_kona_gpio_irq_unmap(struct irq_domain *d, unsigned int irq) |
757651e3 | 543 | { |
d933cc61 LW |
544 | irq_set_chip_and_handler(irq, NULL, NULL); |
545 | irq_set_chip_data(irq, NULL); | |
757651e3 MM |
546 | } |
547 | ||
0b354dc4 | 548 | static const struct irq_domain_ops bcm_kona_irq_ops = { |
757651e3 MM |
549 | .map = bcm_kona_gpio_irq_map, |
550 | .unmap = bcm_kona_gpio_irq_unmap, | |
551 | .xlate = irq_domain_xlate_twocell, | |
552 | }; | |
553 | ||
554 | static void bcm_kona_gpio_reset(struct bcm_kona_gpio *kona_gpio) | |
555 | { | |
556 | void __iomem *reg_base; | |
557 | int i; | |
558 | ||
559 | reg_base = kona_gpio->reg_base; | |
560 | /* disable interrupts and clear status */ | |
561 | for (i = 0; i < kona_gpio->num_bank; i++) { | |
bdb93c03 | 562 | /* Unlock the entire bank first */ |
b66b2a0a | 563 | bcm_kona_gpio_write_lock_regs(reg_base, i, UNLOCK_CODE); |
757651e3 MM |
564 | writel(0xffffffff, reg_base + GPIO_INT_MASK(i)); |
565 | writel(0xffffffff, reg_base + GPIO_INT_STATUS(i)); | |
bdb93c03 | 566 | /* Now re-lock the bank */ |
b66b2a0a | 567 | bcm_kona_gpio_write_lock_regs(reg_base, i, LOCK_CODE); |
757651e3 MM |
568 | } |
569 | } | |
570 | ||
571 | static int bcm_kona_gpio_probe(struct platform_device *pdev) | |
572 | { | |
573 | struct device *dev = &pdev->dev; | |
574 | const struct of_device_id *match; | |
575 | struct resource *res; | |
576 | struct bcm_kona_gpio_bank *bank; | |
577 | struct bcm_kona_gpio *kona_gpio; | |
578 | struct gpio_chip *chip; | |
579 | int ret; | |
580 | int i; | |
581 | ||
582 | match = of_match_device(bcm_kona_gpio_of_match, dev); | |
583 | if (!match) { | |
584 | dev_err(dev, "Failed to find gpio controller\n"); | |
585 | return -ENODEV; | |
586 | } | |
587 | ||
588 | kona_gpio = devm_kzalloc(dev, sizeof(*kona_gpio), GFP_KERNEL); | |
589 | if (!kona_gpio) | |
590 | return -ENOMEM; | |
591 | ||
592 | kona_gpio->gpio_chip = template_chip; | |
593 | chip = &kona_gpio->gpio_chip; | |
594 | kona_gpio->num_bank = of_irq_count(dev->of_node); | |
595 | if (kona_gpio->num_bank == 0) { | |
596 | dev_err(dev, "Couldn't determine # GPIO banks\n"); | |
597 | return -ENOENT; | |
598 | } | |
599 | if (kona_gpio->num_bank > GPIO_MAX_BANK_NUM) { | |
600 | dev_err(dev, "Too many GPIO banks configured (max=%d)\n", | |
601 | GPIO_MAX_BANK_NUM); | |
602 | return -ENXIO; | |
603 | } | |
a86854d0 KC |
604 | kona_gpio->banks = devm_kcalloc(dev, |
605 | kona_gpio->num_bank, | |
606 | sizeof(*kona_gpio->banks), | |
607 | GFP_KERNEL); | |
757651e3 MM |
608 | if (!kona_gpio->banks) |
609 | return -ENOMEM; | |
610 | ||
611 | kona_gpio->pdev = pdev; | |
612 | platform_set_drvdata(pdev, kona_gpio); | |
613 | chip->of_node = dev->of_node; | |
614 | chip->ngpio = kona_gpio->num_bank * GPIO_PER_BANK; | |
615 | ||
616 | kona_gpio->irq_domain = irq_domain_add_linear(dev->of_node, | |
617 | chip->ngpio, | |
618 | &bcm_kona_irq_ops, | |
619 | kona_gpio); | |
620 | if (!kona_gpio->irq_domain) { | |
621 | dev_err(dev, "Couldn't allocate IRQ domain\n"); | |
622 | return -ENXIO; | |
623 | } | |
624 | ||
625 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
626 | kona_gpio->reg_base = devm_ioremap_resource(dev, res); | |
627 | if (IS_ERR(kona_gpio->reg_base)) { | |
628 | ret = -ENXIO; | |
629 | goto err_irq_domain; | |
630 | } | |
631 | ||
632 | for (i = 0; i < kona_gpio->num_bank; i++) { | |
633 | bank = &kona_gpio->banks[i]; | |
634 | bank->id = i; | |
635 | bank->irq = platform_get_irq(pdev, i); | |
636 | bank->kona_gpio = kona_gpio; | |
637 | if (bank->irq < 0) { | |
638 | dev_err(dev, "Couldn't get IRQ for bank %d", i); | |
639 | ret = -ENOENT; | |
640 | goto err_irq_domain; | |
641 | } | |
642 | } | |
643 | ||
23b4faa9 | 644 | dev_info(&pdev->dev, "Setting up Kona GPIO\n"); |
757651e3 MM |
645 | |
646 | bcm_kona_gpio_reset(kona_gpio); | |
647 | ||
0b893123 | 648 | ret = devm_gpiochip_add_data(dev, chip, kona_gpio); |
757651e3 MM |
649 | if (ret < 0) { |
650 | dev_err(dev, "Couldn't add GPIO chip -- %d\n", ret); | |
651 | goto err_irq_domain; | |
652 | } | |
757651e3 MM |
653 | for (i = 0; i < kona_gpio->num_bank; i++) { |
654 | bank = &kona_gpio->banks[i]; | |
b34cc620 TG |
655 | irq_set_chained_handler_and_data(bank->irq, |
656 | bcm_kona_gpio_irq_handler, | |
657 | bank); | |
757651e3 MM |
658 | } |
659 | ||
c69fcea5 | 660 | raw_spin_lock_init(&kona_gpio->lock); |
757651e3 MM |
661 | |
662 | return 0; | |
663 | ||
664 | err_irq_domain: | |
665 | irq_domain_remove(kona_gpio->irq_domain); | |
666 | ||
667 | return ret; | |
668 | } | |
669 | ||
670 | static struct platform_driver bcm_kona_gpio_driver = { | |
671 | .driver = { | |
672 | .name = "bcm-kona-gpio", | |
757651e3 MM |
673 | .of_match_table = bcm_kona_gpio_of_match, |
674 | }, | |
675 | .probe = bcm_kona_gpio_probe, | |
676 | }; | |
8f3e19fa | 677 | builtin_platform_driver(bcm_kona_gpio_driver); |