[mirror_ubuntu-zesty-kernel.git] / drivers / gpio / gpio-bcm-kona.c

/*
 * Copyright (C) 2012-2014 Broadcom Corporation
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation version 2.
 *
 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
 * kind, whether express or implied; without even the implied warranty
 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/bitops.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/gpio.h>
#include <linux/of_device.h>
#include <linux/of_irq.h>
#include <linux/module.h>
#include <linux/irqdomain.h>
#include <linux/irqchip/chained_irq.h>

#define BCM_GPIO_PASSWD				0x00a5a501
#define GPIO_PER_BANK				32
#define GPIO_MAX_BANK_NUM			8

#define GPIO_BANK(gpio)				((gpio) >> 5)
#define GPIO_BIT(gpio)				((gpio) & (GPIO_PER_BANK - 1))

/* There is a GPIO control register for each GPIO */
#define GPIO_CONTROL(gpio)			(0x00000100 + ((gpio) << 2))

/* The remaining registers are per GPIO bank */
#define GPIO_OUT_STATUS(bank)			(0x00000000 + ((bank) << 2))
#define GPIO_IN_STATUS(bank)			(0x00000020 + ((bank) << 2))
#define GPIO_OUT_SET(bank)			(0x00000040 + ((bank) << 2))
#define GPIO_OUT_CLEAR(bank)			(0x00000060 + ((bank) << 2))
#define GPIO_INT_STATUS(bank)			(0x00000080 + ((bank) << 2))
#define GPIO_INT_MASK(bank)			(0x000000a0 + ((bank) << 2))
#define GPIO_INT_MSKCLR(bank)			(0x000000c0 + ((bank) << 2))
#define GPIO_PWD_STATUS(bank)			(0x00000500 + ((bank) << 2))

#define GPIO_GPPWR_OFFSET			0x00000520

#define GPIO_GPCTR0_DBR_SHIFT			5
#define GPIO_GPCTR0_DBR_MASK			0x000001e0

#define GPIO_GPCTR0_ITR_SHIFT			3
#define GPIO_GPCTR0_ITR_MASK			0x00000018
#define GPIO_GPCTR0_ITR_CMD_RISING_EDGE		0x00000001
#define GPIO_GPCTR0_ITR_CMD_FALLING_EDGE	0x00000002
#define GPIO_GPCTR0_ITR_CMD_BOTH_EDGE		0x00000003

#define GPIO_GPCTR0_IOTR_MASK			0x00000001
#define GPIO_GPCTR0_IOTR_CMD_0UTPUT		0x00000000
#define GPIO_GPCTR0_IOTR_CMD_INPUT		0x00000001

#define GPIO_GPCTR0_DB_ENABLE_MASK		0x00000100

#define LOCK_CODE				0xffffffff
#define UNLOCK_CODE				0x00000000

struct bcm_kona_gpio {
	void __iomem *reg_base;
	int num_bank;
	spinlock_t lock;
	struct gpio_chip gpio_chip;
	struct irq_domain *irq_domain;
	struct bcm_kona_gpio_bank *banks;
	struct platform_device *pdev;
};

struct bcm_kona_gpio_bank {
	int id;
	int irq;
	/* Used in the interrupt handler */
	struct bcm_kona_gpio *kona_gpio;
};

static inline struct bcm_kona_gpio *to_kona_gpio(struct gpio_chip *chip)
{
	return container_of(chip, struct bcm_kona_gpio, gpio_chip);
}

static inline void bcm_kona_gpio_write_lock_regs(void __iomem *reg_base,
						int bank_id, u32 lockcode)
{
	writel(BCM_GPIO_PASSWD, reg_base + GPIO_GPPWR_OFFSET);
	writel(lockcode, reg_base + GPIO_PWD_STATUS(bank_id));
}

static void bcm_kona_gpio_lock_gpio(struct bcm_kona_gpio *kona_gpio,
					unsigned gpio)
{
	u32 val;
	unsigned long flags;
	int bank_id = GPIO_BANK(gpio);

	spin_lock_irqsave(&kona_gpio->lock, flags);

	val = readl(kona_gpio->reg_base + GPIO_PWD_STATUS(bank_id));
	val |= BIT(gpio);
	bcm_kona_gpio_write_lock_regs(kona_gpio->reg_base, bank_id, val);

	spin_unlock_irqrestore(&kona_gpio->lock, flags);
}

static void bcm_kona_gpio_unlock_gpio(struct bcm_kona_gpio *kona_gpio,
					unsigned gpio)
{
	u32 val;
	unsigned long flags;
	int bank_id = GPIO_BANK(gpio);

	spin_lock_irqsave(&kona_gpio->lock, flags);

	val = readl(kona_gpio->reg_base + GPIO_PWD_STATUS(bank_id));
	val &= ~BIT(gpio);
	bcm_kona_gpio_write_lock_regs(kona_gpio->reg_base, bank_id, val);

	spin_unlock_irqrestore(&kona_gpio->lock, flags);
}

static int bcm_kona_gpio_get_dir(struct gpio_chip *chip, unsigned gpio)
{
	struct bcm_kona_gpio *kona_gpio = to_kona_gpio(chip);
	void __iomem *reg_base = kona_gpio->reg_base;
	u32 val;

	val = readl(reg_base + GPIO_CONTROL(gpio)) & GPIO_GPCTR0_IOTR_MASK;
	return val ? GPIOF_DIR_IN : GPIOF_DIR_OUT;
}

static void bcm_kona_gpio_set(struct gpio_chip *chip, unsigned gpio, int value)
{
	struct bcm_kona_gpio *kona_gpio;
	void __iomem *reg_base;
	int bank_id = GPIO_BANK(gpio);
	int bit = GPIO_BIT(gpio);
	u32 val, reg_offset;
	unsigned long flags;

	kona_gpio = to_kona_gpio(chip);
	reg_base = kona_gpio->reg_base;
	spin_lock_irqsave(&kona_gpio->lock, flags);

	/* this function only applies to output pin */
	if (bcm_kona_gpio_get_dir(chip, gpio) == GPIOF_DIR_IN)
		goto out;

	reg_offset = value ? GPIO_OUT_SET(bank_id) : GPIO_OUT_CLEAR(bank_id);

	val = readl(reg_base + reg_offset);
	val |= BIT(bit);
	writel(val, reg_base + reg_offset);

out:
	spin_unlock_irqrestore(&kona_gpio->lock, flags);
}

static int bcm_kona_gpio_get(struct gpio_chip *chip, unsigned gpio)
{
	struct bcm_kona_gpio *kona_gpio;
	void __iomem *reg_base;
	int bank_id = GPIO_BANK(gpio);
	int bit = GPIO_BIT(gpio);
	u32 val, reg_offset;
	unsigned long flags;

	kona_gpio = to_kona_gpio(chip);
	reg_base = kona_gpio->reg_base;
	spin_lock_irqsave(&kona_gpio->lock, flags);

	if (bcm_kona_gpio_get_dir(chip, gpio) == GPIOF_DIR_IN)
		reg_offset = GPIO_IN_STATUS(bank_id);
	else
		reg_offset = GPIO_OUT_STATUS(bank_id);

	/* read the GPIO bank status */
	val = readl(reg_base + reg_offset);

	spin_unlock_irqrestore(&kona_gpio->lock, flags);

	/* return the specified bit status */
	return !!(val & BIT(bit));
}

static int bcm_kona_gpio_request(struct gpio_chip *chip, unsigned gpio)
{
	struct bcm_kona_gpio *kona_gpio = to_kona_gpio(chip);

	bcm_kona_gpio_unlock_gpio(kona_gpio, gpio);
	return 0;
}

static void bcm_kona_gpio_free(struct gpio_chip *chip, unsigned gpio)
{
	struct bcm_kona_gpio *kona_gpio = to_kona_gpio(chip);

	bcm_kona_gpio_lock_gpio(kona_gpio, gpio);
}

static int bcm_kona_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
{
	struct bcm_kona_gpio *kona_gpio;
	void __iomem *reg_base;
	u32 val;
	unsigned long flags;

	kona_gpio = to_kona_gpio(chip);
	reg_base = kona_gpio->reg_base;
	spin_lock_irqsave(&kona_gpio->lock, flags);

	val = readl(reg_base + GPIO_CONTROL(gpio));
	val &= ~GPIO_GPCTR0_IOTR_MASK;
	val |= GPIO_GPCTR0_IOTR_CMD_INPUT;
	writel(val, reg_base + GPIO_CONTROL(gpio));

	spin_unlock_irqrestore(&kona_gpio->lock, flags);

	return 0;
}

static int bcm_kona_gpio_direction_output(struct gpio_chip *chip,
					  unsigned gpio, int value)
{
	struct bcm_kona_gpio *kona_gpio;
	void __iomem *reg_base;
	int bank_id = GPIO_BANK(gpio);
	int bit = GPIO_BIT(gpio);
	u32 val, reg_offset;
	unsigned long flags;

	kona_gpio = to_kona_gpio(chip);
	reg_base = kona_gpio->reg_base;
	spin_lock_irqsave(&kona_gpio->lock, flags);

	val = readl(reg_base + GPIO_CONTROL(gpio));
	val &= ~GPIO_GPCTR0_IOTR_MASK;
	val |= GPIO_GPCTR0_IOTR_CMD_0UTPUT;
	writel(val, reg_base + GPIO_CONTROL(gpio));
	reg_offset = value ? GPIO_OUT_SET(bank_id) : GPIO_OUT_CLEAR(bank_id);

	val = readl(reg_base + reg_offset);
	val |= BIT(bit);
	writel(val, reg_base + reg_offset);

	spin_unlock_irqrestore(&kona_gpio->lock, flags);

	return 0;
}

static int bcm_kona_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
{
	struct bcm_kona_gpio *kona_gpio;

	kona_gpio = to_kona_gpio(chip);
	if (gpio >= kona_gpio->gpio_chip.ngpio)
		return -ENXIO;
	return irq_create_mapping(kona_gpio->irq_domain, gpio);
}

static int bcm_kona_gpio_set_debounce(struct gpio_chip *chip, unsigned gpio,
				      unsigned debounce)
{
	struct bcm_kona_gpio *kona_gpio;
	void __iomem *reg_base;
	u32 val, res;
	unsigned long flags;

	kona_gpio = to_kona_gpio(chip);
	reg_base = kona_gpio->reg_base;
	/* debounce must be 1-128ms (or 0) */
	if ((debounce > 0 && debounce < 1000) || debounce > 128000) {
		dev_err(chip->dev, "Debounce value %u not in range\n",
			debounce);
		return -EINVAL;
	}

	/* calculate debounce bit value */
	if (debounce != 0) {
		/* Convert to ms */
		debounce /= 1000;
		/* find the MSB */
		res = fls(debounce) - 1;
		/* Check if MSB-1 is set (round up or down) */
		if (res > 0 && (debounce & BIT(res - 1)))
			res++;
	}

	/* spin lock for read-modify-write of the GPIO register */
	spin_lock_irqsave(&kona_gpio->lock, flags);

	val = readl(reg_base + GPIO_CONTROL(gpio));
	val &= ~GPIO_GPCTR0_DBR_MASK;

	if (debounce == 0) {
		/* disable debounce */
		val &= ~GPIO_GPCTR0_DB_ENABLE_MASK;
	} else {
		val |= GPIO_GPCTR0_DB_ENABLE_MASK |
		    (res << GPIO_GPCTR0_DBR_SHIFT);
	}

	writel(val, reg_base + GPIO_CONTROL(gpio));

	spin_unlock_irqrestore(&kona_gpio->lock, flags);

	return 0;
}

static struct gpio_chip template_chip = {
	.label = "bcm-kona-gpio",
	.owner = THIS_MODULE,
	.request = bcm_kona_gpio_request,
	.free = bcm_kona_gpio_free,
	.get_direction = bcm_kona_gpio_get_dir,
	.direction_input = bcm_kona_gpio_direction_input,
	.get = bcm_kona_gpio_get,
	.direction_output = bcm_kona_gpio_direction_output,
	.set = bcm_kona_gpio_set,
	.set_debounce = bcm_kona_gpio_set_debounce,
	.to_irq = bcm_kona_gpio_to_irq,
	.base = 0,
};

static void bcm_kona_gpio_irq_ack(struct irq_data *d)
{
	struct bcm_kona_gpio *kona_gpio;
	void __iomem *reg_base;
	unsigned gpio = d->hwirq;
	int bank_id = GPIO_BANK(gpio);
	int bit = GPIO_BIT(gpio);
	u32 val;
	unsigned long flags;

	kona_gpio = irq_data_get_irq_chip_data(d);
	reg_base = kona_gpio->reg_base;
	spin_lock_irqsave(&kona_gpio->lock, flags);

	val = readl(reg_base + GPIO_INT_STATUS(bank_id));
	val |= BIT(bit);
	writel(val, reg_base + GPIO_INT_STATUS(bank_id));

	spin_unlock_irqrestore(&kona_gpio->lock, flags);
}

static void bcm_kona_gpio_irq_mask(struct irq_data *d)
{
	struct bcm_kona_gpio *kona_gpio;
	void __iomem *reg_base;
	unsigned gpio = d->hwirq;
	int bank_id = GPIO_BANK(gpio);
	int bit = GPIO_BIT(gpio);
	u32 val;
	unsigned long flags;

	kona_gpio = irq_data_get_irq_chip_data(d);
	reg_base = kona_gpio->reg_base;
	spin_lock_irqsave(&kona_gpio->lock, flags);

	val = readl(reg_base + GPIO_INT_MASK(bank_id));
	val |= BIT(bit);
	writel(val, reg_base + GPIO_INT_MASK(bank_id));

	spin_unlock_irqrestore(&kona_gpio->lock, flags);
}

static void bcm_kona_gpio_irq_unmask(struct irq_data *d)
{
	struct bcm_kona_gpio *kona_gpio;
	void __iomem *reg_base;
	unsigned gpio = d->hwirq;
	int bank_id = GPIO_BANK(gpio);
	int bit = GPIO_BIT(gpio);
	u32 val;
	unsigned long flags;

	kona_gpio = irq_data_get_irq_chip_data(d);
	reg_base = kona_gpio->reg_base;
	spin_lock_irqsave(&kona_gpio->lock, flags);

	val = readl(reg_base + GPIO_INT_MSKCLR(bank_id));
	val |= BIT(bit);
	writel(val, reg_base + GPIO_INT_MSKCLR(bank_id));

	spin_unlock_irqrestore(&kona_gpio->lock, flags);
}

static int bcm_kona_gpio_irq_set_type(struct irq_data *d, unsigned int type)
{
	struct bcm_kona_gpio *kona_gpio;
	void __iomem *reg_base;
	unsigned gpio = d->hwirq;
	u32 lvl_type;
	u32 val;
	unsigned long flags;

	kona_gpio = irq_data_get_irq_chip_data(d);
	reg_base = kona_gpio->reg_base;
	switch (type & IRQ_TYPE_SENSE_MASK) {
	case IRQ_TYPE_EDGE_RISING:
		lvl_type = GPIO_GPCTR0_ITR_CMD_RISING_EDGE;
		break;

	case IRQ_TYPE_EDGE_FALLING:
		lvl_type = GPIO_GPCTR0_ITR_CMD_FALLING_EDGE;
		break;

	case IRQ_TYPE_EDGE_BOTH:
		lvl_type = GPIO_GPCTR0_ITR_CMD_BOTH_EDGE;
		break;

	case IRQ_TYPE_LEVEL_HIGH:
	case IRQ_TYPE_LEVEL_LOW:
		/* BCM GPIO doesn't support level triggering */
	default:
		dev_err(kona_gpio->gpio_chip.dev,
			"Invalid BCM GPIO irq type 0x%x\n", type);
		return -EINVAL;
	}

	spin_lock_irqsave(&kona_gpio->lock, flags);

	val = readl(reg_base + GPIO_CONTROL(gpio));
	val &= ~GPIO_GPCTR0_ITR_MASK;
	val |= lvl_type << GPIO_GPCTR0_ITR_SHIFT;
	writel(val, reg_base + GPIO_CONTROL(gpio));

	spin_unlock_irqrestore(&kona_gpio->lock, flags);

	return 0;
}

static void bcm_kona_gpio_irq_handler(struct irq_desc *desc)
{
	void __iomem *reg_base;
	int bit, bank_id;
	unsigned long sta;
	struct bcm_kona_gpio_bank *bank = irq_desc_get_handler_data(desc);
	struct irq_chip *chip = irq_desc_get_chip(desc);

	chained_irq_enter(chip, desc);

	/*
	 * For bank interrupts, we can't use chip_data to store the kona_gpio
	 * pointer, since GIC needs it for its own purposes. Therefore, we get
	 * our pointer from the bank structure.
	 */
	reg_base = bank->kona_gpio->reg_base;
	bank_id = bank->id;

	while ((sta = readl(reg_base + GPIO_INT_STATUS(bank_id)) &
		    (~(readl(reg_base + GPIO_INT_MASK(bank_id)))))) {
		for_each_set_bit(bit, &sta, 32) {
			int hwirq = GPIO_PER_BANK * bank_id + bit;
			int child_irq =
				irq_find_mapping(bank->kona_gpio->irq_domain,
						 hwirq);
			/*
			 * Clear interrupt before handler is called so we don't
			 * miss any interrupt occurred during executing them.
			 */
			writel(readl(reg_base + GPIO_INT_STATUS(bank_id)) |
			       BIT(bit), reg_base + GPIO_INT_STATUS(bank_id));
			/* Invoke interrupt handler */
			generic_handle_irq(child_irq);
		}
	}

	chained_irq_exit(chip, desc);
}

static int bcm_kona_gpio_irq_reqres(struct irq_data *d)
{
	struct bcm_kona_gpio *kona_gpio = irq_data_get_irq_chip_data(d);

	if (gpiochip_lock_as_irq(&kona_gpio->gpio_chip, d->hwirq)) {
		dev_err(kona_gpio->gpio_chip.dev,
			"unable to lock HW IRQ %lu for IRQ\n",
			d->hwirq);
		return -EINVAL;
	}
	return 0;
}

static void bcm_kona_gpio_irq_relres(struct irq_data *d)
{
	struct bcm_kona_gpio *kona_gpio = irq_data_get_irq_chip_data(d);

	gpiochip_unlock_as_irq(&kona_gpio->gpio_chip, d->hwirq);
}

static struct irq_chip bcm_gpio_irq_chip = {
	.name = "bcm-kona-gpio",
	.irq_ack = bcm_kona_gpio_irq_ack,
	.irq_mask = bcm_kona_gpio_irq_mask,
	.irq_unmask = bcm_kona_gpio_irq_unmask,
	.irq_set_type = bcm_kona_gpio_irq_set_type,
	.irq_request_resources = bcm_kona_gpio_irq_reqres,
	.irq_release_resources = bcm_kona_gpio_irq_relres,
};

static struct of_device_id const bcm_kona_gpio_of_match[] = {
	{ .compatible = "brcm,kona-gpio" },
	{}
};

MODULE_DEVICE_TABLE(of, bcm_kona_gpio_of_match);

/*
 * This lock class tells lockdep that GPIO irqs are in a different
 * category than their parents, so it won't report false recursion.
 */
static struct lock_class_key gpio_lock_class;

static int bcm_kona_gpio_irq_map(struct irq_domain *d, unsigned int irq,
				 irq_hw_number_t hwirq)
{
	int ret;

	ret = irq_set_chip_data(irq, d->host_data);
	if (ret < 0)
		return ret;
	irq_set_lockdep_class(irq, &gpio_lock_class);
	irq_set_chip_and_handler(irq, &bcm_gpio_irq_chip, handle_simple_irq);
	irq_set_noprobe(irq);

	return 0;
}

static void bcm_kona_gpio_irq_unmap(struct irq_domain *d, unsigned int irq)
{
	irq_set_chip_and_handler(irq, NULL, NULL);
	irq_set_chip_data(irq, NULL);
}

static const struct irq_domain_ops bcm_kona_irq_ops = {
	.map = bcm_kona_gpio_irq_map,
	.unmap = bcm_kona_gpio_irq_unmap,
	.xlate = irq_domain_xlate_twocell,
};

static void bcm_kona_gpio_reset(struct bcm_kona_gpio *kona_gpio)
{
	void __iomem *reg_base;
	int i;

	reg_base = kona_gpio->reg_base;
	/* disable interrupts and clear status */
	for (i = 0; i < kona_gpio->num_bank; i++) {
		/* Unlock the entire bank first */
		bcm_kona_gpio_write_lock_regs(kona_gpio, i, UNLOCK_CODE);
		writel(0xffffffff, reg_base + GPIO_INT_MASK(i));
		writel(0xffffffff, reg_base + GPIO_INT_STATUS(i));
		/* Now re-lock the bank */
		bcm_kona_gpio_write_lock_regs(kona_gpio, i, LOCK_CODE);
	}
}

static int bcm_kona_gpio_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	const struct of_device_id *match;
	struct resource *res;
	struct bcm_kona_gpio_bank *bank;
	struct bcm_kona_gpio *kona_gpio;
	struct gpio_chip *chip;
	int ret;
	int i;

	match = of_match_device(bcm_kona_gpio_of_match, dev);
	if (!match) {
		dev_err(dev, "Failed to find gpio controller\n");
		return -ENODEV;
	}

	kona_gpio = devm_kzalloc(dev, sizeof(*kona_gpio), GFP_KERNEL);
	if (!kona_gpio)
		return -ENOMEM;

	kona_gpio->gpio_chip = template_chip;
	chip = &kona_gpio->gpio_chip;
	kona_gpio->num_bank = of_irq_count(dev->of_node);
	if (kona_gpio->num_bank == 0) {
		dev_err(dev, "Couldn't determine # GPIO banks\n");
		return -ENOENT;
	}
	if (kona_gpio->num_bank > GPIO_MAX_BANK_NUM) {
		dev_err(dev, "Too many GPIO banks configured (max=%d)\n",
			GPIO_MAX_BANK_NUM);
		return -ENXIO;
	}
	kona_gpio->banks = devm_kzalloc(dev,
					kona_gpio->num_bank *
					sizeof(*kona_gpio->banks), GFP_KERNEL);
	if (!kona_gpio->banks)
		return -ENOMEM;

	kona_gpio->pdev = pdev;
	platform_set_drvdata(pdev, kona_gpio);
	chip->of_node = dev->of_node;
	chip->ngpio = kona_gpio->num_bank * GPIO_PER_BANK;

	kona_gpio->irq_domain = irq_domain_add_linear(dev->of_node,
						      chip->ngpio,
						      &bcm_kona_irq_ops,
						      kona_gpio);
	if (!kona_gpio->irq_domain) {
		dev_err(dev, "Couldn't allocate IRQ domain\n");
		return -ENXIO;
	}

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	kona_gpio->reg_base = devm_ioremap_resource(dev, res);
	if (IS_ERR(kona_gpio->reg_base)) {
		ret = -ENXIO;
		goto err_irq_domain;
	}

	for (i = 0; i < kona_gpio->num_bank; i++) {
		bank = &kona_gpio->banks[i];
		bank->id = i;
		bank->irq = platform_get_irq(pdev, i);
		bank->kona_gpio = kona_gpio;
		if (bank->irq < 0) {
			dev_err(dev, "Couldn't get IRQ for bank %d", i);
			ret = -ENOENT;
			goto err_irq_domain;
		}
	}

	dev_info(&pdev->dev, "Setting up Kona GPIO\n");

	bcm_kona_gpio_reset(kona_gpio);

	ret = gpiochip_add(chip);
	if (ret < 0) {
		dev_err(dev, "Couldn't add GPIO chip -- %d\n", ret);
		goto err_irq_domain;
	}
	for (i = 0; i < kona_gpio->num_bank; i++) {
		bank = &kona_gpio->banks[i];
		irq_set_chained_handler_and_data(bank->irq,
						 bcm_kona_gpio_irq_handler,
						 bank);
	}

	spin_lock_init(&kona_gpio->lock);

	return 0;

err_irq_domain:
	irq_domain_remove(kona_gpio->irq_domain);

	return ret;
}

static struct platform_driver bcm_kona_gpio_driver = {
	.driver = {
			.name = "bcm-kona-gpio",
			.of_match_table = bcm_kona_gpio_of_match,
	},
	.probe = bcm_kona_gpio_probe,
};

module_platform_driver(bcm_kona_gpio_driver);

MODULE_AUTHOR("Broadcom Corporation <bcm-kernel-feedback-list@broadcom.com>");
MODULE_DESCRIPTION("Broadcom Kona GPIO Driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
757651e3	1	/*
6f587c9f	2	* Copyright (C) 2012-2014 Broadcom Corporation
757651e3 MM	3	*
	4	* This program is free software; you can redistribute it and/or
	5	* modify it under the terms of the GNU General Public License as
	6	* published by the Free Software Foundation version 2.
	7	*
	8	* This program is distributed "as is" WITHOUT ANY WARRANTY of any
	9	* kind, whether express or implied; without even the implied warranty
	10	* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	11	* GNU General Public License for more details.
	12	*/
	13
	14	#include <linux/bitops.h>
	15	#include <linux/err.h>
	16	#include <linux/io.h>
	17	#include <linux/gpio.h>
	18	#include <linux/of_device.h>
	19	#include <linux/of_irq.h>
	20	#include <linux/module.h>
	21	#include <linux/irqdomain.h>
	22	#include <linux/irqchip/chained_irq.h>
	23
	24	#define BCM_GPIO_PASSWD 0x00a5a501
	25	#define GPIO_PER_BANK 32
	26	#define GPIO_MAX_BANK_NUM 8
	27
	28	#define GPIO_BANK(gpio) ((gpio) >> 5)
	29	#define GPIO_BIT(gpio) ((gpio) & (GPIO_PER_BANK - 1))
	30
d762bae4 MM	31	/* There is a GPIO control register for each GPIO */
	32	#define GPIO_CONTROL(gpio) (0x00000100 + ((gpio) << 2))
	33
	34	/* The remaining registers are per GPIO bank */
757651e3 MM	35	#define GPIO_OUT_STATUS(bank) (0x00000000 + ((bank) << 2))
	36	#define GPIO_IN_STATUS(bank) (0x00000020 + ((bank) << 2))
	37	#define GPIO_OUT_SET(bank) (0x00000040 + ((bank) << 2))
	38	#define GPIO_OUT_CLEAR(bank) (0x00000060 + ((bank) << 2))
	39	#define GPIO_INT_STATUS(bank) (0x00000080 + ((bank) << 2))
	40	#define GPIO_INT_MASK(bank) (0x000000a0 + ((bank) << 2))
	41	#define GPIO_INT_MSKCLR(bank) (0x000000c0 + ((bank) << 2))
757651e3 MM	42	#define GPIO_PWD_STATUS(bank) (0x00000500 + ((bank) << 2))
	43
	44	#define GPIO_GPPWR_OFFSET 0x00000520
	45
	46	#define GPIO_GPCTR0_DBR_SHIFT 5
	47	#define GPIO_GPCTR0_DBR_MASK 0x000001e0
	48
	49	#define GPIO_GPCTR0_ITR_SHIFT 3
	50	#define GPIO_GPCTR0_ITR_MASK 0x00000018
	51	#define GPIO_GPCTR0_ITR_CMD_RISING_EDGE 0x00000001
	52	#define GPIO_GPCTR0_ITR_CMD_FALLING_EDGE 0x00000002
	53	#define GPIO_GPCTR0_ITR_CMD_BOTH_EDGE 0x00000003
	54
	55	#define GPIO_GPCTR0_IOTR_MASK 0x00000001
	56	#define GPIO_GPCTR0_IOTR_CMD_0UTPUT 0x00000000
	57	#define GPIO_GPCTR0_IOTR_CMD_INPUT 0x00000001
	58
	59	#define GPIO_GPCTR0_DB_ENABLE_MASK 0x00000100
	60
	61	#define LOCK_CODE 0xffffffff
	62	#define UNLOCK_CODE 0x00000000
	63
	64	struct bcm_kona_gpio {
	65	void __iomem *reg_base;
	66	int num_bank;
	67	spinlock_t lock;
	68	struct gpio_chip gpio_chip;
	69	struct irq_domain *irq_domain;
	70	struct bcm_kona_gpio_bank *banks;
	71	struct platform_device *pdev;
	72	};
	73
	74	struct bcm_kona_gpio_bank {
	75	int id;
	76	int irq;
	77	/* Used in the interrupt handler */
	78	struct bcm_kona_gpio *kona_gpio;
	79	};
	80
	81	static inline struct bcm_kona_gpio to_kona_gpio(struct gpio_chip chip)
	82	{
	83	return container_of(chip, struct bcm_kona_gpio, gpio_chip);
	84	}
	85
bdb93c03 MM	86	static inline void bcm_kona_gpio_write_lock_regs(void __iomem *reg_base,
bdb93c03 MM	87	int bank_id, u32 lockcode)
757651e3 MM	88	{
	89	writel(BCM_GPIO_PASSWD, reg_base + GPIO_GPPWR_OFFSET);
	90	writel(lockcode, reg_base + GPIO_PWD_STATUS(bank_id));
	91	}
	92
bdb93c03 MM	93	static void bcm_kona_gpio_lock_gpio(struct bcm_kona_gpio *kona_gpio,
bdb93c03 MM	94	unsigned gpio)
757651e3	95	{
bdb93c03 MM	96	u32 val;
	97	unsigned long flags;
	98	int bank_id = GPIO_BANK(gpio);
	99
	100	spin_lock_irqsave(&kona_gpio->lock, flags);
	101
	102	val = readl(kona_gpio->reg_base + GPIO_PWD_STATUS(bank_id));
	103	val \|= BIT(gpio);
	104	bcm_kona_gpio_write_lock_regs(kona_gpio->reg_base, bank_id, val);
	105
	106	spin_unlock_irqrestore(&kona_gpio->lock, flags);
757651e3 MM	107	}
757651e3 MM	108
bdb93c03 MM	109	static void bcm_kona_gpio_unlock_gpio(struct bcm_kona_gpio *kona_gpio,
bdb93c03 MM	110	unsigned gpio)
757651e3	111	{
bdb93c03 MM	112	u32 val;
	113	unsigned long flags;
	114	int bank_id = GPIO_BANK(gpio);
	115
	116	spin_lock_irqsave(&kona_gpio->lock, flags);
	117
	118	val = readl(kona_gpio->reg_base + GPIO_PWD_STATUS(bank_id));
	119	val &= ~BIT(gpio);
	120	bcm_kona_gpio_write_lock_regs(kona_gpio->reg_base, bank_id, val);
	121
	122	spin_unlock_irqrestore(&kona_gpio->lock, flags);
757651e3 MM	123	}
757651e3 MM	124
0218d5a8 AL	125	static int bcm_kona_gpio_get_dir(struct gpio_chip *chip, unsigned gpio)
	126	{
	127	struct bcm_kona_gpio *kona_gpio = to_kona_gpio(chip);
	128	void __iomem *reg_base = kona_gpio->reg_base;
	129	u32 val;
	130
	131	val = readl(reg_base + GPIO_CONTROL(gpio)) & GPIO_GPCTR0_IOTR_MASK;
	132	return val ? GPIOF_DIR_IN : GPIOF_DIR_OUT;
	133	}
	134
757651e3 MM	135	static void bcm_kona_gpio_set(struct gpio_chip *chip, unsigned gpio, int value)
	136	{
	137	struct bcm_kona_gpio *kona_gpio;
	138	void __iomem *reg_base;
	139	int bank_id = GPIO_BANK(gpio);
	140	int bit = GPIO_BIT(gpio);
	141	u32 val, reg_offset;
	142	unsigned long flags;
	143
	144	kona_gpio = to_kona_gpio(chip);
	145	reg_base = kona_gpio->reg_base;
	146	spin_lock_irqsave(&kona_gpio->lock, flags);
757651e3	147
757651e3	148	/* this function only applies to output pin */
0218d5a8	149	if (bcm_kona_gpio_get_dir(chip, gpio) == GPIOF_DIR_IN)
757651e3 MM	150	goto out;
	151
	152	reg_offset = value ? GPIO_OUT_SET(bank_id) : GPIO_OUT_CLEAR(bank_id);
	153
	154	val = readl(reg_base + reg_offset);
	155	val \|= BIT(bit);
	156	writel(val, reg_base + reg_offset);
	157
	158	out:
757651e3 MM	159	spin_unlock_irqrestore(&kona_gpio->lock, flags);
	160	}
	161
	162	static int bcm_kona_gpio_get(struct gpio_chip *chip, unsigned gpio)
	163	{
	164	struct bcm_kona_gpio *kona_gpio;
	165	void __iomem *reg_base;
	166	int bank_id = GPIO_BANK(gpio);
	167	int bit = GPIO_BIT(gpio);
	168	u32 val, reg_offset;
	169	unsigned long flags;
	170
	171	kona_gpio = to_kona_gpio(chip);
	172	reg_base = kona_gpio->reg_base;
	173	spin_lock_irqsave(&kona_gpio->lock, flags);
757651e3	174
0218d5a8 AL	175	if (bcm_kona_gpio_get_dir(chip, gpio) == GPIOF_DIR_IN)
	176	reg_offset = GPIO_IN_STATUS(bank_id);
	177	else
	178	reg_offset = GPIO_OUT_STATUS(bank_id);
757651e3 MM	179
757651e3 MM	180	/* read the GPIO bank status */
757651e3 MM	181	val = readl(reg_base + reg_offset);
757651e3 MM	182
757651e3 MM	183	spin_unlock_irqrestore(&kona_gpio->lock, flags);
	184
	185	/* return the specified bit status */
e2f0b005	186	return !!(val & BIT(bit));
757651e3 MM	187	}
757651e3 MM	188
bdb93c03 MM	189	static int bcm_kona_gpio_request(struct gpio_chip *chip, unsigned gpio)
	190	{
	191	struct bcm_kona_gpio *kona_gpio = to_kona_gpio(chip);
	192
	193	bcm_kona_gpio_unlock_gpio(kona_gpio, gpio);
	194	return 0;
	195	}
	196
	197	static void bcm_kona_gpio_free(struct gpio_chip *chip, unsigned gpio)
	198	{
	199	struct bcm_kona_gpio *kona_gpio = to_kona_gpio(chip);
	200
	201	bcm_kona_gpio_lock_gpio(kona_gpio, gpio);
	202	}
	203
757651e3 MM	204	static int bcm_kona_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
	205	{
	206	struct bcm_kona_gpio *kona_gpio;
	207	void __iomem *reg_base;
	208	u32 val;
	209	unsigned long flags;
757651e3 MM	210
	211	kona_gpio = to_kona_gpio(chip);
	212	reg_base = kona_gpio->reg_base;
	213	spin_lock_irqsave(&kona_gpio->lock, flags);
757651e3 MM	214
	215	val = readl(reg_base + GPIO_CONTROL(gpio));
	216	val &= ~GPIO_GPCTR0_IOTR_MASK;
	217	val \|= GPIO_GPCTR0_IOTR_CMD_INPUT;
	218	writel(val, reg_base + GPIO_CONTROL(gpio));
	219
757651e3 MM	220	spin_unlock_irqrestore(&kona_gpio->lock, flags);
	221
	222	return 0;
	223	}
	224
	225	static int bcm_kona_gpio_direction_output(struct gpio_chip *chip,
	226	unsigned gpio, int value)
	227	{
	228	struct bcm_kona_gpio *kona_gpio;
	229	void __iomem *reg_base;
	230	int bank_id = GPIO_BANK(gpio);
	231	int bit = GPIO_BIT(gpio);
	232	u32 val, reg_offset;
	233	unsigned long flags;
	234
	235	kona_gpio = to_kona_gpio(chip);
	236	reg_base = kona_gpio->reg_base;
	237	spin_lock_irqsave(&kona_gpio->lock, flags);
757651e3 MM	238
	239	val = readl(reg_base + GPIO_CONTROL(gpio));
	240	val &= ~GPIO_GPCTR0_IOTR_MASK;
	241	val \|= GPIO_GPCTR0_IOTR_CMD_0UTPUT;
	242	writel(val, reg_base + GPIO_CONTROL(gpio));
	243	reg_offset = value ? GPIO_OUT_SET(bank_id) : GPIO_OUT_CLEAR(bank_id);
	244
	245	val = readl(reg_base + reg_offset);
	246	val \|= BIT(bit);
	247	writel(val, reg_base + reg_offset);
	248
757651e3 MM	249	spin_unlock_irqrestore(&kona_gpio->lock, flags);
	250
	251	return 0;
	252	}
	253
	254	static int bcm_kona_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
	255	{
	256	struct bcm_kona_gpio *kona_gpio;
	257
	258	kona_gpio = to_kona_gpio(chip);
	259	if (gpio >= kona_gpio->gpio_chip.ngpio)
	260	return -ENXIO;
	261	return irq_create_mapping(kona_gpio->irq_domain, gpio);
	262	}
	263
	264	static int bcm_kona_gpio_set_debounce(struct gpio_chip *chip, unsigned gpio,
	265	unsigned debounce)
	266	{
	267	struct bcm_kona_gpio *kona_gpio;
	268	void __iomem *reg_base;
	269	u32 val, res;
	270	unsigned long flags;
757651e3 MM	271
	272	kona_gpio = to_kona_gpio(chip);
	273	reg_base = kona_gpio->reg_base;
	274	/* debounce must be 1-128ms (or 0) */
	275	if ((debounce > 0 && debounce < 1000) \|\| debounce > 128000) {
	276	dev_err(chip->dev, "Debounce value %u not in range\n",
	277	debounce);
	278	return -EINVAL;
	279	}
	280
	281	/* calculate debounce bit value */
	282	if (debounce != 0) {
	283	/* Convert to ms */
	284	debounce /= 1000;
	285	/* find the MSB */
	286	res = fls(debounce) - 1;
	287	/* Check if MSB-1 is set (round up or down) */
	288	if (res > 0 && (debounce & BIT(res - 1)))
	289	res++;
	290	}
	291
	292	/* spin lock for read-modify-write of the GPIO register */
	293	spin_lock_irqsave(&kona_gpio->lock, flags);
757651e3 MM	294
	295	val = readl(reg_base + GPIO_CONTROL(gpio));
	296	val &= ~GPIO_GPCTR0_DBR_MASK;
	297
	298	if (debounce == 0) {
	299	/* disable debounce */
	300	val &= ~GPIO_GPCTR0_DB_ENABLE_MASK;
	301	} else {
	302	val \|= GPIO_GPCTR0_DB_ENABLE_MASK \|
	303	(res << GPIO_GPCTR0_DBR_SHIFT);
	304	}
	305
	306	writel(val, reg_base + GPIO_CONTROL(gpio));
	307
757651e3 MM	308	spin_unlock_irqrestore(&kona_gpio->lock, flags);
	309
	310	return 0;
	311	}
	312
	313	static struct gpio_chip template_chip = {
	314	.label = "bcm-kona-gpio",
afb3690c	315	.owner = THIS_MODULE,
bdb93c03 MM	316	.request = bcm_kona_gpio_request,
bdb93c03 MM	317	.free = bcm_kona_gpio_free,
0218d5a8	318	.get_direction = bcm_kona_gpio_get_dir,
757651e3 MM	319	.direction_input = bcm_kona_gpio_direction_input,
	320	.get = bcm_kona_gpio_get,
	321	.direction_output = bcm_kona_gpio_direction_output,
	322	.set = bcm_kona_gpio_set,
	323	.set_debounce = bcm_kona_gpio_set_debounce,
	324	.to_irq = bcm_kona_gpio_to_irq,
	325	.base = 0,
	326	};
	327
	328	static void bcm_kona_gpio_irq_ack(struct irq_data *d)
	329	{
	330	struct bcm_kona_gpio *kona_gpio;
	331	void __iomem *reg_base;
b7ab6973	332	unsigned gpio = d->hwirq;
757651e3 MM	333	int bank_id = GPIO_BANK(gpio);
	334	int bit = GPIO_BIT(gpio);
	335	u32 val;
	336	unsigned long flags;
	337
	338	kona_gpio = irq_data_get_irq_chip_data(d);
	339	reg_base = kona_gpio->reg_base;
	340	spin_lock_irqsave(&kona_gpio->lock, flags);
757651e3 MM	341
	342	val = readl(reg_base + GPIO_INT_STATUS(bank_id));
	343	val \|= BIT(bit);
	344	writel(val, reg_base + GPIO_INT_STATUS(bank_id));
	345
757651e3 MM	346	spin_unlock_irqrestore(&kona_gpio->lock, flags);
	347	}
	348
	349	static void bcm_kona_gpio_irq_mask(struct irq_data *d)
	350	{
	351	struct bcm_kona_gpio *kona_gpio;
	352	void __iomem *reg_base;
b7ab6973	353	unsigned gpio = d->hwirq;
757651e3 MM	354	int bank_id = GPIO_BANK(gpio);
	355	int bit = GPIO_BIT(gpio);
	356	u32 val;
	357	unsigned long flags;
	358
	359	kona_gpio = irq_data_get_irq_chip_data(d);
	360	reg_base = kona_gpio->reg_base;
	361	spin_lock_irqsave(&kona_gpio->lock, flags);
757651e3 MM	362
	363	val = readl(reg_base + GPIO_INT_MASK(bank_id));
	364	val \|= BIT(bit);
	365	writel(val, reg_base + GPIO_INT_MASK(bank_id));
	366
757651e3 MM	367	spin_unlock_irqrestore(&kona_gpio->lock, flags);
	368	}
	369
	370	static void bcm_kona_gpio_irq_unmask(struct irq_data *d)
	371	{
	372	struct bcm_kona_gpio *kona_gpio;
	373	void __iomem *reg_base;
b7ab6973	374	unsigned gpio = d->hwirq;
757651e3 MM	375	int bank_id = GPIO_BANK(gpio);
	376	int bit = GPIO_BIT(gpio);
	377	u32 val;
	378	unsigned long flags;
	379
	380	kona_gpio = irq_data_get_irq_chip_data(d);
	381	reg_base = kona_gpio->reg_base;
	382	spin_lock_irqsave(&kona_gpio->lock, flags);
757651e3 MM	383
	384	val = readl(reg_base + GPIO_INT_MSKCLR(bank_id));
	385	val \|= BIT(bit);
	386	writel(val, reg_base + GPIO_INT_MSKCLR(bank_id));
	387
757651e3 MM	388	spin_unlock_irqrestore(&kona_gpio->lock, flags);
	389	}
	390
	391	static int bcm_kona_gpio_irq_set_type(struct irq_data *d, unsigned int type)
	392	{
	393	struct bcm_kona_gpio *kona_gpio;
	394	void __iomem *reg_base;
b7ab6973	395	unsigned gpio = d->hwirq;
757651e3 MM	396	u32 lvl_type;
	397	u32 val;
	398	unsigned long flags;
757651e3 MM	399
	400	kona_gpio = irq_data_get_irq_chip_data(d);
	401	reg_base = kona_gpio->reg_base;
	402	switch (type & IRQ_TYPE_SENSE_MASK) {
	403	case IRQ_TYPE_EDGE_RISING:
	404	lvl_type = GPIO_GPCTR0_ITR_CMD_RISING_EDGE;
	405	break;
	406
	407	case IRQ_TYPE_EDGE_FALLING:
	408	lvl_type = GPIO_GPCTR0_ITR_CMD_FALLING_EDGE;
	409	break;
	410
	411	case IRQ_TYPE_EDGE_BOTH:
	412	lvl_type = GPIO_GPCTR0_ITR_CMD_BOTH_EDGE;
	413	break;
	414
	415	case IRQ_TYPE_LEVEL_HIGH:
	416	case IRQ_TYPE_LEVEL_LOW:
	417	/* BCM GPIO doesn't support level triggering */
	418	default:
	419	dev_err(kona_gpio->gpio_chip.dev,
	420	"Invalid BCM GPIO irq type 0x%x\n", type);
	421	return -EINVAL;
	422	}
	423
	424	spin_lock_irqsave(&kona_gpio->lock, flags);
757651e3 MM	425
	426	val = readl(reg_base + GPIO_CONTROL(gpio));
	427	val &= ~GPIO_GPCTR0_ITR_MASK;
	428	val \|= lvl_type << GPIO_GPCTR0_ITR_SHIFT;
	429	writel(val, reg_base + GPIO_CONTROL(gpio));
	430
757651e3 MM	431	spin_unlock_irqrestore(&kona_gpio->lock, flags);
	432
	433	return 0;
	434	}
	435
bd0b9ac4	436	static void bcm_kona_gpio_irq_handler(struct irq_desc *desc)
757651e3 MM	437	{
	438	void __iomem *reg_base;
	439	int bit, bank_id;
	440	unsigned long sta;
476f8b4c	441	struct bcm_kona_gpio_bank *bank = irq_desc_get_handler_data(desc);
757651e3 MM	442	struct irq_chip *chip = irq_desc_get_chip(desc);
	443
	444	chained_irq_enter(chip, desc);
	445
	446	/*
	447	* For bank interrupts, we can't use chip_data to store the kona_gpio
	448	* pointer, since GIC needs it for its own purposes. Therefore, we get
	449	* our pointer from the bank structure.
	450	*/
	451	reg_base = bank->kona_gpio->reg_base;
	452	bank_id = bank->id;
757651e3 MM	453
	454	while ((sta = readl(reg_base + GPIO_INT_STATUS(bank_id)) &
	455	(~(readl(reg_base + GPIO_INT_MASK(bank_id)))))) {
	456	for_each_set_bit(bit, &sta, 32) {
d933cc61 LW	457	int hwirq = GPIO_PER_BANK * bank_id + bit;
	458	int child_irq =
	459	irq_find_mapping(bank->kona_gpio->irq_domain,
	460	hwirq);
757651e3 MM	461	/*
	462	* Clear interrupt before handler is called so we don't
	463	* miss any interrupt occurred during executing them.
	464	*/
	465	writel(readl(reg_base + GPIO_INT_STATUS(bank_id)) \|
	466	BIT(bit), reg_base + GPIO_INT_STATUS(bank_id));
	467	/* Invoke interrupt handler */
d933cc61	468	generic_handle_irq(child_irq);
757651e3 MM	469	}
	470	}
	471
757651e3 MM	472	chained_irq_exit(chip, desc);
	473	}
	474
57ef0428	475	static int bcm_kona_gpio_irq_reqres(struct irq_data *d)
db6b3ad1 LW	476	{
	477	struct bcm_kona_gpio *kona_gpio = irq_data_get_irq_chip_data(d);
	478
e3a2e878	479	if (gpiochip_lock_as_irq(&kona_gpio->gpio_chip, d->hwirq)) {
db6b3ad1 LW	480	dev_err(kona_gpio->gpio_chip.dev,
	481	"unable to lock HW IRQ %lu for IRQ\n",
	482	d->hwirq);
57ef0428 LW	483	return -EINVAL;
57ef0428 LW	484	}
db6b3ad1 LW	485	return 0;
	486	}
	487
57ef0428	488	static void bcm_kona_gpio_irq_relres(struct irq_data *d)
db6b3ad1 LW	489	{
	490	struct bcm_kona_gpio *kona_gpio = irq_data_get_irq_chip_data(d);
	491
e3a2e878	492	gpiochip_unlock_as_irq(&kona_gpio->gpio_chip, d->hwirq);
db6b3ad1 LW	493	}
db6b3ad1 LW	494
757651e3 MM	495	static struct irq_chip bcm_gpio_irq_chip = {
	496	.name = "bcm-kona-gpio",
	497	.irq_ack = bcm_kona_gpio_irq_ack,
	498	.irq_mask = bcm_kona_gpio_irq_mask,
	499	.irq_unmask = bcm_kona_gpio_irq_unmask,
	500	.irq_set_type = bcm_kona_gpio_irq_set_type,
57ef0428 LW	501	.irq_request_resources = bcm_kona_gpio_irq_reqres,
57ef0428 LW	502	.irq_release_resources = bcm_kona_gpio_irq_relres,
757651e3 MM	503	};
757651e3 MM	504
37781292	505	static struct of_device_id const bcm_kona_gpio_of_match[] = {
757651e3 MM	506	{ .compatible = "brcm,kona-gpio" },
	507	{}
	508	};
	509
	510	MODULE_DEVICE_TABLE(of, bcm_kona_gpio_of_match);
	511
	512	/*
	513	* This lock class tells lockdep that GPIO irqs are in a different
	514	* category than their parents, so it won't report false recursion.
	515	*/
	516	static struct lock_class_key gpio_lock_class;
	517
1dc94272	518	static int bcm_kona_gpio_irq_map(struct irq_domain *d, unsigned int irq,
757651e3 MM	519	irq_hw_number_t hwirq)
	520	{
	521	int ret;
	522
1dc94272	523	ret = irq_set_chip_data(irq, d->host_data);
757651e3 MM	524	if (ret < 0)
757651e3 MM	525	return ret;
1dc94272 LW	526	irq_set_lockdep_class(irq, &gpio_lock_class);
1dc94272 LW	527	irq_set_chip_and_handler(irq, &bcm_gpio_irq_chip, handle_simple_irq);
1dc94272	528	irq_set_noprobe(irq);
757651e3 MM	529
	530	return 0;
	531	}
	532
d933cc61	533	static void bcm_kona_gpio_irq_unmap(struct irq_domain *d, unsigned int irq)
757651e3	534	{
d933cc61 LW	535	irq_set_chip_and_handler(irq, NULL, NULL);
d933cc61 LW	536	irq_set_chip_data(irq, NULL);
757651e3 MM	537	}
757651e3 MM	538
0b354dc4	539	static const struct irq_domain_ops bcm_kona_irq_ops = {
757651e3 MM	540	.map = bcm_kona_gpio_irq_map,
	541	.unmap = bcm_kona_gpio_irq_unmap,
	542	.xlate = irq_domain_xlate_twocell,
	543	};
	544
	545	static void bcm_kona_gpio_reset(struct bcm_kona_gpio *kona_gpio)
	546	{
	547	void __iomem *reg_base;
	548	int i;
	549
	550	reg_base = kona_gpio->reg_base;
	551	/* disable interrupts and clear status */
	552	for (i = 0; i < kona_gpio->num_bank; i++) {
bdb93c03 MM	553	/* Unlock the entire bank first */
bdb93c03 MM	554	bcm_kona_gpio_write_lock_regs(kona_gpio, i, UNLOCK_CODE);
757651e3 MM	555	writel(0xffffffff, reg_base + GPIO_INT_MASK(i));
757651e3 MM	556	writel(0xffffffff, reg_base + GPIO_INT_STATUS(i));
bdb93c03 MM	557	/* Now re-lock the bank */
bdb93c03 MM	558	bcm_kona_gpio_write_lock_regs(kona_gpio, i, LOCK_CODE);
757651e3 MM	559	}
	560	}
	561
	562	static int bcm_kona_gpio_probe(struct platform_device *pdev)
	563	{
	564	struct device *dev = &pdev->dev;
	565	const struct of_device_id *match;
	566	struct resource *res;
	567	struct bcm_kona_gpio_bank *bank;
	568	struct bcm_kona_gpio *kona_gpio;
	569	struct gpio_chip *chip;
	570	int ret;
	571	int i;
	572
	573	match = of_match_device(bcm_kona_gpio_of_match, dev);
	574	if (!match) {
	575	dev_err(dev, "Failed to find gpio controller\n");
	576	return -ENODEV;
	577	}
	578
	579	kona_gpio = devm_kzalloc(dev, sizeof(*kona_gpio), GFP_KERNEL);
	580	if (!kona_gpio)
	581	return -ENOMEM;
	582
	583	kona_gpio->gpio_chip = template_chip;
	584	chip = &kona_gpio->gpio_chip;
	585	kona_gpio->num_bank = of_irq_count(dev->of_node);
	586	if (kona_gpio->num_bank == 0) {
	587	dev_err(dev, "Couldn't determine # GPIO banks\n");
	588	return -ENOENT;
	589	}
	590	if (kona_gpio->num_bank > GPIO_MAX_BANK_NUM) {
	591	dev_err(dev, "Too many GPIO banks configured (max=%d)\n",
	592	GPIO_MAX_BANK_NUM);
	593	return -ENXIO;
	594	}
	595	kona_gpio->banks = devm_kzalloc(dev,
	596	kona_gpio->num_bank *
	597	sizeof(*kona_gpio->banks), GFP_KERNEL);
	598	if (!kona_gpio->banks)
	599	return -ENOMEM;
	600
	601	kona_gpio->pdev = pdev;
	602	platform_set_drvdata(pdev, kona_gpio);
	603	chip->of_node = dev->of_node;
	604	chip->ngpio = kona_gpio->num_bank * GPIO_PER_BANK;
	605
	606	kona_gpio->irq_domain = irq_domain_add_linear(dev->of_node,
	607	chip->ngpio,
	608	&bcm_kona_irq_ops,
	609	kona_gpio);
	610	if (!kona_gpio->irq_domain) {
	611	dev_err(dev, "Couldn't allocate IRQ domain\n");
	612	return -ENXIO;
	613	}
	614
	615	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	616	kona_gpio->reg_base = devm_ioremap_resource(dev, res);
	617	if (IS_ERR(kona_gpio->reg_base)) {
	618	ret = -ENXIO;
	619	goto err_irq_domain;
	620	}
	621
	622	for (i = 0; i < kona_gpio->num_bank; i++) {
623	bank = &kona_gpio->banks[i];
624	bank->id = i;
625	bank->irq = platform_get_irq(pdev, i);
626	bank->kona_gpio = kona_gpio;
627	if (bank->irq < 0) {
628	dev_err(dev, "Couldn't get IRQ for bank %d", i);
629	ret = -ENOENT;
630	goto err_irq_domain;
631	}
632	}
633
23b4faa9	634	dev_info(&pdev->dev, "Setting up Kona GPIO\n");
757651e3 MM	635
	636	bcm_kona_gpio_reset(kona_gpio);
	637
	638	ret = gpiochip_add(chip);
	639	if (ret < 0) {
	640	dev_err(dev, "Couldn't add GPIO chip -- %d\n", ret);
	641	goto err_irq_domain;
	642	}
757651e3 MM	643	for (i = 0; i < kona_gpio->num_bank; i++) {
757651e3 MM	644	bank = &kona_gpio->banks[i];
b34cc620 TG	645	irq_set_chained_handler_and_data(bank->irq,
	646	bcm_kona_gpio_irq_handler,
	647	bank);
757651e3 MM	648	}
	649
	650	spin_lock_init(&kona_gpio->lock);
	651
	652	return 0;
	653
	654	err_irq_domain:
	655	irq_domain_remove(kona_gpio->irq_domain);
	656
	657	return ret;
	658	}
	659
	660	static struct platform_driver bcm_kona_gpio_driver = {
	661	.driver = {
	662	.name = "bcm-kona-gpio",
757651e3 MM	663	.of_match_table = bcm_kona_gpio_of_match,
	664	},
	665	.probe = bcm_kona_gpio_probe,
	666	};
	667
	668	module_platform_driver(bcm_kona_gpio_driver);
	669
6f587c9f	670	MODULE_AUTHOR("Broadcom Corporation <bcm-kernel-feedback-list@broadcom.com>");
757651e3 MM	671	MODULE_DESCRIPTION("Broadcom Kona GPIO Driver");
757651e3 MM	672	MODULE_LICENSE("GPL v2");