[mirror_ubuntu-artful-kernel.git] / drivers / gpio / gpio-crystalcove.c

/*
 * gpio-crystalcove.c - Intel Crystal Cove GPIO Driver
 *
 * Copyright (C) 2012, 2014 Intel Corporation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License version
 * 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * Author: Yang, Bin <bin.yang@intel.com>
 */

#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/gpio.h>
#include <linux/seq_file.h>
#include <linux/bitops.h>
#include <linux/regmap.h>
#include <linux/mfd/intel_soc_pmic.h>

#define CRYSTALCOVE_GPIO_NUM	16
#define CRYSTALCOVE_VGPIO_NUM	95

#define UPDATE_IRQ_TYPE		BIT(0)
#define UPDATE_IRQ_MASK		BIT(1)

#define GPIO0IRQ		0x0b
#define GPIO1IRQ		0x0c
#define MGPIO0IRQS0		0x19
#define MGPIO1IRQS0		0x1a
#define MGPIO0IRQSX		0x1b
#define MGPIO1IRQSX		0x1c
#define GPIO0P0CTLO		0x2b
#define GPIO0P0CTLI		0x33
#define GPIO1P0CTLO		0x3b
#define GPIO1P0CTLI		0x43
#define GPIOPANELCTL		0x52

#define CTLI_INTCNT_DIS		(0)
#define CTLI_INTCNT_NE		(1 << 1)
#define CTLI_INTCNT_PE		(2 << 1)
#define CTLI_INTCNT_BE		(3 << 1)

#define CTLO_DIR_IN		(0)
#define CTLO_DIR_OUT		(1 << 5)

#define CTLO_DRV_CMOS		(0)
#define CTLO_DRV_OD		(1 << 4)

#define CTLO_DRV_REN		(1 << 3)

#define CTLO_RVAL_2KDW		(0)
#define CTLO_RVAL_2KUP		(1 << 1)
#define CTLO_RVAL_50KDW		(2 << 1)
#define CTLO_RVAL_50KUP		(3 << 1)

#define CTLO_INPUT_SET	(CTLO_DRV_CMOS | CTLO_DRV_REN | CTLO_RVAL_2KUP)
#define CTLO_OUTPUT_SET	(CTLO_DIR_OUT | CTLO_INPUT_SET)

enum ctrl_register {
	CTRL_IN,
	CTRL_OUT,
};

/**
 * struct crystalcove_gpio - Crystal Cove GPIO controller
 * @buslock: for bus lock/sync and unlock.
 * @chip: the abstract gpio_chip structure.
 * @regmap: the regmap from the parent device.
 * @update: pending IRQ setting update, to be written to the chip upon unlock.
 * @intcnt_value: the Interrupt Detect value to be written.
 * @set_irq_mask: true if the IRQ mask needs to be set, false to clear.
 */
struct crystalcove_gpio {
	struct mutex buslock; /* irq_bus_lock */
	struct gpio_chip chip;
	struct regmap *regmap;
	int update;
	int intcnt_value;
	bool set_irq_mask;
};

static inline int to_reg(int gpio, enum ctrl_register reg_type)
{
	int reg;

	if (gpio >= CRYSTALCOVE_GPIO_NUM) {
		/*
		 * Virtual GPIO called from ACPI, for now we only support
		 * the panel ctl.
		 */
		switch (gpio) {
		case 0x5e:
			return GPIOPANELCTL;
		default:
			return -EOPNOTSUPP;
		}
	}

	if (reg_type == CTRL_IN) {
		if (gpio < 8)
			reg = GPIO0P0CTLI;
		else
			reg = GPIO1P0CTLI;
	} else {
		if (gpio < 8)
			reg = GPIO0P0CTLO;
		else
			reg = GPIO1P0CTLO;
	}

	return reg + gpio % 8;
}

static void crystalcove_update_irq_mask(struct crystalcove_gpio *cg,
					int gpio)
{
	u8 mirqs0 = gpio < 8 ? MGPIO0IRQS0 : MGPIO1IRQS0;
	int mask = BIT(gpio % 8);

	if (cg->set_irq_mask)
		regmap_update_bits(cg->regmap, mirqs0, mask, mask);
	else
		regmap_update_bits(cg->regmap, mirqs0, mask, 0);
}

static void crystalcove_update_irq_ctrl(struct crystalcove_gpio *cg, int gpio)
{
	int reg = to_reg(gpio, CTRL_IN);

	regmap_update_bits(cg->regmap, reg, CTLI_INTCNT_BE, cg->intcnt_value);
}

static int crystalcove_gpio_dir_in(struct gpio_chip *chip, unsigned gpio)
{
	struct crystalcove_gpio *cg = gpiochip_get_data(chip);
	int reg = to_reg(gpio, CTRL_OUT);

	if (reg < 0)
		return 0;

	return regmap_write(cg->regmap, reg, CTLO_INPUT_SET);
}

static int crystalcove_gpio_dir_out(struct gpio_chip *chip, unsigned gpio,
				    int value)
{
	struct crystalcove_gpio *cg = gpiochip_get_data(chip);
	int reg = to_reg(gpio, CTRL_OUT);

	if (reg < 0)
		return 0;

	return regmap_write(cg->regmap, reg, CTLO_OUTPUT_SET | value);
}

static int crystalcove_gpio_get(struct gpio_chip *chip, unsigned gpio)
{
	struct crystalcove_gpio *cg = gpiochip_get_data(chip);
	unsigned int val;
	int ret, reg = to_reg(gpio, CTRL_IN);

	if (reg < 0)
		return 0;

	ret = regmap_read(cg->regmap, reg, &val);
	if (ret)
		return ret;

	return val & 0x1;
}

static void crystalcove_gpio_set(struct gpio_chip *chip,
				 unsigned gpio, int value)
{
	struct crystalcove_gpio *cg = gpiochip_get_data(chip);
	int reg = to_reg(gpio, CTRL_OUT);

	if (reg < 0)
		return;

	if (value)
		regmap_update_bits(cg->regmap, reg, 1, 1);
	else
		regmap_update_bits(cg->regmap, reg, 1, 0);
}

static int crystalcove_irq_type(struct irq_data *data, unsigned type)
{
	struct crystalcove_gpio *cg =
		gpiochip_get_data(irq_data_get_irq_chip_data(data));

	if (data->hwirq >= CRYSTALCOVE_GPIO_NUM)
		return 0;

	switch (type) {
	case IRQ_TYPE_NONE:
		cg->intcnt_value = CTLI_INTCNT_DIS;
		break;
	case IRQ_TYPE_EDGE_BOTH:
		cg->intcnt_value = CTLI_INTCNT_BE;
		break;
	case IRQ_TYPE_EDGE_RISING:
		cg->intcnt_value = CTLI_INTCNT_PE;
		break;
	case IRQ_TYPE_EDGE_FALLING:
		cg->intcnt_value = CTLI_INTCNT_NE;
		break;
	default:
		return -EINVAL;
	}

	cg->update |= UPDATE_IRQ_TYPE;

	return 0;
}

static void crystalcove_bus_lock(struct irq_data *data)
{
	struct crystalcove_gpio *cg =
		gpiochip_get_data(irq_data_get_irq_chip_data(data));

	mutex_lock(&cg->buslock);
}

static void crystalcove_bus_sync_unlock(struct irq_data *data)
{
	struct crystalcove_gpio *cg =
		gpiochip_get_data(irq_data_get_irq_chip_data(data));
	int gpio = data->hwirq;

	if (cg->update & UPDATE_IRQ_TYPE)
		crystalcove_update_irq_ctrl(cg, gpio);
	if (cg->update & UPDATE_IRQ_MASK)
		crystalcove_update_irq_mask(cg, gpio);
	cg->update = 0;

	mutex_unlock(&cg->buslock);
}

static void crystalcove_irq_unmask(struct irq_data *data)
{
	struct crystalcove_gpio *cg =
		gpiochip_get_data(irq_data_get_irq_chip_data(data));

	if (data->hwirq < CRYSTALCOVE_GPIO_NUM) {
		cg->set_irq_mask = false;
		cg->update |= UPDATE_IRQ_MASK;
	}
}

static void crystalcove_irq_mask(struct irq_data *data)
{
	struct crystalcove_gpio *cg =
		gpiochip_get_data(irq_data_get_irq_chip_data(data));

	if (data->hwirq < CRYSTALCOVE_GPIO_NUM) {
		cg->set_irq_mask = true;
		cg->update |= UPDATE_IRQ_MASK;
	}
}

static struct irq_chip crystalcove_irqchip = {
	.name			= "Crystal Cove",
	.irq_mask		= crystalcove_irq_mask,
	.irq_unmask		= crystalcove_irq_unmask,
	.irq_set_type		= crystalcove_irq_type,
	.irq_bus_lock		= crystalcove_bus_lock,
	.irq_bus_sync_unlock	= crystalcove_bus_sync_unlock,
	.flags			= IRQCHIP_SKIP_SET_WAKE,
};

static irqreturn_t crystalcove_gpio_irq_handler(int irq, void *data)
{
	struct crystalcove_gpio *cg = data;
	unsigned int p0, p1;
	int pending;
	int gpio;
	unsigned int virq;

	if (regmap_read(cg->regmap, GPIO0IRQ, &p0) ||
	    regmap_read(cg->regmap, GPIO1IRQ, &p1))
		return IRQ_NONE;

	regmap_write(cg->regmap, GPIO0IRQ, p0);
	regmap_write(cg->regmap, GPIO1IRQ, p1);

	pending = p0 | p1 << 8;

	for (gpio = 0; gpio < CRYSTALCOVE_GPIO_NUM; gpio++) {
		if (pending & BIT(gpio)) {
			virq = irq_find_mapping(cg->chip.irqdomain, gpio);
			handle_nested_irq(virq);
		}
	}

	return IRQ_HANDLED;
}

static void crystalcove_gpio_dbg_show(struct seq_file *s,
				      struct gpio_chip *chip)
{
	struct crystalcove_gpio *cg = gpiochip_get_data(chip);
	int gpio, offset;
	unsigned int ctlo, ctli, mirqs0, mirqsx, irq;

	for (gpio = 0; gpio < CRYSTALCOVE_GPIO_NUM; gpio++) {
		regmap_read(cg->regmap, to_reg(gpio, CTRL_OUT), &ctlo);
		regmap_read(cg->regmap, to_reg(gpio, CTRL_IN), &ctli);
		regmap_read(cg->regmap, gpio < 8 ? MGPIO0IRQS0 : MGPIO1IRQS0,
			    &mirqs0);
		regmap_read(cg->regmap, gpio < 8 ? MGPIO0IRQSX : MGPIO1IRQSX,
			    &mirqsx);
		regmap_read(cg->regmap, gpio < 8 ? GPIO0IRQ : GPIO1IRQ,
			    &irq);

		offset = gpio % 8;
		seq_printf(s, " gpio-%-2d %s %s %s %s ctlo=%2x,%s %s %s\n",
			   gpio, ctlo & CTLO_DIR_OUT ? "out" : "in ",
			   ctli & 0x1 ? "hi" : "lo",
			   ctli & CTLI_INTCNT_NE ? "fall" : "    ",
			   ctli & CTLI_INTCNT_PE ? "rise" : "    ",
			   ctlo,
			   mirqs0 & BIT(offset) ? "s0 mask  " : "s0 unmask",
			   mirqsx & BIT(offset) ? "sx mask  " : "sx unmask",
			   irq & BIT(offset) ? "pending" : "       ");
	}
}

static int crystalcove_gpio_probe(struct platform_device *pdev)
{
	int irq = platform_get_irq(pdev, 0);
	struct crystalcove_gpio *cg;
	int retval;
	struct device *dev = pdev->dev.parent;
	struct intel_soc_pmic *pmic = dev_get_drvdata(dev);

	if (irq < 0)
		return irq;

	cg = devm_kzalloc(&pdev->dev, sizeof(*cg), GFP_KERNEL);
	if (!cg)
		return -ENOMEM;

	platform_set_drvdata(pdev, cg);

	mutex_init(&cg->buslock);
	cg->chip.label = KBUILD_MODNAME;
	cg->chip.direction_input = crystalcove_gpio_dir_in;
	cg->chip.direction_output = crystalcove_gpio_dir_out;
	cg->chip.get = crystalcove_gpio_get;
	cg->chip.set = crystalcove_gpio_set;
	cg->chip.base = -1;
	cg->chip.ngpio = CRYSTALCOVE_VGPIO_NUM;
	cg->chip.can_sleep = true;
	cg->chip.parent = dev;
	cg->chip.dbg_show = crystalcove_gpio_dbg_show;
	cg->regmap = pmic->regmap;

	retval = devm_gpiochip_add_data(&pdev->dev, &cg->chip, cg);
	if (retval) {
		dev_warn(&pdev->dev, "add gpio chip error: %d\n", retval);
		return retval;
	}

	gpiochip_irqchip_add_nested(&cg->chip, &crystalcove_irqchip, 0,
				    handle_simple_irq, IRQ_TYPE_NONE);

	retval = request_threaded_irq(irq, NULL, crystalcove_gpio_irq_handler,
				      IRQF_ONESHOT, KBUILD_MODNAME, cg);

	if (retval) {
		dev_warn(&pdev->dev, "request irq failed: %d\n", retval);
		return retval;
	}

	gpiochip_set_nested_irqchip(&cg->chip, &crystalcove_irqchip, irq);

	return 0;
}

static int crystalcove_gpio_remove(struct platform_device *pdev)
{
	struct crystalcove_gpio *cg = platform_get_drvdata(pdev);
	int irq = platform_get_irq(pdev, 0);

	if (irq >= 0)
		free_irq(irq, cg);
	return 0;
}

static struct platform_driver crystalcove_gpio_driver = {
	.probe = crystalcove_gpio_probe,
	.remove = crystalcove_gpio_remove,
	.driver = {
		.name = "crystal_cove_gpio",
	},
};

module_platform_driver(crystalcove_gpio_driver);

MODULE_AUTHOR("Yang, Bin <bin.yang@intel.com>");
MODULE_DESCRIPTION("Intel Crystal Cove GPIO Driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
104fb1d5 ZL	1	/*
	2	* gpio-crystalcove.c - Intel Crystal Cove GPIO Driver
	3	*
	4	* Copyright (C) 2012, 2014 Intel Corporation. All rights reserved.
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License version
	8	* 2 as published by the Free Software Foundation.
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*
	15	* Author: Yang, Bin <bin.yang@intel.com>
	16	*/
	17
	18	#include <linux/interrupt.h>
f1fb9c61	19	#include <linux/module.h>
104fb1d5 ZL	20	#include <linux/platform_device.h>
104fb1d5 ZL	21	#include <linux/gpio.h>
8dbf2aa3	22	#include <linux/seq_file.h>
104fb1d5 ZL	23	#include <linux/bitops.h>
	24	#include <linux/regmap.h>
	25	#include <linux/mfd/intel_soc_pmic.h>
	26
	27	#define CRYSTALCOVE_GPIO_NUM 16
e189ca56	28	#define CRYSTALCOVE_VGPIO_NUM 95
104fb1d5 ZL	29
	30	#define UPDATE_IRQ_TYPE BIT(0)
	31	#define UPDATE_IRQ_MASK BIT(1)
	32
	33	#define GPIO0IRQ 0x0b
	34	#define GPIO1IRQ 0x0c
	35	#define MGPIO0IRQS0 0x19
	36	#define MGPIO1IRQS0 0x1a
	37	#define MGPIO0IRQSX 0x1b
	38	#define MGPIO1IRQSX 0x1c
	39	#define GPIO0P0CTLO 0x2b
	40	#define GPIO0P0CTLI 0x33
	41	#define GPIO1P0CTLO 0x3b
	42	#define GPIO1P0CTLI 0x43
e189ca56	43	#define GPIOPANELCTL 0x52
104fb1d5 ZL	44
	45	#define CTLI_INTCNT_DIS (0)
	46	#define CTLI_INTCNT_NE (1 << 1)
	47	#define CTLI_INTCNT_PE (2 << 1)
	48	#define CTLI_INTCNT_BE (3 << 1)
	49
	50	#define CTLO_DIR_IN (0)
	51	#define CTLO_DIR_OUT (1 << 5)
	52
	53	#define CTLO_DRV_CMOS (0)
	54	#define CTLO_DRV_OD (1 << 4)
	55
	56	#define CTLO_DRV_REN (1 << 3)
	57
	58	#define CTLO_RVAL_2KDW (0)
	59	#define CTLO_RVAL_2KUP (1 << 1)
	60	#define CTLO_RVAL_50KDW (2 << 1)
	61	#define CTLO_RVAL_50KUP (3 << 1)
	62
	63	#define CTLO_INPUT_SET (CTLO_DRV_CMOS \| CTLO_DRV_REN \| CTLO_RVAL_2KUP)
	64	#define CTLO_OUTPUT_SET (CTLO_DIR_OUT \| CTLO_INPUT_SET)
	65
	66	enum ctrl_register {
	67	CTRL_IN,
	68	CTRL_OUT,
	69	};
	70
	71	/**
	72	* struct crystalcove_gpio - Crystal Cove GPIO controller
	73	* @buslock: for bus lock/sync and unlock.
	74	* @chip: the abstract gpio_chip structure.
	75	* @regmap: the regmap from the parent device.
	76	* @update: pending IRQ setting update, to be written to the chip upon unlock.
	77	* @intcnt_value: the Interrupt Detect value to be written.
	78	* @set_irq_mask: true if the IRQ mask needs to be set, false to clear.
	79	*/
	80	struct crystalcove_gpio {
	81	struct mutex buslock; /* irq_bus_lock */
	82	struct gpio_chip chip;
	83	struct regmap *regmap;
	84	int update;
	85	int intcnt_value;
	86	bool set_irq_mask;
	87	};
	88
104fb1d5 ZL	89	static inline int to_reg(int gpio, enum ctrl_register reg_type)
	90	{
	91	int reg;
	92
9a752b4c HG	93	if (gpio >= CRYSTALCOVE_GPIO_NUM) {
	94	/*
	95	* Virtual GPIO called from ACPI, for now we only support
	96	* the panel ctl.
	97	*/
	98	switch (gpio) {
	99	case 0x5e:
	100	return GPIOPANELCTL;
	101	default:
	102	return -EOPNOTSUPP;
	103	}
	104	}
e189ca56	105
104fb1d5 ZL	106	if (reg_type == CTRL_IN) {
	107	if (gpio < 8)
	108	reg = GPIO0P0CTLI;
	109	else
	110	reg = GPIO1P0CTLI;
	111	} else {
	112	if (gpio < 8)
	113	reg = GPIO0P0CTLO;
	114	else
	115	reg = GPIO1P0CTLO;
	116	}
	117
	118	return reg + gpio % 8;
	119	}
	120
	121	static void crystalcove_update_irq_mask(struct crystalcove_gpio *cg,
	122	int gpio)
	123	{
	124	u8 mirqs0 = gpio < 8 ? MGPIO0IRQS0 : MGPIO1IRQS0;
	125	int mask = BIT(gpio % 8);
	126
	127	if (cg->set_irq_mask)
	128	regmap_update_bits(cg->regmap, mirqs0, mask, mask);
	129	else
	130	regmap_update_bits(cg->regmap, mirqs0, mask, 0);
	131	}
	132
	133	static void crystalcove_update_irq_ctrl(struct crystalcove_gpio *cg, int gpio)
	134	{
	135	int reg = to_reg(gpio, CTRL_IN);
	136
	137	regmap_update_bits(cg->regmap, reg, CTLI_INTCNT_BE, cg->intcnt_value);
	138	}
	139
	140	static int crystalcove_gpio_dir_in(struct gpio_chip *chip, unsigned gpio)
	141	{
435cc3d4	142	struct crystalcove_gpio *cg = gpiochip_get_data(chip);
9a752b4c	143	int reg = to_reg(gpio, CTRL_OUT);
104fb1d5	144
9a752b4c	145	if (reg < 0)
dcdc3018 AL	146	return 0;
dcdc3018 AL	147
9a752b4c	148	return regmap_write(cg->regmap, reg, CTLO_INPUT_SET);
104fb1d5 ZL	149	}
	150
	151	static int crystalcove_gpio_dir_out(struct gpio_chip *chip, unsigned gpio,
	152	int value)
	153	{
435cc3d4	154	struct crystalcove_gpio *cg = gpiochip_get_data(chip);
9a752b4c	155	int reg = to_reg(gpio, CTRL_OUT);
104fb1d5	156
9a752b4c	157	if (reg < 0)
dcdc3018 AL	158	return 0;
dcdc3018 AL	159
9a752b4c	160	return regmap_write(cg->regmap, reg, CTLO_OUTPUT_SET \| value);
104fb1d5 ZL	161	}
	162
	163	static int crystalcove_gpio_get(struct gpio_chip *chip, unsigned gpio)
	164	{
435cc3d4	165	struct crystalcove_gpio *cg = gpiochip_get_data(chip);
104fb1d5	166	unsigned int val;
9a752b4c	167	int ret, reg = to_reg(gpio, CTRL_IN);
104fb1d5	168
9a752b4c	169	if (reg < 0)
dcdc3018 AL	170	return 0;
dcdc3018 AL	171
9a752b4c	172	ret = regmap_read(cg->regmap, reg, &val);
104fb1d5 ZL	173	if (ret)
	174	return ret;
	175
	176	return val & 0x1;
	177	}
	178
	179	static void crystalcove_gpio_set(struct gpio_chip *chip,
	180	unsigned gpio, int value)
	181	{
435cc3d4	182	struct crystalcove_gpio *cg = gpiochip_get_data(chip);
9a752b4c	183	int reg = to_reg(gpio, CTRL_OUT);
104fb1d5	184
9a752b4c	185	if (reg < 0)
dcdc3018 AL	186	return;
dcdc3018 AL	187
104fb1d5	188	if (value)
9a752b4c	189	regmap_update_bits(cg->regmap, reg, 1, 1);
104fb1d5	190	else
9a752b4c	191	regmap_update_bits(cg->regmap, reg, 1, 0);
104fb1d5 ZL	192	}
	193
	194	static int crystalcove_irq_type(struct irq_data *data, unsigned type)
	195	{
435cc3d4 LW	196	struct crystalcove_gpio *cg =
435cc3d4 LW	197	gpiochip_get_data(irq_data_get_irq_chip_data(data));
104fb1d5	198
9a752b4c HG	199	if (data->hwirq >= CRYSTALCOVE_GPIO_NUM)
	200	return 0;
	201
104fb1d5 ZL	202	switch (type) {
	203	case IRQ_TYPE_NONE:
	204	cg->intcnt_value = CTLI_INTCNT_DIS;
	205	break;
	206	case IRQ_TYPE_EDGE_BOTH:
	207	cg->intcnt_value = CTLI_INTCNT_BE;
	208	break;
	209	case IRQ_TYPE_EDGE_RISING:
	210	cg->intcnt_value = CTLI_INTCNT_PE;
	211	break;
	212	case IRQ_TYPE_EDGE_FALLING:
	213	cg->intcnt_value = CTLI_INTCNT_NE;
	214	break;
	215	default:
	216	return -EINVAL;
	217	}
	218
	219	cg->update \|= UPDATE_IRQ_TYPE;
	220
	221	return 0;
	222	}
	223
	224	static void crystalcove_bus_lock(struct irq_data *data)
	225	{
435cc3d4 LW	226	struct crystalcove_gpio *cg =
435cc3d4 LW	227	gpiochip_get_data(irq_data_get_irq_chip_data(data));
104fb1d5 ZL	228
	229	mutex_lock(&cg->buslock);
	230	}
	231
	232	static void crystalcove_bus_sync_unlock(struct irq_data *data)
	233	{
435cc3d4 LW	234	struct crystalcove_gpio *cg =
435cc3d4 LW	235	gpiochip_get_data(irq_data_get_irq_chip_data(data));
104fb1d5 ZL	236	int gpio = data->hwirq;
	237
	238	if (cg->update & UPDATE_IRQ_TYPE)
	239	crystalcove_update_irq_ctrl(cg, gpio);
	240	if (cg->update & UPDATE_IRQ_MASK)
	241	crystalcove_update_irq_mask(cg, gpio);
	242	cg->update = 0;
	243
	244	mutex_unlock(&cg->buslock);
	245	}
	246
	247	static void crystalcove_irq_unmask(struct irq_data *data)
	248	{
435cc3d4 LW	249	struct crystalcove_gpio *cg =
435cc3d4 LW	250	gpiochip_get_data(irq_data_get_irq_chip_data(data));
104fb1d5	251
9a752b4c HG	252	if (data->hwirq < CRYSTALCOVE_GPIO_NUM) {
	253	cg->set_irq_mask = false;
	254	cg->update \|= UPDATE_IRQ_MASK;
	255	}
104fb1d5 ZL	256	}
	257
	258	static void crystalcove_irq_mask(struct irq_data *data)
	259	{
435cc3d4 LW	260	struct crystalcove_gpio *cg =
435cc3d4 LW	261	gpiochip_get_data(irq_data_get_irq_chip_data(data));
104fb1d5	262
9a752b4c HG	263	if (data->hwirq < CRYSTALCOVE_GPIO_NUM) {
	264	cg->set_irq_mask = true;
	265	cg->update \|= UPDATE_IRQ_MASK;
	266	}
104fb1d5 ZL	267	}
	268
	269	static struct irq_chip crystalcove_irqchip = {
	270	.name = "Crystal Cove",
	271	.irq_mask = crystalcove_irq_mask,
	272	.irq_unmask = crystalcove_irq_unmask,
	273	.irq_set_type = crystalcove_irq_type,
	274	.irq_bus_lock = crystalcove_bus_lock,
	275	.irq_bus_sync_unlock = crystalcove_bus_sync_unlock,
61e749d7	276	.flags = IRQCHIP_SKIP_SET_WAKE,
104fb1d5 ZL	277	};
	278
	279	static irqreturn_t crystalcove_gpio_irq_handler(int irq, void *data)
	280	{
	281	struct crystalcove_gpio *cg = data;
	282	unsigned int p0, p1;
	283	int pending;
	284	int gpio;
	285	unsigned int virq;
	286
	287	if (regmap_read(cg->regmap, GPIO0IRQ, &p0) \|\|
	288	regmap_read(cg->regmap, GPIO1IRQ, &p1))
	289	return IRQ_NONE;
	290
	291	regmap_write(cg->regmap, GPIO0IRQ, p0);
	292	regmap_write(cg->regmap, GPIO1IRQ, p1);
	293
	294	pending = p0 \| p1 << 8;
	295
dcdc3018	296	for (gpio = 0; gpio < CRYSTALCOVE_GPIO_NUM; gpio++) {
104fb1d5 ZL	297	if (pending & BIT(gpio)) {
104fb1d5 ZL	298	virq = irq_find_mapping(cg->chip.irqdomain, gpio);
e733a2fb	299	handle_nested_irq(virq);
104fb1d5 ZL	300	}
	301	}
	302
	303	return IRQ_HANDLED;
	304	}
	305
	306	static void crystalcove_gpio_dbg_show(struct seq_file *s,
	307	struct gpio_chip *chip)
	308	{
435cc3d4	309	struct crystalcove_gpio *cg = gpiochip_get_data(chip);
104fb1d5 ZL	310	int gpio, offset;
	311	unsigned int ctlo, ctli, mirqs0, mirqsx, irq;
	312
dcdc3018	313	for (gpio = 0; gpio < CRYSTALCOVE_GPIO_NUM; gpio++) {
104fb1d5 ZL	314	regmap_read(cg->regmap, to_reg(gpio, CTRL_OUT), &ctlo);
	315	regmap_read(cg->regmap, to_reg(gpio, CTRL_IN), &ctli);
	316	regmap_read(cg->regmap, gpio < 8 ? MGPIO0IRQS0 : MGPIO1IRQS0,
	317	&mirqs0);
	318	regmap_read(cg->regmap, gpio < 8 ? MGPIO0IRQSX : MGPIO1IRQSX,
	319	&mirqsx);
	320	regmap_read(cg->regmap, gpio < 8 ? GPIO0IRQ : GPIO1IRQ,
	321	&irq);
	322
	323	offset = gpio % 8;
	324	seq_printf(s, " gpio-%-2d %s %s %s %s ctlo=%2x,%s %s %s\n",
	325	gpio, ctlo & CTLO_DIR_OUT ? "out" : "in ",
	326	ctli & 0x1 ? "hi" : "lo",
	327	ctli & CTLI_INTCNT_NE ? "fall" : " ",
	328	ctli & CTLI_INTCNT_PE ? "rise" : " ",
	329	ctlo,
	330	mirqs0 & BIT(offset) ? "s0 mask " : "s0 unmask",
	331	mirqsx & BIT(offset) ? "sx mask " : "sx unmask",
	332	irq & BIT(offset) ? "pending" : " ");
	333	}
	334	}
	335
	336	static int crystalcove_gpio_probe(struct platform_device *pdev)
	337	{
	338	int irq = platform_get_irq(pdev, 0);
	339	struct crystalcove_gpio *cg;
	340	int retval;
	341	struct device *dev = pdev->dev.parent;
	342	struct intel_soc_pmic *pmic = dev_get_drvdata(dev);
	343
	344	if (irq < 0)
	345	return irq;
	346
	347	cg = devm_kzalloc(&pdev->dev, sizeof(*cg), GFP_KERNEL);
	348	if (!cg)
	349	return -ENOMEM;
	350
	351	platform_set_drvdata(pdev, cg);
	352
	353	mutex_init(&cg->buslock);
	354	cg->chip.label = KBUILD_MODNAME;
	355	cg->chip.direction_input = crystalcove_gpio_dir_in;
	356	cg->chip.direction_output = crystalcove_gpio_dir_out;
	357	cg->chip.get = crystalcove_gpio_get;
	358	cg->chip.set = crystalcove_gpio_set;
	359	cg->chip.base = -1;
dcdc3018	360	cg->chip.ngpio = CRYSTALCOVE_VGPIO_NUM;
104fb1d5	361	cg->chip.can_sleep = true;
58383c78	362	cg->chip.parent = dev;
104fb1d5 ZL	363	cg->chip.dbg_show = crystalcove_gpio_dbg_show;
	364	cg->regmap = pmic->regmap;
	365
828e47e4	366	retval = devm_gpiochip_add_data(&pdev->dev, &cg->chip, cg);
104fb1d5 ZL	367	if (retval) {
	368	dev_warn(&pdev->dev, "add gpio chip error: %d\n", retval);
	369	return retval;
	370	}
	371
d245b3f9 LW	372	gpiochip_irqchip_add_nested(&cg->chip, &crystalcove_irqchip, 0,
d245b3f9 LW	373	handle_simple_irq, IRQ_TYPE_NONE);
104fb1d5 ZL	374
	375	retval = request_threaded_irq(irq, NULL, crystalcove_gpio_irq_handler,
	376	IRQF_ONESHOT, KBUILD_MODNAME, cg);
	377
	378	if (retval) {
	379	dev_warn(&pdev->dev, "request irq failed: %d\n", retval);
828e47e4	380	return retval;
104fb1d5 ZL	381	}
104fb1d5 ZL	382
35ca3f61 LW	383	gpiochip_set_nested_irqchip(&cg->chip, &crystalcove_irqchip, irq);
35ca3f61 LW	384
104fb1d5	385	return 0;
104fb1d5 ZL	386	}
	387
	388	static int crystalcove_gpio_remove(struct platform_device *pdev)
	389	{
	390	struct crystalcove_gpio *cg = platform_get_drvdata(pdev);
	391	int irq = platform_get_irq(pdev, 0);
104fb1d5 ZL	392
	393	if (irq >= 0)
	394	free_irq(irq, cg);
da26d5d8	395	return 0;
104fb1d5 ZL	396	}
	397
	398	static struct platform_driver crystalcove_gpio_driver = {
	399	.probe = crystalcove_gpio_probe,
	400	.remove = crystalcove_gpio_remove,
	401	.driver = {
	402	.name = "crystal_cove_gpio",
104fb1d5 ZL	403	},
	404	};
	405
	406	module_platform_driver(crystalcove_gpio_driver);
	407
	408	MODULE_AUTHOR("Yang, Bin <bin.yang@intel.com>");
	409	MODULE_DESCRIPTION("Intel Crystal Cove GPIO Driver");
	410	MODULE_LICENSE("GPL v2");